JP2002093982A - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method thereforInfo
- Publication number
- JP2002093982A JP2002093982A JP2000277978A JP2000277978A JP2002093982A JP 2002093982 A JP2002093982 A JP 2002093982A JP 2000277978 A JP2000277978 A JP 2000277978A JP 2000277978 A JP2000277978 A JP 2000277978A JP 2002093982 A JP2002093982 A JP 2002093982A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- die pad
- resin
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45644—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に係り、特に、ＣＳＰ（チップ・サイズ・パ
ッケージ）の一種であるＱＦＮ（クワッド・フラット・
リードレス・パッケージ）のパッケージ構造を有する半
導体装置をプリント配線板等に実装する際の信頼性を高
めるのに有用なプロセス技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a QFN (Quad Flat Package) which is a kind of CSP (Chip Size Package).
The present invention relates to a process technology useful for improving reliability when a semiconductor device having a package structure of a leadless package is mounted on a printed wiring board or the like.
【０００２】[0002]
【従来の技術】ＱＦＮのパッケージ構造については、そ
の標準仕様がＪＥＤＥＣ１１−５３４によって定められ
ている。その仕様形態は図１に示される通りであり、
（ａ）はパッケージの裏面から見た概略構造、（ｂ）及
び（ｃ）はそれぞれ（ａ）のＢ−Ｂ’線及びＣ−Ｃ’線
に沿って見た断面構造を示している。図中、１は半導体
素子、２は半導体素子１を搭載するためのダイパッド
部、３は外部端子として供されるリード部、４は半導体
素子１の電極をリード部３に接続するボンディングワイ
ヤ、５は半導体素子１及びボンディングワイヤ４を保護
するための封止樹脂を示す。2. Description of the Related Art The standard specifications of the package structure of a QFN are defined by JEDEC11-534. Its specification is as shown in FIG.
(A) shows a schematic structure as viewed from the back surface of the package, and (b) and (c) show cross-sectional structures as viewed along the line BB 'and CC' of (a), respectively. In the figure, 1 is a semiconductor element, 2 is a die pad for mounting the semiconductor element 1, 3 is a lead part provided as an external terminal, 4 is a bonding wire for connecting an electrode of the semiconductor element 1 to the lead 3, 5. Denotes a sealing resin for protecting the semiconductor element 1 and the bonding wires 4.
【０００３】このＪＥＤＥＣ１１−５３４によるＱＦＮ
パッケージの仕様によれば、組み立て後、すなわち最終
的な形態の半導体装置において、ダイパッド部２及びリ
ード部３は、パッケージの裏面から規定の厚さＰ（＝
０．０２ｍｍ）を標準として凸状に突出させることが推
奨されている（図１（ｂ）及び（ｃ）参照）。特に、リ
ード部３を突出させることは、本装置をプリント配線板
等の実装用基板に実装する際に、当該基板上のランドに
付着されたはんだとの接合をより確実なものにする（つ
まり、高信頼度の実装を実現する）という意味で、重要
である。The QFN based on this JEDEC 11-534
According to the specifications of the package, after assembly, that is, in the final form of the semiconductor device, the die pad portion 2 and the lead portion 3 have a specified thickness P (=
(0.02 mm) as a standard, it is recommended to protrude in a convex shape (see FIGS. 1B and 1C). In particular, projecting the lead portion 3 ensures that when the device is mounted on a mounting board such as a printed wiring board, bonding with solder attached to lands on the board is more reliable (that is, , Realizing a highly reliable implementation).
【０００４】このような特殊な構造を有するＱＦＮパッ
ケージ（半導体装置）は、リードフレームを基板として
用いる通常のプラスチックパッケージのプロセスと同様
にして作製することができる。基本的なプロセスとして
は、リードフレームのダイパッド部に半導体素子を搭載
する処理（ダイ・ボンディング）、半導体素子の電極と
リードフレームのリード部とをワイヤにより電気的に接
続する処理（ワイヤ・ボンディング）、半導体素子、ワ
イヤ等を封止樹脂により封止する処理（モールディン
グ）、リードフレームを各パッケージ単位に分割する処
理（ダイシング）などを含む。また、モールディングの
形態として、個別モールディング方式、一括モールディ
ング方式などが用いられる。A QFN package (semiconductor device) having such a special structure can be manufactured in the same manner as a normal plastic package process using a lead frame as a substrate. As a basic process, a process of mounting a semiconductor element on a die pad portion of a lead frame (die bonding) and a process of electrically connecting an electrode of the semiconductor element and a lead portion of the lead frame by a wire (wire bonding) , A process of molding semiconductor elements, wires, and the like with a sealing resin (molding), and a process of dividing a lead frame into package units (dicing). As a form of molding, an individual molding method, a collective molding method, or the like is used.
【０００５】個別モールディング方式では、その一例と
して図２（ａ）及び（ｂ）に示すように、ダイ・ボンデ
ィング（リードフレーム１１のダイパッド部１２への半
導体素子１０の搭載）及びワイヤ・ボンディング（半導
体素子１０の電極とリードフレーム１１のリード部１３
とのワイヤ１４による接続）が行われた後のリードフレ
ーム１１に対し、このリードフレーム１１を絶縁性の弾
性体シート１５を介して搭載する下側の金型１６ａと、
封止樹脂１７の最終形状に応じた凹部を有する上側の金
型（モールディング金型１６ｂ）とを用いて、加熱及び
加圧しながらモールディング金型１６ｂによりリードフ
レーム１１を単体毎に（個々の半導体素子単位で）弾性
体シート１５に押し込んで封止樹脂１７を充填する。In the individual molding method, as shown in FIGS. 2A and 2B, die bonding (mounting of the semiconductor element 10 on the die pad portion 12 of the lead frame 11) and wire bonding (semiconductor) are shown as examples. Electrode of element 10 and lead portion 13 of lead frame 11
And a lower mold 16a for mounting the lead frame 11 via an insulating elastic sheet 15 with respect to the lead frame 11 after the connection with the wire 14 is performed.
Using the upper mold (molding mold 16b) having a concave portion corresponding to the final shape of the sealing resin 17, the lead frame 11 is individually formed by the molding mold 16b while heating and pressing (individual semiconductor elements). The sealing resin 17 is filled by pressing into the elastic sheet 15 (in units).
【０００６】これに対し一括モールディング方式では、
同様にしてダイ・ボンディング及びワイヤ・ボンディン
グが行われた後のリードフレームに対し、このリードフ
レームの全面（半導体素子が搭載されている側と反対側
の面）に特殊な有機樹脂フィルムを貼り付け、同様に金
型を用いた加熱及び加圧処理により複数個の半導体素子
単位で封止樹脂を充填する。On the other hand, in the batch molding method,
Similarly, a special organic resin film is attached to the entire surface of the lead frame (the surface opposite to the side on which the semiconductor element is mounted) on the lead frame after die bonding and wire bonding have been performed. Similarly, the sealing resin is filled in units of a plurality of semiconductor elements by a heat and pressure treatment using a mold.
【０００７】[0007]
【発明が解決しようとする課題】上述したように、個別
モールディング方式では金型の圧力によりリードフレー
ムを単体毎に弾性体シートに押し込んで封止樹脂を充填
しており、このとき、図２（ａ）及び（ｂ）に例示する
ように、リード部１３に対してはそのエッジ部分が金型
１６ｂによって直に押圧されているが、ダイパッド部１
２に対しては封止樹脂１７を介して間接的に圧力が加え
られるため、ダイパッド部１２に対する押しつけ圧力
は、リード部１３に対する押しつけ圧力よりも相対的に
小さくなる。その結果、この押しつけ圧力の差に起因し
て、ダイパッド部１２とリード部１３を同じ高さに揃え
ることができないという不都合が生じる。As described above, in the individual molding method, the lead frame is pushed into the elastic sheet by a single unit by the pressure of the mold and filled with the sealing resin. As illustrated in a) and (b), the edge portion of the lead portion 13 is directly pressed by the die 16b.
2 is applied indirectly via the sealing resin 17, so that the pressing pressure on the die pad portion 12 is relatively smaller than the pressing pressure on the lead portion 13. As a result, there is a disadvantage that the die pad portion 12 and the lead portion 13 cannot be aligned at the same height due to the difference in the pressing pressure.
【０００８】特に、リードフレームの厚さは極めて薄い
ため（０．１２５ｍｍ程度）、上記の押しつけ圧力の差
に抗してリード部１３とダイパッド部１２との相互の位
置関係（特に厚さ方向）を、当初の同じ高さのまま（図
２（ａ）に示す状態で）維持することは極めて困難であ
る。図２（ｂ）の例示では、リード部１３はパッケージ
の裏面から突出しているが、ダイパッド部１２はパッケ
ージの裏面から露出していない。In particular, since the thickness of the lead frame is extremely thin (about 0.125 mm), the mutual positional relationship between the lead portion 13 and the die pad portion 12 (particularly in the thickness direction) against the difference in the pressing pressure described above. It is extremely difficult to maintain the same height at the beginning (in the state shown in FIG. 2A). In the example of FIG. 2B, the lead portion 13 protrudes from the back surface of the package, but the die pad portion 12 is not exposed from the back surface of the package.
【０００９】ダイパッド部１２については、リード部１
３とは違い、プリント配線板等への実装という点では必
ずしもパッケージの裏面から露出もしくは突出させる必
要はないが、搭載する半導体素子１０で発生された熱を
外部に逃す（放熱効果）という点ではパッケージの裏面
から露出もしくは突出させた方が望ましい。また、リー
ド部１３については、図２（ｂ）に例示したようにパッ
ケージの裏面から突出させることはできるが、金型１６
ｂによる押圧力はリード部１３のエッジ部分に加えられ
るため、場合によっては、図２（ｃ）に例示するよう
に、リード部１３がパッケージの裏面から傾斜して露出
するといった不都合が生じる。これは、プリント配線板
等への実装時の信頼性を損なうものである。The die pad 12 has a lead 1
Unlike the case of No. 3, it is not always necessary to expose or protrude from the back surface of the package in terms of mounting on a printed wiring board or the like, but in terms of releasing heat generated in the mounted semiconductor element 10 to the outside (radiation effect). It is desirable to expose or protrude from the back surface of the package. The lead portion 13 can protrude from the back surface of the package as illustrated in FIG.
Since the pressing force b is applied to the edge portion of the lead portion 13, in some cases, there is a disadvantage that the lead portion 13 is inclined and exposed from the back surface of the package as illustrated in FIG. 2C. This impairs reliability at the time of mounting on a printed wiring board or the like.
【００１０】さらに、個別モールディング方式では単体
毎に樹脂封止を行っているため、一括モールディング方
式と比べると、パッケージの組み立ての効率化という点
で難点がある。これに対し、一括モールディング方式の
場合、パッケージの組み立ての効率化という点では有利
であるが、リードフレームの全面に有機樹脂フィルムを
貼り付けるため、モールディング時の加熱処理の際に、
リードフレームと有機樹脂フィルムの熱膨張率の差に起
因して、リードフレームが反ってしまうという不都合が
生じる。さらに、リードフレームの片面に一括モールデ
ィングされた封止樹脂との間にも熱膨張率の差があるた
め、リードフレームの反りが顕著になったり、或いは逆
方向に反ってしまうという不都合が生じる。その結果、
パッケージの裏面から突出させるべきリード部及びダイ
パッド部の高さは、不均一となってしまう可能性が高
い。[0010] Further, in the individual molding method, since resin sealing is performed for each single unit, there is a problem in that the efficiency of package assembly is improved as compared with the collective molding method. On the other hand, in the case of the batch molding method, although it is advantageous in terms of increasing the efficiency of package assembly, since the organic resin film is attached to the entire surface of the lead frame, during the heat treatment during molding,
Due to the difference in the coefficient of thermal expansion between the lead frame and the organic resin film, there is an inconvenience that the lead frame is warped. Furthermore, since there is also a difference in the coefficient of thermal expansion between the encapsulating resin and the encapsulating resin that is collectively molded on one side of the lead frame, there is a problem that the warp of the lead frame becomes remarkable or warps in the opposite direction. as a result,
The height of the lead portion and the die pad portion to be projected from the back surface of the package is likely to be non-uniform.
【００１１】また、一括モールディング方式の場合、現
状の技術では、有機樹脂フィルムの材料の選定、有機樹
脂フィルムをリードフレームに貼り付ける方法、有機樹
脂フィルムを貼り付けたリードフレームを用いてパッケ
ージの組み立てを安定して行う方法などが確立されてい
ないため、ＱＦＮパッケージとしての信頼性を一定に維
持するのは困難である。In the case of the batch molding method, according to the current technology, a material for an organic resin film is selected, a method of attaching the organic resin film to a lead frame, and assembly of a package using the lead frame to which the organic resin film is attached. However, it has been difficult to maintain the reliability of the QFN package at a constant level because a method for stably performing the method has not been established.
【００１２】このように個別モールディング方式、一括
モールディング方式のいずれを用いた半導体装置（ＱＦ
Ｎパッケージ）においても、リード部及びダイパッド部
の突出高さは安定しておらず、必ずしも同じ高さに突出
させることができないため、プリント配線板等に実装し
た時の信頼性が保てないという課題があった。本発明
は、上述した従来技術における課題に鑑み創作されたも
ので、パッケージの裏面からリード部及びダイパッド部
を均一の高さで安定に突出可能とし、ひいてはプリント
配線板等への実装時の信頼性を高め、放熱性の向上にも
寄与することができる半導体装置及びその製造方法を提
供することを目的とする。As described above, the semiconductor device (QF) using either the individual molding method or the collective molding method
N package), the protrusion heights of the lead portion and the die pad portion are not stable and cannot always be protruded at the same height, so that reliability when mounted on a printed wiring board or the like cannot be maintained. There were challenges. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems in the related art, and enables a lead portion and a die pad portion to stably project at a uniform height from the back surface of a package, and furthermore, the reliability at the time of mounting on a printed wiring board or the like. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can enhance the heat dissipation and contribute to the improvement of heat dissipation.
【００１３】[0013]
【課題を解決するための手段】上記の従来技術の課題を
解決するため、本発明の一形態に係る半導体装置は、所
要箇所に開口部を有し、該開口部によってダイパッド部
及びその周囲のリード部が画定されたリードフレーム
と、該リードフレームの一方の面側の前記ダイパッド部
上に搭載された半導体素子と、該半導体素子の電極と前
記リードフレームの一方の面側の前記リード部とが電気
的に接続されたボンディングワイヤと、前記半導体素
子、前記ボンディングワイヤ及び前記リードフレームの
一方の面側の前記リード部が封止された樹脂と、前記リ
ードフレームの開口部の一方の面側に、該リードフレー
ムの厚さよりも所定の厚さだけ薄い厚さで充填された樹
脂とを備えてなることを特徴とする。In order to solve the above-mentioned problems of the prior art, a semiconductor device according to an embodiment of the present invention has an opening at a required position, and the opening forms a die pad portion and its surroundings. A lead frame in which a lead portion is defined, a semiconductor element mounted on the die pad portion on one surface side of the lead frame, an electrode of the semiconductor element and the lead portion on one surface side of the lead frame; A bonding wire electrically connected, a resin in which the semiconductor element, the bonding wire, and the lead portion on one surface side of the lead frame are sealed, and one surface side of an opening of the lead frame. And a resin filled with a thickness smaller by a predetermined thickness than the thickness of the lead frame.
【００１４】また、本発明の他の形態に係る半導体装置
の製造方法は、ダイパッド部及びその周囲のリード部を
画定する開口部を有する単位リードフレームが複数個連
結されたリードフレームを形成する工程と、前記リード
フレームの開口部の一方の面側に、該リードフレームの
厚さよりも所定の厚さだけ薄い厚さで樹脂を充填する工
程と、前記リードフレームの一方の面側の各ダイパッド
部上にそれぞれ半導体素子を搭載する工程と、前記各半
導体素子の電極と前記リードフレームの一方の面側の対
応する各リード部とをそれぞれボンディングワイヤによ
り電気的に接続する工程と、前記各半導体素子、前記各
ボンディングワイヤ及び前記リードフレームの一方の面
側の各リード部を封止樹脂により封止する工程と、前記
各半導体素子が搭載されたリードフレームをそれぞれ１
個の半導体素子が含まれるように各半導体装置に分割す
る工程とを含むことを特徴とする。According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a lead frame in which a plurality of unit lead frames each having an opening defining a die pad portion and a lead portion around the die pad portion are connected. Filling one side of the opening of the lead frame with a resin having a thickness smaller by a predetermined thickness than the thickness of the lead frame; and each die pad portion on one side of the lead frame. Mounting a semiconductor element thereon, electrically connecting an electrode of each semiconductor element and a corresponding lead portion on one surface side of the lead frame with a bonding wire, respectively, Sealing each of the bonding wires and each of the lead portions on one side of the lead frame with a sealing resin; It has been the lead frame each 1
And dividing the semiconductor device into individual semiconductor devices so as to include the individual semiconductor elements.
【００１５】本発明に係る半導体装置及びその製造方法
によれば、リードフレームの開口部に、該リードフレー
ムの厚さよりも所定の厚さだけ薄い厚さで該リードフレ
ームの一方の面から内側に樹脂が充填されているので、
この充填された樹脂の端面から見ると、リード部及びダ
イパッド部をその所定の厚さだけ突出させることができ
る。このとき、開口部に充填された樹脂により、リード
部とダイパッド部との相互の位置関係（特に厚さ方向）
は固定化されているので、リード部及びダイパッド部の
突出高さを安定に保持することができる。According to the semiconductor device and the method of manufacturing the same according to the present invention, the thickness of the lead frame is reduced by a predetermined thickness smaller than the thickness of the lead frame from one surface of the lead frame to the inside thereof. Since the resin is filled,
When viewed from the end face of the filled resin, the lead portion and the die pad portion can be protruded by a predetermined thickness. At this time, the mutual positional relationship (particularly in the thickness direction) between the lead portion and the die pad portion is caused by the resin filled in the opening.
Is fixed, so that the protruding height of the lead portion and the die pad portion can be stably maintained.
【００１６】これによって、後の工程で樹脂封止（モー
ルディング）を行ったときに、従来技術に見られたよう
な不都合（押しつけ圧力や熱膨張率の差に起因する突出
高さの不均一、リード部の傾斜した露出など）が生じる
可能性を排除することができる。これは、プリント配線
板等に実装する際の信頼性の向上に寄与する。また、半
導体素子を搭載するダイパッド部は外部に露出している
ので、このダイパッド部を介して装置内部の熱（主とし
て半導体素子で発生された熱）を装置外部に効果的に逃
すことができる（放熱性の向上）。[0016] Thus, when resin molding (molding) is performed in a later step, inconveniences such as the prior art (unevenness of the protrusion height due to the difference in pressing pressure and thermal expansion coefficient, (E.g., oblique exposure of the lead portion) can be eliminated. This contributes to an improvement in reliability when mounting on a printed wiring board or the like. Further, since the die pad portion on which the semiconductor element is mounted is exposed to the outside, heat inside the device (mainly heat generated in the semiconductor device) can be effectively released to the outside of the device via the die pad portion ( Improvement of heat dissipation).
【００１７】[0017]
【発明の実施の形態】図３は本発明の一実施形態に係る
半導体装置（ＱＦＮパッケージ）の断面的な構成を示し
たものである。図中、２０は本実施形態に係る半導体装
置、２１は基板フレームとして供されるリードフレーム
を示し、このリードフレーム２１には、予め所要箇所
（図示の例では２箇所）に開口部が形成されており、該
開口部によってダイパッド部２２及びその周囲のリード
部２３が画定されている。また、２４はリードフレーム
２１の一方の面側（図示の例では上側）のダイパッド部
２２上に搭載された半導体素子、２５は半導体素子２４
の電極とリードフレーム２１の一方の面側のリード部２
３とを電気的に接続したボンディングワイヤ、２６は半
導体素子２４、ボンディングワイヤ２５及びリードフレ
ーム２１の一方の面側のリード部２３を覆うように形成
された封止樹脂を示す。FIG. 3 shows a sectional structure of a semiconductor device (QFN package) according to an embodiment of the present invention. In the drawing, reference numeral 20 denotes a semiconductor device according to the present embodiment, 21 denotes a lead frame provided as a substrate frame, and an opening is formed in a required portion (two portions in the illustrated example) of the lead frame 21 in advance. The die portion 22 and the lead portion 23 around the die pad portion 22 are defined by the opening. Reference numeral 24 denotes a semiconductor element mounted on the die pad portion 22 on one surface side (upper side in the illustrated example) of the lead frame 21, and reference numeral 25 denotes a semiconductor element 24.
And the lead 2 on one side of the lead frame 21
Reference numeral 26 denotes a bonding wire electrically connected to the reference numeral 3, and denotes a sealing resin formed so as to cover the semiconductor element 24, the bonding wire 25, and the lead portion 23 on one surface side of the lead frame 21.
【００１８】また、２７は本発明の特徴をなす樹脂を示
し、この樹脂２７は、リードフレーム２１の開口部に、
リードフレーム２１の厚さよりも所定の厚さｄだけ薄い
厚さでリードフレーム２１の一方の面から内側に充填さ
れている。言い換えると、リードフレーム２１の他方の
面側（図示の例では下側）のダイパッド部２２及びリー
ド部２３の露出している面は、リードフレーム２１の開
口部に充填された樹脂２７の端面からその所定の厚さｄ
だけ突出している。リード部２３の突出している部分
は、本装置２０をプリント配線板等の実装用基板に実装
する際に、はんだ等により当該基板上のランドに接合さ
れる。Reference numeral 27 denotes a resin which is a feature of the present invention.
The lead frame 21 is filled from one surface to the inside with a thickness smaller by a predetermined thickness d than the thickness of the lead frame 21. In other words, the exposed surfaces of the die pad portion 22 and the lead portion 23 on the other surface side (the lower side in the illustrated example) of the lead frame 21 are separated from the end surface of the resin 27 filled in the opening of the lead frame 21. Its predetermined thickness d
Only protruding. The protruding portion of the lead portion 23 is joined to a land on the board by soldering or the like when the device 20 is mounted on a mounting board such as a printed wiring board.
【００１９】この所定の厚さｄは、ＪＥＤＥＣ１１−５
３４によって推奨されている規定の厚さＰ（図１参照）
と同じ厚さ（０．０２ｍｍ前後）に選定されている。ま
た、リードフレーム２１の厚さは、０．１２５ｍｍ前後
に選定されている。なお、リードフレーム２１には、電
気伝導度及び熱伝導度が大きく、且つ熱膨張係数が小さ
く、プレス成形性や打ち抜き性などの加工特性が良い材
料が用いられ、代表的には銅（Ｃｕ）をベースにした合
金が好適に用いられる。The predetermined thickness d is determined by JEDEC 11-5.
The specified thickness P recommended by 34 (see FIG. 1)
And the same thickness (about 0.02 mm). Further, the thickness of the lead frame 21 is selected to be around 0.125 mm. The lead frame 21 is made of a material having high electrical conductivity and thermal conductivity, a low coefficient of thermal expansion, and good processing characteristics such as press formability and punching property. Typically, copper (Cu) is used. An alloy based on is preferably used.
【００２０】また、ボンディングワイヤ２５の材料とし
ては、典型的には金（Ａｕ）、アルミニウム（Ａｌ）な
どが用いられるが、導電性を高めるためにＣｕ線にＡｕ
の被覆を施したものを用いてもよい。また、封止樹脂２
６の材料としては、典型的には耐熱性エポキシ樹脂とシ
リカとの混合組成物が用いられるが、このエポキシ樹脂
に代えてポリイミド樹脂等の他の耐熱性樹脂を用いても
よい。リードフレーム２１の開口部に充填する樹脂２７
についても、封止樹脂２６と同様の材料が用いられる。As a material of the bonding wire 25, gold (Au), aluminum (Al), or the like is typically used.
May be used. In addition, sealing resin 2
As the material of No. 6, a mixed composition of a heat-resistant epoxy resin and silica is typically used, but another heat-resistant resin such as a polyimide resin may be used instead of the epoxy resin. Resin 27 filling opening of lead frame 21
Also, the same material as the sealing resin 26 is used.
【００２１】以下、本実施形態に係る半導体装置２０を
製造する方法について、その製造工程を順に示す図４及
び図５を参照しながら説明する。先ず最初の工程では
（図４（ａ）参照）、リードフレーム２１を形成するた
めの金属板（厚さが０．１２５ｍｍ前後で、Ｃｕをベー
スにした合金の板）を用意し、例えばプレス成形によ
り、その所要箇所にダイパッド部２２及びその周囲のリ
ード部２３を画定する開口部３０を形成する。Hereinafter, a method of manufacturing the semiconductor device 20 according to the present embodiment will be described with reference to FIGS. First, in the first step (see FIG. 4A), a metal plate (a plate of an alloy having a thickness of about 0.125 mm and based on Cu) for forming the lead frame 21 is prepared, for example, by press molding. As a result, an opening 30 defining the die pad portion 22 and the lead portion 23 around the die pad portion 22 is formed at the required location.
【００２２】さらに、このリードフレーム２１の一方の
面に、厚さが５０μｍ〜７５μｍ程度の絶縁性の樹脂フ
ィルム３１を接着剤により接着する。この樹脂フィルム
３１の材料としては、ポリイミド樹脂等の耐熱性樹脂が
好適に用いられる。なお、ここではリードフレーム２１
と樹脂フィルム３１とを接着剤により接着させている
が、予め樹脂フィルム３１の片面に接着剤が塗布された
接着性樹脂フィルムを用いてもよい。Further, an insulating resin film 31 having a thickness of about 50 μm to 75 μm is bonded to one surface of the lead frame 21 with an adhesive. As a material of the resin film 31, a heat-resistant resin such as a polyimide resin is preferably used. Here, the lead frame 21
And the resin film 31 are adhered by an adhesive, but an adhesive resin film in which an adhesive is applied to one surface of the resin film 31 in advance may be used.
【００２３】次の工程では（図４（ｂ）参照）、樹脂フ
ィルム３１が接着されたリードフレーム２１を、樹脂フ
ィルム３１が接着されている側を下にして下側の金型３
２ａの上に搭載する。また、下側の金型３２ａに対応す
る上側の金型（モールディング金型３２ｂ）は、図示の
ように所定の厚さｄに応じた凹凸面を有している。つま
り、リードフレーム２１のダイパッド部２２及びリード
部２３の各々の位置に対応する部分のモールディング金
型３２ｂの表面に、所定の厚さｄに応じた凹部が形成さ
れている。In the next step (see FIG. 4B), the lead frame 21 to which the resin film 31 is adhered is placed on the lower mold 3 with the side to which the resin film 31 is adhered down.
2a. The upper mold (molding mold 32b) corresponding to the lower mold 32a has an uneven surface corresponding to a predetermined thickness d as shown in the figure. That is, a concave portion corresponding to the predetermined thickness d is formed on the surface of the molding die 32b at a position corresponding to each position of the die pad portion 22 and the lead portion 23 of the lead frame 21.
【００２４】次の工程では（図４（ｃ）参照）、下側の
金型３２ａに樹脂フィルム３１を介して搭載されたリー
ドフレーム２１に対し、モールディング金型３２ｂによ
り、リードフレーム２１の開口部にポリイミド樹脂等の
耐熱性樹脂２７を充填しながら、約２００℃の温度で加
熱すると共に図中矢印で示すように加圧する。次の工程
では（図４（ｄ）参照）、加熱及び加圧処理が行われた
リードフレーム２１（及び樹脂フィルム３１）を金型３
２ａ，３２ｂから取り出し、樹脂フィルム３１をリード
フレーム２１から剥離して除去する。In the next step (see FIG. 4 (c)), the opening of the lead frame 21 is formed by the molding die 32b on the lead frame 21 mounted on the lower die 32a via the resin film 31. Is filled with a heat-resistant resin 27 such as a polyimide resin, and is heated at a temperature of about 200 ° C. and pressurized as indicated by an arrow in the figure. In the next step (see FIG. 4D), the lead frame 21 (and the resin film 31) on which the heat and pressure treatments have been performed are placed in the mold 3.
Then, the resin film 31 is removed from the lead frame 21 and removed.
【００２５】これによって、図示のようにダイパッド部
２２及びリード部２３の各端面がリードフレーム２１の
開口部に充填された樹脂２７の端面から所定の厚さｄだ
け突出した構造体が作製されたことになる。次の工程で
は（図４（ｅ）参照）、リードフレーム２１を上下反転
させて（つまり、ダイパッド部２２及びリード部２３の
突出している側の面を下にして）保持用の治具（図示せ
ず）で保持し、リードフレーム２１の一方の面側（図示
の例では上側）の各ダイパッド部２２上にそれぞれ半導
体素子２４を搭載する。As a result, as shown in the figure, a structure was produced in which each end face of the die pad portion 22 and the lead portion 23 protruded from the end face of the resin 27 filled in the opening of the lead frame 21 by a predetermined thickness d. Will be. In the next step (see FIG. 4E), the holding jig (see FIG. 4E) is turned upside down (ie, with the protruding surfaces of the die pad portion 22 and the lead portion 23 facing down). (Not shown), and a semiconductor element 24 is mounted on each die pad portion 22 on one surface side (upper side in the illustrated example) of the lead frame 21.
【００２６】具体的には、ダイパッド部２２にエポキシ
系樹脂等の接着剤を塗布し、半導体素子２４の裏面（電
極が形成されている側と反対側の面）を下にして、接着
剤によりダイパッド部２２に半導体素子２４を接合す
る。次の工程では（図５（ａ）参照）、各半導体素子２
４の電極をリードフレーム２１の一方の面側（図示の例
では上側）の対応する各リード部２３にそれぞれボンデ
ィングワイヤ２５により電気的に接続する。これによっ
て、半導体素子２４がリードフレーム２１に実装された
ことになる。Specifically, an adhesive such as an epoxy resin is applied to the die pad portion 22, and the back surface of the semiconductor element 24 (the surface opposite to the side on which the electrodes are formed) is turned down. The semiconductor element 24 is bonded to the die pad section 22. In the next step (see FIG. 5A), each semiconductor element 2
The four electrodes are electrically connected to corresponding lead portions 23 on one surface side (upper side in the illustrated example) of the lead frame 21 by bonding wires 25, respectively. Thus, the semiconductor element 24 is mounted on the lead frame 21.
【００２７】次の工程では（図５（ｂ）参照）、個別モ
ールディング方式により、各半導体素子２４、各ボンデ
ィングワイヤ２５及び各リード部２３を封止樹脂２６で
封止する。これは、図２（ａ）及び（ｂ）に示した方法
と同様にして行うことができる。すなわち、ダイ・ボン
ディング及びワイヤ・ボンディングが行われた後のリー
ドフレーム２１に対し、このリードフレーム２１を絶縁
性の樹脂シート３３を介して搭載する下側の金型３４ａ
と、封止樹脂２６の最終形状に応じた凹部を有する上側
の金型（モールディング金型３４ｂ）とを用いて、加熱
及び加圧しながらモールディング金型３４ｂによりリー
ドフレーム２１を単体毎に樹脂シート３３に押し込んで
封止樹脂２６を充填する。封止の手法としては、典型的
にトランスファモールドが用いられる。In the next step (see FIG. 5B), each semiconductor element 24, each bonding wire 25 and each lead 23 are sealed with a sealing resin 26 by an individual molding method. This can be performed in the same manner as in the method shown in FIGS. 2 (a) and 2 (b). That is, the lower mold 34a for mounting the lead frame 21 via the insulating resin sheet 33 with respect to the lead frame 21 after the die bonding and the wire bonding is performed.
Using the upper mold (molding mold 34b) having a concave portion corresponding to the final shape of the sealing resin 26, the lead frame 21 is separated into individual resin sheets 33 by the molding mold 34b while applying heat and pressure. To fill the sealing resin 26. As a sealing method, a transfer mold is typically used.
【００２８】そして、加熱及び加圧処理が行われたリー
ドフレーム２１（及び樹脂シート３３）を金型３４ａ，
３４ｂから取り出し、樹脂シート３３をリードフレーム
２１から剥離して除去する。最後の工程では（図５
（ｃ）参照）、ダイサー等により、破線で示すように分
割線Ｄ−Ｄ’に沿ってリードフレーム２１をそれぞれ１
個の半導体素子２４が含まれるように各パッケージ単位
に分割し、本実施形態（図３）の半導体装置２０を得
る。Then, the lead frame 21 (and the resin sheet 33) which has been subjected to the heating and pressurizing treatments is placed in a mold 34a,
The resin sheet 33 is removed from the lead frame 21 and removed. In the last step (Fig. 5
(See (c)), the lead frames 21 are each moved by a dicer or the like along the dividing line DD ′ as indicated by a broken line.
The semiconductor device 24 is divided into package units so as to include the semiconductor elements 24, thereby obtaining the semiconductor device 20 of the present embodiment (FIG. 3).
【００２９】以上説明したように、本実施形態に係る半
導体装置２０及びその製造方法によれば、リードフレー
ム２１の開口部（図４（ａ）に示す開口部３０）に、リ
ードフレーム２１の厚さよりも所定の厚さｄだけ薄い厚
さでリードフレーム２１の一方の面から内側に樹脂２７
が充填されているので、この充填された樹脂２７の端面
から見ると、リード部２３及びダイパッド部２２をその
所定の厚さｄだけ突出させることができる。As described above, according to the semiconductor device 20 and the method of manufacturing the same according to the present embodiment, the thickness of the lead frame 21 is changed to the opening of the lead frame 21 (the opening 30 shown in FIG. 4A). The resin 27 has a thickness smaller by a predetermined thickness d than the resin
Is filled, so that the lead portion 23 and the die pad portion 22 can protrude by a predetermined thickness d when viewed from the end face of the filled resin 27.
【００３０】このとき、開口部に充填された樹脂２７に
より、リード部２３とダイパッド部２２との相互の位置
関係（特に厚さ方向）は固定化されるので、リード部２
３及びダイパッド部２２の突出高さを安定に保持するこ
とができる。従って、後の工程で樹脂封止（モールディ
ング）を行ったときに、従来技術に見られたような、金
型による押しつけ圧力の差に起因してダイパッド部とリ
ード部を同じ高さに揃えることができないといった不都
合や、リード部がパッケージの裏面から傾斜して露出す
るといった不都合などが生じる可能性を排除することが
できる。これによって、本装置２０をプリント配線板等
に実装したときの信頼性を高めることが可能となる。At this time, the mutual positional relationship (particularly in the thickness direction) between the lead portion 23 and the die pad portion 22 is fixed by the resin 27 filled in the opening portion.
3 and the protrusion height of the die pad portion 22 can be stably held. Therefore, when resin molding (molding) is performed in a later step, the die pad portion and the lead portion are aligned at the same height due to the difference in the pressing pressure by the mold as seen in the related art. It is possible to eliminate the possibility of the inconvenience that the lead portion cannot be formed, or the inconvenience that the lead portion is exposed by being inclined from the back surface of the package. This makes it possible to enhance the reliability when the device 20 is mounted on a printed wiring board or the like.
【００３１】また、ダイパッド部２２の半導体素子２４
が搭載されている側と反対側の面は外部に露出している
ので、半導体素子２４で発生された熱をダイパッド部２
２を介して外部に効果的に逃すことができる。つまり、
ダイパッド部２２はヒートスプレッダとして機能し、放
熱性の向上に寄与する。上述した実施形態では、個別モ
ールディング方式を用いて半導体素子２４等の樹脂封止
を行った場合（図５（ｂ）参照）について説明したが、
樹脂封止の形態はこれに限定されないことはもちろんで
あり、これに代えて一括モールディング方式を用いても
よい。The semiconductor element 24 of the die pad portion 22
Since the surface on the side opposite to the side where is mounted is exposed to the outside, the heat generated in the semiconductor element 24 is transferred to the die pad portion 2.
2 can effectively escape to the outside. That is,
The die pad portion 22 functions as a heat spreader and contributes to an improvement in heat dissipation. In the above-described embodiment, the case where the resin sealing of the semiconductor element 24 and the like is performed using the individual molding method (see FIG. 5B) has been described.
It goes without saying that the form of resin sealing is not limited to this, and a batch molding method may be used instead.
【００３２】図６は一括モールディング方式を用いた場
合の実施形態に係る半導体装置（ＱＦＮパッケージ）の
断面的な構成を示したものである。本実施形態（図６）
に係る半導体装置２０ａは、上述した実施形態（図３）
に係る半導体装置２０と比べて、モールディング方式の
違いに起因して生じる封止樹脂２６ａの形状において相
違するのみである。他の構成（構造）については、上述
した実施形態の場合と同じであるので、その説明は省略
する。FIG. 6 shows a cross-sectional structure of a semiconductor device (QFN package) according to the embodiment when the collective molding method is used. This embodiment (FIG. 6)
The semiconductor device 20a according to the embodiment described above (FIG. 3)
The only difference is the shape of the sealing resin 26a caused by the difference in the molding method as compared with the semiconductor device 20 according to the first embodiment. Other configurations (structures) are the same as those in the above-described embodiment, and thus description thereof will be omitted.
【００３３】また、本実施形態に係る半導体装置２０ａ
の製造プロセスは、上述した実施形態の場合と基本的に
同じであり、モールディングの工程以降の工程において
相違するのみである。すなわち、上述した図４（ａ）〜
図５（ａ）の工程と同様の処理を行った後、図７（ａ）
及び（ｂ）に例示するように、ダイ・ボンディング及び
ワイヤ・ボンディングが行われた後のリードフレーム２
１に対し、このリードフレーム２１の全面（半導体素子
２４が搭載されている側と反対側の面）に絶縁性の樹脂
フィルム３３ａを貼り付けて下側の金型３５ａに搭載
し、上側の金型（モールディング金型３５ｂ）により加
熱及び加圧しながら複数個の半導体素子単位で封止樹脂
２６ａを充填し、そして、リードフレーム２１（及び樹
脂フィルム３３ａ）を金型３５ａ，３５ｂから取り出
し、樹脂フィルム３３ａをリードフレーム２１から剥離
除去した後、ダイサー等により、破線で示すように分割
線Ｄ−Ｄ’に沿ってリードフレーム２１をそれぞれ１個
の半導体素子２４が含まれるように各パッケージ単位に
分割し、本実施形態（図６）の半導体装置２０ａを得
る。The semiconductor device 20a according to the present embodiment
Is basically the same as that of the above-described embodiment, and differs only in the steps after the molding step. That is, FIG.
After performing the same processing as the step of FIG. 5A, FIG.
And (b), the lead frame 2 after the die bonding and the wire bonding are performed.
1, an insulating resin film 33a is attached to the entire surface of the lead frame 21 (the surface opposite to the side on which the semiconductor element 24 is mounted) and mounted on a lower mold 35a. The sealing resin 26a is filled in units of a plurality of semiconductor elements while heating and pressing with a mold (molding mold 35b), and the lead frame 21 (and the resin film 33a) is taken out of the molds 35a and 35b. After peeling and removing 33a from the lead frame 21, the lead frame 21 is divided into each package unit by a dicer or the like so as to include one semiconductor element 24 along the dividing line DD 'as shown by a broken line. Then, the semiconductor device 20a of the present embodiment (FIG. 6) is obtained.
【００３４】[0034]
【発明の効果】以上説明したように本発明によれば、予
めリードフレームの開口部にリードフレームの厚さより
も所定の厚さだけ薄い厚さで樹脂を充填しておくことに
より、パッケージの裏面からリード部及びダイパッド部
をその所定の厚さ分だけ安定に突出させることができ
る。これによって、本装置をプリント配線板等に実装し
たときの信頼性を向上させることが可能となり、また放
熱性の向上にも寄与することが可能となる。As described above, according to the present invention, the opening of the lead frame is previously filled with a resin having a thickness smaller than the thickness of the lead frame by a predetermined thickness, so that the back surface of the package can be filled. Therefore, the lead portion and the die pad portion can be stably protruded by a predetermined thickness. This makes it possible to improve the reliability of the device when mounted on a printed wiring board or the like, and to contribute to the improvement of heat radiation.
【図１】ＪＥＤＥＣによるＱＦＮパッケージの仕様の形
態を示す図である。FIG. 1 is a diagram showing a form of specifications of a QFN package according to JEDEC.
【図２】従来技術の一例に係るＱＦＮパッケージの問題
点の説明図である。FIG. 2 is an explanatory diagram of a problem of a QFN package according to an example of the related art.
【図３】本発明の一実施形態に係る半導体装置（ＱＦＮ
パッケージ）の構成を示す断面図である。FIG. 3 shows a semiconductor device (QFN) according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a configuration of a package.
【図４】図３の半導体装置の製造工程（その１）を示す
断面図である。FIG. 4 is a cross-sectional view showing a manufacturing step (part 1) of the semiconductor device of FIG. 3;
【図５】図４の製造工程に続く製造工程（その２）を示
す断面図である。FIG. 5 is a cross-sectional view showing a manufacturing step (part 2) following the manufacturing step in FIG. 4;
【図６】本発明の他の実施形態に係る半導体装置（ＱＦ
Ｎパッケージ）の構成を示す断面図である。FIG. 6 shows a semiconductor device (QF) according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a configuration of an (N package).
【図７】図６の半導体装置の製造工程の一部を示す断面
図である。FIG. 7 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device of FIG. 6;
２０，２０ａ…半導体装置（ＱＦＮパッケージ） ２１…リードフレーム ２２…ダイパッド部 ２３…リード部 ２４…半導体素子 ２５…ボンディングワイヤ ２６，２６ａ…封止樹脂 ２７…リードフレームの開口部に充填された樹脂 20, 20a: Semiconductor device (QFN package) 21: Lead frame 22: Die pad portion 23: Lead portion 24: Semiconductor element 25: Bonding wire 26, 26a: Sealing resin 27: Resin filled in the opening of the lead frame
Claims (5)
ってダイパッド部及びその周囲のリード部が画定された
リードフレームと、 該リードフレームの一方の面側の前記ダイパッド部上に
搭載された半導体素子と、 該半導体素子の電極と前記リードフレームの一方の面側
の前記リード部とが電気的に接続されたボンディングワ
イヤと、 前記半導体素子、前記ボンディングワイヤ及び前記リー
ドフレームの一方の面側の前記リード部が封止された樹
脂と、 前記リードフレームの開口部の一方の面側に、該リード
フレームの厚さよりも所定の厚さだけ薄い厚さで充填さ
れた樹脂とを備えてなることを特徴とする半導体装置。1. A lead frame having an opening at a required location and defining a die pad and a lead around the die pad, and the lead frame is mounted on the die pad on one surface side of the lead frame. A semiconductor element, a bonding wire electrically connected to an electrode of the semiconductor element and the lead portion on one surface side of the lead frame, and one surface of the semiconductor element, the bonding wire and the lead frame. And a resin filled on one surface side of the opening of the lead frame with a predetermined thickness smaller than the thickness of the lead frame. A semiconductor device, comprising:
画定する開口部を有する単位リードフレームが複数個連
結されたリードフレームを形成する工程と、 前記リードフレームの開口部の一方の面側に、該リード
フレームの厚さよりも所定の厚さだけ薄い厚さで樹脂を
充填する工程と、 前記リードフレームの一方の面側の各ダイパッド部上に
それぞれ半導体素子を搭載する工程と、 前記各半導体素子の電極と前記リードフレームの一方の
面側の対応する各リード部とをそれぞれボンディングワ
イヤにより電気的に接続する工程と、 前記各半導体素子、前記各ボンディングワイヤ及び前記
リードフレームの一方の面側の各リード部を封止樹脂に
より封止する工程と、 前記各半導体素子が搭載されたリードフレームをそれぞ
れ１個の半導体素子が含まれるように各半導体装置に分
割する工程とを含むことを特徴とする半導体装置の製造
方法。2. A step of forming a lead frame in which a plurality of unit lead frames each having an opening defining a die pad portion and a lead portion around the die pad portion are connected, and one surface side of the opening portion of the lead frame. A step of filling the resin with a thickness smaller by a predetermined thickness than the thickness of the lead frame; a step of mounting a semiconductor element on each die pad portion on one surface side of the lead frame; Electrically connecting the respective electrodes and the corresponding lead portions on one surface side of the lead frame by bonding wires, respectively; and the semiconductor devices, the bonding wires, and the one surface side of the lead frame. A step of sealing each lead portion with a sealing resin; and a step of sealing the lead frame on which each of the semiconductor elements is mounted with one semiconductor element. The method of manufacturing a semiconductor device which comprises a step of dividing to the respective semiconductor devices be included.
厚さに応じた凹凸面を有する金型を用い、加熱及び加圧
して行うことを特徴とする請求項２に記載の半導体装置
の製造方法。3. The semiconductor device according to claim 2, wherein the step of filling the resin is performed by heating and pressing using a mold having an uneven surface corresponding to the predetermined thickness. Production method.
個の半導体素子単位で行うことを特徴とする請求項２に
記載の半導体装置の製造方法。4. The step of sealing with the sealing resin comprises:
3. The method according to claim 2, wherein the method is performed for each semiconductor element.
数個の半導体素子単位で行うことを特徴とする請求項２
に記載の半導体装置の製造方法。5. The method according to claim 2, wherein the step of sealing with the sealing resin is performed for a plurality of semiconductor elements.
13. The method for manufacturing a semiconductor device according to item 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000277978A JP2002093982A (en) | 2000-09-13 | 2000-09-13 | Semiconductor device and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000277978A JP2002093982A (en) | 2000-09-13 | 2000-09-13 | Semiconductor device and manufacturing method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002093982A true JP2002093982A (en) | 2002-03-29 |
Family
ID=18763210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000277978A Withdrawn JP2002093982A (en) | 2000-09-13 | 2000-09-13 | Semiconductor device and manufacturing method therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002093982A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002110884A (en) * | 2000-10-02 | 2002-04-12 | Nitto Denko Corp | Lead frame laminate |
| US6710246B1 (en) | 2002-08-02 | 2004-03-23 | National Semiconductor Corporation | Apparatus and method of manufacturing a stackable package for a semiconductor device |
| US6723585B1 (en) * | 2002-10-31 | 2004-04-20 | National Semiconductor Corporation | Leadless package |
| JP2004214233A (en) * | 2002-12-26 | 2004-07-29 | Renesas Technology Corp | Semiconductor device and manufacturing method therefor |
| JP2007531310A (en) * | 2004-04-02 | 2007-11-01 | フェアチャイルド セミコンダクター コーポレイション | Surface-mount multichannel optical coupling device |
| JP2007294637A (en) * | 2006-04-25 | 2007-11-08 | Denso Corp | Method for manufacturing semiconductor device |
| JP2008166417A (en) * | 2006-12-27 | 2008-07-17 | Shinko Electric Ind Co Ltd | Lead frame, its manufacturing method, and semiconductor device |
| US7432583B2 (en) | 2003-01-22 | 2008-10-07 | National Semiconductor Corporation | Leadless leadframe package substitute and stack package |
| JP2014154689A (en) * | 2013-02-07 | 2014-08-25 | Seiko Instruments Inc | Semiconductor device |
-
2000
- 2000-09-13 JP JP2000277978A patent/JP2002093982A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002110884A (en) * | 2000-10-02 | 2002-04-12 | Nitto Denko Corp | Lead frame laminate |
| US6710246B1 (en) | 2002-08-02 | 2004-03-23 | National Semiconductor Corporation | Apparatus and method of manufacturing a stackable package for a semiconductor device |
| US6723585B1 (en) * | 2002-10-31 | 2004-04-20 | National Semiconductor Corporation | Leadless package |
| JP2004214233A (en) * | 2002-12-26 | 2004-07-29 | Renesas Technology Corp | Semiconductor device and manufacturing method therefor |
| US7432583B2 (en) | 2003-01-22 | 2008-10-07 | National Semiconductor Corporation | Leadless leadframe package substitute and stack package |
| JP2007531310A (en) * | 2004-04-02 | 2007-11-01 | フェアチャイルド セミコンダクター コーポレイション | Surface-mount multichannel optical coupling device |
| JP2007294637A (en) * | 2006-04-25 | 2007-11-08 | Denso Corp | Method for manufacturing semiconductor device |
| JP2008166417A (en) * | 2006-12-27 | 2008-07-17 | Shinko Electric Ind Co Ltd | Lead frame, its manufacturing method, and semiconductor device |
| JP2014154689A (en) * | 2013-02-07 | 2014-08-25 | Seiko Instruments Inc | Semiconductor device |
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