TWI236716B - Window ball grid array semiconductor package with substrate having opening and method for fabricating the same - Google Patents
Window ball grid array semiconductor package with substrate having opening and method for fabricating the same Download PDFInfo
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- TWI236716B TWI236716B TW093104217A TW93104217A TWI236716B TW I236716 B TWI236716 B TW I236716B TW 093104217 A TW093104217 A TW 093104217A TW 93104217 A TW93104217 A TW 93104217A TW I236716 B TWI236716 B TW I236716B
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- substrate
- wafer
- opening
- item
- gap
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Links
- 239000000758 substrate Substances 0.000 title claims abstract description 200
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 41
- 239000011347 resin Substances 0.000 claims abstract description 37
- 229920005989 resin Polymers 0.000 claims abstract description 37
- 239000000853 adhesive Substances 0.000 claims abstract description 29
- 230000001070 adhesive effect Effects 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 26
- 229910000679 solder Inorganic materials 0.000 claims abstract description 23
- 238000005538 encapsulation Methods 0.000 claims abstract description 15
- 239000000084 colloidal system Substances 0.000 claims description 40
- 125000006850 spacer group Chemical group 0.000 claims description 40
- 238000004806 packaging method and process Methods 0.000 claims description 23
- 239000008393 encapsulating agent Substances 0.000 claims description 13
- 238000000465 moulding Methods 0.000 claims description 11
- 238000007639 printing Methods 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 7
- 239000002245 particle Substances 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 4
- 239000011800 void material Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 239000003795 chemical substances by application Substances 0.000 claims 2
- 101100433727 Caenorhabditis elegans got-1.2 gene Proteins 0.000 claims 1
- 239000004840 adhesive resin Substances 0.000 claims 1
- 229920006223 adhesive resin Polymers 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 44
- 238000003466 welding Methods 0.000 description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- SUDBRAWXUGTELR-HPFNVAMJSA-N 5-[[(2r,3r,4s,5s,6r)-3,4,5-trihydroxy-6-(hydroxymethyl)oxan-2-yl]oxymethyl]-1h-pyrimidine-2,4-dione Chemical compound O[C@@H]1[C@@H](O)[C@H](O)[C@@H](CO)O[C@H]1OCC1=CNC(=O)NC1=O SUDBRAWXUGTELR-HPFNVAMJSA-N 0.000 description 1
- 241000251468 Actinopterygii Species 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000002757 inflammatory effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000001356 surgical procedure Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
1236716 五、發明說明（1) 【發明所屬之技術領域】 而本發明係有關一種半導體封裝件及其製法，尤指一種 開1型球柵陣列（window ball grid array，WBGA)半導體 孔攻件—以使晶片接置於基板上且遮覆貫穿該基板之開 並藉夕數穿通於該開孔中之録線電性連接該晶片至基 反’以及一種製造該半導體封裝件之方法。 【先前技術】 半導體封裝件係一種承載有如半導體晶片等之主 牛的電子裝置，其結構主要使至少一晶片接置於美 數=銲線等之導電元件電性連接至該基：，且： 可包括多數呈陣列方4 1所铋害。该半導體封裝件復 盆盥接执右ΐ ϋ 的銲球植設於基板的另—側， 俨封梦Γ f Γ片/、1干線的一側相對。此種具有銲球之丰、曾 =裝件稱為球栅陣列（ball grld array，BGA)2:導 f銲球作為輸入/輸出（input/output，1/0〕端，2件， :二言二封裝件中之晶片得與外界裝置如印刷電路：之以 體封裝:之%1!11^括brrd，PCB)成電性連接關係。惟半暮 度、基板厚：：i銲球：ί U f銲線之封裝膠體的厚 -步縮小。 ”“度，而使整體封裝件尺寸難以： 為能有效縮小半導體封裝 型（window-type)封裝件，以使用且 :盆—種開窗 基板為名。第4F圖即顯示知門/牙 ' 中之開孔的 裡白夫開自型球栅陣列封穿1236716 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly to a type 1 window ball grid array (WBGA) semiconductor hole tapping device— The chip is placed on the substrate and covers the opening through the substrate, and the recording wire passing through the opening is electrically connected to the chip to the substrate, and a method for manufacturing the semiconductor package. [Previous technology] A semiconductor package is an electronic device that carries a main device such as a semiconductor wafer. Its structure mainly makes at least one chip be electrically connected to a conductive element such as a US $ = bonding wire and so on: and: It can include most of the bismuth in the array. The solder balls of the semiconductor package are mounted on the other side of the substrate, and the side of the seal Γ f Γ sheet / 1 is opposite. This kind of solder ball has been called a ball grld array (BGA) 2: the f solder ball is used as the input / output (input / output, 1/0) end, 2 pieces, two The chip in the second package must be electrically connected to an external device such as a printed circuit: the body package:% 1! 11 (including brrd, PCB). However, at half-time, the thickness of the substrate: i solder ball: the thickness of the encapsulation gel of the U f wire is reduced in steps. "", Which makes the overall package size difficult: In order to effectively reduce the size of the semiconductor package (window-type) packages, the use of: and pot-a kind of window substrate. Figure 4F shows the opening of the Li Baifu open-type ball grid array in Zhimen
17436 聯測.ptd 第6頁 1236716 五、發明說明（2) >^十 5 士口 |^| 戶斤 - “ AA ^ ，不’ ~半導體晶片1 1藉膠黏劑1 2接置於基板1 〇 的上表面1〇〇上且诫 缸介、s<復基板1 〇之開孔1 0 2。該晶片11並藉多 面W開孔1 〇 2中之銲線1 3電性連接至基板1 0的下表 面101。同時，曰ρ 44壯_躺t Γ日日片1 1與鮮線1 3分別為上封裝膠體1 4及下 1 ί) ΐ\ Ί :包覆’且多數銲球1 6植設於基板1 0下表面 \ /下封農膠體15之區域。 驟制ΐ述開窗型球拇陣列封裝件得以第4A至4F圖之製程步 鄉製付。 W、a I先如第4Α圖所示（上視圖及沿4Α-4Α線切開所示之 -,n Q ^ ^ 由夕數基板1 〇組成之基板片1 ’其中各基 攸J· u具有一書空甘上 呈古- m h /、中之開孔ί 0 2 ’該開孔1 ο 2較佳呈矩形， :彳_κ 乂長側邊及二相對較短側邊。接著，進行一置 曰制ρ φ ding)製程及銲線（wire_b〇nding)作業。於置 # ^ , nnu ^ 曰曰片1 1精膠黏劑1 2接置於各基板1 〇之上17436 联 测 .ptd Page 6 1236716 V. Description of the invention (2) > ^ Ten 5 Shikou | ^ | Household catties-"AA ^, no '~ semiconductor wafer 1 1 by adhesive 1 2 connected to the substrate The upper surface of 10 is 100, and the cylinder 1 and the s < composite substrate 1 10 are open holes 102. The wafer 11 is electrically connected to the substrate by the bonding wires 1 3 in the multi-faceted W openings 102. 10 Lower surface 101. At the same time, ρ 44 Zhuang_lie t Γ Japanese and Japanese film 1 1 and fresh line 1 3 are the upper encapsulation gel 1 4 and the lower 1 ί) ΐ \ Ί: coating 'and most solder balls 1 6 is placed on the lower surface of the substrate 10 // lower the agricultural colloid 15 area. The window-type ball-thumb-array package can be fabricated in steps shown in Figures 4A to 4F. W, a I first As shown in Fig. 4A (the top view and the cut along the line 4A-4A are shown as-, n Q ^ ^ a substrate sheet 1 'composed of a number of substrates 1 〇, where each base J · u has a book empty on top Chenggu-mh /, the opening in the middle 0 2 'The opening 1 ο 2 is preferably rectangular,: 彳 _κ 乂 long side and two relatively short sides. Next, a set of system ρ φ ding) process and wire_bonding operation. # ^, nnu ^ 1 on a fine bonding adhesive 12 placed on each substrate 1 billion
表面1 0 0上並遮覆兮I paa ; n9+ — ^旻々基板1 0之開孔1 02，該膠黏劑1 2敷設於 J 1Λ9 —二較長側邊，而於晶片11與基板1 0之間位於開 之一 乂短側邊處存留有未有膠黏劑1 2填充的空隙G。 ^ 4 ，於鲜線作業中，形成多數穿通於各基板丨〇之開孔 1 02中的銲線1 3 ’用以電性連接晶片丨丨至對應基板丨〇之下 表面1 0 1。 如第4B圖所示（下視圖及沿4B-4B線切開所示之剖視 圖）’製備一封裝模具，具有一上模丨7及一下模i 8，該上 模1 7形成有一向上凹陷空穴1 70，而該下模丨8形成有多數 向下凹陷空穴1 80各對應至一列基板丨〇之開孔1 〇2。該向上The surface 1 0 0 covers the surface I paa; n9 + — ^ 旻 々 the opening 1 02 of the substrate 10, the adhesive 12 is laid on J 1Λ9 — the two longer sides, and the wafer 11 and the substrate 1 There is a gap G between 0 and 0 on the short side of the opening which is not filled with the adhesive 12. ^ 4, in the fresh line operation, a plurality of bonding wires 1 3 ′ formed in the openings 10 of each substrate 丨 are formed to electrically connect the chip 丨 to the lower surface 101 of the corresponding substrate 〇. As shown in FIG. 4B (bottom view and cross-sectional view taken along line 4B-4B), a packaging mold is prepared, which has an upper mold 7 and a lower mold i 8, and the upper mold 17 is formed with an upward recessed cavity. 1 70, and the lower die 8 is formed with a plurality of downwardly recessed holes 1 80 each corresponding to an opening 10 of a row of substrates 0 0. Should go up
17436聯測.ptd17436 United Test.ptd
1236716 ---------------- 五、發明說明（3) ~ --- 凹陷空穴1 70之尺寸足以收納所有接置於基板丨〇上之晶片 1 1。各向下凹陷空六；1 80之尺寸覆蓋住該對應列之所^基 板1 0^孔1 〇 2並容納突出於基板1 〇下表面1 〇 1上的銲線1 3線 弧°亥封裝模具觸接至基板片1上，以使上模1 7接置於基 板1〇之上表面1〇〇上，而下模18接置於基板1〇之下表面 =:4C圖所示（沿二相互垂直線切開所示之剖視圖）， 氣=二模壓（m〇lding)作業，將一習知樹脂材料（如環 二ΐ入夂下模18之向下凹陷空穴180中以形成多數下封 15’各下封裝膠體15填充於對應列之開孔102並包 ί ΐί 線13,而位於晶片11與基板10間之空隙G往往 …法兀王為该樹脂材料所填滿。 J後如第4 D圖所示，進行一第二模壓作業，將兮妙 ΐ ΐ17之向上凹陷空穴170中以形成、-上封V i =包覆所有接置於基板10上的晶片11。 u及ΐίίΓ及第二模壓作業後，自基板片1上移除上模 區：：ί板10之下表面1上未為下封裝膠體 …上^^所域^’二多^^求^於基板^之下表面 業，切割上封裝膠辦14其士 切早（singulation)作 一晶片η及多數銲球16，第具有早離之基板i〇、1236716 ---------------- V. Description of the invention (3) ~ --- The size of the recessed cavity 1 70 is sufficient to accommodate all the wafers 1 1 placed on the substrate. Each of the downward recesses is empty; the size of 1 80 covers the corresponding column of the substrate 1 0 ^ hole 1 0 2 and accommodates the bonding wires protruding on the lower surface 1 0 1 of the substrate 1 3 line arc ° Hai package The mold is in contact with the substrate sheet 1 so that the upper mold 17 is placed on the upper surface 100 of the substrate 10, and the lower mold 18 is placed on the lower surface of the substrate 10 == 4C Two cross-sections are shown by cutting perpendicular to each other), gas = two moulding operation, a conventional resin material (such as ring two into the hollow cavity 180 of the lower mold 18 to form a majority of the bottom Each of the seals 15 ′ is filled with the openings 102 in the corresponding rows and covered with the 13 ΐί line 13, and the gap G between the wafer 11 and the substrate 10 is often ... the King Wuwu is filled with the resin material. As shown in FIG. 4D, a second molding operation is performed to form the upward recessed cavity 170 of Xi Miaoΐ ΐ17 to form,-seal V i = cover all the wafers 11 placed on the substrate 10. u and After the upper mold and the second molding operation, the upper mold area is removed from the substrate sheet 1: The lower surface 1 of the lower plate 10 is not a lower encapsulating gel ... The upper region ^ 'two more ^^ ^ ^ Industry under the surface, cutting the packaging adhesive 14 do Chevalier cut early (singulation) η as a wafer and a plurality of solder balls 16, on a substrate from the early i〇,
17436 聯測.Ptd 1236716 五、發明說明（4) 然而’上述半導體封裝件之製法會產生諸多缺點。其 一為切割遮覆於各列基板之開孔的下封裝膠體時，由於下 封裝膠體與基板以不同材料製成，下封裝膠體與基板邊緣 交界部分會承党極大應力而易產生脫層（deiaminati〇n)。 再者’下模之向下凹陷空穴的尺寸需隨基板開孔之尺寸而 變化以使該向下凹陷空穴能完全覆蓋住該開孔且不會遮覆 到基板上預定用以植設銲球之區域。換言之，當使用具有 不同尺寸開孔之基 之向下凹陷空穴， 程需分二階段進行 用以填充基板開孔 上封裝膠體用以包 程更為複雜，且易 之第一模壓作業中 方之區域往往缺乏 箝制住，因而使注 經由開孔邊緣漏出 脂溢膠可能會污染 域，而使銲球無法 半導體封裝件之信 板開孔之較短側邊 滿’易使氣洞殘留 ^，使封裝件結構 脂材料時會產生極 板時，需製備新的下 故會大幅增加生產成 ，包括第一模壓作業 及包覆銲線，以及第 覆晶片。該二階段之 造成樹脂溢膠問題。 ’基板下表面上圍繞 來自上模之支撐而^ 入下模之向下凹陷空 或溢膠至該難以穩固 基板下表面上預定_ 穩固地銲接或電性連 賴性。另外，位於晶 處的空隙通常無法完 於該空隙中而導致氣 受損。注入下模之$ 大模流衝擊而造成金旱 模開設有適合尺寸 本。此外，模壓製 以形成下封裝膠體 二模壓作業以形成 模壓作業不僅使製 於形成下封裝膠體 開孔且位於晶片下 法為封裝模具穩固 穴中的樹脂材料易 箝制住的區域。樹 以植設銲球之區 接至基板，而有損 片與基板之間且基 全為樹脂材料所填 爆（P〇pc〇rn)現 下凹陷空穴中的樹 線偏移及相鄰銲線17436 Joint test. Ptd 1236716 V. Description of the invention (4) However, the method of manufacturing the above-mentioned semiconductor package will have many disadvantages. One is to cut the lower packaging colloid covering the openings of the substrates in each row. Because the lower packaging colloid and the substrate are made of different materials, the boundary between the lower packaging colloid and the substrate edge will be subject to extreme stress and easy to delaminate deiaminati〇n). Furthermore, the size of the downwardly recessed cavity of the lower mold needs to change with the size of the opening of the substrate so that the downwardly recessed cavity can completely cover the opening and not cover the substrate. The area of the solder ball. In other words, when using a downwardly recessed cavity with a base having different sizes of openings, the process needs to be performed in two stages to fill the encapsulating gel on the substrate openings to cover the process, which is more complicated and easier. The area is often lack of clamping, so that the leakage of grease through the edge of the opening may contaminate the area, making the solder ball unable to fill the short side of the opening of the letter board of the semiconductor package, which easily causes air holes to remain ^, When a polar material is generated when the package is made of a structural fat material, it is necessary to prepare a new structure, which will greatly increase the production, including the first molding operation and the covered wire, and the second wafer. This two-stage problem caused resin overflow. ’The lower surface of the substrate surrounds the support from the upper mold and the bottom of the lower mold is recessed or overflows to the difficult-to-stabilize lower surface of the substrate. Predetermined _ stable soldering or electrical reliability. In addition, the voids at the crystals usually cannot be completed in the voids, resulting in gas damage. Injecting the lower mold with a large mold flow impact caused the golden dry mold to be opened with a suitable size. In addition, molding to form the lower packaging colloid. Second molding operation to form the molding operation not only makes the resin material in the cavity where the lower packaging colloid openings are formed and is located in the stable cavity of the packaging mold under the wafer. The tree is connected to the substrate with the area where the solder ball is planted, and the tree line in the depression cavity and the adjacent welding are popped between the damaged sheet and the substrate and the base is filled with resin material (P0pc). line
1236716 於提供 壓製程 樹脂流 產生過 於長1供 板之開 裝膠體 象。 於提供 整合封 因而增1236716 In the process of providing the resin, the resin flow produced an over-long 1-sheet opening gel image. Increase in the provision of integrated closures
17436聯測.ptd ’更降低半導體封裝件之信賴 種WBGA半導體封裝件得以解決上 止樹脂溢膠、避免銲線偏移、及 性，實為重要課題。 提供一種開窗型球栅陣列半導體 平坦下模及一成本低之間隔件 (〇 n e - s t e ρ)之模壓製程，該間隔 開孔之基板，故得有效較低生產 五、發明說明（5) 間之接觸，導致短路現象 性。 因此’如何發展出_ 述缺點而能避免脫層、防 降低生產成本與製程複雜 【發明内容】 本發明之一目的在於 封裝件及其製法，使用一 (s p a c e r )以進行單一步驟 件可適用於具有各種尺寸 成本及簡化製程。 本發明之另一目的在 體封裝件及其製法，於模 隙作為樹脂模流通道以供 開孔中，因而不會對銲線 線偏移及樹脂溢膠。 本發明之又一目的在 體封裝件及其製法，各基 充，故不需再對該單獨封 免脫層（delamination)現 本發明之又一目的在 體封裝件及其製法，使一 及填充於基板之開孔中， 度。 一種開窗型球柵陣列半導 中’晶片與基板之間的空 入該空隙而填充於基板: 度模流衝擊，故能避免鲜 一種開窗型球柵陣列半 孔中為單獨封裝膠體所 進行切割或分離，而能避 一種開窗型球柵陣列17436 joint test.ptd ’reduced the reliability of semiconductor packages. This kind of WBGA semiconductor package is an important issue to solve the problem of resin overflow, avoiding wire offset, and reliability. Provided is a window-type ball grid array semiconductor flat lower mold and a low-cost spacer (One-ste ρ) molding process, the space-opening substrate, so that the production can be effectively lowered. 5. Description of the invention (5) Contact between them, resulting in a short circuit phenomenon. Therefore, how to develop the disadvantages described above can avoid delamination, reduce production costs, and reduce the complexity of the process. [Summary of the Invention] One object of the present invention is to provide a package and a method for making the same. Available in various size costs and simplified processes. Another object of the present invention is a body package and a method for manufacturing the same. The mold gap serves as a resin mold flow path for openings, so that the welding line does not shift and the resin overflows. Another object of the present invention is a body package and a method for manufacturing the same, each base being filled, so there is no need to delaminate the separate seal. Another object of the present invention is a body package and a method for manufacturing the same Fill in the openings of the substrate. A window-type ball grid array semiconductor is used to fill the gap between the wafer and the substrate and fill the substrate: a degree of mold flow impact, so it is possible to avoid a kind of window-type ball grid array half-holes that are individually encapsulated by colloids. Cut or separate while avoiding a windowed ball grid array
裝膠體包覆晶片與銲V 進半導體封裳件之她Y以 戒仵之機蜮強 第10頁 1236716 五、發明說明（6) 本發明之又一目的在於接板 滅私姑从 …上、口 1、一種開窗型球栅陣列半導 體封裝件及其製法，形成另一圭+壯n .^ 甘上0日， 封裳膠體以改善用以包覆晶 片14隹干線並填充於基板開孔中夕 #蓋*^ ⑺力曰細〜^ 之整合封裝膠體的外觀使其 元美並進一步確保知線付元全兔』 n ^ 馬封裝膠體所包覆。 為達成上揭及其他目的，太a 他加屯、# ^ ^ 本發明揭露一種開窗型球柵 息七：士 ^ ^ 暴板，具有一上表面及一相 對之下表面，並開設有一貫穿复士 ..^ ^ ^ , 牙其中之開孔；至少一晶片， ^ .s ^ ^ ^ $上表面且遮覆該開孔，並藉多 數牙通於該開孔中之銲線電性造 冰分曰u β日士/ 運接至該基板之下表面，而 使δ亥曰日片與基板之間存留有未炎 ^ a ill ^ ^ ^ ^ 禾為该膠黏劑所填充之空隙； 一以树月日材料製成之弟一模壓4+ μ^ ^ ^ 愛封震膠體，形成於該基板之 上下表面上，用以包覆該晶片 人 7. ^ a u Λ ^ ^ ΛΛ ^ 及1干線’其中該樹脂材料流 入該曰曰片與基板之間的空隙而埴 τ 隙中卜第二非模壓製成之封該基板之開孔及該空 裝膠體形成於基板下表面上；二體:用以包覆該第一封 於該基板之下表面上未形成有;=，以及多數銲球，植設 露。 乂有§亥弟二封裝膠體的區域並外 上揭開窗型球柵陣列半導 方式而由下述製程步驟製得，勺缸羞件可以批次（batch) 之基板片，各該基板且有一 ^ •製備一包括多數基板 設有一貫穿其中之開i;养一相對之下表面並開 該基板之上表面上且遮覆^門^-蜊接置至少一晶片於各 存留有未為該膠黏劑所填^ ^处隙而使該晶片與基板之間 基板之開孔中的輝，線，以上：成多數穿通於各該 &線電性連接該晶片至該基She is equipped with colloid-coated wafers and soldered. She is stubborn in the semiconductor package. Page 10 1236716 V. Description of the invention (6) Another object of the present invention is to connect the board and destroy the uncle from the upper and lower mouths. 1. A window-type ball grid array semiconductor package and a method for forming the same, forming another Gui + Zhuang n 0. On the 0th, sealing the colloid to improve the 14 mm trunk line used to cover the wafer and fill the opening in the substrate.夕 # 盖 * ^ The appearance of the integrated encapsulation colloid of ⑺ 力 曰 ^ ~ ^ makes it Yuanmei and further ensures that the line of attention is covered by the encapsulation colloid. In order to achieve the above disclosure and other purposes, the present invention discloses a window-type ball grid. Seven: Shi ^ ^ storm plate, which has an upper surface and a relatively lower surface, and is provided with a through Fu Shi .. ^ ^ ^, the opening in the tooth; at least one chip, ^ .s ^ ^ ^ $ The top surface and the opening are covered, and the majority of the teeth pass through the welding wires in the opening to make electrical The ice content u β sunshi / transported to the lower surface of the substrate, so that there is a non-inflammatory ^ a ill ^ ^ ^ ^ between the δHai sun plate and the substrate; the gap filled by the adhesive; A younger brother made of the material of the tree and the sun is a molded 4+ μ ^ ^ ^ love seal shock colloid formed on the upper and lower surfaces of the substrate to cover the chip person 7. ^ au Λ ^ ^ ΛΛ ^ and 1 The main line is in which the resin material flows into the gap between the film and the substrate, and in the gap, a second non-molded opening for sealing the substrate and the empty gel are formed on the lower surface of the substrate; the two bodies : Used to cover the first seal on the lower surface of the substrate; not formed; and most solder balls, planting dew. §Haidi's second encapsulation area and the window-type ball grid array semiconducting method are opened and prepared by the following process steps. The scoop can be a batch of substrate pieces. There is a ^ • preparation of a substrate including a plurality of substrates provided with an opening through it; raising a relatively lower surface and opening the upper surface of the substrate and covering the door ^-clams are placed at least one wafer in each The gap filled by the adhesive causes the glow, wire, and above in the opening of the substrate between the chip and the substrate: a majority of the & wires are electrically connected to the chip to the base
ms 17436聯測.ptd 第11頁 1236716 具有多數通孔之間隔 面上’其中各該通孔 間隔件之厚度大於該 度’以使形成於各該 孔及對應的基板開孔 形成一第一封裝膠體 材料注入該多數基板 且該晶片與基板之間 隔件之通孔及該空隙 該間隔件，而使該形 設多數銲球於各該基 區域並外露；形成一 覆该第一封裝膠體形 多數銲球於各該基板 的區域並外露；以及 面上的部分以及該基 別的半導體封裝件各 五、發明說明（7) 板之下表面；製備一 隔件至該基板之下表 該基板之開孔，且該 之下表面上的線弧高 納於對應的間隔件通 製程，藉一樹脂材料 表面上，以使該樹脂 覆5亥晶片並流入該’ 該基板的開孔、該間 線；自該基板上移除 一封裝膠體露出；植 形成有該封裝膠體的 之封裝膠體，用以包 表面上的部分；植設 成有該第二封裝膠體 膠體形成於基板上表 基板，而形成多數個 板0 件，並接置該間 對應於並大於各 銲線突出於基板 晶片上的銲線收 中；進行一模壓 於該基板之上下 之上表面上而包 的空隙以填充於 中且包覆該銲 成於基板上之第 _ 板之下表面上未 第二非模壓製成 成於各該基板下 之下表面上未形 切割該第一封裝 板片以分離各該 具有一單離之基 上述半導體封裝件及复ms 17436 联 测 .ptd Page 11 1236716 The spacer surface with most through holes 'wherein the thickness of each of the through-hole spacers is greater than the degree' so that a first package is formed in each of the holes and the corresponding substrate opening. Colloidal material is injected into the majority of the substrate and the through holes of the spacer between the wafer and the substrate and the gap and the spacer, so that the plurality of solder balls are formed at each of the base regions and exposed; forming a colloidal majority covering the first package Solder balls are exposed on the area of each substrate; and the surface part and the semiconductor package of the base each. 5. Description of the invention (7) The lower surface of the board; prepare a spacer to the substrate below the substrate A hole is formed, and the line arc on the lower surface is higher than the corresponding spacer pass process, by borrowing a resin material on the surface, so that the resin is covered with a 5 Hai wafer and flows into the opening of the substrate, the line Removing a packaging colloid from the substrate to expose it; planting the packaging colloid with the packaging colloid to cover a portion on the surface; planting the second packaging colloid colloid formed on the surface of the substrate, and shaped A large number of 0 boards are placed in parallel, and the space corresponding to and larger than each welding line protruding on the substrate wafer is retracted; a mold is pressed on the upper and lower upper surfaces of the substrate, and the gap is wrapped to fill in the middle And the second package which is welded and formed on the lower surface of the substrate is not second non-molded, and the first package plate is not cut on the lower surface of each substrate to separate each of them. Lifting the above semiconductor package and complex
與基板之間及基板開孔夕”製法具有诸夕優點。位於 空隙，係供用以形成扭ΐ二較短側邊處未敷設有膠黏； 該樹脂材料注入上槿夕Ϊ膠體之樹脂材料流通的通道 基板開孔中並包覆銲綠二穴中時，其流入該空隙而填〕The method of making holes with the substrate and opening the substrate has various advantages. It is located in the gap and is used to form the short side of the torsion. The glue is not applied at the short side. When the channel substrate is opened in the hole and covered with the solder green cavity, it flows into the gap and fills it]
充，因而避免習知氣洞或隙亦為該，旨材I 4氧爆現象。因此，流入空P.、_Charge, so to avoid the known air holes or gaps, this is the purpose of I 4 oxygen explosion phenomenon. Therefore, the inflow of empty P., _
第12頁 1236716 (8) 會對銲 現象。 較不會 膠體的 具有通 使間隔 該通孔 造成本 具有對 因此， 一整合 基板開 裝膠體 成於基 基板間 成之封 面上的 完全為 印刷技 式】 五、發明說明 脂模流不 移或短路 擊或壓力 成有封裝 外，使用 尺寸，而 模之間。 隔件之製 時，可用 產成本。 基板。藉 及填充於 度。該封 或切單形 裝膠體與 非模壓製 基板下表 確保銲線 知點膠或 本 〇 【實施方 線產生過 再者，由 經開孔邊 區域，故 孔之間隔 件箝制於 中亦填充 低，故當 應尺寸之 該平坦下 封裝膠體 孔中，故 分別填充 板下表面 產生脫層 裝膠體， 部分，以 封裝膠體 術製成而 度衝擊或壓力，而 於降低脂模流衝擊 緣而溢膠至基板下 能確保製成封裝件 件，該通孔尺寸對 基板下表面與具有 有該包覆銲線之樹 使用開設有不同尺 通孔的間隔件而不 模配合適當間隔件 (第一封裝膠體）包 能增進半導體封裝 於各基板之開孔中 上的封裝膠體部分 (de 1 am i nat i on)° 用以包覆第一封裝 改善封裝件之外觀 所包覆；該第二封 不會大幅增加製程 能避免銲線偏 或壓力，該衝 表面上不需形 之信賴性。另 應基板開孔之 平坦表面的下 脂材料。該間 寸開孔之基板 會大幅增加生 可適用於各種 覆晶片與銲線 件之機械強 ’故不需切割 ，故可避免封 此外，一第二 膠體形成於各 使其完美並能 裝膠體係以習 複雜性及成 以下係藉由特定的具體實例說明本發明之實施方式， 熟悉此技藝之人士可由本說明書所揭示之内容輕易地瞭解 本發明之其他優點與功效。本發明亦可藉由其他不同的具Page 12 1236716 (8) Butt welding phenomenon. The colloid is less likely to have a gap so that the through holes cause the pair to have the correct pair. Therefore, an integrated substrate is assembled with a gel formed on the cover formed between the base substrates. It is entirely a printing technique. Short-circuited or pressured into the package outside, use dimensions while between molds. When manufacturing the spacer, the available production cost. Substrate. Borrow and fill in degrees. The sealed or cut single-shaped gel and non-molded substrate are as shown in the table below to ensure that the welding wire is known to be dispensed or printed. [The square wire has been produced again. It is filled by the edge area of the hole, so the spacer of the hole is clamped in the middle and filled. Low, so when the size of the flat lower encapsulation colloid hole should be sized, the lower surface of the plate is filled separately to produce delaminated colloid. Part of it is made by encapsulation colloid surgery to reduce impact or pressure, and to reduce the impact edge of the fat mold flow. Spilling glue under the substrate can ensure that the package is made. The size of the through-hole uses a spacer with different through-holes for the lower surface of the substrate and the tree with the covered bonding wire without the proper spacer (section A packaging gel) package can enhance the packaging gel portion (de 1 am nat i on) of the semiconductor package in the opening of each substrate, and is used to cover the first package to improve the appearance of the package; the second Sealing does not greatly increase the manufacturing process, which can avoid welding line bias or pressure, and does not require form reliability on the punched surface. It should also be greased on the flat surface of the substrate opening. The substrate of this inch opening will greatly increase the mechanical strength applicable to various wafer-covered and wire-bonding parts, so it does not need to be cut, so it can avoid sealing. In addition, a second gel is formed on each to make it perfect and can be glued. The system's complexity and accomplishment are described below by way of specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented by other different tools.
17436聯測.ptd 第13頁 123671617436 joint test.ptd page 13 1236716
五、發明說明（9) 體實例加以施行式座田 丄 & .V. Description of the Invention (9) Examples are given in the form of the execution type Zada &.
μ 二Μ用，本說明書中的各項細節亦可美#V =點…，在不恃離本發明之精神下進行各4: (第一實施例） 第囷所示，本發明第一實施例所揭露之開窗切王七 柵陣列（WBGA)半導Μ 丨乃路《開固型球 · V體封衣件使用一基板2 0作為晶片承載件 (ChiP Carrier)’包括：具有一上表面2 0 0及一相對之下 表面2 0 1的基板2 〇，該基板2 〇並開設有一貫穿其中之開孔 2 0 2，至少一晶片2 1，藉一膠黏劑2 2接置於該基板2 〇之上 表面2 0 0且遮覆該開孔2〇2，並藉多數穿通於該開孔2〇2中 之鲜線2 3電性連接至該基板2 〇之下表面2 〇丨，而使該晶片 2 1與基板2 0之間存留有未為該膠黏劑2 2所填充之空隙2 5 ; 一第一模壓製成之封裝膠體24，形成於該基板20之上下表 面2 0 0、2 0 1上，用以包覆該晶片2 1及銲線2 3並填充於該基 板2 0之開孔2 0 2及該晶片2 1與基板2 0之間的空隙2 5中；一 第二非模壓製成之封裝膠體26，用以包覆該第一封裝膠體 2 4形成於基板2 0下表面2 0 1上的部分；以及多數銲球2 7， 植設於該基板2 0之下表面2 0 1上未形成有該第二封裝膠體 26的區域並外露。 上述開窗型球柵陣列半導體封裝件得以第2A至2G圖所 示之製程步驟製得。 如第2 A圖所示，首先，製備一由多數基板2 0組成之基 板片2，其係以習知樹脂材料例如環氧樹脂、聚亞醯胺 (P 〇 1 y i m i d e )樹脂、B T ( b i s m a 1 e i m i d e t r i a z i n e )樹脂、For μ μM, the details in this specification can also be beautiful #V = point ..., each of which is performed without departing from the spirit of the present invention: (First Embodiment) As shown in (ii), the first implementation of the present invention The example disclosed in the window-cutting King Seven-Grid Array (WBGA) semiconductor M is a road-opening ball. The V-body coating uses a substrate 20 as a chip carrier (ChiP Carrier). It includes: A substrate 2 0 with a surface 2 0 and a relatively lower surface 2 01. The substrate 2 0 is provided with an opening 2 2 passing therethrough. At least one wafer 2 1 is connected by an adhesive 22. The upper surface 200 of the substrate 2 0 covers the opening 200, and is electrically connected to the lower surface 2 of the substrate 2 by a plurality of fresh wires 2 3 passing through the opening 200.丨 and a gap 2 5 is left between the wafer 21 and the substrate 20 that is not filled with the adhesive 22; a first mold-molded packaging gel 24 is formed on the upper and lower surfaces of the substrate 20 2 0 0 and 2 01 are used to cover the wafer 21 and the bonding wire 23 and fill the opening 2 0 2 of the substrate 20 and the gap 2 5 between the wafer 21 and the substrate 2 5 Medium; a second non-modular The produced encapsulating gel 26 is used to cover the portion of the first encapsulating gel 24 formed on the lower surface 201 of the substrate 20; and most of the solder balls 27 are implanted on the lower surface 2 of the substrate 20 The area where the second encapsulant 26 is not formed on 01 is exposed. The above-mentioned window-type ball grid array semiconductor package is manufactured by the process steps shown in FIGS. 2A to 2G. As shown in FIG. 2A, first, a substrate sheet 2 composed of a plurality of substrates 20 is prepared, which is made of conventional resin materials such as epoxy resin, polyimide resin, BT (bisma 1 eimidetriazine) resin,
17436聯測.ptd 第14頁 1236716 五、發明說明（10) FR撕脂等製成。各基板20具有一上表面2 0 0及一相對之下 表面2 0 1並開設有一貫穿其中之開孔2 0 2，其中該開孔2 0 2 較佳呈矩形，具有二相對較長側邊及二相對較短側邊。基 板片2之製造採用習知技術，故予此不予贅述。 如第2B圖所示（上視圖及沿2B-2B線切開所示之剖視 圖），接著，藉一膠黏劑2 2接置至少一晶片2 1於各基板2 0 之上表面2 0 0上且遮覆該基板2 0之開孔2 0 2。該晶片2 1具有 一形成有多數電子電路（未圖示）與銲墊211之作用表面210 以及一相對之非作用表面2 1 2。該晶片2 1之表面積大於基 板2 0之開孔2 0 2，而使晶片2 1能完全覆蓋住該開孔2 0 2。晶 片21係以面朝下（face-down)方式接置於各基板20上，以 使晶片2 1之作用表面2 1 0朝向基板2 0之開孔2 0 2，並藉該膠 黏劑2 2黏置於基板2 0之上表面2 0 0上，其中該勝黏劑2 2係 敷設於晶片2 1與基板2 0之間且通常沿著開孔2 〇 2之二較長 側邊’而使晶片2 1與基板2 0之間且位於開孔2 〇 2之二較短 側邊處存留有未為膠黏劑2 2所填充之空隙2 5。該敷設之膠 黏劑2 2具有一預定厚度，而使晶片2 1與基板2 〇之間的空隙 2 5之高度與膠黏劑2 2之厚度相同，該預定之厚度或高度得 使用以形成封裝膠體（未圖示）之樹脂材料粒子得順利通過 該空隙25。 、 然後，進行一銲線（wire bonding)作業以形成多數穿 通於各基板2 0之開孔2 〇 2中的銲線2 3，該銲線2 3係一端連 接至晶片2 1上的銲墊2 1 1，而另一端連接至基板2 〇的下表 面201，藉之以使晶片21電性連接至基板2〇。銲線23可以17436 United Test. Ptd Page 14 1236716 V. Description of the invention (10) FR tearing and other products. Each substrate 20 has an upper surface 2 0 0 and a relatively lower surface 2 0 1 and an opening 2 2 is formed therethrough. The opening 2 2 is preferably rectangular and has two relatively long sides. And two relatively short sides. The manufacturing of the substrate sheet 2 is based on conventional techniques, so it will not be repeated here. As shown in FIG. 2B (top view and cross-sectional view taken along line 2B-2B), then, an adhesive 22 is used to connect at least one wafer 21 to the upper surface 2 0 of each substrate 2 0 And covering the openings 202 of the substrate 20. The wafer 21 has an active surface 210 on which a plurality of electronic circuits (not shown) and pads 211 are formed, and an opposite non-active surface 2 1 2. The surface area of the wafer 21 is larger than the opening 2202 of the substrate 20, so that the wafer 21 can completely cover the opening 2202. The wafer 21 is placed on each substrate 20 in a face-down manner so that the active surface 2 1 of the wafer 21 faces the opening 2 2 of the substrate 2 0, and the adhesive 2 is borrowed by the adhesive 2 2 is placed on the upper surface 2 0 of the substrate 20, wherein the adhesive agent 2 2 is laid between the wafer 21 and the substrate 20 and usually along the longer side of the opening 2 02 2 ' In addition, a gap 25, which is not filled with the adhesive 22, is left between the wafer 21 and the substrate 20 and located at the shorter side of the opening 2202. The laid-up adhesive 22 has a predetermined thickness such that the height of the gap 25 between the wafer 21 and the substrate 20 is the same as the thickness of the adhesive 22, and the predetermined thickness or height can be used to form The resin material particles of the sealing colloid (not shown) can pass through the gap 25 smoothly. Then, a wire bonding operation is performed to form a plurality of bonding wires 23 that pass through the openings 20 of each substrate 20, and the bonding wires 23 are connected to the bonding pads on the wafer 21 at one end. 2 1 1, and the other end is connected to the lower surface 201 of the substrate 20, whereby the chip 21 is electrically connected to the substrate 20. Welding wire 23 can
17436聯測.ptd 第15頁 1236716 五、發明說明（ll) 金（g ο 1 d )製成’故可稱為金線。銲線作業係屬習知技術， 故予此不予贅述。 如第2 C圖所示，製備一較佳以堅硬材料製成之間隔件 2 8，具有多數貝牙其中之通孔2 8 0 ’並接置該間隔件2 8至 該多數基板2 0之下表面2 0 1上；其中各通孔2 8 0對應於並大 於各基板2 0之開孔2 0 2 ’且該間隔件2 8之厚度大於該銲線 23突出於基板2 0之下表面201上的線弧高度，以使形成於 各晶片2 1上的銲線2 3線弧收納於對應的間隔件2 8通孔2 8 0 中 。 如第2 D圖所示（沿二相互垂直線切開所示之剖視圖）， 鲁 進行一模壓（mo 1 d i ng )製程以使用一樹脂材料（如環氧樹脂 等）形成一第一封裝膠體2 4於基板20之上下表面200、201 上。利用一具有上模2 9 0及下模2 9 1之封裝模具2 9，該上模 2 9 0開設有一空穴2 9 2其尺寸足以覆蓋所有基板2 〇，而下模 2 9 1為一具有一平坦頂面2 9 3之平坦模具以與間隔件2 8觸 接。於模壓製程進行時，上述完成置晶（接置晶片2丨）及銲 線作業之基板片2置入並箝制於封裝模具2 9的上模2 9 0與下 模2 9 1之間，其中上模2 9 0觸接所有基板2 〇之上表面2 0 0， 以使所有接置於基板2 0上的晶片2 1收納於上模2 9 0之空穴 2 9 2中，而下模2 9 1的平坦頂面2 9 3則與間隔件2 8觸接，以 馨 使間隔件2 8夾置於基板2 0之下表面2 〇 1與下模2 9 1的平坦頂 面2 9 3之間，藉此銲線2 3係收納於各基板2 〇開孔2 0 2與間隔 件28通孔2 8 0中且為下模291所封閉。此時，該樹脂材料即 /主入上模2 9 0之空穴2 9 2中以填充於整個空穴2 9 2中及包覆17436 联 测 .ptd Page 15 1236716 V. Description of the invention (ll) Gold (g ο 1 d) is made of ’, so it can be called gold wire. Welding is a well-known technique, so it will not be repeated here. As shown in FIG. 2C, a spacer 28, which is preferably made of a hard material, is prepared. The spacer 28 has a plurality of through holes 2 8 0 ′ therein, and the spacer 28 is connected to the majority of the substrates 20 The lower surface 2 0 1; each through hole 2 8 0 corresponds to and is larger than the opening 2 2 2 ′ of each substrate 20 and the thickness of the spacer 28 is greater than the bonding wire 23 protruding from the lower surface of the substrate 20 The height of the line arc on 201 is such that the bonding wire 2 3 line arc formed on each wafer 21 is received in the corresponding spacer 28 through-hole 2 8 0. As shown in FIG. 2D (a cross-sectional view cut along two mutually perpendicular lines), Lu performs a molding (mo 1 di ng) process to use a resin material (such as epoxy resin) to form a first encapsulant 2 4 on the upper and lower surfaces 200, 201 of the substrate 20. A packaging mold 2 9 having an upper mold 2 9 0 and a lower mold 2 9 1 is used. The upper mold 2 9 0 is opened with a cavity 2 9 2 which is large enough to cover all the substrates 2. The lower mold 2 9 1 is one. A flat mold having a flat top surface 2 9 3 to contact the spacer 2 8. During the molding process, the above-mentioned substrate wafer 2 that has completed the wafer placement (attach wafer 2 丨) and wire bonding operations is placed and clamped between the upper mold 2 9 0 and the lower mold 2 9 1 of the packaging mold 2 9, of which The upper mold 2 9 contacts all the substrates 2 0 and the upper surface 2 0 so that all the wafers 21 placed on the substrate 2 0 are received in the holes 2 9 2 of the upper mold 2 9 0 and the lower mold 2 9 0 The flat top surface 2 9 1 2 9 3 is in contact with the spacer 2 8, and the spacer 2 8 is sandwiched between the lower surface 2 0 of the substrate 2 0 and the flat top surface 2 9 1 of the lower mold 2 9 Between 3, the bonding wire 2 3 is received in each of the substrate 20 openings 202 and the spacer 28 through-holes 280 and is closed by the lower mold 291. At this time, the resin material / mainly enters the cavity 2 9 2 of the upper mold 2 9 0 to fill the entire cavity 2 9 2 and cover
17436聯測.ptd 第16頁 1236716 五、發明說明（12) 所有接置於基板2 0上的晶片2 1，且該樹脂材料亦自上模 2 9 0之空穴2 9 2流入晶片21與基板20之間的空隙25至基板20 的開孔2 0 2及間隔件2 8之通孔2 8 0中。空隙2 5之高度如上定 義足以使樹脂材料粒子順利通過其中，而使樹脂材料能包 覆銲線2 3並填充於基板2 0的開孔2 0 2、間隔件2 8之通孔 2 8 0、及晶片2 1與基板2 0之間的空隙2 5 (位於開孔2 0 2之二 較短側邊處且未敷設有膠黏劑2 2 )中。當樹脂材料固化 後，即形成整合之第一封裝膠體2 4於基板2 0之上下表面 2 0 0、2 0 1上’其中形成於基板2 〇上表面2 0 0上的第一封裝 膠體24部分係單一膠體包覆所有晶片21，而形成於基板 下表面201上的第一封裝膠體24部分包括多數單獨膠體各 填充於一對應之基板2 0開孔2 0 2、間隔件2 8通孔2 8 0、及曰 曰曰 片21與基板20之間的空隙25中。由於間隔件28的厚度大於 銲線2 3突出於基板2 0下表面2 0 1上的線弧高度，填充於間 隔件2 8之通孔2 8 0中的樹脂材料得完全包覆住銲線2 3線 弧。再者，由於間隔件2 8以堅硬材料製成且下模2 9丨之頂 面2 9 3平坦，故間隔件28可穩固地箝制於基板片2與下模 2 9 1之間，而能避免樹脂材料溢膠至間隔件2 8與下模2 91頂 面2 9 3間之介面及基板2 0之下表面2 0 1上不需形成有第一封 裝膠體2 4的區域。 ^ 當第一封裝膠體2 4完成後，自基板2 〇上移除封裝模具 2 9及間隔件2 8，而使形成於基板2 0之上下表面2 〇 〇、2 0 1上 的第一封裝膠體24露出。惟該第一封裝膠體24形成於基板 2 0下表面2 0 1上的部分包括多數單獨膠體各流入晶片2 1與17436 联 测 .ptd Page 16 1236716 V. Description of the invention (12) All the wafers 2 1 placed on the substrate 20, and the resin material also flows from the holes 2 9 2 of the upper mold 2 9 0 into the wafer 21 and The gap 25 between the substrates 20 is in the opening 20 2 of the substrate 20 and the through-hole 2 8 0 of the spacer 28. The height of the void 25 as defined above is sufficient to allow the resin material particles to pass through it smoothly, so that the resin material can cover the bonding wire 2 3 and fill the openings 2 0 of the substrate 2 2 and the through holes 2 8 of the spacer 2 8 And the gap 2 5 between the wafer 21 and the substrate 20 (located at the shorter side of the opening 2202 bis and not provided with the adhesive 2 2). When the resin material is cured, an integrated first encapsulating gel 24 is formed on the upper and lower surfaces of the substrate 20, and the first encapsulating gel 24 is formed on the upper surface 200 of the substrate 20. The part is a single colloid covering all the wafers 21, and the first encapsulating gel 24 formed on the lower surface 201 of the substrate includes a plurality of individual colloids each filled in a corresponding substrate 20 openings 2 0, spacers 2 8 through holes 2 8 0 and the space 25 between the sheet 21 and the substrate 20. Since the thickness of the spacer 28 is greater than the height of the arc of the wire 23 protruding from the lower surface 2 0 of the substrate 20, the resin material filled in the through hole 2 8 0 of the spacer 28 must completely cover the wire. 2 3 line arcs. Furthermore, since the spacer 2 8 is made of a hard material and the top surface 2 9 3 of the lower mold 2 9 丨 is flat, the spacer 28 can be firmly clamped between the substrate sheet 2 and the lower mold 2 91. Avoid overflowing the resin material to the interface between the spacer 2 8 and the top surface 2 91 of the lower mold 2 91 and the lower surface 2 1 of the substrate 20 without the area where the first encapsulant 24 is formed. ^ After the first encapsulant 24 is completed, the encapsulation mold 29 and the spacer 28 are removed from the substrate 20, so that the first package formed on the upper and lower surfaces of the substrate 20, 200, and 201 is formed. The colloid 24 is exposed. However, the portion of the first encapsulant 24 formed on the lower surface 201 of the substrate 20 includes a plurality of individual colloids each flowing into the wafer 21 and
17436聯測.ptd 第17頁 1236716 五、發明說明（13) " -- =0之間的空隙2 5中之樹脂材料製成，故該單獨膠體通 二二#不佳之外觀，而可能因此未完全包覆住銲線2 3而使 二=吁線23露出，此則影響後續完成之封裝件的品質及信 賴性。 ^第2E圖所示，進行〜點膠或印刷製程以於第一封裝 24,成於基板20下表面2〇1上的部分之各單獨膠體上 ‘而二2二，裝膠體26、，以改善該單獨膠體之外觀使其完 、此:保銲線23完全為封裝膠體24、26所包覆。 以开^ HF圖，Γ ’進行一植球（bal 1 implanting)作業 ϊίΐ 多鮮球27於各該基板20下表面2〇1上為形 第二封裝膠體“、26之外露區域。突出於基板 2 0下表面201上之第一鱼筮一 係小於銲球27之高度。 U勝 26的厚度總和 举，第ΓΪ所示’進行-切單(Singulation)作 部分以及基板片2以分離基而板2〇上表面2 0 0上的 導體封裝件各具有—各基板2〇,而形成多數個別的半 所示）。該銲球2 7作A b之基板2 〇及多數銲球2 7 (如第1圖 / β知球」7作為輪入/輸出端以使 (如印刷電路板）成電性連接關係。 片2m外界表置 上述半導體封裝件及直制 與基板之間及基板開孔二^ 者夕優點。位於晶片 空隙，係供用以形成封裳二^二未敷設有膠黏劑的 該樹脂材料注人上模之^ :^料流通的通道。當 基板開孔中並包覆銲線，^時該空隙:=該空隙而填充於 工μ /、為該樹脂材料所填17436 联 测 .ptd Page 17 1236716 V. Description of the invention (13) "-The space between 2 and 5 is made of resin material, so the separate colloid has a poor appearance, which may The welding wire 23 is not completely covered and the second wire 23 is exposed, which affects the quality and reliability of the subsequently completed package. ^ As shown in FIG. 2E, a dispensing or printing process is performed to the first package 24, each of the individual colloids formed on the bottom surface 201 of the substrate 20, and the colloids 26, 22, and Improve the appearance of the separate colloid to finish it. This: The soldering protection wire 23 is completely covered by the encapsulating gel 24,26. According to the HF image, Γ ′ performs a bal 1 implanting operation. A plurality of fresh balls 27 are formed on the lower surface 201 of each substrate 20 to form a second encapsulating gel “26, which is an exposed area. It protrudes from the substrate. The first fish bladder on the lower surface 201 is less than the height of the solder ball 27. The thickness of U win 26 is the sum of the thicknesses, as shown in ΓΪ'sing-singulation (Singulation) operation part and the substrate sheet 2 to separate the base and The conductive packages on the upper surface of the board 20 each have-each substrate 20, and most of the individual halves are formed.) The solder ball 27 is used as the substrate 20 of the A b and most of the solder balls 27 ( As shown in Figure 1 / β Zhiqiu "7 as a wheel input / output terminal to make (such as a printed circuit board) an electrical connection relationship. Sheet 2m outside the surface of the above-mentioned semiconductor package and direct and the substrate and the substrate openings Advantages of the second party. It is located in the gap between the wafers and is used to form the resin material that is not covered with an adhesive. This resin material is injected into the upper mold ^: ^ channel for material circulation. When the substrate is opened and covered Welding wire, the gap when ^: = the gap is filled in the work μ /, filled by the resin material
1236716 五、發明說明（14) ^ 充，因而避免習知氧、、P] -V、 脂模流不會對銲線產此’流入空隙之樹 移或短路現象。再*，由1而能避免銲線偏 擊或壓力較不會經開孔邊緣而溢膠至基板ί 衝 :有：裝膠體的區•，故能婦=二需形 外，使用具有通孔之間隔 姑、S 3丨Ρ二賴性。另 尺寸，而使間隔件箝制y 5 2 、對應基板開孔之 模之間。《孔中亦以板下ϋ與具有平坦表面的下 隔件之製造成本低，故A 4包復t線之樹脂材料。該間 時，可用具有對應尺以==同尺寸開孔之基板 Γ之通孔的間隔件而不會大幅辦+ 產成本。因此’該平垣下模配合適當間隔件可適用i ^ t填充於基板開孔中，Α能增進半導：械：線 度。該封裝膠體分別填充於各基板之開孔中， 或切單形成於基板下表面上的封裝膠體部A，故可ς刀: 裝膠體與基板間產生脫層Wdamination^此外，一丄 非模壓製成之封裝膠體，用以包覆第一封裝膠體形成於: 基板下表面上的部分，以改善封裝件之外觀使其完美並能 確保1線完全為封裝膠體所包覆；該第二封裝膠體係以^ 知點膠或印刷技術製成而不會大幅增加製程複雜性及成 本0 (第二實施例） 第3圖顯示本發明第二實施例之半導體封裝件。如圖 所示’此半導體封裝件之結構大致與第一實施例所揭露之1236716 V. Description of the invention (14) ^ charge, so to avoid the phenomenon of oxygen, P, -V, and die flow will not cause the welding wire to move into the gap tree or short-circuit phenomenon. Again *, 1 can avoid the welding line bias or pressure from leaking to the substrate through the edge of the hole. Punching: Yes: the area where the colloid is installed. The interval is S2P. Another dimension, so that the spacer clamps between y 5 2 and the die corresponding to the hole in the substrate. << The hole in the hole also uses a plate underbody and a lower spacer with a flat surface to make the manufacturing cost low, so A 4 covers the resin material of the t wire. At this time, a spacer having a through hole of a substrate Γ with a hole of the same size with a corresponding ruler can be used without substantial increase in production cost. Therefore, 'the flat bottom mold can be filled with the appropriate openings in the opening of the substrate, and A can improve the semiconducting: mechanical: linearity. The encapsulating gel is filled in the openings of the substrates, or the encapsulating gel portion A formed on the lower surface of the substrate is cut, so the knife can be delaminated: In addition, a delamination occurs between the colloid and the substrate. The finished encapsulant is used to cover the part of the first encapsulant formed on the lower surface of the substrate to improve the appearance of the package and make it perfect and ensure that the 1 line is completely covered by the encapsulant; the second encapsulant The system is manufactured by using a known dispensing or printing technology without significantly increasing process complexity and cost. (Second Embodiment) FIG. 3 shows a semiconductor package according to a second embodiment of the present invention. As shown in the figure, the structure of this semiconductor package is roughly the same as that disclosed in the first embodiment.
17436 聯測.ptd17436 Joint Test.ptd
1236716 五、發明說明（15) 封裝件（第1圖）相同，其不同處在於晶片2 1之非作用表面 2 1 2不為第一封裝膠體2 4所包覆而外露。該外露之非作用 表面2 1 2得有效助於散逸晶片2 1運作所產生之熱量，因而 增加半導體封裝件之散熱效率。 上述實施例僅為例示性說明本發明之原理及其功效， 而非用於限制本發明。任何熟習此項技藝之人士均可在不 違背本發明之精神與範疇下，對上述實施例進行修飾與變 化。因此，本發明之權利保護，應如後述之申請專利範圍 所歹|J 。1236716 V. Description of the invention (15) The package (picture 1) is the same, except that the non-active surface 2 1 2 of the chip 21 is not covered and exposed by the first encapsulant 2 4. The exposed non-acting surface 2 1 2 can effectively help dissipate the heat generated by the operation of the chip 2 1, thereby increasing the heat dissipation efficiency of the semiconductor package. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the protection of the rights of the present invention should be as described in the scope of patent application mentioned later | J.
17436 聯測.ptd 第20頁 1236716 圖式簡單說明 【圖式簡單說明】 為讓本發明之上述及其他目的、特徵以及優點能更明 顯易懂，將與較佳實施例，並配合所附圖示，詳細說明本 發明之實施例，所附圖示之内容簡述如下： 第1圖係本發明第一實施例之半導體封裝件之剖視 圖， 第2A至2G圖係第1圖所示之半導體封裝件的製程步驟 不意圖， 第3圖係本發明第二實施例之半導體封裝件之剖視 圖；以及 第4A至4F圖係習知半導體封裝件的製程步驟示意圖。 1 基 板 片 10 基 板 100 上 表 面 101 下 表 面 102 開 孔 11 晶 片 12 膠 黏 劑 13 銲 線 14 上 封 裝 膠 體 15 下 封 裝 膠體 16 銲 球 17 上 模 170 向 上 凹 陷 空 穴 18 下 模 180 向 下 凹 陷 空 穴 2 基 板 片 20 基 板 200 上 表 面 201 下 表 面 202 開 孔 21 晶 片 210 作 用 表 面 211 非 作 用 表 面 22 膠 黏 劑17436 联 测 .ptd Page 20 1236716 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, it will be combined with the preferred embodiments and the accompanying drawings. The detailed description of the embodiment of the present invention is as follows. The attached diagram is briefly described as follows: FIG. 1 is a cross-sectional view of the semiconductor package of the first embodiment of the present invention, and FIGS. 2A to 2G are the semiconductors shown in FIG. The process steps of the package are not intended. FIG. 3 is a cross-sectional view of the semiconductor package of the second embodiment of the present invention; and FIGS. 4A to 4F are schematic diagrams of process steps of a conventional semiconductor package. 1 Substrate sheet 10 Substrate 100 Upper surface 101 Lower surface 102 Opening hole 11 Wafer 12 Adhesive 13 Welding wire 14 Upper package gel 15 Lower package gel 16 Solder ball 17 Upper mold 170 Cavity upward 18 Cavity 18 downward cavity Cavity 2 Substrate sheet 20 Substrate 200 Upper surface 201 Lower surface 202 Opening hole 21 Wafer 210 Active surface 211 Non-active surface 22 Adhesive
17436聯測.ptd 第21頁 123671617436 joint test.ptd page 21 1236716
圖式簡單說明 23 銲線 24 第 一 封 裝 膠 體 25 空隙 26 第 二 封 裝 膠 體 27 鲜球 28 間 隔 件 280 通孔 29 封 裝 模 具 290 上模 291 下 模 292 空穴 293 平 坦 頂 面 G 空隙 第22頁 17436聯測.ptdBrief description of the drawing 23 Welding wire 24 First encapsulant 25 Gap 26 Second encapsulant 27 Fresh ball 28 Spacer 280 Through hole 29 Encapsulation mold 290 Upper mold 291 Lower mold 292 Cavity 293 Flat top G Gap Page 22 17436 Joint test.ptd
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW093104217A TWI236716B (en) | 2004-02-20 | 2004-02-20 | Window ball grid array semiconductor package with substrate having opening and method for fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW093104217A TWI236716B (en) | 2004-02-20 | 2004-02-20 | Window ball grid array semiconductor package with substrate having opening and method for fabricating the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI236716B true TWI236716B (en) | 2005-07-21 |
| TW200529333A TW200529333A (en) | 2005-09-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114512562A (en) * | 2022-01-29 | 2022-05-17 | 福斯特(嘉兴)新材料有限公司 | Double-glass assembly, packaging method thereof and electronic component |
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| JP2023035608A (en) * | 2021-09-01 | 2023-03-13 | キオクシア株式会社 | Method for manufacturing semiconductor device |
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| CN114512562A (en) * | 2022-01-29 | 2022-05-17 | 福斯特(嘉兴)新材料有限公司 | Double-glass assembly, packaging method thereof and electronic component |
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