M407485M407485
五、新型說明： 【新型所屬之技術領域 本創作係有關於可堆疊半導體封裝技術，特別係有關 於一種全模封可堆疊半導體封裝構造，可運用於高密度 封裝堆疊模組的架構（Package- On- Package m〇dule， POP) 〇 【先前技術】 隨著電子產品的微小化發展趨勢，印刷電路板表面可 供設置半導體封裝構造的面積越來越小。故有一種半導 體封裝構造之立體堆疊技術，是將複數個可堆疊半導體 封裝構造相互堆疊一起，成為封裝堆疊模組 (Package-On-Package module, POP)，以符合小型表面接 合面積與高密度元件設置之要求。習知可堆疊半導體封 裝構造之模封膠體局部形成於基板之上表面中央，基板 之周邊不會有模封膠體，以顯露轉接墊，以供封裝堆疊。 因此，可堆疊半導體封裝構造之侧邊強度不足時，基板 翹曲會影響堆疊良率。此外’非全面覆蓋的模封膠體必 須是使用頂洗口模封（top gate molding)技術，模封機台 缺乏共用性。 美國發明專利第 7,067,91 1 號「Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture」揭示一種可堆疊半導體封裝構 造，其模封膠體係全面覆蓋基板之上表面，以加強封裝 構造之側邊強度。然而’模封膠體在晶片側邊係設有貫 3 M407485 孔，以顯露封裝堆疊（P0P)轉接塾，方可進 以…孔係在模封夥體形成之後，另以雷射裝機堆械疊 孔，疋㈣等後續製程予以製作，製程步驟繁項，成本 較南。並且’在貫孔形成時^易於控制 :該模封夥體之厚度，故會損傷到基板内部結構=p 轉接墊或線料等。此外，以往㈣裝堆疊 — 顆半導體封裝構造經切割為單體化分離之後，再逐= 上壓合回銲’除了會增加製程 部的銲球若經歷過多的回銲，易…：裝堆疊體最底 【新型内容】 “有脆裂的問題。 本創作之主要目的係在於提供一種全模封可堆疊半 體封裝構造，可使用側澆口模封方式形成一模封膠 體，同時形成模封貫孔，可與其他產品共用側凌口模封 機台’達到降低封裝成本與提昇製程良率之效用。、 本創作之次一目的係在於提供一種全模封可 導體封裝構造，能在封裝製程中整合封裝堆疊，並且不 會有翹曲導致無法使基板條疊壓之情事。 本創作的目的及解決其技術問題是採用以下技術方 案來實現的。依據本創作揭示之一種全模封可堆疊半導 體封裝構造’包含一基板’其係具有一上表面與一下表 面’該基板於該上表面係具有複數個P0P轉接墊；一晶 片’其係設置於該基板；一模封膠體，其係完全覆蓋該 基板之該上表面’以密封該晶片’其中該模封膠體係具 有以側澆口模封同時形成之複數個模封貫孔，以顯露該 4 M407485 些卿轉接塾；以及銲料，其係填入於該1^^1 其中該些模封貫孔係為擴大開口。 本創作的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在刖述的全模封可堆疊半導體封裝構造中，該些模封 貫孔之深度係可大於該基板條之板厚。 在前述的全模封可堆疊半導體封裝構造中，該模封膠 體係可沿著該基板之邊緣切齊。 在前述的全模封可堆疊半導體封裝構造中，另可包含 有複數個打線形成之銲線，以使該晶片電性連接至該基 ❶ 以土 在前述的全模封可堆疊半導體封裝構造中，另可包含 複數個外接端子，其係設置於該基板之該下表面。 在前述的全模封可堆疊半導體封裝構造中，該銲料係 可填滿該些模封貫孔並稍突出於該模封膠體。 在前述的全模封可堆疊半導體封裝構造中，該些POP 轉接墊係可犬出於該基板之該上表面。 在前述的全模封可堆疊半導體封裝構造中，該基板之 該上表面係可缺乏銲罩層。 在前述的全模封可堆疊半導體封裝構造中，於該全模 封可堆叠半導體封裝構造上係可整合有另一半導體封裝 構造，其下方設有複數個對準於該些模封貫孔之外接墊。 在前述的全模封可堆疊半導體封裝構造中，該另一半 導體封裝構造係可具有複數個鑛切側面，其係與該模封 5 M407485V. New description: [New technology field] This creation is about stackable semiconductor packaging technology, especially related to a full-molded package stackable semiconductor package structure, which can be applied to the architecture of high-density package stacking modules (Package- On-Package m〇dule, POP) 〇 [Prior Art] With the trend toward miniaturization of electronic products, the area on the surface of printed circuit boards where semiconductor package structures can be placed is becoming smaller and smaller. Therefore, there is a three-dimensional stacking technology of a semiconductor package structure in which a plurality of stackable semiconductor package structures are stacked on each other to form a package-on-package module (POP) to conform to a small surface joint area and a high-density element. Requirements for setup. The mold encapsulant of the conventional stackable semiconductor package structure is partially formed in the center of the upper surface of the substrate, and there is no mold encapsulation around the substrate to expose the transfer pad for package stacking. Therefore, when the side strength of the stackable semiconductor package structure is insufficient, the substrate warpage affects the stacking yield. In addition, the 'non-commonly covered molding compound must use top gate molding technology, and the molding machine lacks commonality. US Patent No. 7,067,91, "Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture" discloses a stackable semiconductor package structure in which a molding compound system completely covers the upper surface of the substrate to reinforce the side of the package structure. strength. However, the 'molding gel is provided with 3 M407485 holes on the side of the wafer to expose the package stack (P0P) transfer 塾 before the hole is formed in the molded body, and the laser is installed. Subsequent processes such as stacking holes and 疋(4) are produced, and the process steps are complicated, and the cost is relatively south. And 'when the through hole is formed ^ is easy to control: the thickness of the molded body is damaged, so that the internal structure of the substrate = p transfer pad or wire material is damaged. In addition, in the past (4) stacking--the semiconductor package structure was cut into singulated and separated, and then press-back-welding--in addition to increasing the soldering ball in the process part, if it experienced excessive reflow, it is easy to: The bottom [new content] "There is a problem of brittle cracking. The main purpose of this creation is to provide a full-molded sealable half-package structure, which can be formed by a side gate molding method to form a mold seal and form a mold seal. The through hole can be shared with other products to achieve the effect of reducing the packaging cost and improving the yield of the process. The second purpose of this creation is to provide a full-die sealed conductor package structure that can be packaged. The package stack is integrated in the process, and there is no warpage, which makes it impossible to laminate the substrate strips. The purpose of the present invention and solving the technical problems thereof are achieved by the following technical solutions. A full-molded seal according to the present disclosure can be used. The stacked semiconductor package structure includes a substrate having an upper surface and a lower surface. The substrate has a plurality of PMOS pads on the upper surface; a wafer 'The system is disposed on the substrate; a mold encapsulant completely covering the upper surface of the substrate to seal the wafer. The mold encapsulation system has a plurality of mold seals formed by side gate molding simultaneously a hole to expose the 4 M407485 and a solder, and the solder is filled in the 1^^1, wherein the molded through holes are enlarged openings. The purpose of the present invention and solving the technical problems thereof may also be adopted. The following technical measures are further implemented. In the fully-encapsulated stackable semiconductor package structure described above, the depth of the molded vias may be greater than the thickness of the substrate strip. In the foregoing fully-molded stackable semiconductor package structure The mold encapsulation system can be aligned along the edge of the substrate. In the foregoing all-molded stackable semiconductor package structure, a plurality of wire bonding wires can be further included to electrically connect the wafer to the In the foregoing all-sealed stackable semiconductor package structure, the substrate may further comprise a plurality of external terminals disposed on the lower surface of the substrate. In the foregoing all-molded stackable semiconductor package structure The solder system can fill the mold through holes and protrude slightly from the mold sealing body. In the foregoing all-sealed stackable semiconductor package structure, the POP transfer pads can be dogs out of the substrate. The upper surface. In the foregoing fully-molded stackable semiconductor package construction, the upper surface of the substrate may lack a solder mask layer. In the aforementioned full-molded stackable semiconductor package structure, the full-mode-stackable semiconductor can be stacked The package structure may be integrated with another semiconductor package structure, and a plurality of pads aligned with the mold via holes are disposed under the package. In the foregoing all-molded stackable semiconductor package structure, the other semiconductor package The structural system may have a plurality of ore cut sides, which are attached to the mold seal 5 M407485
膠體之邊緣切齊。 在前述的全模封可堆疊半導體封裝構造中，該另一半 導體封裝構造係包含有複數個設於該些外接墊之突出端 子，其係嵌埋於該些模封貫孔内並焊接至該銲料，並且 該些突出端子之長度係小於該些模封貫孔之深度。 在前述的全模封可堆疊半導體封裝構造中，該些突出 1子之形狀係可為狀並與該些模#貫孔為非對稱。 【實施方式】 依據本創作之第一具體實施例，揭示一種全模封可堆 疊半導體封裝製程。 ”月參閱第1圖所示，一種全模封可堆疊半導體封裝製 程包下步驟：「提供一基板條」步驟1、「設置複數 個晶片」步驟2、「電性連接」步驟3、「以侧溱口模封方 式形成一模封膠體」步驟4、「填入鮮料」步驟5、「基板 條疊壓」步驟6、「外接端子設置」步驟7以及「鑛切」 步驟8纟中’「提供-基板條」步驟1、「設置複數個晶 片」步驟2以側澆口模封方式形成一模封膠體」步驟 與真入銲料」步驟5為主要步驟，其餘步驟為選擇 性替代、省略或者是作為本創作具體化說明之次要步 驟’依步驟順序詳述如下。 首先’在「提供-基板條」步驟1中，如第2A及3 圖所不S供第-基板條11〇,該第一基板條係 具有複數個基板單元⑴，該些基板單元m係矩陣排 列在模封區112内’每一基板單元⑴係具有複數個 6 -TW /h-Q^ 年月 POP 轉接聲 1 1 ·, 乜 ___ 11 每一基板單元111係具有一上表面 下表面115»該上表面114為晶片設置面’而該 下表面115則為外接端子設置面。其中’該些POP轉接 與複數個内接指係形成於該上表面114。「基板單 元」所心者為單顆封裂構造所需的基板，通常該第—基 板條110在封裝製程中係一體構成有複數個基板單元 1U°該第一基板條110係具有一層以上的線路圖案，可 為硬質的印刷電路板或是軟質的電路薄膜。「POP」係為 PaCkage-〇n-Package的簡稱，中文為封裝堆疊，「p〇p轉 接墊」即是指在多個半導體封裝構造立體堆疊時電性連 接上方半導體封裝構造之金屬墊。較佳地，該些POP轉 接塾113係可突出於該些基板單元U1之上表面114, 以利被一上模具210之壓柱211平貼壓觸。通常該些pop 轉接塾113的表面突出方法可為表面金屬層（如錄金層） 之加厚電鍍’以高出於該基板單元之銲罩層（solder mask)，另一種更低成本的方法為，該些基板單元1丨丨之 上表面114係缺乏銲罩層。即該些基板單元U1之上表 面114僅有線路層，不需要形成銲罩層，便可使該些pop 轉接墊113為表面突出並且基板成本更低。 之後，在「設置複數個晶片」步驟2中，如第2B圖 所示，設置複數個晶片1 20於該第一基板條丨丨〇之上表 面114。該些晶片120係具有複數個鲜塾121，該些鲜塾 121係形成於該晶片120之一主動面。在本實施例中， 可藉由一黏晶層122之黏貼，將該晶片120之一背面黏 7 M407485 . 接於該第一基板條110 之上表面114 明· 5· 1 年月The edges of the gel are aligned. In the foregoing all-sealed stackable semiconductor package structure, the other semiconductor package structure includes a plurality of protruding terminals disposed on the external pads, embedded in the molded through holes and soldered to the Solder, and the length of the protruding terminals is less than the depth of the molded through holes. In the foregoing all-molded stackable semiconductor package structure, the protrusions may be shaped and asymmetrical with the vias. [Embodiment] According to a first embodiment of the present invention, an all-molded package stackable semiconductor package process is disclosed. "Please refer to Figure 1 for a full-mold package stackable semiconductor package process package. Steps: "Provide a substrate strip" Step 1, "Set multiple wafers" Step 2, "Electrical connection" Step 3, "To Side Mouth Sealing Forms a Mold Sealant Step 4, "Filling Fresh Material" Step 5, "Substrate Strip Lamination" Step 6, "External Terminal Setting" Step 7 and "Mine Cutting" Step 8 ' Step 1 of "Providing - Substrate Strip" Step 2: "Setting a plurality of wafers" Step 2 Forming a molding compound by side gate molding" Step and true soldering step 5 is the main step, and the remaining steps are selective replacement and omission Or as a secondary step in the specific description of this creation, the details are as follows in the order of steps. First, in step 1 of the "providing-substrate strip", as shown in FIGS. 2A and 3, the first substrate strip has a plurality of substrate units (1), and the substrate units are m-matrices. Arranged in the molding area 112, each substrate unit (1) has a plurality of 6 - TW / hQ ^ POP transition sounds 1 1 ·, 乜___ 11 each substrate unit 111 has an upper surface lower surface 115 » The upper surface 114 is a wafer mounting surface 'and the lower surface 115 is an external terminal mounting surface. Wherein the POP transfer and the plurality of inscribed fingers are formed on the upper surface 114. The substrate unit is a substrate required for a single cracking structure. Generally, the first substrate strip 110 is integrally formed with a plurality of substrate units 1U in the packaging process. The first substrate strip 110 has more than one layer. The circuit pattern can be a hard printed circuit board or a soft circuit film. "POP" is an abbreviation for PaCkage-〇n-Package, Chinese is a package stack, and "p〇p transfer pad" refers to a metal pad electrically connected to the upper semiconductor package structure when a plurality of semiconductor package structures are three-dimensionally stacked. Preferably, the POP transfer ports 113 protrude from the upper surface 114 of the substrate unit U1 so as to be flatly pressed by the pressing posts 211 of an upper mold 210. Generally, the surface protrusion method of the pop transfer ports 113 may be a thick plating of a surface metal layer (such as a gold layer) to be higher than a solder mask of the substrate unit, and another lower cost. The method is that the surface 114 of the substrate unit 1 is lacking a solder mask layer. That is, the surface 114 of the substrate unit U1 has only a wiring layer, and it is not necessary to form a solder mask layer, so that the pop transfer pads 113 can be surface-surfaced and the substrate cost is lower. Thereafter, in step 2 of "setting a plurality of wafers", as shown in Fig. 2B, a plurality of wafers 1 20 are disposed on the surface 114 of the first substrate strip. The wafers 120 have a plurality of fresh shovel 121 formed on one of the active faces of the wafer 120. In this embodiment, one of the wafers 120 can be adhered to the back surface of the wafer 120 by adhesion of a die layer 122. The upper surface of the first substrate strip 110 is exposed to the surface 114.
。在不同實施例中， 該些晶片120或可利用覆晶技術設置於該第一基板條 110之上表面114,以凸塊（圖未繪出）電性連接該些晶片 120與該第一基板條11〇。 之後，在「電性連接」步驟3中，如第2(：圖所示， 可利用打線技術形成複數個銲線123，其係電性連接該 些晶片120之銲墊121至該第一基板條11〇之内接指。 故「電性連接」步驟3係實施在上述「設置複數個晶片」 步驟2與「以側澆口模封方式形成一模封膠體」步驟4 之間，以使該些晶片1 20電性連接至該些基板單元丨丨i。 在不同實施例中，該些晶片120係覆晶接合於該第一基 板條110，則「設置複數個晶片」步驟2與「電性連接」 步驟3可以同時執行。 第2D至2G圖係有關於「以側澆口模封方式形成— 模封膠體」步驟4之詳細圖解說明。如第2D圖所示， 設置一上模具210於該第一基板條11〇之上表面ιΐ4, 一平坦之下模具（圖未繪出）係位於該第一基板條Η 〇之 下表面115下方，以使該上模具21〇可沿著該模封區ιΐ2 邊緣緊壓住該第一基板條110。並且，該上模具21〇係 具有複數個可壓觸該第一基板條11〇之壓柱211，對應 於該些POP轉接墊113。在一較佳的型態中，由於該些 POP轉接墊113為表面突出，並且該些壓柱211之壓觸 面係可完全覆蓋該些POP轉接墊113之上表面，使得該 些POP轉接墊113之上表面被全面密合貼緊，以避免一 8 M407485 ;月正‘. In different embodiments, the wafers 120 may be disposed on the upper surface 114 of the first substrate strip 110 by using a flip chip technology, and the bumps (not shown) are electrically connected to the wafers 120 and the first substrate. Article 11〇. Then, in the "Electrical Connection" step 3, as shown in FIG. 2, a plurality of bonding wires 123 can be formed by a wire bonding technique, and the pads 121 of the wafers 120 are electrically connected to the first substrate. The internal connection of the strip 11 is so that the "electrical connection" step 3 is performed between the step 2 of "setting a plurality of wafers" and the step 4 of forming a mold-molding body by side gate molding, so that The plurality of wafers 120 are electrically connected to the substrate units 丨丨i. In different embodiments, the wafers 120 are flip-chip bonded to the first substrate strip 110, and then “set a plurality of wafers” step 2 and “ Electrical connection" Step 3 can be performed simultaneously. The 2D to 2G drawings are detailed illustrations of Step 4 of "Forming by Side Gate Molding - Molding Glue". As shown in Figure 2D, an upper mold is provided. 210 is on the first substrate strip 11 〇 above the surface ι 4, a flat lower mold (not shown) is located below the first substrate strip 〇 lower surface 115, so that the upper mold 21 can be along The edge of the mold sealing area ι 2 is pressed against the first substrate strip 110. And, the upper mold 21〇 And a plurality of pressing columns 211 for pressing the first substrate strip 11 ,, corresponding to the POP transfer pads 113. In a preferred form, since the POP transfer pads 113 are surface protruding, The pressure contact surfaces of the pressing columns 211 can completely cover the upper surfaces of the POP transfer pads 113, so that the upper surfaces of the POP transfer pads 113 are fully tightly pressed to avoid an 8 M407485; '
補充I 模封膠體130之溢料覆蓋至該些pop轉接塾之上表 面，防止後續銲料形成之假焊或/與空焊問題的發生。 如第2E圖所示，利用側澆口模封方式（side gate molding)形成一模封膠體13〇。複數個側澆口（side以^) 係位於該第一基板條！丨〇之一側邊緣，該模封膠體i 3〇 之覆蓋區域即是該模封區112，故該模封膠體13〇可連 續地覆蓋該些基板單元U1之上表面114，但不覆蓋該 些POP轉接墊113。如第2F圖所示，該模封膠體13〇 係填滿該上模具210之模穴，以密封該些晶片12〇與該 些銲線123’並可加以固化成形。如第扣及4圖所示， 進行脫模，由於該上模具21〇之壓柱211係壓觸該第一 基板條110之該些P0P轉接墊113,在分離該上模具21〇 之後，該模封膠體130在形成之同時便具有複數個模封 貫孔131，以顯露該些p〇p轉接墊113，不需要雷射、 機械鑽孔或是蝕刻等後續製帛，亦不會有㈣該第一基 板條no之情事。較佳地，該些壓柱211係可為往端^ 收斂之錐體柱，以使該些模封貫?L m具有擴大開口， 以利脫膜。由於該些模_L 131係貫穿該模封膠體 130’故該些模封貫孔131之深度即是該模封膠體"ο 之厚度。當該些模封貫?匕131之深度係可大於該第一基 板條110之板厚，即是該模封膠體13〇 基板條利用本創作「以側淹口模封方：形= 封膠體」步驟4中同時形成該模封膠體130之該些模封 貫孔131 ’僅需要更換具有壓柱211 t上模便可 9 共用傳統職口㈣機台， 之後’在「填入銲料步 m 」，驟5中，如第2H圖所示， 可利用一印刷模板22〇以網板 板 P 刷（screen printing)或鋼 版印刷⑽的設傭，以填入鲜料i4〇於該此 ㈣^131°如第21圖所示，該銲料刚係可填滿; 些模封貫孔131並猶突出於該模封膠體·在脫離印 刷模板220之後，可回鋅該銲料140,故在每-模封貫 孔131内且突出之該銲料14〇可作為一可堆疊半導體封 裝構造之突出銲接端子。通f該些銲料i4G係可為錫# 銲劑或無斜鮮劑，以錫96.5%_銀3%_銅〇 5%之無錯_ 為例，當該銲_ 14G到達回銲溫度約攝氏217度以上， 最高回銲溫度約為攝氏245度時能產生焊接之濕潤性。 本創作之另一特點在於整合了整合半導體封裝製程 與封裝堆疊，在「鋸切」步驟8之前先進行一「基板條 疊壓」步驟6。如第2了及2K圖所示，提供一已封裝之 第二基板條310，該第一基板條11〇係與該第二基板條 31〇疊合熱壓（如第5及6圖所示）。如第2J圖所示，該 第二基板條310係具有一上表面312與一下表面313。 其中’該下表面313設有複數個外接墊311，複數個第 一晶片32〇 '第二晶片係設置於該第二基板條31〇 之上表面3 12。例如，可利用一黏晶層323黏貼，使該 些第一晶片320、第二晶片321以堆叠方式黏著於該上 表面3 1 2。可利用打線技術形成複數個銲線324，其係電 性連接該些第一晶片320與第二晶片321之銲墊322至 ΒΙΓδ： M407485 年月曰 該第二基板條310。並以一封膠體no密^些第- 補充丨 B曰 片320、第二晶片321與該些銲線324,提供適當的封裝 保護以防止電性短路與塵埃污染。而在該第二基板條 310之下表面313之外接墊311係對準於第一基板條ιι〇 之該些POP轉接墊113，由於該銲料14〇稍突出於該模 封膠體130，故在「基板條疊壓」步驟6中可焊接至該 些外接墊311，以電性連接該第一基板條11〇與該第二 基板條3 1 0。 之後，在「外接端子設置」步驟7中，如第21及7 圖所示，設置複數個外接端子15〇於該些基板單元^ 之下表面115。在本實施例中，該些外接端子15〇係可 為銲球’以構成球格陣列（BGA)封裝。 最後’進行「鋸切」步驟8，如第2L及8圖所示， 利用一切割刀具230，沿著該些基板單元}丨丨之邊緣（即 切割道116)同時切割該第一基板條11〇與該第二基板條 3 10 ’包含了切割該些模封膠體13〇與33〇，得到複數個 全模封可堆疊半導體封裝構造（如第2M圖所示），其中每 一可堆疊半導體封裝構造在單體化分離時便已完成封襄 堆疊’故能節省表面接合步驟，該些銲球丨5 〇可一次回 銲便接合至一外部印刷電路板（圖未繪出），不需要再往 上堆疊另一半導體封裝構造。 本創作另揭示依上述製程所製成之一全模封可堆疊 半導體封裝構造。如第2M圖所示，該全模封可堆疊半 導體封裝構造主要包含一基板（即上述基板單元11丨>、— M407485The flash of the supplemental I molding compound 130 covers the upper surface of the pop transfer rafts to prevent the occurrence of false soldering or/and void soldering problems with subsequent solder formation. As shown in Fig. 2E, a mold sealing body 13 is formed by side gate molding. A plurality of side gates (side with ^) are located in the first substrate strip! One of the side edges of the cymbal, the covering area of the molding compound i 3 即 is the molding area 112, so the molding compound 13 连续 can continuously cover the upper surface 114 of the substrate unit U1, but does not cover the Some POP transfer pads 113. As shown in Fig. 2F, the molding compound 13 is filled with the cavity of the upper mold 210 to seal the wafers 12 and the bonding wires 123' and can be cured. As shown in FIG. 4 and FIG. 4, the demolding is performed. Since the pressing post 211 of the upper mold 21 is pressed against the PMOS pad 113 of the first substrate strip 110, after the upper mold 21 is separated, The molding compound 130 has a plurality of molded through holes 131 at the same time to expose the p〇p transfer pads 113, and does not require subsequent processes such as laser, mechanical drilling or etching, and does not There are (4) the first substrate strip no. Preferably, the pressure posts 211 are tapered columns that converge toward the ends so that the mold seals have an enlarged opening to facilitate film release. Since the molds _L 131 extend through the mold seal 130', the depth of the mold through holes 131 is the thickness of the mold seal. When the depth of the mold seals 131 is greater than the thickness of the first substrate strip 110, that is, the mold seal 13 〇 the substrate strip is molded by the side of the mold: a side seal molding: shape = sealant In the step 4, the molded through holes 131' of the molding compound 130 are simultaneously formed. Only the upper mold having the pressing column 211 t needs to be replaced, and the conventional working port (four) machine is shared, and then the "filling in the solder step m" is performed. In step 5, as shown in FIG. 2H, a printing template 22 can be used to screen the screen board or the stencil printing (10) to fill the fresh material i4. ^131°, as shown in Fig. 21, the solder can be filled; some of the mold holes 131 are still protruding from the mold seal. After the print template 220 is removed, the solder 140 can be returned to the solder 140. The solder 14 embossed in the through hole 131 and protruded as a protruding solder terminal of a stackable semiconductor package structure. The solder i4G system can be tin # solder or no skewer, with tin 96.5%_silver 3%_copper 5% error-free _ as an example, when the solder _ 14G reaches the reflow temperature of about 217 Celsius Above the degree, the highest reflow temperature is about 245 degrees Celsius, which can produce the wettability of the weld. Another feature of this creation is the integration of the integrated semiconductor package process and package stack. A "substrate strip laminate" step 6 is performed prior to the "sawing" step 8. As shown in Figures 2 and 2K, a packaged second substrate strip 310 is provided, and the first substrate strip 11 is laminated to the second substrate strip 31 to be hot pressed (as shown in Figures 5 and 6). ). As shown in Fig. 2J, the second substrate strip 310 has an upper surface 312 and a lower surface 313. The lower surface 313 is provided with a plurality of external pads 311, and a plurality of first wafers 32' are disposed on the upper surface 312 of the second substrate strip 31'. For example, the first wafer 320 and the second wafer 321 may be adhered to the upper surface 3 1 2 in a stacked manner by a bonding layer 323. A plurality of bonding wires 324 can be formed by a wire bonding technique, which electrically connects the pads 322 of the first and second wafers 320 and 321 to ΒΙΓδ: M407485. And a piece of colloidal-complementary 丨B 曰 320, second wafer 321 and the bonding wires 324 are provided with appropriate package protection to prevent electrical short circuit and dust pollution. In the outer surface 313 of the second substrate strip 310, the pads 311 are aligned with the POP transfer pads 113 of the first substrate strip. Since the solder 14 protrudes slightly from the mold seal 130, In the "substrate strip lamination" step 6, the external pads 311 can be soldered to electrically connect the first substrate strip 11 and the second substrate strip 310. Thereafter, in the "external terminal setting" step 7, as shown in Figs. 21 and 7, a plurality of external terminals 15 are provided on the lower surface 115 of the substrate unit. In the present embodiment, the external terminals 15 may be solder balls ' to form a ball grid array (BGA) package. Finally, the 'saw-cutting step 8 is performed. As shown in FIGS. 2L and 8, the first substrate strip 11 is simultaneously cut along the edges of the substrate units (ie, the dicing streets 116) by a cutting tool 230. The second substrate strip 3 10 ′ includes cutting the molding compounds 13 〇 and 33 〇 to obtain a plurality of full-molded stackable semiconductor package structures (as shown in FIG. 2M ), wherein each stackable semiconductor The package structure has completed the sealing stack during the singulation separation, so the surface bonding step can be saved. The solder balls 丨5 can be bonded to an external printed circuit board (not shown) in one reflow, no need Another semiconductor package construction is stacked up. The present invention further discloses an all-molded, stackable semiconductor package structure fabricated in accordance with the above process. As shown in FIG. 2M, the full-molded package stackable semiconductor package structure mainly includes a substrate (ie, the above-mentioned substrate unit 11丨>, - M407485
晶片1 2 Ο、 一上表面 一模封膠體130以及銲料I40。該基114與一下表面115，該基板於該上表面U4 係具有複數個POP轉接墊113。該晶片120係設置於該 基板之該上表面114。該模封膠體130係完全覆蓋該基 板之上表面114，以密封該晶片120’其中該模封膠體 1 3 0係具有以側澆口模封同時形成之複數個模封貫孔 131 ’以顯露該些POP轉接墊113。銲料140係填入於該 些模封貫孔13 1。在本實施例中，該模封膠體13〇係為 模封陣列封裝（Mold Array Package, MAP)型態，該模封 膠體1 30係沿著該基板之邊緣切齊並全面覆蓋該上表面 Π心該銲料14〇係填滿該些模封貫孔13丨並稍突出於該 模封膠體130，以接合一上方半導體封裝構造（如第2M 圖所不）。該全模封可堆疊半導體封裝構造可另包含有複 數個外接端子1 50，例如銲球，其係設置於該基板單元 111之下表面115。 在本創作之第二具體實施例中，一種全模封可堆疊半 導體封裝製程之主要步驟，如提供基板條、設置晶片與 封膠等等’其係大致與前述第一具體實施例相同，不再 贅述。 請參閱第9A及9B圖所示，在基板條疊壓步驟時， 兩基板條（即㈣—基板條1及該第二基板條3 10)在疊 壓之前預先完成個別封膠’但不鑛切。該第二基板條3 i 〇 〇 表自313之外接塾311位置設置有複數個突出端 子341，以插接至該些模封貫孔131並與該銲料14〇銲 12 M407485 ，正 補充 年月 接’增加鲜接強度以提昇封裝產品可靠度 10B圖所示）。在本實施例中，該些突出端子341係可為 導體柱’故該銲料14〇係、可不冑出於該模封貫孔⑴便 可焊接至該些突出端子341。該些突出端子341可為電 鍍形成之銅柱、打線形成之金柱、蝕刻厚銅層所形成之 銅柱、或其它金屬柱體。 在本實施例中，該些突出端子341係具有頂窄底寬之 梯形截面’如半圓錐體形或半方錐體形。依正負光阻的 選擇與蝕刻液的調配可利用過度曝光、不足曝光或不足 蝕刻的技術，以具體製成該些突出端子341的形狀。而 該些突出端子341之熔點係高於銲料14〇之回銲溫度。 因此，利用該些突出端子3 4 1接合在該些模封貫孔i 3丄 内之銲料140,增加了接合面積與接合形狀複雜度，達 成較高的銲接可靠度並降低裂縫（crack)成長可能。 另在本創作之第三具體實施例中揭示一種全模封可 堆疊半導體封裝製程，其主要步驟係與前述第一具體實 施例之製程步驟相同。如第11A及11B圖所示，該第二 基板條310在下表面313之外接墊311位置設置有複數 個突出端子342 ’在本實施例中，該些突出端子342係 可為具有尖端之錐形體，以利插接至該些模封貫孔 1 3 1。該銲料！ 4〇係可填滿該些模封貫孔1 3 i。如第1 2a 及12B圖所示，在基板條疊壓步驟中，該些突出端子3 係插接至該些模封貫孔131並與該銲料14〇銲接。 本創作之第四具體實施例揭示一種全模封可堆叠半 13 M407485 年月曰 導體封裝製程’其主要步驟係與前述第一 製程步驟相同。如第13A及13B圖所示，該第二基板條 ?之下“ 313之外接塾311位置設置有複數個突出 私子343 ’可為圓柱之導體柱。該辉料14〇係可未填滿 該些模封貫孔m(如第13B圖所示）。如第14A與14B 圖所示’在基板條疊壓步驟巾，該些突出端子343係插 接至=些模封貫孔131並與該銲料140接合。因此，本 創作提供了 —種能用以整合半導體封裝製程與封裝堆疊 之全模封可堆疊半導體封裝構造。 以上所述，僅是本創作的較佳實施例而已，並非對本 創作作任何形式上的限制，雖然本創作已以較佳實施例 揭露如上，然而並非用以限定本創作，任何熟悉本專業 的技術人員，在不脫離本創作技術方案範圍内，當可利 用上述揭示的技術内容作出些許更動或修飾為等同變化 的等效實施例，但凡是未脫離本創作技術方案的内容， 依據本創作的技術實質對以上實施例所作的任何簡單修 改、等同變化與修飾，均仍屬於本創作技術方案的範圍 内。 【圖式簡單說明】 第1圖：依據本創作之第一具體實施例，一種全模封可 堆疊半導體封裝製程之流程圖。 第2A至2M圖：依據本創作之第一具體實施例，繪示該 全模封可堆疊半導體封裝製程之基板條截面示 意圖。 M407485 ' 第3圖 依據本創作之第一具體實施例 第一基板條之立體示意圖。 I 5. 年月曰 補充| 製程中所提供 第4圖 第5圖 第6圖 依據本創作之第一具體實施例’製程中已封膠 之第一基板條之立體示意圖。 依據本創作之第一具體實施例，製程中在基板 條疊壓步驟時，兩基板條疊壓前之立體示意圖。 依據本創作之第一具體實施例，製程中在基板 條疊壓步驟之後’兩已疊壓基板條之立體示意 圖〇 第7圖.依據本創作之第一具體實施例，製程中之外接 端子設置步驟時，第一基板條設罝外接端子之 立體示意圖與截面圖。 第8圖：依據本創作之第一具體實施例，製程中之鋸切 基板條步驟時，兩基板條之立體示意圖。 第9A至9B圖：依據本創作之第二具體實施例，製程中 在基板條疊壓步驟時，兩基板條疊壓前之立體 示意圖與截面圖。 第1 Ο A至1 〇B圖：依據本創作之第二具體實施例，製程 中在基板條疊壓步驟之後，兩已疊壓基板條之 立體示意圖與截面圖。 之第三具體實施例，製程 時，兩基板條疊壓前之立 之第三具體實施例，製程 第11A至11B圖：依據本創作 中在基板條疊壓步_ 體示意圖與戴面圖。 第UA至圖：依據本創作 15 M407485 ••心 1 1 年月曰_Μΐ·ί·The wafer 1 2 Ο, an upper surface, a molding compound 130, and a solder I40. The base 114 and the lower surface 115 have a plurality of POP transfer pads 113 on the upper surface U4. The wafer 120 is disposed on the upper surface 114 of the substrate. The molding compound 130 completely covers the upper surface 114 of the substrate to seal the wafer 120', wherein the molding compound 130 has a plurality of molded through holes 131' formed by molding with side gates to expose The POP transfer pads 113. Solder 140 is filled in the molded through holes 13 1 . In this embodiment, the molding compound 13 is in the form of a Mold Array Package (MAP), and the molding compound 130 is aligned along the edge of the substrate and completely covers the upper surface. The solder 14 is filled with the mold vias 13 and slightly protrudes from the mold paste 130 to bond an upper semiconductor package structure (as shown in FIG. 2M). The fully packaged stackable semiconductor package construction can further include a plurality of external terminals 150, such as solder balls, disposed on the lower surface 115 of the substrate unit 111. In a second embodiment of the present invention, a main step of a fully-encapsulated stackable semiconductor package process, such as providing a substrate strip, providing a wafer and a sealant, etc., is substantially the same as the first embodiment described above, Let me repeat. Referring to Figures 9A and 9B, in the substrate strip lamination step, the two substrate strips (i.e., (4) - the substrate strip 1 and the second substrate strip 3 10) are pre-finished individually before lamination, but not mine. cut. The second substrate strip 3 i is provided with a plurality of protruding terminals 341 from the outer surface of the 313, so as to be inserted into the molded through holes 131 and soldered to the solder 14 by 12 M407485. Connect 'to increase the strength of the fresh joint to improve the reliability of the packaged product shown in Figure 10B. In this embodiment, the protruding terminals 341 can be conductor posts, so that the solder 14 can be soldered to the protruding terminals 341 without the molded vias (1). The protruding terminals 341 may be copper pillars formed by electroplating, gold pillars formed by wire bonding, copper pillars formed by etching a thick copper layer, or other metal pillars. In the present embodiment, the protruding terminals 341 have a trapezoidal cross section of a narrow bottom width such as a semi-conical shape or a semi-pyramid shape. The selection of the positive and negative photoresists and the etchant can be made by overexposure, underexposure or insufficient etching to specifically shape the protruding terminals 341. The protruding points of the protruding terminals 341 are higher than the reflow temperature of the solder 14 。. Therefore, the solder 140 bonded to the molded vias i 3 利用 by the protruding terminals 34 1 increases the joint area and the joint shape complexity, achieves high soldering reliability, and reduces crack growth. may. Further, in a third embodiment of the present invention, a full-molded package stackable semiconductor package process is disclosed, the main steps of which are the same as the process steps of the first specific embodiment. As shown in FIGS. 11A and 11B, the second substrate strip 310 is provided with a plurality of protruding terminals 342 in the outer pad 311 of the lower surface 313. In the embodiment, the protruding terminals 342 may be tapered with a tip end. , Eli plugged into the molded through holes 1 3 1 . The solder! 4 〇 can fill the molded through holes 1 3 i. As shown in FIGS. 1 2a and 12B, in the substrate strip lamination step, the protruding terminals 3 are inserted into the molded vias 131 and soldered to the solder 14 . A fourth embodiment of the present invention discloses a full-mold package stackable half 13 M407485 曰 conductor package process' whose main steps are the same as the first process steps described above. As shown in Figures 13A and 13B, under the second substrate strip, "the outer edge of the 313 is provided with a plurality of protrusions 343" which may be the conductor posts of the cylinder. The phosphor 14 may not be filled. The molded through holes m (as shown in FIG. 13B). As shown in FIGS. 14A and 14B, in the substrate strip lamination step, the protruding terminals 343 are inserted into the plurality of molded through holes 131. Bonding to the solder 140. Accordingly, the present disclosure provides a fully encapsulated stackable semiconductor package structure that can be used to integrate a semiconductor package process and package stack. The above is merely a preferred embodiment of the present invention, not The present invention has been limited in any form, and although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use it without departing from the scope of the present invention. The technical content disclosed above is modified or modified to be equivalent to the equivalent embodiment, but any simple modification to the above embodiment according to the technical essence of the present invention without departing from the technical solution of the present invention. The equivalent change and modification are still within the scope of the technical solution of the present invention. [Simplified description of the drawings] FIG. 1 is a flow chart of a full-module stackable semiconductor package process according to the first embodiment of the present invention. 2A to 2M: According to a first embodiment of the present invention, a schematic cross-sectional view of a substrate strip of the full-mold package stackable semiconductor package process is shown. M407485 ' FIG. 3 is a first substrate according to the first embodiment of the present invention. Fig. 3 is a perspective view of the first substrate strip which has been sealed in the process according to the first embodiment of the present invention. According to a first embodiment of the present invention, in the process of the substrate strip lamination step, a schematic view of the two substrate strips before lamination. According to the first embodiment of the present invention, after the substrate strip lamination step in the process FIG. 7 is a perspective view of two stacked substrate strips. According to the first embodiment of the present invention, when the external terminal is disposed in the process, the first substrate strip is provided with an external terminal. FIG. 8 is a perspective view showing the two substrate strips in the process of sawing the substrate strip in the process according to the first embodiment of the present invention. FIGS. 9A to 9B: according to the second specific embodiment of the present invention Embodiments, in the process of the substrate strip lamination step, a schematic view and a cross-sectional view of the two substrate strips before lamination. 1 Ο A to 1 〇 B diagram: According to the second embodiment of the present invention, the substrate is in the process After the strip lamination step, a schematic view and a cross-sectional view of the two laminated substrate strips. The third embodiment, during the manufacturing process, the third embodiment before the stacking of the two substrate strips, the process of the 11A to 11B : According to the creation of the substrate strip step _ body diagram and wearing surface map. UA to map: according to the creation of 15 M407485 •• heart 1 1 year month 曰 _ Μΐ · ί ·
補无I 中在基板條疊壓步驟之後，兩已疊壓基板條之 立體示意圖與截面圖。 第1 3A至13B圖：依據本創作之第四具體實施例，製程 中在基板條疊壓步驟時，兩基板條疊壓前之立 體示意圖與截面圖。 第1 4A至14B圖：依據本創作之第四具體實施例，製程 中在基板條疊壓步驟之後，兩已疊壓基板條之 立體示意圖與截面圖。 【主要元件符號說明】 1 提供一基板條 2 設置複數個晶片 3 電性連接 4 以側澆口模封方式形成一模封膠體 5 填入銲料 6 基板條疊壓 7 外接端子設置 8 鋸切 110第一基板條 111基板單元 112模封區 113 POP轉接墊 114上表面 115下表面 116切割道 120晶片 121銲墊 122黏晶層 123銲線 130模封膠體 131模封貫孔 140銲料 150外接端子 M407485 脚· 5· 月曰 210上模具 211壓柱 220印刷模板 230切割刀具 310第二基板條 311外接墊 312上表面 313下表面 320第一晶片 321第二晶片 322銲墊 323黏晶層 324銲線 330封膠體 341突出端子 342突出端子 343突出端子 丨補充| 17In Fig. 1, a perspective view and a cross-sectional view of the two laminated substrate strips after the substrate strip lamination step. Figs. 1 3A to 13B are schematic views and cross-sectional views of the two substrate strips before lamination in the substrate strip lamination step according to the fourth embodiment of the present invention. Figures 14A to 14B are perspective views and cross-sectional views of two laminated substrate strips after the substrate strip lamination step in the process according to the fourth embodiment of the present invention. [Main component symbol description] 1 Provide a substrate strip 2 Set a plurality of wafers 3 Electrical connection 4 Form a molding compound by side gate molding 5 Fill in solder 6 Substrate strip laminate 7 External terminal setting 8 Sawing 110 First substrate strip 111 substrate unit 112 molding area 113 POP transfer pad 114 upper surface 115 lower surface 116 cutting channel 120 wafer 121 solder pad 122 adhesive layer 123 bonding wire 130 molding adhesive 131 molding through hole 140 solder 150 external connection Terminal M407485 foot · 5 · month 曰 210 upper mold 211 column 220 printing template 230 cutting tool 310 second substrate strip 311 external pad 312 upper surface 313 lower surface 320 first wafer 321 second wafer 322 solder pad 323 adhesive layer 324 Welding wire 330 sealing body 341 protruding terminal 342 protruding terminal 343 protruding terminal 丨 supplementary | 17