TWI255560B - Semiconductor package with photosensitive chip and fabrication method thereof - Google Patents

Abstract

A semiconductor package with a photosensitive chip and a fabrication method thereof are provided. A substrate having a core is prepared. A solder mask layer is applied over a surface of the core and formed with an opening to expose a continuous peripheral portion on the surface of the core. At least one photosensitive chip is mounted on and electrically connected to the substrate. An encapsulation dam is formed on the continuous peripheral portion of the core and surrounds the chip. The dam includes a shoulder portion adjacent to and flush with the solder mask layer, and a protruded support portion surrounding the shoulder portion. A lid is attached to the support portion of the dam for sealing the dam such that the chip is received in a space defined by the substrate, the dam and the lid.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a photo-sensitive semiconductor package in which at least one photo-sensitive wafer such as a complementary metal oxide semiconductor (CMOS) is connected. , a complementary metal oxide semiconductor), and a method of manufacturing the semiconductor package. [Prior Art] A semiconductor package is an electronic device for carrying an active component such as a semiconductor chip, and the structural feature is mainly that the wafer is placed on a substrate, and the wafer is electrically connected to the conductive component (such as a bonding wire or the like). A substrate, and an encapsulant made of a resin compound (such as an epoxy resin) is formed on the substrate to cover the wafer and the bonding wire from external moisture and contaminants. The encapsulant is typically opaque, so photo-sensitive wafers that require light to operate, such as complementary metal oxide semiconductor (CMOS) wafers, are not suitable for use in such semiconductor packages. In view of the above, U.S. Patent No. 6,590,269 discloses a semiconductor package having an improved structure of encapsulant for allowing light to reach a photo-sensitive wafer (as shown in Fig. 4), the photo-sensitive wafer The 10 is connected to a substrate 1 1 and electrically connected to the substrate 11 by a plurality of bonding wires 12 . An encapsulant 13 is formed on the substrate 1 1 and has a wall structure surrounding the wafer 10 and the bonding wire 12; the wall-shaped encapsulant 13 forms a cavity 1 4 to receive the wafer 1 0 and wire bonding 1 2. A cover member 15 is attached to the encapsulant 13 to cover the cavity 14 so that the wafer 10 and the bonding wire 12 are hermetically separated from the outside atmosphere. The cover member 15 is made of a material that is transparent or transparent to allow light to pass therethrough to reach the wafer 10 for operation of the wafer 10;

17715^S.ptd Page 7 1255560 V. INSTRUCTION DESCRIPTION (2) A semiconductor package for use in a photo-sensitive wafer. However, the above semiconductor package may disadvantageously cause a number of disadvantages. The encapsulant system formed on the substrate is adhered to the solder resist layer (s ο 1 dermask) disposed on the substrate, and the adhesion between the resin compound forming the encapsulant and the solder resist material is poor and the encapsulant colloid is in contact with the substrate. The area is not large, so it is easy to cause delamination between the encapsulant and the substrate, thereby reducing the reliability of the semiconductor package. Furthermore, since the encapsulant is formed on the substrate by a molding method, the resin compound is easily spilled into the substrate on the substrate without being formed into a region where the encapsulant is not formed in the molding operation. The welding finger (b ο ndfinger ), so the wire is not soldered well to the contaminated welding finger, resulting in a low quality electrical connection between the wafer and the substrate. Therefore, it is an important subject to provide a semiconductor package having a photo-sensitive chip which can improve the adhesion between the encapsulant and the substrate and prevent the occurrence of overflow on the substrate. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package having a photo-sensitive wafer and a method for fabricating the same, which can improve the adhesion between the substrate and the package dam structure formed thereon, thereby avoiding the substrate and the package dam structure. Another purpose of the present invention is to provide a semiconductor package having a photo-sensitive wafer and a method of manufacturing the same, which can prevent the resin compound used to form the package dam structure from overflowing onto the substrate, thereby ensuring Reliability and electrical connection quality of semiconductor packages.

] 77]5石夕品.ptd Page 8 1255560 V. Description of the Invention (3) In order to achieve the above and other objects, the present invention discloses a semiconductor package having a photo-sensitive wafer, comprising: a substrate having a core layer Forming a plurality of conductive traces on at least one surface of the core layer, each of the conductive traces having an end portion, wherein a solder resist layer is applied on the surface of the core layer to cover the conductive traces, thereby The solder resist layer is exposed outside the opening, and the solder resist layer is provided with an opening to expose a continuous peripheral portion on the surface of the core layer; at least one photo-sensitive wafer is disposed on the substrate and electrically connected to the substrate An exposed end portion of the conductive trace; a package dam structure formed on the continuous peripheral portion of the core layer and surrounding the wafer, wherein the dam structure includes a shoulder portion and a protruding support portion, the shoulder portion abutting And the solder resist layer is flush with the solder resist layer, and the support portion surrounds the shoulder and has a height greater than the thickness of the wafer; a cover member is attached to the support portion of the dam structure to cover the layer Dam structure, and make the wafer Placed in a space defined by the substrate, a dam structure and surrounded by the cover; and the majority of the solder balls, implanted on the substrate contact is provided on one side with respect to the wafer. The method for fabricating a semiconductor package comprises the steps of: preparing a substrate having a core layer, forming a plurality of conductive traces on at least one surface of the core layer, each of the conductive traces having one end portion and applying a solder resist layer The conductive trace is covered on the surface of the core layer, and the solder resist layer is exposed outside the end portion, wherein the solder resist layer is provided with an opening to expose a continuous peripheral portion on the surface of the core layer; a package dam structure on a continuous peripheral portion of the core layer, wherein the dam structure includes a shoulder portion and a protruding support portion adjacent to the solder resist layer and flush with the solder resist layer And the support surrounds the shoulder and defines an air surrounded by the dam structure

] 7715石夕品.ptd Page 9 1255560 V. Description of invention (4); at least the outer end of the covered dam structure covered with the exposed end of the dam and the cover is surrounded by the connection The semi-conductive structure is formed on the portion, so that the adhesion to the core layer is between the trees, and is used to form a barrier mm (preferably 0. 5 lipid compound influent will quickly absorb the overflow glue to the Reliability and power of the opening on the substrate. [Embodiment] The following is a method for applying a photo-sensitive wafer in the surrounding space by using other embodiments of the invention familiar with the art, and electrically connecting the cover member to the structure. And the space in which the wafer is accommodated; and the side of the wafer, the body package having the substrate core layer of the shelf structure is made of a grease material to avoid the width of the continuous dam structure of the core layer. The hole is connected to the outside of the mold and the overflowing adhesive on the substrate has a lot of solder joint quality. Therefore, the sealing of the peripheral portion of the dam structure is obtained, so that the area of the heat resisting area is near the surface of the substrate and the substrate is dyed. The wafer is located in the Connecting the chip to the conductive traces on the support bar structure of the dam portion disposed in the seal structure of the dam, most of the solder balls provided on the substrate the substrate relative advantages. One of them is a continuous peripheral core layer contact exposed by the opening of the dam dam layer, and the dam structure effectively promotes delamination between the dam structure and the substrate and the substrate. The subdivided flux-receiving layer openings have a large mold cavity of about 0.1 to 1. When forming the edge of the agent layer for the dam structure, the resin compound increases the viscosity and thus does not. In view of this, the wafer and the bonding wire are not, so that the semiconductor package can be ensured by a specific example of the advantages and effects of the present specification. The present specification or application, the description explains the embodiments of the present invention, and the disclosed content can be easily understood or can be based on various details in other books.

7715石夕品.口士(1 Page 10 1255560 V. OBJECTS OF THE INVENTION (5) Various modifications and changes can be made without departing from the spirit and scope of the invention. As shown in Fig. 1, the present invention The semiconductor package includes a substrate 20 having a core layer 2 1 formed on at least one surface 210 of the core layer 2 1 with a plurality of conductive traces 2 2 , each conductive trace 22 having one end a portion 2 2 0, wherein a solder resist layer 2 3 is applied on the surface 210 of the core layer 2 1 to cover the conductive traces 2 2, and the end portion 2 2 0 is exposed to the solder resist layer 2 3 And the solder resist layer 2 3 defines a continuous peripheral portion 2 1 1 on the surface 2 1 0 of the core layer 2 1 except for the opening 2 3 0 ; at least one photo-sensitive wafer 24 is attached to the substrate 20 And electrically connected to the conductive trace 2 2, the exposed end portion 2 2 0; the package dam structure 25 is formed on the continuous peripheral portion 21 of the core layer 2 1 and surrounds the wafer 24, wherein The dam structure 25 includes a shoulder portion 26 and a protruding support portion 2, 7. The shoulder portion 26 is adjacent to the solder resist layer 23 and flush with the solder resist layer 23, and the support portion 27 around The shoulder portion 26 has a height greater than the thickness of the wafer 24; a cover member 2 8 is attached to the support portion 27 of the dam structure 25 to cover the dam structure 25, so that the wafer 24 The space is accommodated in the space B surrounded by the substrate 20, the dam structure 2 5 and the cover member 28; and a plurality of solder balls 290 are implanted on the substrate 20 with respect to one of the wafers 24 The above semiconductor package can be fabricated by the process steps shown in Figures 2A to 2D. First, as shown in Fig. 2A (cross-sectional view and simplified top view), a substrate 2 having a core layer 2 1 is prepared. 0, the core layer 2 1 may be made of a material such as epoxy resin, polyamidamine resin, BT (bisma 1 eimidetriazine) resin or FR 4 resin, etc. on the opposite surface of the core layer 2 1 2 0 0 1 2 separate shape

] 7715石夕品.ptd Page 11 1255560 V. Description of the invention (6) A plurality of conductive traces 2 2 such that each conductive trace 2 2 has an end portion 2 2 〇; the opposite surface 2 1 0, 2 1 2 The conductive traces 2 2 are electrically connected to each other through the conductive vias 2 2 1 . The conductive traces 22 are completed by techniques such as exposure, development, and etching, and thus will not be described herein. Then, a solder resist layer 2 3 (having a thickness of about 25 to 5 mm) is applied on the surfaces 210 and 21 of the core layer 21 to cover the conductive traces 22, and the ends of the conductive traces 2 2 are respectively disposed. The portion 2 2 0 exposes the solder resist layer 2 3 , wherein the exposed end portion 2 2 on the surface 2 1 0 (upper surface) of the layer 2 is used as a bond finger in a subsequent process, and is located at the core The exposed end portion 220 on the surface 212 (lower surface) of the layer 21 serves as a solder ball pad (ba 1 1 pa ^ ) in a subsequent process. The solder resist layer 2 3 opens a continuous peripheral portion 2 上 on the upper surface 210 of the core layer 2 1 through a hole 2 3 贯穿 extending through the solder resist layer 23; the lower portion of the second layer is shown in FIG. The simplified top view (not drawn to scale) is primarily used to display the open cell 2 30 of the solder resist layer 23 or the exposed peripheral portion 211 on the core layer 21. Then, as shown in FIG. 2, a molding process is performed, and a package mold 3 having an upper mold 30 and a lower mold 31 is used, wherein the upper mold 3 is opened and provided with a concave mold cavity (uPwardb). —recessed cavity 32. From the cross-sectional view, a protrusion 33 is preferably formed at a corner above the inner side of the upper die cavity 32 (i.e., a corner closer to a central portion of the die 3). The substrate 2 is placed in the package mold 3 so as to be sandwiched between the upper mold 3 and the lower mold 3, and the upper mold cavity 32 is corresponding to the continuous peripheral portion 211 on the core layer 21 of the substrate 20. The width of the upper concave cavity 3 2 is smaller than the width of the anti-flux layer 23, and the width of the opening 2 3 0 is about 1·1 to 1 mm, preferably 0.5 mm, so that a resist layer 2 3 and an upper mold are used. 3 〇 疋 之 之 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Product.ptd Page 12 1255560 V. INSTRUCTIONS (7) ^^ ——— --- The thickness of the agent layer 23 (about 25 to 50 mm). Then, the feather (for example, an epoxy resin, etc.) is injected onto the upper surface of the upper die 63 and the anti-flux layer 23 to refill the opening 23 The continuous peripheral portion 21 is formed on the upper side - the package junction = the resin compound flows into the portion A of the opening 230 and is close to the solder resist f/true edge. 'The resin compound is fast due to the small space of the portion A: % The heat from the encapsulating mold 3 increases the viscosity and thus lowers it = $ & therefore 'the resin compound will stay in the part A without further, only the glue (f 1 ash ) to the opening 2 3 0 Or the interface between the upper mold 30 and the substrate 20/the predetermined area on the US board 20, such as the wafer connection area, is not dyed by the resin overflow. / / When the resin compound is cured, the package mold 3 can be removed from the substrate 20, thus completing the package dam structure 25, as shown in Fig. 2C. The package dam structure 2 5 is directly formed on the core layer 2 1 of the substrate 20, and includes a shoulder portion 26 and a protruding support portion 27. The shoulder portion 26 corresponds to the opening portion 203 portion A' filled with the resin compound so that the shoulder portion 26 abuts the solder resist layer 23 and is flush with the solder resist layer 23. The support portion 27 corresponds to the upper cavity 3 2 of the upper mold 30 filled with the resin compound, and the support portion 27 surrounds the shoulder portion 26 and surrounds a space B on the substrate 20. Since the upper right corner of the upper concave cavity 3 2 has the projection 3 3 , a corresponding recessed portion 210 is formed at the inner upper corner of the formed support portion 27 . As shown in FIG. 2C, after the package dam structure 25 is completed, at least one photo-sensitive wafer 24, such as a complementary metal oxide semiconductor (CMOS) wafer, is placed on the substrate 20 and the wafer 24 is placed on the substrate. When the dam structure is surrounded by 25 spaces.

] 7715 石夕品.ptd Page 13 1255560 V. Description of the Invention (8) The wafer 24 has a plurality of electronic components (not shown), lines (not shown) and pads 2 4 2 of the active surface 2 4 〇 and a non-active surface 241 are bonded to the substrate 2 。. Then, a solder wire (wlre-b〇ndlng) process is performed to form and solder a plurality of bond wires 291, such as gold wires, to the pads 2 4 2 on the active surface 240 of the wafer 24 and the substrate 2 0 core layer 2 1 The exposed end of the upper surface 210 or the solder tab 22 is used to electrically connect the wafer 24 to the substrate 20. As shown in Fig. 2D, a cover member 2 is attached to the support portion 27 of the dam structure 2 5 to adhere the 4 cover member 2 8 to the recess portion 2 7 of the support portion 27 to cover The space B+ is accommodated, and the wafer 24 and the bonding wire 291 are accommodated in the space B surrounded by the dam structure 25, the base 285 and the dam member 28. Therefore, the wafer 24 and the bonding wire 291 are borrowed from the splicing member 28 The external environment is airtight. The cover member 28 can be made of a translucent material that allows light to pass through the cover member 28 to reach the wafer 24 for operation of the crotch panel 24. Finally, implant most of the solder balls 2 9 外 on the exposed end of the lower surface of the substrate 2 2 2 2 2 or the solder ball pad 2 2 〇, the solder ball 2 9 〇 as a different input / output ^ / (seven) ^ call The seven/(10) soil is called "end" so that the wafer can be electrically connected to an external device such as a printed circuit board (not shown), the semiconductor package. ^ Square, in another embodiment, the semiconductor package of the present invention can be batch The (bat = h) mode is obtained by the process steps shown in the μ to 3D. First, as shown in FIG. 3A, a substrate piece 2 composed of a plurality of array-arranged substrates 20 is prepared. The structure of the crucible is the same as that of the above-mentioned FIG. 2a, and therefore will not be described here, and the solder resist layer 2 3 has a grid-like opening 2 3 0' to expose the corresponding surface of the upper surface 21 of the core layer 21 2〇

17715 Shi Xipin. Routine (1

1255560 V. Description of the invention (9) A continuous peripheral portion 2 1 1 . Then, as shown in Fig. 3B, the encapsulating gel c composed of the mold pressing and/or dam structure 25 is formed, and each of the barriers is formed by a continuous peripheral portion 2 of the substrate 20 which is a plurality of substrates. The same structure 2 5 is located in each pair including a shoulder portion 26 and a protruding support portion 27, each dam structure 25 agent layer 23 and flush with the solder resist layer 23 and the Z 2, 26 adjacent to the rejection The weld 26 surrounds an empty B on the substrate 2, and the teeth 27 are connected around the shoulder 25 by its branch portion 27. A pair of connected Zhongmu, the dam structure part 2 7 0 bamboo in f屮 夕念-士牙# 2 7 is better to make it sag, for example compared to the dividing line (Figure Ζ ί ^ support The recessed portion 27 of the portion 27 is at the upper right corner, and the recess portion of the left support portion 27 is at the upper left corner. After that, at least one photo-sensitive wafer 24 is placed on each substrate 2〇 and the The cymbal 24=in the space β surrounded by the corresponding dam structure 25, the wafer 24 is electrically connected to the substrate by a plurality of bonding wires 形成 formed on the upper surface 2丨〇 of the core layer 2 2 〇, replanting most of the solder balls 2 9 外 on the exposed end of the lower surface 2 1 2 of each substrate 2 〇 core layer 2 1 or solder balls 塾 2 2 〇. Eight as shown in Figure 3 (: All the single (3111 § 11181: 丨〇 11) processes cut the adjacent support portions 27 and the substrate sheets 2 of the adjacent dam structure 25 along the knife boundary line (the dotted line shown in FIG. 3) to separate the substrates 2 Finally, as shown in FIG. 3D, a cover member 28 is attached to the support portion 27 of the block structure 25 on each of the substrates 20 so that the respective wafers 24 are accommodated. The shed structure 2 5, the substrate 2 0 And the space B surrounded by the cover member 28. Thus, most of the individual semiconductor packages of the present invention are completed. The above-described semiconductor package of the present invention has many advantages.

177]5 .品.ptd Page 15 1255560 V. The invention description ( ίο) is formed in the sapling due to the welding body, not exposed by the dam production layer, and the effect is outside, the blocking agent dam Adding a piece of semi-functional hole to join the welding die when the crystal is added to ensure that it is open to the touch plate and the refusal to form a rim, and it is true that the layer of the effect layer of the layer is effective. Installed as the layer of the original welding and the construction of the seal, the agent. , the art refused to pick up the welding of the knot and the domain domain Ming technology borrowed straight, the dam week due to the rejection of the district area of the project to support the support, near heat dye. This layer is formed without the support of the smear, and the core dam material avoids the width of the structure and has a slab of rubber. The slab is capable of splicing. The hole mold base is overflowing. Heji is the core and the core dam is m) From the case of the opening and receiving of the tree, the outbound 5 is a case of the outside. Into the force and dew into the hole into the power, the shape is io flow suction open plate and only the upper layer of the hairline is used to ^J speed of the basic example of the composition of the core, with (# As soon as the Lai Shi knotting part and the intermediaries are in the m-chemical glue, the real-life field side plate and the large lm fat spillover are described in the block base. There are _ tree meeting pieces, and the dam is installed. The layer 1 has not been replaced by a non-encapsulated barrier.

The above and other objects, features and advantages of the present invention will become more apparent and understood. The embodiments of the present invention are described in detail with reference to the accompanying drawings, and the accompanying drawings are briefly described as follows: FIG. 1 is a cross-sectional view of the semiconductor package of the present invention; FIGS. 2A to 2D are shown in FIG. Schematic diagram of a set of process steps of a semiconductor package; FIGS. 3A to 3D are diagrams showing another set of process steps of the semiconductor package shown in FIG. 1; and FIG. 4 is a cross-sectional view of a conventional semiconductor package. 11 Substrate 12 Solder wire 13 Encapsulant 14 Hole 15 Cover 2 Substrate 20 Substrate 21 Core 210 Surface (upper surface) 211 Peripheral portion 212 Surface (lower surface) 22 Conductive trace 220 End 221 Conductive penetration L 23 Retaining agent layer 230 > 2 3 0' opening 24 wafer 240 active surface 241 non-active surface 242 pad 25 package dam structure 2 6 shoulder 27 support 270 recess 28 cover

177] 5 Shi Xi Pin.ptd Page 17 1255560

]77] 5 Shi Xi Pin.ptd Page 18

Claims (1)

1255560 6. Patent application scope 1. A semiconductor package having a photo-sensitive wafer, comprising: a substrate having a core layer, a plurality of conductive traces being formed on at least one surface of the core layer, each of the conductive traces having An end portion, wherein a solder resist layer is applied on the surface of the core layer to cover the conductive trace, and the solder resist layer is exposed outside the end portion, and the solder resist layer has an opening to expose the core a continuous peripheral portion on the surface of the layer; at least one photo-sensitive wafer attached to the substrate and electrically connected to the exposed end portion of the conductive trace; a package dam structure formed in a continuous peripheral portion of the core layer And surrounding the wafer, wherein the dam structure comprises a shoulder portion and a protruding support portion, the shoulder portion is adjacent to the solder resist layer and flush with the solder resist layer, and the support portion surrounds the shoulder portion and Having a height greater than the thickness of the wafer; and a cover member attached to the support portion of the dam structure to cover the dam structure, such that the wafer is received by the substrate, the dam structure and the cover member Surrounded In the space. 2. The semiconductor package of claim 1 of the patent application, comprising a plurality of solder balls, implanted on the substrate opposite to one side of the wafer. 3. The semiconductor package of claim 1, wherein the shoulder of the dam structure has a width of from 1 to 1 mm. 4. The semiconductor package of claim 3, wherein the shoulder has a width of 0.5 m. 5. The semiconductor package of claim 1 of the patent scope, wherein each end portion 17715 石夕品.口士(] Page 19 1255560 VI. Patent application scope as a welding finger for soldering wire for electrically connecting a wafer to a substrate. 6. Semiconductors as claimed in claim 1 a package, wherein the core layer is made of a material selected from the group consisting of epoxy resin, polyamidamine resin, BT (bismaleimide triazine resin, and FR 4 resin). A semiconductor package, wherein the cover member is translucent. 8. The semiconductor package of claim 1, wherein the dam structure is made of a resin compound. 9. A semiconductor having a photo-sensitive chip The method for manufacturing a package comprises the following steps: 'Preparing a substrate having a core layer, a plurality of conductive traces are formed on at least one surface of the core layer, each of the conductive traces having one end portion, and a solder resist layer is disposed on the substrate The conductive layer is covered on the surface of the core layer, and the solder resist layer is exposed outside the end portion, wherein the solder resist layer is provided with an opening to expose a continuous peripheral portion on the surface of the core layer. Forming a package dam structure on a continuous peripheral portion of the core layer, wherein the dam structure includes a shoulder portion and a protruding support portion adjacent to the solder resist layer and flush with the solder resist layer And the support portion surrounds the shoulder and defines a space surrounded by the dam structure; at least one photo-sensitive wafer is attached to the substrate and the wafer is placed ]77〗 5 Shi Xipin. Mouth (1 page 20, 1255560) 6. The patent application scope is in the space surrounded by the dam structure, and electrically connects the wafer to the exposed end of the conductive trace; A cover member is disposed on the support portion of the dam structure to cover the collapse structure ′ so that the wafer is received in a space surrounded by the collapse structure, the substrate and the cover member. The method of claim 9 further comprises implanting a plurality of solder balls on the substrate opposite to one side of the wafer. 1 1. The method of claim 9 wherein the dam structure shoulder The width of the portion is from 0.1 to 1 mm. 1 2 . The method of claim 11, wherein the width of the shoulder is 0.5 mm 〇1 3. The method of claim 9 of the patent application, wherein each The end portion is used as a welding finger for soldering a wire for electrically connecting the wafer to the substrate. The method of claim 9, wherein the core layer is selected from the group consisting of epoxy resin, Made of a material consisting of a group of polyamidosamine resin, BT resin and FR 4 resin. The method of claim 9, wherein the cover member is translucent. 16. The method of claim 9, wherein the dam structure is made of a resin compound. The method for manufacturing a semiconductor package of an inductive wafer comprises the steps of: preparing a substrate piece composed of a plurality of arrayed substrates, the substrate piece having a core layer, and forming a plurality of conductive traces on at least one surface of the core layer a line, each of the conductive traces having one end, and ] 77] 5石夕品.ptd Page 21 1255560 VI. The patent application scope lays a solder resist layer on the surface of the core layer to cover the conductive trace, so that the end portion exposes the solder resist layer. Wherein the solder resist layer is provided with an opening to expose a continuous peripheral portion of the substrate corresponding to the substrate; forming a package colloid composed of a plurality of dam structures, each of the dam structures being located on each corresponding substrate On the continuous peripheral portion, each of the dam structures includes a shoulder portion and a protruding support portion adjacent to the solder resist layer and flush with the solder resist layer, and the support portion surrounds the shoulder portion Defining a space surrounded by the dam structure, and adjacent dam structures are connected by their support portions; at least one light-sensitive wafer is attached to each of the substrates and the wafer is surrounded by each dam structure And electrically connecting the wafer to the exposed end of the conductive trace; cutting the connected support portion of the adjacent dam structure and the substrate piece to separate the substrates; and connecting a cover member On the substrate A support structure portion of the upper dam to dam closed over the structure, so that the wafer is accommodated in a space defined by the dam structure, the substrate and surrounded by the cover member. 18. The method of claim 17, wherein the method comprises implanting a plurality of solder balls on each of the substrates with respect to one side of the wafer. 19. The method of claim 17, wherein the shoulder of the dam structure has a width of 0.1 to 1 mm. 2 0 . The method of claim 19, wherein the width of the shoulder is 0. 5 mm 〇 ] 7715石夕品. 口士(1 page 22 1255560 VI. Patent application scope 2 1. For the method of claim 17 of the patent application, each of the ends is used as a welding finger for welding thereon. A method of bonding a wafer to a bonding wire of a substrate. 2 2. The method of claim 17, wherein the core layer is a group selected from the group consisting of epoxy resin, polyamido resin, BT resin, and FR4 resin. The material of the group is made. 2 3. The method of claim 17, wherein the dam structure is made of a resin compound. 177] 5 Shi Xi Pin.ptd Page 23