TW200525768A - Semiconductor package with photosensitive chip and fabrication method thereof - Google Patents

Abstract

A semiconductor package with a photosensitive chip and a fabrication method thereof are provided. A substrate having a core is prepared. A solder mask layer is applied over a surface of the core and formed with an opening to expose a continuous peripheral portion on the surface of the core. At least one photosensitive chip is mounted on and electrically connected to the substrate. An encapsulation dam is formed on the continuous peripheral portion of the core and surrounds the chip. The dam includes a shoulder portion adjacent to and flush with the solder mask layer, and a protruded support portion surrounding the shoulder portion. A lid is attached to the support portion of the dam for sealing the dam such that the chip is received in a space defined by the substrate, the dam and the lid.

Description

200525768 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly to a light-sensitive semiconductor package provided with at least one light-sensitive chip such as a complementary metal-oxide-semiconductor (CMOS) , Complementary metal oxide semiconductor) chip, and manufacturing method of the semiconductor package. [Previous technology] A semiconductor package is an electronic device used to carry active components such as semiconductor wafers. Its structural characteristics are mainly that the wafer is placed on a substrate, and the wafer is electrically connected to the substrate by conductive elements (such as bonding wires). A substrate is formed on the substrate to form a packaging colloid made of a resin compound (such as epoxy resin, etc.) to cover the wafer and the bonding wire to protect it from external moisture and pollutants. The packaging colloid is usually opaque, so light-sensitive wafers that require light to operate, such as complementary metal-oxide-semiconductor (CMOS) wafers, are not suitable for this type of semiconductor package. In view of this, U.S. Patent No. 6,590,269 discloses a semiconductor package having an improved structure of a packaging colloid that allows light to reach a light-sensitive chip (as shown in FIG. 4). The light-sensitive chip 10 is connected to a substrate 1 1 and is electrically connected to the substrate 11 by a plurality of bonding wires 12. An encapsulating gel 13 is formed on the substrate 11 and has a wall structure surrounding the wafer 10 and the bonding wires 12. The encapsulating gel 13 having a wall shape forms a cavity 14 to receive the wafer 1. 0 和 焊线 1 2. A cover member 15 is placed on the packaging gel 13 to cover the cavity 14 so that the wafer 10 and the bonding wire 12 can be hermetically isolated from the outside atmosphere. The cover 15 is made of a light-transmissive or transparent material that allows light to penetrate therethrough and reach the wafer 10 for the wafer 10 to operate; thus providing 11

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1III liil] 77] 5 Shi Xipin. Ptd Page 7 200525768 4 V. Description of the invention (2) A semiconductor package used for light-sensitive wafers. However, the above-mentioned semiconductor package may disadvantageously cause many disadvantages. The encapsulant system formed on the substrate is adhered to the solder resist layer (s ο 1 dermask) laid on the substrate. Due to the poor adhesion of the resin compound forming the encapsulant and the solder resist material and the contact between the encapsulant and the substrate The area is small, so it is easy to cause delamination (de 1 aminati ο η) between the packaging gel and the substrate, thereby reducing the reliability of the semiconductor package. In addition, since the encapsulation gel is formed on the substrate by molding (m ο 1 ding), the resin compound is easily spilled (f 1 ash) to the area of the substrate where the encapsulation colloid is to be formed during the molding operation, thereby contaminating the layout. The solder fingers (b ο ndfinger) on the substrate, so the bonding wire cannot be soldered to the contaminated solder fingers well, resulting in low quality of the electrical connection between the chip and the substrate. Therefore, how to provide a semiconductor package with a light-sensitive chip, which can improve the adhesion between the packaging gel and the substrate and avoid the occurrence of glue overflow on the substrate, is an important issue. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package having a light-sensitive chip and a method for manufacturing the same, which can improve the adhesion between the substrate and the packaging dam structure formed thereon, so as to avoid the substrate and the package from collapsing. Delamination e 1 aminati (η) occurred between the structures. Another object of the present invention is to provide a semiconductor package with a light-sensitive chip and a manufacturing method thereof, which can prevent the resin compound used to form the packaging dam structure from overflowing onto the substrate, thereby ensuring the reliability of the semiconductor package and Electrical connection quality.

] 77] 5 Shi Xipin · ptd Page 8 200525768 V. Description of the Invention (3) In order to achieve the disclosure and other §s of the present invention, a semiconductor package with a light-sensitive chip includes a substrate and a core layer. A plurality of conductive traces are formed on at least one surface of the core layer. Each of the conductive traces has one end portion, and a solder resist layer is laid on the surface of the core layer to cover the conductive traces so that the end portions are outside. The solder resist layer 9 is exposed and a continuous peripheral portion on the surface of the core layer is exposed beyond the opening of the solder resist layer; at least one light-sensitive chip is placed on the substrate and electrically connected to the conductive trace. Exposed end --- the enclosing dam structure is formed on the continuous peripheral portion of the core layer and surrounds the wafer 9 wherein the dam structure includes a shoulder and a protruding support A shoulder portion is adjacent to the solder resist layer and is flush with the solder resist layer, and the support portion surrounds the shoulder portion and has a thickness greater than 1¾ degrees of the wafer thickness, and a cover member is connected to the support portion of the dam structure to seal The dam structure is covered so that the wafer is accommodated in the space surrounded by the dam structure and the cover of the substrate, and most solder balls are planted on one side of the substrate with respect to one side of the wafer. The method for exposing a semiconductor package includes the following steps: Preparation — A substrate having a core layer has a plurality of conductive traces formed on at least one surface of the core layer, and each of the conductive traces has one end portion and is applied with -in. 6 A flux layer is on the surface of the core layer to cover the conductive traces so that the end portion exposes the solder resist layer, wherein the solder resist layer has an opening outside to expose the surface of the core layer. < A continuous peripheral portion 5 on the core layer is formed on a continuous peripheral portion of the core layer 5 wherein the dam structure includes a shoulder and a sudden support portion, and the shoulder is adjacent to the solder resist. Layer and is flush with the solder resist layer while the support surrounds the shoulder and is defined as a void surrounded by the dam structure ___

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III] 77] 5 Shi Xipin.]] 1 () Page 9 200525768 V. Description of the Invention (4); At least the exposed end of the envelope of the dam structure covers the dam junction and the cover. The surrounding semiconducting structure is formed on the part with the crystal connected, so that the core layer 1 is adhered by the tree, or it is exposed to form a mm (preferably 0 · 5 lipid compound inflow) Reliability and electrical implementation for quickly absorbing spilled glue to the opening and then placing it on the substrate] The following is one of the applications of the present invention, which is familiar with this technology. Shed collapse structure made of grease material to avoid the continuous dam structure support width of the core layer (mm); the openings are connected in parallel to the outer surface of the mold and the quality of the overflowing adhesive connection on the substrate

A light-sensitive chip is on the substrate and the chip is located in the surrounding space, and the chip is electrically connected to the conductive track; a cover is connected to the support portion of the dam structure for sealing, and There are many advantages to accommodating the wafer in the space of the dam structure and the substrate; and to plant most solder balls on the substrate. One is to encapsulate the dam. The continuous perimeter exposed through the opening of the solder resist layer directly contacts the core layer. Due to the dam structure, it is necessary to effectively promote the delamination between the dam structure and the substrate. The peripheral portion of the solder resist layer opening has most of the mold cavity of the packaging mold approximately 0.1 to 1, so when the tree forming the dam structure is near the edge of the solder resist layer, the resin combines heat to make it sticky. Sexual increase, and therefore not the area. In view of this, the chip and the bonding wire will not stain the area, so that it can ensure that the semiconductor package is described by a specific specific embodiment of the present invention. Persons can easily understand the advantages and effects from the content disclosed in this specification. The present invention may also have other different implementations or applications, and the details in this specification may also be based on __] 77] 5 silicon products. Ptd page 10 200525768 V. Description of the invention (5) Different viewpoints and applications, Various modifications and changes can be made without departing from the spirit of the invention. As shown in FIG. 1, the semiconductor package of the present invention includes a substrate 20 having a core layer 21 and a plurality of conductive traces 2 2 formed on at least one surface 2 1 0 of the core layer 21. Each conductive trace 22 has one end portion 2 2 0, and a solder resist layer 23 is laid on the surface 2 1 0 of the core layer 21 to cover the conductive trace 2 2 so that the end portion 2 A solder resist layer 23 is exposed at 2 0, and the solder resist layer 23 is provided with an opening 2 3. A continuous peripheral portion 2 1 1 on the surface 2 1 0 of the core layer 2 is exposed outside; at least one light-sensitive wafer 24, connected to the substrate 20 and electrically connected to the exposed end 2 2 of the conductive trace 2 2; the package dam structure 25 is formed on the continuous peripheral portion 2 1 of the core layer 2 1 The dam structure 25 includes a shoulder portion 26 and a protruding support portion 27. The shoulder portion 6 is adjacent to the solder resist layer 23 and is in contact with the solder resist layer 2 3. Flush, and the support portion 27 surrounds the shoulder portion 26 and has a height greater than the thickness of the wafer 24; a cover member 28 is connected to the support portion 27 of the dam structure 25 to cover the Dam structure 2 5 while making crystal The sheet 24 is housed in a space B surrounded by the substrate 20, the dam structure 25, and the cover member 28; and most of the solder balls 290 are planted on the substrate 20 with respect to the wafer 2 4 on one side. The above semiconductor package can be manufactured by the process steps shown in FIGS. 2A to 2D. First, as shown in FIG. 2A (cross-sectional view and simplified upper view), a substrate 20 having a core layer 21 is prepared. The core layer 21 may be made of epoxy resin, polyurethane resin, BT (bis ni a 1 eimidetriazine) resin or FR 4 resin. Shapes on the opposite surfaces 2 1 0, 2 1 2 of the core layer 2 1 2

] 77] 5Shi Xipin.ptd Page] 1 200525768 • Fifth, the description of the invention (6). A plurality of conductive traces 22 are formed so that each conductive trace 22 has one end 2 2 0; the opposite surface 2 1 The conductive traces 2 on 0, 2 1 2 are electrically connected to each other through the conductive through holes 2 2 1. The conductive trace 22 is completed by conventional techniques such as exposure (e X ρ s s u r e), development (development), and etching (e t ch i ng), so it will not be repeated here. Next, a solder resist layer 2 3 (having a thickness of about 25 to 50 mm) is respectively laid on the surfaces 2 1 0 and 2 1 2 of the core layer 2 to cover the conductive traces 2 to make the conductive traces. The solder resist layer 23 is exposed at the end 2 2 0 of the wire 2 2, and the exposed end 2 2 0 on the surface 2 1 0 (upper surface) of the core layer 2 is used as a bonding finger in subsequent processes. ), And the exposed end portion 2 2 0 located on the surface 21 2 (lower surface) of the core layer 21 is used as a fresh ball pad (ba 1 1 pad) in subsequent processes. The solder resist layer 23 opens a continuous peripheral portion 2 1 1 on the upper surface 2 1 0 of the core layer 21 outside the opening 2 3 0 penetrating through the solder resist layer 23; The simplified upper view (not drawn to scale) is mainly used to show the open holes 2 3 0 of the anti-fluorescent agent layer 2 3 or the continuous peripheral portion 2 1 1 exposed on the core layer 2 1. Then, as shown in Figure 2B, a molding process is performed, using a packaging mold 3 having an upper mold 30 and a lower mold 31, wherein the upper mold 30 has an upper cavity (uPwardly) -recessed cavity) 32, from a sectional view, it is preferable that a protruding portion 33 is formed at a corner above the inner side of the upper concave cavity 32 (ie, a corner closer to the central portion of the mold 3). The substrate 20 is placed in the packaging mold 3 to be sandwiched between the upper mold 30 and the lower mold 31, and the upper cavity 32 is corresponding to the continuous peripheral portion on the substrate 20 core layer 21. 2 1 1. The width of the upper cavity 32 is smaller than that of the solder resist layer 23 and the width of the openings 2 3 0 is about 0 mm to 1 mm, preferably 0.5 mm. The opening defined by 3 〇 2 3 0 The space of part A is small and its size corresponds to rejection of freshness

] 77] 5 silicon products.]: ^ (1 page) 2 200525768 V. Description of the invention (7) ——---- thickness of the agent layer 23 (approximately 25 to 50 mm). The face of the signature A compound (such as epoxy resin, etc.) is injected onto it; or a conventional resinization is to be found in the upper cavity 32 of the upper bismuth 30 and the upper cavity 6 3 2 and the solder resist layer 2 3 Μ a 〇q η,

Du μ ^ 4 _, true & opening 23, in order to form a package dam structure 25 at the core layer of the substrate 20, ′, σ σ up to σ points 2 1 1. When the resin compound flows into the portion A of the opening 2 3 0 and is close to the edge of the solder resist layer 23 'because the space of the portion A is small, the resin compound quickly absorbs heat from the packaging mold 3 and makes it sticky Increase and therefore decrease its flow rate. Therefore, the 'resin compound will stay in part A without further flashing to the outside of the opening 2 30 or to the interface between the upper mold 30 and the substrate 20, so a predetermined area on the substrate 20 such as a wafer receiving area That is, it will not be contaminated by resin overflow glue. After the resin compound is cured, the packaging mold 3 can be removed from the substrate 20, so that the packaging dam structure 25 is completed, as shown in FIG. 2C. The packaging dam structure 25 is directly formed on the core layer 21 of the substrate 20, and includes a shoulder portion 26 and a protruding support portion 27. The shoulder portion 26 corresponds to the opening 2 3 0 portion A filled with the resin compound, and the shoulder portion 6 is adjacent to the solder resist layer 23 and is flush with the solder resist layer 23. The support portion 27 corresponds to the upper cavity 32 of the upper mold 30 filled with the resin compound, and the support portion 27 surrounds the shoulder portion 26 and surrounds a space B on the substrate 20. Since the upper right corner of the upper cavity 32 has a protruding portion 3 3, a corresponding recessed portion 2 70 is formed at the upper upper corner of the inner side of the support portion 27. As shown in FIG. 2C, after the packaging dam structure 25 is completed, at least one light-sensitive wafer 24 such as a complementary metal-oxide-semiconductor (CMOS) wafer is placed on the substrate 20 and the wafer 24 is located in the dam. In the space B surrounded by the dam structure 25.

] 77] 5Shi Xipin.ptd Page] 3 200525768 V. Description of the invention (8) The wafer 2 has a function surface 24 with most electronic elements (pattern) and pads 242 = /), wiring (not B 4 uw and a relative non-book idler 241, so that the non-active surface 241 is adhered to the substrate 20. Then, a wire-bonding process is performed, such as gold wire to the active surface 24 of the chip 24 The stubborn stem 9 on 0> | The exposed end of the upper surface 210 or the welding finger 2 of the 291 cases of the bonding wire, and the core layer 21 of the dry substrate 20 is connected to the substrate 20. 22, which makes the wafer 24 electrically Even as shown in FIG. 2D, the connection-covering member 28 is attached to the support portion 27 of the collapsed structure 25, so that the support member 28 is adhered to the selection portion and the recessed portion 2? 〇 is space #, and The wafer 24 and the bonding wire 291 are housed in a space clock surrounded by the collapsing structure 25, the main board 20, and the cover 28, so the chip 24 and the bonding wire 29iJ and the cover 28 are hermetically isolated from the external environment. The cover 28 can be made of translucent or transparent material, so that light can penetrate the cover 28 and reach the wafer 24 for operation of the wafer 24. Finally, a plurality of solder balls 29 are planted on the substrate 20 and the core layer 2 1 The exposed end on the lower surface 2 1 2 or the solder ball pad 2 2 0. The solder ball 2 9 0 is used as an input / output (I / O, input / output) terminal so that the chip 24 can communicate with external devices such as printed circuits. The board (not shown) is electrically connected, so that the semiconductor package of the present invention is completed. In another embodiment, the semiconductor package of the present invention can be batched from 3A to 3D It is made by the process steps shown in the figure. First, as shown in FIG. 3A, a substrate sheet 2 composed of a plurality of substrates 20 arranged in an array is prepared, and the structure of the substrate 20 is the same as that shown in the foregoing FIG. 2A, so it will not be repeated here. While the solder resist layer 2 3 is provided with a grid-like opening 2 3 0 ′, the upper surface 2 1 of the core layer 2 1 is exposed corresponding to each substrate 20

] 77] 5 Shi Xipin. Ptd Page 14 200525768 V. Description of the invention (9) A continuous peripheral part 21 1 Bu Then, as shown in Figure 3B, a molding process is performed to form a majority of the collapsed structure 25 The encapsulating colloid c, each of the collapsing structures is put on the continuous peripheral portions 21 of each pair 2 3 20]. Similarly, each dam structure μ dagger-shoulder 26 and a protruding support portion 27, Yan Hai shoulder portion 26 is adjacent to: layer two! The solder resist layer 23 is uniform, and the supporting portion 27 surrounds the shoulder portion 9 and the space B on the base plate 20, and the adjacent dam structure 25 is connected by its supporting portion 27. -For the connected support portion 27, its recess j 2 70 is preferably located at the exposed corner. For example, compared with the dividing line (the dotted line shown in the figure), the recessed portion 27 of the right support portion 27 is located at The upper right corner, and the recessed part 27 of the left support part 27 is located at the upper left corner. Then, at least one light-sensitive wafer 24 is placed on each substrate 20 and the wafer 24 is placed in the space b surrounded by the corresponding dam structure 25. The wafer 24 is formed by a majority on the rage layer 2 丨The bonding wires 2 9 on the upper surface 2 丨 are electrically connected to the substrate 20, and then a plurality of solder balls 2 9 〇 are planted on each substrate 2 〇 core layer 2 丨 exposed ends on the lower surface 2 1 2 or welding Ball 2 2 0. As shown in Fig. 3C, 'single order (s 丨 ngu 1 a ^ 丨 0 n) process is performed, and the supporting portions 2 adjacent to the dam structure 25 are cut along the dividing line (dashed line shown in Fig. 3B). 7 and the substrate sheet 2 to separate each substrate 20. Finally, as shown in FIG. 3D, a cover member 2 8 is connected to the supporting portion 27 of the dam structure 25 on each substrate 20, so that each wafer 24 is placed in the corresponding dam. In the space B surrounded by the structure 25, the substrate 20, and the cover 28. This completes most individual semiconductor packages of the present invention. The semiconductor package of the present invention described above has many advantages. One is

1 1 I! Ί I 1 ί 1 1 iJrj 1 Page 15 200525768 'Fifth, description of the invention (ίο) The packaging dam structure is formed on the continuous peripheral portion of the substrate core layer exposed by the opening of the solder resist layer, and The dam structure is in direct contact with the core layer. Because the dam structure and the core layer are made of resin material, the adhesion between the dam structure and the substrate can be effectively improved, and the dam structure and the substrate can be avoided. Delamination occurs. Further, the opening of the solder resist layer for exposing the continuous peripheral portion of the core layer has a cavity larger than about 0.1 to 1 mm (preferably 0.5 mm) of the packaging mold cavity used to form the dam structure support portion. Width, so when the resin compound used to form the dam structure flows into the opening and approaches the edge of the solder resist layer, the resin compound will quickly absorb the heat from the mold and increase its viscosity, because | Area outside the opening and on the substrate. In view of this, the chip and the bonding wire will not be connected to the contaminated area on the substrate, so it can ensure the reliability of the semiconductor package and the quality of the electrical connection. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the protection of the rights of the present invention should be as listed in the patent application scope mentioned later.

] 77] 5 Silicon products · ptd Page 16 200525768 Simple illustration of the drawings [Simplified illustration of the drawings] In order to make the above and other objects, features, and advantages of the present invention more obvious and easier to understand, it will cooperate with the preferred embodiments The attached drawings describe the embodiments of the present invention in detail, and the contents of the attached drawings are briefly described as follows: FIG. 1 is a cross-sectional view of the semiconductor package of the present invention; FIGS. 2A to 2D are the semiconductor package shown in FIG. Figures 3A to 3D are schematic diagrams of another set of process steps of the semiconductor package shown in Figure 1; and Figure 4 is a cross-sectional view of a conventional semiconductor package. 10 Wafer 11 Substrate 12 Welding wire 13 Encapsulant 14 Cavity 15 Cover 2 Substrate piece 20 Substrate 2 1 Core layer 210 Surface (upper surface) 21 1 Peripheral portion 212 Surface (lower surface) 22 Conductive trace 220 End 221 Conductive Shell hole 23 Solder resist layer 2 3 0 > 2 3 0, Opening hole 24 crystal M 240 Active surface 241 Non-active surface 242 Solder pad 25 Encapsulation dam structure 26 Shoulder 27 Support 270 Depression 28 Cover

] 77] 5 Shi Xipin.ptd Page] 7 200525768

Brief description of the drawing. 290 solder ball 291 welding line 3 packaging mold 29 upper mold 30 lower mold 31 upper concave cavity 32 protruding part A part B space C packaging gel] 77] 5 Shi Xipin. Ptci page 18

Claims (1)

200525768 VI. Application for patent scope 1. A semiconductor package with a light-sensitive chip, comprising: a substrate having a core layer, and a plurality of conductive traces formed on at least one surface of the core layer, each of the conductive traces having At one end, one of the solder resist layers is laid on the surface of the core layer to cover the conductive traces, so that the end portion exposes the solder resist layer, and the solder resist layer has an opening outside to expose the core. A continuous peripheral portion on the surface of the layer; at least one light-sensitive chip connected to the substrate and electrically connected to the exposed end of the conductive trace; a package dam structure formed on the continuous peripheral portion of the core layer The dam structure includes a shoulder portion and a protruding support portion, the shoulder portion is adjacent to the solder resist layer and is flush with the solder resist layer, and the support portion surrounds the shoulder portion and Having a height greater than the thickness of the wafer; and a cover member connected to a support portion of the dam structure to cover the dam structure so that the wafer is accommodated in the substrate, the dam structure and the cover member package Space. 2. For example, the semiconductor package of claim 1 includes a plurality of solder balls, which are implanted on the substrate with respect to a side on which a wafer is connected. 3. The semiconductor package of claim 1, wherein the width of the shoulder of the dam structure is 0.1 to 1 mm. 4. The semiconductor package of claim 3, wherein the width of the shoulder is 0.5 mm. 5. If the semiconductor package of the first scope of the application for a patent, wherein each of the ends ] 77] 5 Silicon Product.ptd Page 19 200525768 6. Scope of Patent Application As a soldering finger, there are welding wires for electrically connecting the chip to the substrate. 6. The semiconductor package according to item 1 of the application, wherein the core layer is made of a material selected from the group consisting of epoxy resin, polyurethane resin, BT (bismaleimide triazine) resin and FR4 resin. . 7. The semiconductor package of claim 1, wherein the cover is translucent. 8. The semiconductor package of claim 1, wherein the dam junction I structure is made of a resin compound. A method for manufacturing a semiconductor package with a light-sensitive chip, comprising the following steps: preparing a substrate having a core layer, and forming a plurality of conductive traces on at least one surface of the core layer, each of the conductive traces having one end portion, A flux resist layer is laid on the surface of the core layer to cover the conductive traces, so that the end portion exposes the flux resist layer, wherein the flux resist layer is provided with an opening outside the core layer to expose the surface of the core layer. A continuous peripheral portion; forming a packaged dam structure on the continuous peripheral portion φ of the core layer, wherein the dam structure includes a shoulder and a protruding support portion, the shoulder is adjacent to the solder resist layer and is in contact with the solder resist layer; The solder resist layer is flush, and the support portion surrounds the shoulder and defines a space surrounded by the dam structure; at least one light-sensitive wafer is placed on the substrate and the wafer is positioned ] 77] 5 silicon product.ptd page 20 200525768 6. The scope of the patent application is in the space surrounded by the dam structure, and the chip is electrically connected to the exposed end of the conductive trace; and a cover is connected. The support structure of the dam structure is used to cover the dam structure, so that the chip is accommodated in a space surrounded by the dam structure, a base plate and a cover member. 10. The manufacturing method according to item 9 of the scope of patent application, further comprising planting a plurality of solder balls on the substrate with respect to one side of the wafer. 11. The manufacturing method according to item 9 of the scope of patent application, wherein the width of the shoulder of the dam structure is 0.1 to 1 mm. 1 2. As for the manufacturing method of item 11 of the patent application scope, wherein the width of the shoulder is 0.5 mm 〇1 3. As for the manufacturing method of item 9 of the patent application scope, each of the ends is used as a welding finger for welding on it Designed with bonding wires for electrically connecting the chip to the substrate. 14. The manufacturing method according to item 9 of the scope of patent application, wherein the core layer is made of a material selected from the group consisting of epoxy resin, polyurethane resin, B T resin and F R 4 resin. 1 5. The manufacturing method according to item 9 of the scope of patent application, wherein the cover is transparent. 16. The manufacturing method according to item 9 of the scope of patent application, wherein the dam structure is made of a resin compound. 1 7. A method for manufacturing a semiconductor package with a light-sensitive wafer, including the following steps: preparing a substrate sheet composed of a plurality of substrates arranged in an array, the substrate sheet having a core layer, and at least one of the core layers; A plurality of conductive traces are formed on the surface, each of the conductive traces has one end portion, and ] 77] 5 Silicon Product.ptd Page 2] 200525768 • Sixth, the scope of patent application. Laying a solder resist layer on the surface of the core layer to cover the conductive traces, so that the end portion exposes the solder resist layer, wherein the solder resist layer is provided with an opening outside to expose the corresponding layers on the surface of the core layer. A continuous peripheral portion of the substrate; forming a sealing gel composed of a plurality of dam structures, each of the dam structures is located on a continuous peripheral portion of each corresponding substrate, wherein each of the dam structures includes a shoulder and a A protruding support portion, the shoulder portion is adjacent to the solder resist layer and is flush with the solder resist layer, and the support portion surrounds the shoulder portion and defines a space surrounded by the dam structure, Φ and adjacent The dam structure is connected by its supporting portion; at least one light-sensitive chip is connected to each of the substrates so that the chip is located in a space surrounded by each of the dam structures, and the chip is electrically connected to the exposed conductive traces. An end portion; cutting a supporting portion of the adjacent dam structure and the substrate piece to separate each of the substrates; and a cover member is provided on the supporting portion of the dam structure on each of the substrates to cover the dam Dam structure while The wafer is housed in a space surrounded by the dam structure, the substrate, and the cover. 18. According to the manufacturing method of item 17 in the scope of patent application, the method includes planting a plurality of solder balls on each side of the substrate opposite to one side of the wafer. 19. The manufacturing method according to item 17 of the scope of patent application, wherein the width of the shoulder of the dam structure is 0.1 to 1 mm. 2 〇 As for the manufacturing method of item 19 in the scope of patent application, wherein the width of the shoulder is 0.5 mm 〇 ] 77] 5 Shi Xipin.ptd Page 22, 200525768 VI. Application for Patent Scope 2 1. According to the manufacturing method of No. 17 in the scope of patent application, each of the ends is used as a welding finger, and there is a soldering device for electrical properties. Wires connecting the die to the substrate. 22. The manufacturing method according to item 17 of the scope of patent application, wherein the core layer is made of a material selected from the group consisting of free epoxy resin, polyimide resin, B T resin and F R 4 resin. 2 3. The manufacturing method according to item 17 of the scope of patent application, wherein the dam structure is made of a resin compound. ] 77] 5 Shi Xipin · ptd Page 23