TW200939421A - Multi-window ball grid array package - Google Patents

Multi-window ball grid array package Download PDF

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Publication number
TW200939421A
TW200939421A TW097108583A TW97108583A TW200939421A TW 200939421 A TW200939421 A TW 200939421A TW 097108583 A TW097108583 A TW 097108583A TW 97108583 A TW97108583 A TW 97108583A TW 200939421 A TW200939421 A TW 200939421A
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TW
Taiwan
Prior art keywords
wafer
window
substrate
ball
grid array
Prior art date
Application number
TW097108583A
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Chinese (zh)
Inventor
Ming-Yao Chen
Original Assignee
Powertech Technology Inc
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Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW097108583A priority Critical patent/TW200939421A/en
Publication of TW200939421A publication Critical patent/TW200939421A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Disclosed is multi-window Ball Grid Array (BGA) package, primarily comprising a substrate with plural windows, a chip disposed on the substrate, a plurality of bonding wires, a molding compound and a plurality of spherical terminals. The bonding wires pass through the windows to electrically connect the chip with the substrate. The molding compound is formed in the windows and on the upper and lower surfaces of the substrate to encapsulate the chip and the bonding wires. It is characterized in that the substrate further has a plurality of clipped side boards on which the ball pads are disposed. The clipped side boards are not encapsulated by the molding compound. The spherical terminals are bonded to the ball pads to located outside of the molding compound. Accordingly, the clipped side boards are configured for symmetric clipping of top and bottom mold tools to solve the problem of contamination of the ball pads easily caused by mold flash over the plural windows.

Description

200939421 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種半導體裝置，特別係有關 種多窗口球格陣列封裝構造。 ’、有關於— 【先前技術】 在半導體封裝領域中，—種窗口球 (window ball grid arra , 裝構造200939421 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a multi-window ball grid array package structure. ‘,有约— 【Prior Art】 In the field of semiconductor packaging, the window ball grid arra

θ 8 arr^ Package, wBGA package) , A ❹ Ο 疋將用以承載晶片之電路基板開設有-個貫通之二 口：以便於允許金屬鲜線或是已知的電性連接元心 過由口，以電性連接基板與晶片。透過該窗口可 收藏金屬銲線與降低元件高度而減少封裝厚度 金屬銲線與晶片適當密封以達到保護效果。纟先進 進程演化中，為了達到高容量與尺寸微小化之要求的 應增加半㈣晶片的可堆疊數量以組合—多晶片封裝 構造，或疋晶片表面增加更多的微間距銲 筑*基' 板 的窗口數量亦會增加，然在壓模封膠過程中窗口數 量越多則越有模封溢膠至基板而污染到球墊的問題， 並且不可控制，嚴重影響封裝產品之可靠性。 美國專利第US 7,205,656號揭示一種窗口型球格陣 列封裝構造。如第i圖所示，該窗口型球格陣列封裝構 造100主要包含一基板110、一第一晶片12〇、複數個 第一銲線130、一封膠體140以及複數個球形端子15〇。 該基板110係具有一第一表面111、一相對之第-表面 112以及/貫穿該第一表面ill與該第二表面ιΐ2之中 6 200939421 央窗口 113’如狹長貫穿槽。該基板u〇之兩側邊各形 成有一缺口型窗口 114，以供銲線190之通過。該基板 Π0係作為晶片載體並具有單層或多層線路結構。習知地， 該基板110之該第一表面112係供黏晶之用，該基板110之 該第二表面112係設有複數個球墊115，可用以設置複數個 球形端子150。該第一晶片12〇係設於該基板11〇之該第 一表面111並具有複數個位於其主動面中央之第一銲 Q 塾121。可利用複數個第一銲線130通過該中央窗口 113 電性連接該些第一銲墊121至該基板11〇。該封膠體140 常見為環氧模封化合物（Epoxy Molding Compound， EMC)，係形成於該第一表面in、該第二表面H2以及 該窗口 113’以密封該第一晶片120與該些第一銲線 130»該些球形端子150係設於該第二表面112之該些 球墊115而位於該封膠體140之底部，以作為整體封裝 構造對外之電性導接。習知的結構中，該些球墊115係 〇 位於該中央窗口丨13與兩側缺口型窗口 114之間，該些 球形端子丨50係對準於該第一晶片120的下方。 為了增加内部積體電路的容量或功能，該窗口球格陣 列封裝構造100另包含有一第二晶片160、複數個第二 銲線170、一第三晶片180以及複數個第三銲線190。 該第二晶片1 60係與該第一晶片120可為背對背貼合， 而設於該第一晶片120上，I經由該些第二銲線170電 性連接至該基板110。該第三晶片180係面對面貼合設 於該第二晶片160上並利用該些第三銲線190通過該些 7 200939421 缺口型窗口 114以電性連接至該基板11〇。一間隔片i8i 可介設於該第三晶片iSO與該第二晶片16〇之間，以避 免該些第二銲線170碰觸到該第三晶片18〇之主動面。 如第1圖所示’該封膠體140係突出地局部形成於該 基板11〇之該第二表面112，以覆蓋第一銲線13〇與該 些第三銲線190，因此該封膠體14〇須形成在該些球墊 115之兩側在模封時，該基板11〇包含該些球塾115θ 8 arr^ Package, wBGA package) , A ❹ Ο 疋 The circuit board for carrying the chip is provided with two through-holes: in order to allow the metal fresh wire or the known electrical connection element to pass through the mouth To electrically connect the substrate to the wafer. Through this window, metal wire can be collected and the height of the component can be reduced to reduce the package thickness. The metal wire and the wafer are properly sealed for protection. In the evolution of advanced processes, in order to achieve high capacity and size miniaturization, the stackable number of half (four) wafers should be increased to combine-multi-chip package structures, or to add more micro-pitch soldering* base plates to the wafer surface. The number of windows will also increase. However, the more the number of windows in the molding process, the more the problem is that the glue overflows to the substrate and contaminates the ball pad, and it is uncontrollable, which seriously affects the reliability of the packaged product. A window type grid array package construction is disclosed in U.S. Patent No. 7,205,656. As shown in FIG. 1, the window type ball grid array package structure 100 mainly includes a substrate 110, a first wafer 12, a plurality of first bonding wires 130, a gel 140, and a plurality of ball terminals 15A. The substrate 110 has a first surface 111, an opposite first surface 112, and/or a central opening 113 through the first surface ill and the second surface ι2. A notch window 114 is formed on each of the two sides of the substrate u to pass the bonding wire 190. The substrate Π0 serves as a wafer carrier and has a single layer or a multilayer wiring structure. Conventionally, the first surface 112 of the substrate 110 is used for die bonding. The second surface 112 of the substrate 110 is provided with a plurality of ball pads 115 for setting a plurality of ball terminals 150. The first wafer 12 is disposed on the first surface 111 of the substrate 11 and has a plurality of first solder electrodes 121 located at the center of the active surface. A plurality of first bonding wires 130 may be used to electrically connect the first pads 121 to the substrate 11 through the central window 113. The sealant 140 is generally an epoxy resin compound (EMC) formed on the first surface in, the second surface H2, and the window 113' to seal the first wafer 120 and the first The soldering wires 130 are disposed on the bottom of the sealing body 140 at the bottom of the sealing body 140 to be externally electrically connected. In the conventional structure, the ball pads 115 are located between the central window 13 and the notched windows 114 on both sides, and the ball terminals 50 are aligned below the first wafer 120. In order to increase the capacity or function of the internal integrated circuit, the window cell array package structure 100 further includes a second wafer 160, a plurality of second bonding wires 170, a third wafer 180, and a plurality of third bonding wires 190. The second wafer 160 and the first wafer 120 can be back-to-back, and are disposed on the first wafer 120, and are electrically connected to the substrate 110 via the second bonding wires 170. The third wafers 180 are disposed on the second wafer 160 face-to-face and are electrically connected to the substrate 11 through the 7 200939421 notched windows 114 by the third bonding wires 190. A spacer i8i can be disposed between the third wafer iSO and the second wafer 16A to prevent the second bonding wires 170 from contacting the active surface of the third wafer 18. As shown in FIG. 1 , the encapsulant 140 is partially formed on the second surface 112 of the substrate 11 以 to cover the first bonding wire 13 〇 and the third bonding wires 190 , so the encapsulant 14 The substrate 11 includes the balls 115 when it is not required to be formed on both sides of the ball pads 115.

之部位無法被上下模具有效爽平，容易產生溢膠而污染 至該二球墊115，該些球形端子15〇易有掉球與假焊之 情事，影響該窗口球㈣列封裝構造之電性連接傳輸 品質。 【發明内容】 本發明之主要目的係在於提供一種多窗口球格陣列 封裝構造，能解決習知基板因多窗口容易模封溢膠而汙 染到球勢之問題。 本發明之次一目的係在於提供一種多窗口球格陣列 封裝構造，利用窗口及銲線反打線方法，增加晶片之可 堆疊數量，並可降低封裝高度與節省基板空間。 本發明之另一目的係在於提供一種多窗口球格陣列 封裝構造，可達到基板非對稱鑄模之上下模流平衡。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明所揭示之一種多窗口球格陣列 封裝構造，主要包含-基板、一第—晶片、複數個第一 銲線、〃封膠體以及複數個球形端子。該基板係具有一 8 表 Ο αυ93942ι 第 面與訪第 相對之第二表面以及複數個貫穿該 部，誃此 表面之窗口，該基板係更具有複數個 該其知4側爽板部設有複數個球墊。該第一晶片 墊。該些第χ 表面，該第一晶片係具有複數個 讀此笛~〜銲線係通過至少一之該些窗口並電 ‘弟一銲執 面、該第-至該基板。該封膠體係形成於該 些第一銲：表面以及該些窗口，以密封該第-晶 於該些側办：不密封該些側夾板部。該些球形端 本發明的目部之該些球墊而位於該封膠體之外 措施進一击香的及解決其技術問題還可採用以 艾η現。 迷之多窗口球格陣列封 在該第一 I ^ 4衣稱k中，邊些侧 衣面之側邊與該篦-主 該封膠體之外側。 表面之側邊皆可 在前述之多窗口球格 該干5对裝構造中，該第二 二 之間的區域係可被 饭该封膠體所覆蓋。 1述之多窗口球格陣列封 第二表面上的厚度係可」構造中，該封膠 在1、f免 ;在該第一表面上的屬 在刖述之多窗口球格陣 ^ ^ L L 可展構造中’該封膠 第-“上的厚度係可大於在該晶片度。 在曰别述之多窗口球袼陣列封裝構造中，可 第一日日片與複數個第二銲線，誃 曰 晶片上並經由該些第二銲線電:-曰曰片係設於 在前述之多窗口球格陣列連接至該基板。 早歹J封袭構造中，該第二 第一表 侧夾板 係設於 第一銲 性連接 第一表 片與該 子係設 側。 下技術 夾板部 顯露於 表面在 體在該 -度。 體在該 含有一 該第一 晶片係 9 200939421 可與該第一晶片為背對背貼合。 在前述之多窗口球格陣列封裝構造中，町另包含有立 少一第二晶片與複數個第三銲線，該第三晶片係設於該 第二晶片上並經由該些第三銲線電棟連接至該基板。 在前述之多窗口球格陣列封裝構造中，該封膠體在該 第二表面上的厚度係可大於在該第彡晶片上的厚度。 在前述之多窗口球格陣列封裝構造中，該第三晶片係 可與該第二晶片為面對面貼合，並且該些第三銲線係通 過至少一之該些窗口。 在前述之多窗口球格陣列封裝構造中，可另包含有一 膜覆線黏膠（F〇Wadhesive)，其係形成於該第三晶片與 該第二晶片之間並包覆該些第二銲線之一端。 在刖述之多窗口球格陣列封裝構造中，每一第一銲線係 八有'、》s端與線尾端，該結球端係可接合於該基板之The parts can not be effectively smoothed by the upper and lower molds, and it is easy to generate overflow glue and pollute the two ball pads 115. The spherical terminals 15 are easy to fall off the ball and the false welding, which affects the electrical connection of the window ball (four) column package structure. Transmission quality. SUMMARY OF THE INVENTION The main object of the present invention is to provide a multi-window ball grid array package structure, which can solve the problem that a conventional substrate is contaminated by a multi-window and can be contaminated by a multi-window. A second object of the present invention is to provide a multi-window ball grid array package structure, which utilizes a window and wire bond back-wire method to increase the number of stacks of wafers, and to reduce the package height and save substrate space. Another object of the present invention is to provide a multi-window ball grid array package structure that achieves a lower mold flow balance above the asymmetric mold of the substrate. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a multi-window ball grid array package structure mainly includes a substrate, a first wafer, a plurality of first bonding wires, a sealant, and a plurality of ball terminals. The substrate has a second surface opposite to the first surface and a plurality of windows extending through the portion, the surface of the substrate, and the substrate has a plurality of Ball mats. The first wafer pad. The first wafer surface has a plurality of readings of the flute-~ soldering wire passing through at least one of the windows and electrically discharging the first surface to the substrate. The encapsulation system is formed on the first weld: surface and the windows to seal the first crystal to the sides: the side splints are not sealed. The ball ends of the ball pads of the object of the present invention are located outside the sealant. The measures to solve the technical problem can also be adopted. The multi-window ball grid array is sealed in the first I^4 nickname k, the side edges of the side garments and the outer side of the 篦-main sealant. The sides of the surface can be covered by the above-mentioned multi-window ball in the dry 5-pair configuration, and the area between the second two can be covered by the sealant. The thickness of the multi-window ball grid array on the second surface can be constructed, the sealant is free at 1, f; the multi-window sphere array on the first surface is ^ ^ LL In the expandable structure, the thickness of the sealant can be greater than the thickness of the wafer. In the multi-window ball array package structure, the first day and the second wire can be And the second bonding wire is electrically connected to the substrate: the cymbal is connected to the substrate in the multi-window ball grid array. The second first side clamping plate is in the early sealing structure. The first solder joint is connected to the first surface and the sub-system side. The lower technical splint portion is exposed on the surface at the body. The body includes a first wafer system 9 200939421 and the first The wafer is back-to-back. In the multi-window ball grid array package structure, the town further includes a second wafer and a plurality of third bonding wires, and the third wafer is disposed on the second wafer and The third wire grids are connected to the substrate. The multi-window ball grid array structure The thickness of the encapsulant on the second surface may be greater than the thickness on the second wafer. In the multi-window ball grid array package configuration, the third wafer may be face to face with the second wafer. Laminating, and the third bonding wires pass through at least one of the windows. In the foregoing multi-window ball grid array package structure, a film covered adhesive (F〇Wadhesive) may be further included, which is formed on Between the third wafer and the second wafer, and covering one end of the second bonding wires. In the multi-window ball grid array package structure, each of the first bonding wires has a ', s end And the end of the wire, the ball end can be bonded to the substrate

該第一表面’該線尾端係接合於對應之S -銲墊。 【實施方式] _依據本發明之第一具體實施例，請參閱第2圖 丁種多囪口球格陣列封裝構造200係主要包含一 板 210、一第一 片220、複數個第一銲線230、一 膝體240以及複數個球 球化鳊子250。該基板210係具 第 表面 211、— ig ^ 相斗咕 邳對之第二表面212以及複數個 穿該第一表面21〗與該第一 丹成弟—表面212之窗口 213。該 板210係作為晶片載 β * 戰體並具有單層或多層線路結構，例如 層或多層印刷電路板。此 涊二_ 口 213之一般的形狀係為狹 10 200939421 槽孔，其長度可小於或等於該基板210之對應側邊之長度， 並由該第一表面211貫穿至該第二表面212。該些窗口 213 之周圍係可設有複數個内接墊（圖未繪出）以供晶片打線電性 連接之用。此外，如第2圖所示，該基板210係更具有 複數個側夾板部2 1 4，該些側夾板部2 1 4設有複數個球 墊215。例如圓形之接球墊，其係設於相對於該基板21〇 之該第二表面212之同一表面，該些球整215係可呈多排 0 排列或是格狀陣列型態。因此，該些球墊2 1 5不位於該些 窗口 2 1 3之間。 該第一晶片220係設於該基板210之該第一表面 211 ’該第一晶片220係具有複數個第一銲墊221，並 對準顯露於一個或一個以上之該些窗口 213。如第2圖 所示，在本實施例中，該些第一銲墊221係可為周邊銲 墊。該些第一銲線230係通過至少一之該些窗口 213並 電性連接該些第一銲墊221至該基板210。每一第一銲 〇 線230係具有一結球端23 l(ball bond)與一線尾端232(或稱 訂合式接合端，stitch bond)。較佳地，如第2圖所示，該 結球端231係可接合於該基板210之該第二表面212, 該線尾端232係接合於對應之第一銲墊221，而形成一 種逆向打線（reverse bonding)之結構。其可較容易控制打 線之方向，避免該些第一銲線230打線時會接觸到該基 板21〇之對應窗口 213之開口邊緣。 該封膠體240係形成於該第一表面211、該第二表 面2 12以及該些窗口 213，以密封該第一晶片220與該 11 200939421 些第一銲線230但不密封該些侧夾板部214，以顯露出 該些球墊215。具體而言，該些側夾板部214之上表面 與下表面皆顯露於該封膠體2 4 0之外侧。 β亥封膠體240係為轉移成形（transfer m〇iding，或可稱為 壓模）的技術加以形成之。此外，如第2圖所示，該第二 表面212在該些窗口 213之間的區域係可被該封膠體 240所覆蓋’以使該基板21〇之該第一表面211與該第 ❹ 二表面212有大致相同之封膠區域，有助於下模流的控 制並減少模封溢膠。在本實施例中，該封膠體2 4 〇在該 第一表面211上的厚度係可大於在該第二表面212上的 厚度’而該些側夾板部214在該第一表面211之側邊可 提供作為預留溢膠區域，即使發生溢膠會先形成於該第 —表面2 1 1而不會污染到位於該第二表面2丨2側邊之該 些球墊2 1 5。 並且，該些球形端子250係設於該些側夾板部214 © 之該些球塾215而位於該封膠體240之外側，可為周邊 配置’以供作為外部輸入端及/或輸出端，以使該多窗口球 格陣列封裝構造200能與外界裝置形成電性連接關係。該 ~球形端子250係可包含金屬球、錫膏、接觸墊或接觸針。 在本實施例中，如第2圖所示，該些球形端子25〇係為金 屬球，特別是可焊接之錫球。例如，可藉由加熱該些球形端 子2 5 〇以表面接合至一外部印刷電路板。 該些侧爽板部214在相對於該些球形端子25〇之另 —表面（即位於該上表面211之側邊）不被該封膠體24〇 12 200939421 所覆蓋，故該些側夾板部214之上表面與下表面的顯露 區域與形狀可大致相等。該些側夾板部214可提供作為 上下模具對稱夾合，以解決習知多窗口因容易模封溢膠 而污染到球墊的問題，進而提昇該多窗口球格陣列封裝 構造200之電性連接與傳輪品質。由於該多窗口球袼陣列 封裝構造200可以解決習知多窗口造成模封溢膠而污 染到球絷的問題’故可特別運用到多晶片封裝。 ❹ 該多窗口球格陣列封裝構造200可另包含有一第二 晶片260與複數個第二銲線270，該第二晶片260係設 於該第，晶片220上並經由該些第二銲線230電性連接 至該基板210。該第二晶片220係可與該第一晶片210 為背對背貼合。在本實施例中，該第二晶片220係與該 第一晶片21〇具有相同之尺寸。 此外’該多窗口球格陣列封裝構造200可另包含有 至少一第三晶片280與複數個第三銲線29〇，該第三晶 〇 片280係設於該第二晶片260上並經由該些第三銲線 290電性連接至該基板210。該第三晶片280係可與該 第二晶片260為面對面貼合。具體而言，如第2圖所示， 可藉由〆膜覆線黏膠281(Film-Over-Wire adhesive)黏 合該第彡晶片280之主動面與該第二晶片260之主動 面，並包覆該些第二銲線270之一端，藉以覆蓋並固定 該些第二·録線270之晶片接合端。較佳地，該膜覆線黏 膠2 8 1係具有緩衝彈性，並在黏晶時具有B階或半固化 特性，衣加熱到一適當溫度能產生黏著力與流動度，以 13 200939421 完成對該些第二銲線270之局部包覆。 該些第三銲線290係通過至少一之該些窗口 213而 電性連接至該基板210,而可省略該第三晶片28〇上方 打線冋度。較佳地，该第三銲線29〇亦可以逆向打線 之方法，由該基板21〇之該第二表面212打線接合至該 第三晶片280 »此外，該封膠體24〇在該第二表面212 上的厚度係可大於在該第三晶片28〇上的厚度有助於 〇 基板非對稱鑄模之上下模流平衡，並能改善模流不均勻 及熱應力不平衡而造成基板翹曲之問題，進而提高半導 體封裝產品的良率與可靠度。 本發明之第二具體實施例揭示另一種多窗口球格陣列 封裝構，造，主要元件大致係與第一實施例相同。如第3圖 所示，該多窗口球格陣列封裝構造300主要包含一基板 3 10、一晶片320、複數個銲線33〇、一封膠體34〇以及 複數個球形端子350,該基板31〇係具有一第一表面 〇 311相對之第二表面312、一中央窗口 313以及複 數個周邊由口 316。在本實施例中，該基板31〇係可為單 層線路結構，可減少佈線成本，第二表面312係可包含複 數個内接墊（圖未繪出），以供該晶片3 2 〇電性連接至該 基板31〇〇該中央窗口 313與該些周邊窗口 316 一般的形狀 係為狹長貫穿槽孔’其長度可小於該基板3丨〇之對應侧邊之 長度，並由該第一表面311貫穿至該第二表面312。如第3 及4圖所不，該基板3丨〇係更具有複數個側夾板部3 j 4， β亥些侧夾板部3 1 4設有複數個球墊3〖5。該些球墊3 i 5 14 200939421 係設於相對於該基板310之該第二表面312之同一表 面，該些球墊3 15係可呈多排排列或是格狀陣列型態。 如第3圖所示，該晶片320係設於該基板310之該 第一表面311，該晶片320係具有複數個銲墊321。如 第3圖所示，在本實施例中，該晶片320係具有多端子 且微間距之銲墊排列，該些銲墊321係包含中央銲墊與 周邊銲墊，分別顯露於該中央窗口 313與該些周邊窗口 316。該些銲線330係分別通過該中央窗口 313與該些 周邊窗口 316並電性連接該些銲墊321至該基板310。 該封膠體3 40係形成於該第一表面311、該第二表 面312、該中央窗口 313以及該些周邊窗口 316，以密 封該晶片320與該些銲線330。該封膠體340係不密封 該些側夾板部 314之上下表面，以顯露出該些球墊 315。具體而論，該些侧夾板部314之上表面與下表面 係分別連接在該第一表面3 11之侧邊與該第二表面3 1 2 © 之側邊，並且顯露於該封膠體340之兩對稱外側。 此外，如第3圖所示’該第二表面312在該中央窗 口 3 1 3與該些周邊窗口 3 1 6之間的區域係可被該封膠體 3 40所覆蓋，以使該基板310之該第一表面311與該第 二表面312有大致相同之封膠區域，以減少在該第二表 面3 1 2之模封溢膠。 通常該封膠體340在該第二表面312上的厚度係小 於在該第一表面311上的厚度，用以密封該晶片320。 較佳地’該封膠體340在該第二表面312上的厚度係可 15 200939421 大於在該晶片320上的厚度，導致下模流速 上模流之速度，該封膠體340在該第一表面 位可先行注膠填滿，以使該些側夾板部3 1 4 面3 11之側邊可提供作為預留溢膠區域，即 會先形成於該第一表面311而不會污染到 表面312側邊之該些球墊315。 具體而言，如第3及4圖所示，該些球 ❹ 係設於該些侧夾板部3 1 4之該些球墊3 1 5而 體3 40之外側，以供作為輸入端及/或輸出端， 口球格陣列封裝構造300可藉由該些球形端 接合至一外部印刷電路板。較佳地，該些側夾 相對於該些球形端子35〇之另一表面不被舞 所覆蓋，以使該些側夾板部3丨4之上表面與 有大致相同之顯露面積。該些侧夾板部314 上下模具對稱夹合，以解決習知多窗口因容 © 而污染到球塾的問題，進而提昇該多窗口球 構造300之電性連接傳輸品質。 以上所述，僅是本發明的較佳實施例而 本發明作任何形式上的限制，本發明技術方 所附申凊專利範圍為準。任何熟悉本專業的 利用上述揭示的技術内容作出些許更動或 變化的等效實施例，但凡是未脫離本發明技 $，依據本發明的技術實質對以上實施例所 單修改f同變化與修飾，均仍屬於本發明 度可稍慢於 3 11上的部 在該第一表 使發生溢膠 位於該第二 形端子350 位於該封膠 以使該多窗 子350表面 板部3 1 4在 [封膠體3 4〇 下表面可具 可提供作為 易模封溢膠 格陣列封裝 已，並非對 案範圍當依 技術人員可 修飾為等同 術方案的内 作的任何簡 技術方案的 16 200939421 ❹ 範圍内。 【圖式簡單說明】 第1圖：習知窗口型球格陣 m撕 平〗封裝構造之截面示意圖。 第2圖：依據本發明之第一 具體實施例，一種多窗口球 格陣列封襄構造之截面示意圖。 依據本發明之第二具體實施例， 格陣列封裝構造之截面示意圖。 依據本發明之第二具體實施例，該多窗口球格 /列封裝構造之底面示意圖。 【主要元件符號說明】 100窗口型球格陣列封裝構造 第3圖 第4圖 種多窗口球 ❹ 110基板 113中央窗口 120第一晶片 130第一銲線 140封膠體 1 70第二銲線 111第一表面114缺口型窗口 121第一銲塾 150球形端子 18〇第三晶片 112第二表面 115球墊 190第三銲線 200多窗口球格陣列封装構造 210基板 211第一表面 213窗口 214侧夾板部 220第一晶片 221第一銲墊 230第一銲線 231結球端 240封膠體 250球形端子 160第二晶片 181間隔片 212第二表面 215球墊 232線尾端 17 200939421 270第二銲線 281膜覆線黏膠 260第二晶片 280第三晶片 290第三銲線 300多窗口球格陣列封裝構造 ❹ 310基板 313中央窗口 316周邊窗口 320晶片 330銲線 311第一表面 3 14側夾板部 321銲墊 340封膠體 312第二表面 3 1 5球墊 3 5 0球形端子The first surface & the end of the wire is bonded to the corresponding S-pad. [Embodiment] According to the first embodiment of the present invention, please refer to FIG. 2, the multi-burden ball grid array package structure 200 mainly includes a board 210, a first sheet 220, and a plurality of first bonding wires. 230, a knee body 240 and a plurality of ball scorpions 250. The substrate 210 has a first surface 211, a second surface 212 of the ig 相 邳 pair, and a plurality of windows 213 extending through the first surface 21 and the first Dan Chengdi surface 212. The board 210 is a wafer-loaded beta* warfare body and has a single or multi-layer wiring structure, such as a layer or multilayer printed circuit board. The general shape of the second port 213 is a narrow 10 200939421 slot, the length of which may be less than or equal to the length of the corresponding side of the substrate 210, and the first surface 211 extends through the second surface 212. A plurality of internal pads (not shown) may be disposed around the windows 213 for electrically connecting the wafers. Further, as shown in Fig. 2, the substrate 210 further includes a plurality of side plate portions 2 1 4, and the side plate portions 2 1 4 are provided with a plurality of ball pads 215. For example, a circular ball pad is disposed on the same surface of the second surface 212 relative to the substrate 21, and the ball 215 series may be in a plurality of rows or a grid array. Therefore, the ball pads 2 15 are not located between the windows 2 1 3 . The first wafer 220 is disposed on the first surface 211 of the substrate 210. The first wafer 220 has a plurality of first pads 221 and is aligned with the one or more of the windows 213. As shown in Fig. 2, in the embodiment, the first pads 221 may be peripheral pads. The first bonding wires 230 pass through at least one of the windows 213 and electrically connect the first pads 221 to the substrate 210. Each of the first solder wires 230 has a ball bond 23l and a wire tail end 232 (or a stitch bond). Preferably, as shown in FIG. 2, the ball end 231 is engageable with the second surface 212 of the substrate 210, and the wire end 232 is bonded to the corresponding first pad 221 to form a reverse wire. (reverse bonding) structure. It is easier to control the direction of the wire, and the first wire bond 230 is prevented from contacting the opening edge of the corresponding window 213 of the substrate 21 when the wire is wound. The encapsulant 240 is formed on the first surface 211, the second surface 214, and the windows 213 to seal the first wafer 220 and the 11 200939421 first bonding wires 230 but not to seal the side clamping portions. 214 to reveal the ball pads 215. Specifically, the upper surface and the lower surface of the side plate portions 214 are exposed on the outer side of the sealant 240. The β-sea sealant 240 is formed by a technique of transfer molding or may be referred to as a stamper. In addition, as shown in FIG. 2, the area of the second surface 212 between the windows 213 can be covered by the encapsulant 240 so that the first surface 211 of the substrate 21 and the second surface are The surface 212 has substantially the same encapsulation area to aid in the control of the lower mold flow and to reduce over-molding. In this embodiment, the thickness of the sealant 24 4 on the first surface 211 can be greater than the thickness on the second surface 212 and the side cleats 214 are on the side of the first surface 211. It can be provided as a reserved overflow area, and even if overflow occurs, it will be formed on the first surface 21 1 without contaminating the ball pads 2 15 located on the side of the second surface 2丨2. Moreover, the ball terminals 250 are disposed on the outer side of the seal body 240 of the side clamp portions 214, and may be disposed on the periphery for use as an external input end and/or an output end. The multi-window ball grid array package structure 200 can be electrically connected to an external device. The ball terminal 250 can comprise a metal ball, a solder paste, a contact pad or a contact pin. In the present embodiment, as shown in Fig. 2, the spherical terminals 25 are metal balls, particularly solder balls. For example, the ball terminals can be surface bonded to an external printed circuit board by heating the spherical terminals 25. The side plate portions 214 are not covered by the sealant 24〇12 200939421 at the other surface (ie, the side of the upper surface 211) with respect to the spherical terminals 25, so the side plate portions 214 The exposed areas and shapes of the upper and lower surfaces may be substantially equal. The side plate portions 214 can be provided as a symmetric clamping of the upper and lower molds to solve the problem that the conventional multi-window contaminates the ball pad due to easy molding of the glue, thereby improving the electrical connection of the multi-window ball grid array package structure 200. Passing the wheel quality. Since the multi-window ball array array package structure 200 can solve the problem that the conventional multi-window causes the mold to overflow and stain the ball, it can be particularly applied to the multi-chip package. The multi-window ball grid array package structure 200 can further include a second wafer 260 and a plurality of second bonding wires 270. The second wafer 260 is disposed on the first wafer 220 and via the second bonding wires 230. Electrically connected to the substrate 210. The second wafer 220 can be attached back to back with the first wafer 210. In this embodiment, the second wafer 220 has the same size as the first wafer 21A. In addition, the multi-window ball grid array package structure 200 may further include at least one third wafer 280 and a plurality of third bonding wires 29 系. The third wafer 280 is disposed on the second wafer 260 and The third bonding wires 290 are electrically connected to the substrate 210. The third wafer 280 can be in face-to-face contact with the second wafer 260. Specifically, as shown in FIG. 2, the active surface of the second wafer 280 and the active surface of the second wafer 260 may be bonded by a film-over-wire adhesive 281 (Film-Over-Wire adhesive). One end of the second bonding wires 270 is covered to cover and fix the wafer bonding ends of the second recording lines 270. Preferably, the film-coated adhesive has a cushioning elasticity and has a B-stage or semi-curing property when the crystal is bonded, and the coating is heated to a suitable temperature to generate adhesion and fluidity, and is completed by 13 200939421. The second bonding wires 270 are partially covered. The third bonding wires 290 are electrically connected to the substrate 210 through at least one of the windows 213, and the wire twisting above the third wafer 28 can be omitted. Preferably, the third bonding wire 29〇 can also be reversely wired. The second surface 212 of the substrate 21 is wire bonded to the third wafer 280. Further, the sealing body 24 is disposed on the second surface. The thickness on 212 can be greater than the thickness on the third wafer 28〇 to help balance the lower mold flow on the asymmetric mold of the substrate, and can improve the problem of substrate warpage caused by uneven mold flow and thermal stress imbalance. To improve the yield and reliability of semiconductor package products. The second embodiment of the present invention discloses another multi-window ball grid array structure, and the main components are substantially the same as those of the first embodiment. As shown in FIG. 3 , the multi-window ball grid array structure 300 mainly includes a substrate 3 10 , a wafer 320 , a plurality of bonding wires 33 , a gel 34 〇 , and a plurality of ball terminals 350 . There is a first surface 〇 311 opposite the second surface 312, a central window 313, and a plurality of peripheral ports 316. In this embodiment, the substrate 31 can be a single-layer circuit structure, which can reduce the wiring cost, and the second surface 312 can include a plurality of internal pads (not shown) for the wafer 3 2 to be charged. The central window 313 and the peripheral window 316 are generally shaped as an elongated through slot [the length of which may be less than the length of the corresponding side of the substrate 3丨〇, and the first surface is 311 extends through the second surface 312. As shown in Figs. 3 and 4, the substrate 3 has a plurality of side plate portions 3 j 4 , and the β side plate portions 3 1 4 are provided with a plurality of ball pads 3 5 . The ball pads 3 i 5 14 200939421 are disposed on the same surface of the second surface 312 of the substrate 310, and the ball pads 3 15 may be arranged in a plurality of rows or in a lattice array. As shown in FIG. 3, the wafer 320 is disposed on the first surface 311 of the substrate 310. The wafer 320 has a plurality of pads 321 . As shown in FIG. 3, in the embodiment, the wafer 320 has a multi-terminal and fine pitch pad arrangement, and the pads 321 include a central pad and a peripheral pad, respectively exposed to the central window 313. With the peripheral windows 316. The bonding wires 330 are electrically connected to the peripheral pads 316 and the pads 321 to the substrate 310 through the central window 313. The encapsulant 340 is formed on the first surface 311, the second surface 312, the central window 313, and the peripheral windows 316 to seal the wafer 320 and the bonding wires 330. The encapsulant 340 does not seal the upper upper surface of the side splint portions 314 to reveal the ball pads 315. Specifically, the upper surface and the lower surface of the side clamping plate portion 314 are respectively connected to the side of the first surface 3 11 and the side of the second surface 3 1 2 ©, and are exposed to the sealing body 340. Two symmetrical outer sides. In addition, as shown in FIG. 3, the area of the second surface 312 between the central window 313 and the peripheral windows 316 can be covered by the encapsulant 340 so that the substrate 310 The first surface 311 and the second surface 312 have substantially the same encapsulation area to reduce the overfilling of the second surface 31. Typically, the sealant 340 has a thickness on the second surface 312 that is less than the thickness on the first surface 311 for sealing the wafer 320. Preferably, the thickness of the encapsulant 340 on the second surface 312 is greater than the thickness on the wafer 320, resulting in a velocity of the mold flow at the lower mold flow rate at which the encapsulant 340 is located. The glue can be filled first so that the side edges of the side plate portions 3 1 4 face 3 11 can be provided as a reserved overflow area, that is, first formed on the first surface 311 without contaminating the surface 312 side. The ball pads 315 are on the side. Specifically, as shown in FIGS. 3 and 4, the ball joints are disposed on the outer sides of the ball pads 3 1 5 and the body 3 40 of the side splint portions 3 1 4 for use as input terminals and/or Alternatively, the ball grid array package structure 300 can be bonded to an external printed circuit board by the ball ends. Preferably, the side clips are not covered by the dance with respect to the other surface of the ball terminals 35 so that the upper surfaces of the side plate portions 3丨4 have substantially the same exposed area. The side plate portions 314 are symmetrically sandwiched between the upper and lower molds to solve the problem that the conventional multi-window is contaminated to the ball, thereby improving the electrical connection quality of the multi-window ball structure 300. The above is only a preferred embodiment of the present invention and the present invention is to be limited in any form, and the scope of the appended claims is subject to the scope of the claims. Any equivalent embodiment of the present invention that utilizes the above-discussed technical content may be modified or modified, and the present invention may be modified and modified in accordance with the technical spirit of the present invention. The portion of the invention that can be slightly slower than 3 11 in the first table causes the overflow to occur at the second terminal 350 located in the sealant so that the multi-window 350 surface plate portion 3 1 4 The lower surface of the colloidal 3 4 can be provided as an easy-to-wear sealed cell array package, and is not within the scope of any of the simple technical solutions that can be modified by the skilled person as an equivalent solution. [Simple description of the figure] Fig. 1: Schematic diagram of a conventional window type lattice array m tearing. Figure 2 is a cross-sectional view showing a multi-window ball grid array sealing structure in accordance with a first embodiment of the present invention. A schematic cross-sectional view of a lattice array package structure in accordance with a second embodiment of the present invention. According to a second embodiment of the present invention, a schematic diagram of the bottom surface of the multi-window ball/column package construction. [Main component symbol description] 100 window type ball grid array package structure Fig. 3, Fig. 4, multi-window ball ❹ 110 substrate 113 center window 120 first wafer 130 first bonding wire 140 encapsulant 1 70 second bonding wire 111 A surface 114 notched window 121 first soldering 150 ball terminal 18 〇 third wafer 112 second surface 115 ball pad 190 third bonding wire 200 multi-window ball grid array package structure 210 substrate 211 first surface 213 window 214 side splint Port 220 first wafer 221 first pad 230 first bonding wire 231 ball end 240 encapsulant 250 ball terminal 160 second wafer 181 spacer 212 second surface 215 ball pad 232 wire end 17 200939421 270 second wire 281 Film-covered adhesive 260 second wafer 280 third wafer 290 third bonding wire 300 multi-window ball grid array package structure 310 substrate 313 central window 316 peripheral window 320 wafer 330 bonding wire 311 first surface 3 14 side splint portion 321 Pad 340 sealant 312 second surface 3 1 5 ball pad 3 5 0 ball terminal

1818

Claims (1)

200939421 十、申請專利範園： 1、 一種多窗口球格陣列封裝構造，包含： 晶片 -基板，係具有一第一表面、一相對之第二表面以及複 數個貫穿該第一表面與該第二表面之窗口，該基板係更 具有複數個側夾板部，該些側夾板部設有複數個球墊； 一第一晶片，係設於該基板之該第一表面，該第 係具有複數個第一銲墊； ❹ ❹ 複數個第-銲線’係通過至少—之該些窗口並電性連接 該些第一銲墊至該基板； -封膠體’係形成於該第一表面、該第二表面以及該些 窗口 ’以密封該第1片與該些第—銲線但μ封該： 側夾板部；以及 複數個球形端子，係設於該些側夾板部之該些球墊而位 於該封膠體之外側。 2、 如申請專利範固第丨項所述之多窗口球格陣列_ 造，其中該些側夾板部在該第一表面之侧邊與該第二表 面之侧邊皆顯露於該封膠體之外側。 3、 如申請專利範圍第丨項所述之多窗口球格陣列封裝構 造’其中該第二表面在該些窗口之間的區域係被 體所覆蓋。 修 4、 如申請專利範圍第i項所述之多窗口球格陣列封 造，其中該封膠體在該第二表面上的厚 ： /表面上的厚度。 在該第 5、 如申請專利範圍第15戈4項所述之多窗口球格陣列封裝 200939421 構造’其中該封膠體在該第 在該晶片上的厚度。 二表面上的厚度係大於 口球格陣列封裝構 二銲線，該第二晶 二銲線電性連接至 6、如申請專利範圍第1項所述之多窗 造，另包含有一第二晶片與複數個第 片係攻於該第一晶片上並經由該些第 該基板。200939421 X. Patent application garden: 1. A multi-window ball grid array package structure comprising: a wafer-substrate having a first surface, an opposite second surface, and a plurality of through the first surface and the second a surface window, the substrate further has a plurality of side plate portions, wherein the side plate portions are provided with a plurality of ball pads; a first wafer is disposed on the first surface of the substrate, the first system has a plurality of a solder pad; ❹ ❹ a plurality of first solder wires ' passing through at least the windows and electrically connecting the first pads to the substrate; - a sealant ' is formed on the first surface, the second a surface of the window and the plurality of windows to seal the first piece and the first wire bonds; but the side plate portion; and a plurality of ball terminals are disposed on the ball pads of the side plate portions The outside of the sealant. 2. The multi-window ball grid array of claim 2, wherein the side splint portions are exposed on the side of the first surface and the side of the second surface are exposed to the sealant. Outside. 3. The multi-window ball grid array package structure of claim 2, wherein the area of the second surface between the windows is covered by the body. 4. The multi-window ball grid array package of claim i, wherein the sealant has a thickness on the second surface: / a thickness on the surface. In the fifth aspect, the multi-window ball grid array package 200939421 as described in claim 5 of the patent application has a structure in which the sealant is on the thickness of the wafer. The thickness of the two surfaces is greater than that of the ball grid array package, and the second crystal wire is electrically connected to the multi-window of the first aspect of the patent application, and further includes a second wafer. And a plurality of the first pieces are attacked on the first wafer and passed through the first substrate. 7、 如申請專利範圍第6項所述之多窗口球袼陣列封襞構 造，其中該第二晶片係與該第一晶片為背對背貼合。 8、 如申請專利範圍第6項所述之多窗口球格陣列:裝構 造，另包含有至少一第三晶片與複數個第三銲線，該第 三晶片係設於該第二晶片上並經由該些第三銲線電 接至該基板。 9、 如申請專利範圍帛8項所述之多窗口球格陣列封装構 造，其中該封膠體在該第二表面上的厚度係大於在該第 三晶片上的厚度。 10、 如中請專利範圍第8項所述之？ 球格陣列封裝構 造，其中該第三晶片係與該第二晶片為面對面貼合，並 該些第二銲線係通過至少一之該些窗口。 U、如申請專利範圍第1〇項所述之多窗口球格陣列封裝構 造，另包含有一膜覆線黏膠（FOW adhesiVe)，其係形成 於該第三晶片與該第二晶片之間並包覆該些第二銲線之 〆端。 、 12、如申請專利範圍第i項所述之多窗口球格陣列封裝構 造，其中每一第一銲線係具有一結球端與—線尾端，其 20 200939421 中該結球端係接合於該基板之該第二表面，該線尾端係 接合於對應之第一銲墊。7. The multi-window ball python array package structure of claim 6, wherein the second wafer is bonded back to back with the first wafer. 8. The multi-window ball grid array of claim 6, further comprising at least one third wafer and a plurality of third bonding wires, the third wafer being disposed on the second wafer and Electrically connected to the substrate via the third bonding wires. 9. The multi-window ball grid array package of claim 8, wherein the sealant has a thickness on the second surface that is greater than a thickness on the third wafer. 10. What is stated in item 8 of the patent scope? The ball grid array package structure, wherein the third wafer is in face-to-face contact with the second wafer, and the second bonding wires pass through at least one of the windows. U. The multi-window ball grid array package structure of claim 1, further comprising a film-coated adhesive (FOW adhesiVe) formed between the third wafer and the second wafer Covering the ends of the second bonding wires. 12. The multi-window ball grid array package structure of claim i, wherein each of the first bonding wires has a ball end and a wire tail end, and wherein the ball end is bonded to the ball in 20 200939421 The second surface of the substrate is bonded to the corresponding first pad. 21twenty one
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