TWI353664B - Back-to-back stacked multi-chip package and method - Google Patents

Back-to-back stacked multi-chip package and method Download PDF

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Publication number
TWI353664B
TWI353664B TW096147772A TW96147772A TWI353664B TW I353664 B TWI353664 B TW I353664B TW 096147772 A TW096147772 A TW 096147772A TW 96147772 A TW96147772 A TW 96147772A TW I353664 B TWI353664 B TW I353664B
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TW
Taiwan
Prior art keywords
wafer
wire
substrate
pads
chip package
Prior art date
Application number
TW096147772A
Other languages
Chinese (zh)
Other versions
TW200926389A (en
Inventor
Ji Cheng Lin
Chi Chung Yu
Li Chih Fang
Original Assignee
Powertech Technology Inc
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Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW096147772A priority Critical patent/TWI353664B/en
Publication of TW200926389A publication Critical patent/TW200926389A/en
Application granted granted Critical
Publication of TWI353664B publication Critical patent/TWI353664B/en

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    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
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    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
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    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48991—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on the semiconductor or solid-state body to be connected
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
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  • Wire Bonding (AREA)

Abstract

Disclosed is a back-to-back multi-chip package. Two chips are disposed on a substrate in back-to-back stacking and are electrically connected to the substrate by a plurality of short long bonding wires respectively. The package further includes at least a wire-freezing component and a molding compound encapsulating the chips. The wire-freezing component clothes partial wire sections of the long wires and adheres to an active surface of an upper chip. Accordingly, the back-to-back stacked chips can selected from a universal kind of chips having central pads to reduce managing cost of chip species. Additionally, the problems of wire-sweeping of long wires on chip active surface and touching the chip edges will be solved.

Description

Γ353664 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種背對背堆疊之多晶片封裝技 術，特別係有關於一種防止晶片上沖線與碰觸晶片邊緣 之背對背堆疊之多晶片封裝構造及其製造方法。 【先前技術】 在積體電路之多晶片封裝構造的領域中，複數個半 導體晶片可堆疊設置於一基板上，以達到高密度之封裝 並節省整個元件的表面接合面積。其中，依晶片主動面 朝向方向的不相同，晶片堆疊方式可進一步區別為背對 面之晶片主動面朝上堆疊、面對面之覆晶堆疊以及背對 背之晶片堆疊。 請參閱第1圖所示，習知背對背堆疊之多晶片封裝 構造1 00主要包含一基板1 1 0、背對背堆疊之一第一晶 片120與一第二晶片140、複數個銲線13 1與132、以 及一模封膠體160。該第一晶片120之第一主動面121 係貼附於該基板1 1 0之上表面111，並使複數個位於該 第一主動面121之中央銲墊123對準於該基板110之打 -線槽孔1 1 3内。該些第一銲線1 3 1通過該打線槽孔11 3 以電性連接該些中央銲墊1 23至該基板1 1 0。該第二晶 片1 40之第二背面1 42係貼附於該第一晶片1 20之第一 背面1 22，即背對背方式晶片堆疊。該第二晶片140之 第二主動面141係形成有複數個周邊銲墊143，可藉由 該些第二銲線132電性連接該些周邊銲墊143至該基板 5 1353664 1 1 0。該模封膠體1 6 0係用以密封該第一晶片120 第二晶片1 40以及該些銲線1 3 1與1 3 2。複數個外 子170係設置於該基板110之下表面112。然而， 一晶片 1 2 0與該第二晶片1 4 0之銲墊配置位置並 同，方可減少該些銲線132在該第二晶片140上的 長度，故在製造時則必須製作不同種類之晶片，該 晶片 140在晶圓等級須另製作一層重分配線 (Redistribution Layer, RDL)以將原在中央鲜墊之 改變為周邊銲墊143，使得製造成本增加，並因晶 類增加亦會造成物料較難以控管。 我國專利公告第 407354號「一種雙晶片之封 造」，揭示一種以背對背晶片堆疊方式多晶片封 造，其中上層晶片與下層晶片係具有配置位置相同 央銲墊，故可減少晶片種類以降低製造成本。當上 線電性連接上層晶片之中央銲墊至基板時，上層銲 上層晶片之主動面之懸空長度較長，在模封時，由 封膠體之注膠沖擊力將使上層銲線產生沖線問題 外，上層晶之中央銲墊與基板之打線接指不在同 面，上層銲線易接觸到上層晶片之邊緣造成短路 題。 【發明内容】 本發明之主要目的係在於提供一種背對背堆疊 晶片封裝構造及其製造方法，可選用相同具有中央 配置之上層晶片與下層晶片做背對背晶片堆疊，藉 、該 接端 該第 不相 懸空 第二 路層 位置 片種 裝構 裝構 之中 層銲 線在 於模 0此 一平 之問 之多 銲墊 以降 6 Γ353664 低晶片之製造成本與管理成本，並能解決長銲線在上 晶片上沖線以及碰觸晶片邊緣之問題。 本發明之次一目的係在於提供一種背對背堆疊之 晶片封裝構造及其製造方法，得有效界定所使用之線 結元件之形成區域。 本發明之另一目的係在於提供一種背對背堆疊之 晶片封裝構造及其製造方法，能修正並固定長銲線在 層晶片上之形狀，以使長銲線在該上層晶片上為接近 平，並在該上層晶片之邊緣能為大幅度彎曲。 本發明之另一目的係在於提供一種背對背堆疊之 晶片封裝構造及其製造方法，能創造一種模擬下模流 道之上模流通道，以達上下模流平衡。 本發明的目的及解決其技術問題是採用以下技術 案來實現的。依據本發明之一種背對背堆疊之多晶片 裝構造主要包含一基板、一第一晶片、複數個第一 線、一第二晶片、複數個第二銲線、至少一線凍結元 以及一模封膠體。該第一晶片係設置於該基板上並具 複數個第一銲墊。該些第一銲線係電性連接該第一晶 之該些第一銲墊至該基板。該第二晶片係以背對背堆 方式設置於該第一晶片上並具有複數個第二銲墊。該 第二銲線係電性連接該第二晶片之該些第二銲墊至 基板。該線凍結元件係黏附至該第二晶片之一主動面 並包覆該些第二銲線之一局部線段。該模封膠體係密 該些第一銲線、該些第二銲線、該第一晶片、一第二 層 多 凍 多 上 水 多 通 方 封 銲 件 有 片 疊 些 該 上 封 晶 7 I3536'64 片以及該線凍結元件。其中，該些第一銲墊與該些第二 銲墊皆為中央型銲墊，以使該些第二銲線長於該些第一 銲線。此外，另揭示前述背對背堆疊之多晶片封裝構 造之製造方法。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的背對背堆疊之多晶片封裝構造中，該第一晶 片與該第二晶片係可為實質相同之晶片。 • 在前述的背對背堆疊之多晶片封裝構造中，該線凍結 . 元件係可為液態塗佈之固化膠體。 在前述的背對背堆疊之多晶片封裝構造中，該線凍結 元件係可為複數條狀，並沿著該些第二銲墊之排列方向 黏附至該第二晶片之一主動面上。 在前述的背對背堆疊之多晶片封裝構造中，該基板係 可具有一打線槽孔，以供該些第一銲線之通過，並且該 I 些線凍結元件係不覆蓋該些第二銲墊，以使該些線凍結 元件在條與條之間係形成有一上模流通道。 在前述的背對背堆疊之多晶片封裝構造中，由該些條 .狀線凍結元件形成之該上模流通道係可具有一間隙，其 係不小於該打線槽孔之寬度。 在前述的背對背堆疊之多晶片封裝構造中，該些線凍 結元件係可不覆蓋至該第一晶片與該第二晶片之側面 以及該基板之一上表面。 在前述的背對背堆疊之多晶片封裝構造中，該線凍結 8 1353664 元件係可包含有一線徵以及一覆線物質，其中該線徵係 位於該些第二銲線之下方，用以支撐該些第二鍀線並定 義該些第二鲜線被該覆線物質包覆之局部線段。 在前述的背對背堆疊之多晶片封裝構造中，該線墩係 可為LOC(Lead-〇n-Chip，引腳在晶片上蜇式）黏晶膠 帶。 在前述的背對背堆疊之多晶片封裝構造中，該覆線物 質係可為液態環氧樹脂。 在前述的背對背堆疊之多晶片封裝構造中，可另包含 有複數個LOC黏晶膠帶，以黏著該第一晶片之一主動 面至該基板。 在前述的背對背堆疊之多晶片封裝構造中，可另包含 有複數個外接端子，其係接合該基板之一下表面。 在前述的背對背堆疊之多晶片封裝構造中，該些外接 端子係可包含複數個銲球。 【實施方式】 依據本發明之第一具體實施例，具體揭示一種背對 背堆疊之多晶片封裝構造。請參閱第2圖所示，一種背 對背堆疊之多晶片封裝構造200主要包含一基板2丨〇、 一第一晶片2 2 0、複數個第一銲線2 3 j、一第二晶片 240、複數個第二銲線232、至少一線凍結元件25〇以 及一模封膠體2 6 0。 該基板210係具有一上表面211、—下表面212以 及一打線槽孔2 1 3，該打線槽孔2 1 3係由該上表面2 1 1 9 1353664 貫穿至該下表面212，以供該些第一銲線 該下表面2 1 2位於該打線槽孔2 1 3之兩側 個複數第一接指214’該上表面211係形 二接指215。而該基板210係可為多層印 使該些第一接指214與該些第二接指215 該下表面212之外接墊（圖中未緣出，在 端子170之接合部位）。 該第一晶片2 2 0係設置於該基板2 1 〇 並具有一第一主動面22 1以及一相對之第 該第一主動面221係形成有複數個第一銲 位於該第一主動面 221之中央區域，即 223為中央銲墊。其中，該第一晶片220 面221係朝向該基板210並使該些第一銲 於該打線槽孔2 1 3内。該些第一銲線23 1 槽孔213並電性連接該第一晶片220之 223至該基板210之該些第一接指214， 片220與該基板210之電性互連。 該第二晶片2 4 0係具有一第二主動面 之第二背面242以及複數個形成於該第二 第二銲墊2M。該第二晶片240之該第二 設於該第一晶片220之該第一背面222， 240係以背對背晶片堆疊方式設置於該 上，而使該第二主動面241係為朝上。請 示，該些第二銲墊243係位於該第二晶片 23 1之通過》 係形成有複數 成有複數個第 刷電路板，以 電性連接至在 第2圖中外接 之上表面211 一背面222 ， 墊2 2 3，其係 該些第一銲墊 之該第一主動 墊223係對準 係通過該打線 該些第一銲墊 達到該第一晶 2 41、一相對 主動面24 1之 背面242係貼 即該第二晶片 第一晶片220 參閱第3圖所 240之該第二 10Γ 353664 IX. DESCRIPTION OF THE INVENTION: 1. Field of the Invention This invention relates to a multi-chip package technology for back-to-back stacking, and more particularly to a multi-chip package structure for preventing back-to-back stacking of punched and touched wafer edges on a wafer. And its manufacturing method. [Prior Art] In the field of multi-chip package construction of integrated circuits, a plurality of semiconductor wafers can be stacked on a substrate to achieve high-density packaging and save surface joint area of the entire component. Wherein, depending on the orientation of the active faces of the wafers, the wafer stacking pattern can be further distinguished by the wafer face active face-up stacking, the face-to-face flip chip stacking, and the back-to-back wafer stack. Referring to FIG. 1 , a conventional back-to-back stacked multi-chip package structure 100 mainly includes a substrate 110, a back-to-back stack, a first wafer 120 and a second wafer 140, and a plurality of bonding wires 13 1 and 132. And a molding encapsulant 160. The first active surface 121 of the first wafer 120 is attached to the upper surface 111 of the substrate 110, and a plurality of central pads 123 located on the first active surface 121 are aligned with the substrate 110. The slot hole is 1 1 3 inside. The first bonding wires 133 are electrically connected to the central pads 1 23 to the substrate 110 through the wire slot holes 11 3 . The second back surface 1 42 of the second wafer 140 is attached to the first back surface 1 22 of the first wafer 120, i.e., a back-to-back wafer stack. The second active surface 141 of the second wafer 140 is formed with a plurality of peripheral pads 143. The second bonding wires 132 are electrically connected to the peripheral pads 143 to the substrate 5 1353664 1 1 0. The molding compound 160 is used to seal the first wafer 120 and the second wafers 140 and the bonding wires 133 and 133. A plurality of outer 170s are disposed on the lower surface 112 of the substrate 110. However, the position of the pads of the second wafer 140 is the same as that of the second wafer 140, so that the length of the bonding wires 132 on the second wafer 140 can be reduced, so different types must be fabricated during manufacturing. The wafer 140 has a redistribution layer (RDL) at the wafer level to change the original fresh pad to the peripheral pad 143, so that the manufacturing cost increases and the crystal type increases. The material is more difficult to control. China Patent Publication No. 407,354, "A Double-Chip Sealing", discloses a multi-wafer sealing in a back-to-back wafer stacking manner, in which the upper wafer and the lower wafer have the same layout pads, so that the wafer type can be reduced to reduce manufacturing. cost. When the upper wire is electrically connected to the central pad of the upper layer wafer to the substrate, the active surface of the upper layer of the upper layer wafer has a longer flying length. When the molding is performed, the impact force of the sealing body of the upper sealing layer causes the upper bonding wire to have a problem of punching. In addition, the central pad of the upper layer is not in the same plane as the wire bonding of the substrate, and the upper bonding wire is easy to contact the edge of the upper wafer to cause a short circuit problem. SUMMARY OF THE INVENTION The main object of the present invention is to provide a back-to-back stacked chip package structure and a manufacturing method thereof, which can be used as a back-to-back wafer stack having the same central layer and the lower layer wafer, and the terminal is not suspended. The middle layer of the second layer position is a multi-layer solder pad that reduces the manufacturing cost and management cost of the low-wafer chip, and can solve the long solder wire on the upper wafer. And the problem of touching the edge of the wafer. A second object of the present invention is to provide a wafer package structure for back-to-back stacking and a method of fabricating the same that effectively defines the formation regions of the wire bond components used. Another object of the present invention is to provide a back-to-back stacked chip package structure and a method of fabricating the same that can correct and fix the shape of a long bond wire on a layer wafer such that the long bond wire is nearly flat on the upper wafer, and The edge of the upper wafer can be greatly curved. Another object of the present invention is to provide a back-to-back stacked wafer package structure and a method of fabricating the same that can create a simulated mold flow channel above the lower mold flow path for up-and-down mold flow balance. The object of the present invention and solving the technical problems thereof are achieved by the following techniques. A multi-chip package structure for back-to-back stacking according to the present invention mainly comprises a substrate, a first wafer, a plurality of first lines, a second wafer, a plurality of second bonding wires, at least one wire freezing element, and a molding compound. The first wafer is disposed on the substrate and has a plurality of first pads. The first bonding wires are electrically connected to the first pads of the first crystal to the substrate. The second wafer is disposed on the first wafer in a back-to-back stack and has a plurality of second pads. The second bonding wire is electrically connected to the second pads of the second wafer to the substrate. The wire freezing component is adhered to one of the active faces of the second wafer and covers a partial line segment of the second bonding wires. The mold sealing system is dense with the first bonding wires, the second bonding wires, the first wafer, and a second layer of multi-frozen multi-water multi-passing sealing members having a stack of the upper sealing crystals 7 I3536' 64 pieces and the line freeze component. The first bonding pads and the second bonding pads are all central bonding pads, so that the second bonding wires are longer than the first bonding wires. Further, a manufacturing method of the above-described back-to-back stacked multi-wafer package structure is disclosed. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the multi-chip package construction of the back-to-back stack described above, the first wafer and the second wafer may be substantially identical wafers. • In the aforementioned back-to-back stacked multi-chip package construction, the line is frozen. The component can be a liquid coated cured colloid. In the foregoing multi-chip package structure of the back-to-back stack, the line freeze element may be in a plurality of strips and adhered to one of the active faces of the second wafer along the arrangement direction of the second pads. In the multi-chip package structure of the back-to-back stack, the substrate may have a wire slot for the first wire to pass, and the wire freeze elements do not cover the second pads. So that the line freezing elements form an upper mold flow channel between the strips. In the multi-chip package construction of the back-to-back stack described above, the upper mold flow path formed by the strip-shaped line freezing elements may have a gap which is not less than the width of the wire-groove hole. In the multi-chip package construction of the back-to-back stack described above, the wire-freezing components may not cover the sides of the first wafer and the second wafer and the upper surface of one of the substrates. In the foregoing multi-chip package structure of the back-to-back stack, the line freeze 8 1353664 component may include a line sign and a wire covering substance, wherein the line sign is located below the second wire lines to support the line The second line defines a partial line segment in which the second fresh line is covered by the covering material. In the multi-chip package construction of the back-to-back stack described above, the line can be a LOC (Lead-〇n-Chip) die bond adhesive tape. In the aforementioned multi-chip package construction of back-to-back stacking, the overlying material system may be a liquid epoxy resin. In the foregoing multi-chip package construction of back-to-back stacking, a plurality of LOC die-bonding tapes may be additionally included to adhere the active surface of one of the first wafers to the substrate. In the foregoing multi-chip package construction of back-to-back stacking, a plurality of external terminals may be further included which are bonded to a lower surface of the substrate. In the aforementioned multi-chip package construction of back-to-back stacking, the external terminals may comprise a plurality of solder balls. [Embodiment] According to a first embodiment of the present invention, a multi-chip package structure of a back-to-back stack is specifically disclosed. Referring to FIG. 2, a multi-chip package structure 200 for back-to-back stacking mainly includes a substrate 2, a first wafer 2 2 0, a plurality of first bonding wires 2 3 j , a second wafer 240, and a plurality A second bonding wire 232, at least one wire freezing component 25A, and a molding compound 260. The substrate 210 has an upper surface 211, a lower surface 212, and a wire slot 2 1 3, and the wire slot 2 1 3 is penetrated from the upper surface 2 1 1 9 1353664 to the lower surface 212 for the The lower surface 2 1 2 of the first bonding wire is located on the two sides of the wire slot 2 1 3, and the upper surface 211 is formed by the second finger 215. The substrate 210 can be multi-layer printed with the first contact fingers 214 and the second contact fingers 215 of the lower surface 212 of the outer pads (not shown in the figure, at the junction of the terminals 170). The first wafer 220 is disposed on the substrate 2 1 〇 and has a first active surface 22 1 and an opposite first active surface 221 is formed with a plurality of first solders on the first active surface 221 . The central area, 223, is the center pad. The first wafer 220 surface 221 faces the substrate 210 and the first portions are soldered into the wire slot 2 1 3 . The first bonding wires 23 1 are electrically connected to the first electrodes 220 of the first substrate 220 to the first contacts 214 of the substrate 210 , and the pads 220 are electrically connected to the substrate 210 . The second wafer 240 is a second back surface 242 having a second active surface and a plurality of second pads 2M are formed on the second surface. The second back surface 222, 240 of the second wafer 240 disposed on the first wafer 220 is disposed on the back-to-back wafer stack such that the second active surface 241 is oriented upward. It is noted that the second pads 243 are located on the second wafer 23 1 and are formed with a plurality of second brush circuit boards electrically connected to the outer surface 211 of the second surface in FIG. 222, a pad 2 2 3, wherein the first active pads 223 of the first pads are aligned, and the first pads 2 41 and a relative active surface 24 1 are obtained by the wires. The back surface 242 is attached to the second wafer first wafer 220. Referring to the second 10 in FIG.

1353664 動面241之中央區域，故該些第二銲塾243 銲墊。較佳地，該第—晶片220與該第二晶片 為實質相同之晶片’例如晶片尺寸、電性功能 置位置皆為相同’以減少晶片種類進而降低晶 成本與官理成本。該些第二銲線232係電性連 晶片240之該些第二銲墊243至該基板210之 接指215,達到該第二晶片24〇與該基板21〇 連。因此，該些第一銲墊2 23與該些第二銲墊 中央型銲墊，並使該些第二銲線232長於該些 23 1° 请參閱第2圖所示，該線凍結元件25〇令 第二銲線232之一局部線段並黏附至該第二^ 該第二主動Φ 241上。這裡所指的「凍結“ 結元件250在塗施時為液態或膠態而具有^ 性，並在產品完成後為固態，以固著封住該在 232。該線凌結元件25〇係可為液態塗佈之吕 具有熱固化性或光m化性’能包覆銲線線段3 於該第二晶片240之該第二主動面241。請^ 所示，在本實施例中，該線凍結元件25〇係$ 狀，並沿著該些第二薛塾243之#列方向黏托 晶片240之該第三主動面241上，具有打線招 之功效。請參閱第2圖所示，該些線凍結元辛 不覆蓋至該第一晶片220與該第二晶片24〇戈 該基板210之該上表面211，即位於該些第_ 亦為中央 240係可 與銲墊配 片之製造 接該第二 該些第二 之電性互 243皆為 第一銲線 包覆該些 片240之 指該線）東 當之流動 第二銲線 化膠體， 後更附著 閱第4圖 為複數條 至該第二 易於塗佈 250係可 側面以及 銲線232 111353664 The central area of the moving surface 241, so the second soldering 243 pads. Preferably, the first wafer 220 and the second wafer are substantially the same wafers, for example, the wafer size and the electrical functional position are the same 'to reduce the wafer type and thereby reduce the crystal cost and the legal cost. The second bonding wires 232 are electrically connected to the second pads 243 of the wafer 240 to the contacts 215 of the substrate 210, so that the second wafer 24 is connected to the substrate 21. Therefore, the first pad 2 23 and the second pad central type pads, and the second bonding wires 232 are longer than the 23 1°, as shown in FIG. 2, the line freezing element 25 A partial line segment of the second bonding wire 232 is adhered to the second second active Φ 241. The "frozen" knot member 250 referred to herein is liquid or colloidal when applied, and is solid after completion of the product to secure the seal at 232. The wire splicing element 25 can be a liquid coated lacquer having a thermosetting or photo-makeability capable of covering the wire segment 3 to the second active surface 241 of the second wafer 240. In the present embodiment, the line freezing element 25 is $-shaped, and the third active surface 241 of the wafer 240 is adhered along the # column direction of the second 塾243. The effect of recruiting. Referring to FIG. 2, the line freeze elements do not cover the first wafer 220 and the second wafer 24, and the upper surface 211 of the substrate 210 is located at the first and second centers. The second electrical mutual 243 may be connected to the second bonding wire 243 of the first bonding wire to cover the wire 240). More attached to Figure 4 is a plurality of strips to the second easy to apply 250 series side and wire 232 11

1353664 之最高弧向處，以増加兮此治土 770。哀些線凍結元件250固化 重效果，藉以改變並固定兮*社 該些第二銲線232在第 2 4 0上之形狀。在該線凌沾_ 粟、疋件2 5 0轉變成固態 巧*以避免該些第二銲飨Μ，+ 冲碌23 2在該第二晶片24〇上 線與避免碰觸至該第二晶κ Β曰片2 4 〇之邊緣。 該模封膠體260俜宓以# , 糸在封該些第一銲線231、 二銲線232、該第一晶Η 日曰片220、一第二晶片24〇 線凍結元件2 5 0 ’以避备 避免或背對背堆疊之多晶片 造200之内部元件受到外 界污¥物污染。較佳址 線束結元件250係不覆蓋該些第二銲墊243,以 線康結元# 250在條與條之間係形成有一上模 261 ’其係對稱形成於該 、 邊打線槽孔2丨3之下模 262，以在模封時達上下 、机之平衡《在本實施 由該些條狀線凍結元件Μ Λ… 日七ρ^βλ ^ 5〇形成之該上模流通i| 可具有一間隙’其係不小 ^ 个j於该打線槽孔213之$ 具體而言，該背對背堆 s之夕曰日片封裝構造 玎另包含有複數個外接端子2 Y稱& ) 其係接合該基 之該下表面2 1 2，以作*兮也μ a邗马”亥背對背堆疊之多晶片 造200之輸出/輸入端’用以電性連接之一外部 印刷電路板。在本實施例中，該些外接端子2 7 〇 含複數個鮮球。 因此’本發明之該背對背堆疊之多晶片封裝才』 可使用實質相同的該第一晶片220與該望_曰u ^ —晶片 堆疊’也因而不必耗時費工地製作另一種周邊鲜 前的垂 一晶片 之後， 產生沖 該些第 以及該 封裝構 ，該些 使該些 流通道 流通道 例中， 26 1係 ，度。 200係 板210 封裴構 裝置如 係可包 :造 200 240做 墊型之 12 1353664 晶月’不僅可降低晶片之製造成本也可使晶片物料較易 於控管。此外，亦可藉由該線凍結元件2 5 〇穩固該些第 二銲線232’避免在封膠過程中該些第二銲線232產生 沖線之現象或/及碰觸至該第二晶片24〇之第二主動面 24 1之邊緣’而引發短路或是損害該些第二銲線23 2之 電性連接品質。 第5 A至5 Η圖係用以說明前述背對背堆疊之多晶片 封裝構造2 00之一具體製造方法。首先，請參閱第5Α 圖所示’提供一基板210，該基板210係具有一上表面 211、一下表面212以及一打線槽孔213，該下表面212 係形成有複數個位於該打線槽孔2 1 3兩側之第一接指 2 1 4 ’該上表面2 1 1係形成有複數個第二接指2 1 5。 接著’請參閱第5Β圖所示，設置一第一晶片220 於該基板210之該上表面211。其中該第一晶片220係 以該第一主動面221朝下之方式貼設於該基板210,並 使該些第一銲墊223對準於該打線槽扎2 13内’以顯露 該些第一銲墊223。接著，請參閱第5C圖所示’打線 (wire-bonding)形成複數個第一銲線23卜其係穿過該打 線槽孔213並電性連接該第一晶片220之該些第一銲塾 223至該基板210之該些第一接指214。 在第一次電性連接後，請參閱第5D圖所示，以背對 背堆疊方式設置一第二晶片240於該第一晶片220上’ 也就是將該第二晶片24〇之一第二背面242貼設於該第 一晶片220之該第一背面222。其中，該第二晶片240 13 1353664 係具有複數個第二銲墊243，其係形成至該 240之一第二主動面241之中央區域。接著， 5E圖所示，打線形成複數個第二銲線232以 該第二晶片240之該些第二銲墊243至該基板 些第二接指215。其中，該些第一銲墊2 23與 銲墊243皆為中央型銲墊，以使該些第二銲線 該些第一銲線23 1。 之後，請參閱第5F及4圖所示，形成至少 元件2 5 0於該第二晶片2 4 0上，該線凍結元件 包覆該些第二銲線23 2之一局部線段，再黏附 主動面2 4 1上。在本實施例中，該線凍結元件 為液態塗佈之固化膠體，以液態塗晝方式黏附 晶片2 4 0並加以熟化。例如，能以加熱或照射 適當之手段使該線凍結元件2 5 0轉變為固態。 結元件2 5 0在塗施時係可為膠稠態，又形成於 銲線230之最高弧高處，提供一較佳垂重效果 正該些第二銲線230之形狀。在一較佳狀態， 銲線232在該第二晶片240之第二主動面241 呈接近水平，並在該第二晶片240之第二主動 邊緣能為大幅度彎曲。當該線凍結元件 2 5 0 態，能固定封住該些第二銲線2 3 2之易沖線線 免在後續模封製程中產生沖線。 最後，請參閱第5G圖所示，形成一模封 於該基板210之該上表面211與該下表面21: 第二晶片 請參閱第 電性連接 210之該 該些第二 232長於 一線束結 250係先 至該第二 250係可 至該第二 紫外光等 當該線凍 該些第二 ，藉以修 該些第二 之上方概 面241之 轉變成固 段，以避 膠體 260 ，用以密 14 切 3664 封該些第一銲線231、該些第二銲線232、該第一晶片 220、一第二晶片240以及該線凍結元件250。具體而 S ’請參閱第5H圖所示，該背對背堆疊之多晶片封裝 構造2〇〇之製造方法係可另包含之步驟有：設置複數個 外接端子270以接合該基板210之該下表面212。The highest arc of 1353664 is added to the 770. The line freeze element 250 cures the weight effect, thereby changing and fixing the shape of the second wire 232 on the 240th. In the line Ling _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ κ Β曰 2 2 〇 〇 edge. The molding compound 260 is sealed with the first bonding wire 231, the second bonding wire 232, the first wafer bonding plate 220, and the second wafer 24, and the wire freezing component 2 5 0 ' The internal components of the multi-wafer fabrication 200 that avoids or are stacked back-to-back are contaminated by external contamination. Preferably, the wire bundle bonding component 250 does not cover the second bonding pads 243, and an upper die 261 is formed between the strips and the wires by the wire bonding element #250. The system is symmetrically formed on the side wire slot 2丨3 below the mold 262, in order to achieve the balance of the upper and lower, the machine in the mold sealing "in this implementation by the strip line freezing element Λ 日 ... 七 ρ ^ β λ ^ 5 之 formed by the upper mold i| Specifically, the back-to-back stack s has a plurality of external terminals 2 Y & Bonding the lower surface 2 1 2 of the base to make the output/input end of the multi-chip stack 200 of the back-to-back stack for electrically connecting one of the external printed circuit boards. In the example, the external terminals 27 7 include a plurality of fresh balls. Therefore, the multi-chip package of the back-to-back stack of the present invention can use substantially the same first wafer 220 and the wafer stack. 'Therefore, it is not necessary to take time and effort to make another kind of peripherally floating wafer. The first and the package structure, the flow channel of the flow channel, in the example of 26 1 system, the 200-series plate 210 sealing device can be packaged: made of 200 240 do pad type 12 1353664 crystal moon 'not only The manufacturing cost of the wafer can be reduced, and the wafer material can be easily controlled. Further, the second bonding wire 232' can be stabilized by the wire freezing component 2 5 to avoid the second bonding wire during the sealing process. 232 generates a phenomenon of punching or/and touches the edge of the second active surface 24 1 of the second wafer 24 to cause a short circuit or damage the electrical connection quality of the second bonding wires 23 2 . A to 5 is a specific manufacturing method for explaining the foregoing multi-chip package structure 200 of the back-to-back stack. First, please refer to FIG. 5 to provide a substrate 210 having an upper surface 211, The lower surface 212 and the first wire 212 are formed with a plurality of first fingers 2 1 4 ' on both sides of the wire slot 2 1 3 . The upper surface 2 1 1 is formed with a plurality of Two fingers 2 1 5. Then 'please refer to Figure 5, set one The wafer 220 is disposed on the upper surface 211 of the substrate 210. The first wafer 220 is attached to the substrate 210 with the first active surface 221 facing downward, and the first pads 223 are aligned with the substrate The wire slot 2 is inside the wire 2 to expose the first pads 223. Next, referring to the wire-bonding shown in FIG. 5C, a plurality of first bonding wires 23 are formed to pass through the wire slot. 213 and electrically connecting the first pads 223 of the first wafer 220 to the first fingers 214 of the substrate 210. After the first electrical connection, as shown in FIG. 5D, a second wafer 240 is disposed on the first wafer 220 in a back-to-back stacking manner, that is, the second wafer 24 is replaced by a second back surface 242. The first back surface 222 of the first wafer 220 is attached. The second wafer 240 13 1353664 has a plurality of second pads 243 formed in a central region of the second active surface 241 of the 240. Next, as shown in FIG. 5E, a plurality of second bonding wires 232 are formed by the second bonding pads 232 of the second wafer 240 to the second bonding fingers 215 of the substrate. The first pads 2 23 and the pads 243 are all central pads, so that the second wires are the first wires 23 1 . After that, as shown in FIGS. 5F and 4, at least the component 250 is formed on the second wafer 240, and the line freezing component covers a partial line segment of the second bonding wires 23, and then adheres to the active portion. Face 2 4 1 on. In this embodiment, the wire freezing member is a liquid-coated cured colloid, and the wafer 250 is adhered in a liquid coating manner and cured. For example, the wire freezing member 250 can be converted to a solid state by heating or irradiation. The junction element 250 can be in a colloidal state when applied, and formed at the highest arc height of the bonding wire 230 to provide a preferred sag effect. The shape of the second bonding wire 230. In a preferred state, the bonding wire 232 is approximately horizontal on the second active surface 241 of the second wafer 240 and can be substantially curved at the second active edge of the second wafer 240. When the line freezes the element 250 state, the easy-to-print line of the second bonding wire 2 3 2 can be fixedly sealed to avoid punching in the subsequent molding process. Finally, as shown in FIG. 5G, the upper surface 211 and the lower surface 21 of the substrate 210 are formed. The second wafer is referred to as the second electrical connection 210. The second 232 is longer than the first beam junction. The 250 series first to the second 250 series can be to the second ultraviolet light, etc., when the line freezes the second portions, thereby repairing the second upper surface 241 into a solid segment to avoid the colloid 260 for The first bonding wire 231, the second bonding wires 232, the first wafer 220, a second wafer 240, and the wire freezing member 250 are sealed. Specifically, as shown in FIG. 5H, the back-to-back stacked multi-chip package structure can further include a plurality of external terminals 270 for bonding the lower surface 212 of the substrate 210. .

在本發明之第二具體實施例中，揭示另一種背對背 堆叠之多晶片封裝構造，請參閱第6圖所示，該背對背 堆叠之多晶片封裝構造300主要包含一基板310、一第 ''晶片320、複數個第一銲線331、一第二晶片340、 複數個第二銲線3 3 2、至少一線凍結元件3 5 0以及一模 封膠體360。該基板3 10係具有一打線槽孔3 13，以供 。亥些苐一銲線3 3 1通過。該第一晶片3 2 〇係設置於該基 % 3 1 〇上並具有複數個第一銲墊323。在本實施例中’ @背對背堆疊之多晶片封裝構造3〇〇係可另包含有複數個 C點晶膠帶380’以黏著該第一晶片320之一第·一主 動面3 2 1至該基板3 1 0❶該些第一銲線3 3丨係電性連接 5亥第一晶片320之該些第一銲墊323至該基板310。 該第二晶片3 4 0係以背對背堆疊方式設置於該第一 晶片320上並具有複數個第二銲墊343，該些第二銲墊 343係位於該第二晶片340之一第二主動面341之中央 區域。該些第二銲線3 3 2係電性連接該第二晶片3 4 0之 該些第二銲垫3 43至該基板310。 部線段並黏附至該第二晶片340之一第二主動面341 15 1353664 上。請再參閱第6圖所示，在本實施例中，該線凍結元 件350係可包含有一線墩351以及一覆線物質352，其 中該線墩351係位於該些第二銲線332之下方，用以支 撐該些第二銲線332並定義該些第二銲線332被該覆線 物質352包覆之局部線段，可完全避免了該些第二銲線 3 3 2碰觸到該第二晶片3 40之可能性並限制了該覆線物 質了 5 2之形成區域。較佳地’該線徵3 5 1係可為 LOC(Lead-On-Chip，引腳在晶片上型式）黏晶膠帶，在 •該些第二銲線332形成之前，預先設置於該第二晶片 340上。該覆線物質352係可為液態環氧樹脂。該線墩 3 5 1能有效界疋所使用之線珠結元件3 5 〇之該覆線物質 3 5 2形成區域’避免該覆線物質3 52之溢流擴散。 該模封膠體360係密封該些第一銲線33丨、該些第 二銲線332、該第一晶片32〇、一第二晶片34〇以及該 線凍結元件350。該背對背堆疊之多晶片封裝構造3〇〇係 φ 可另包含有複數個接合至該基板310之外接端子3 7〇。 請參閱第6圖所示，由於該些第一銲墊323與該些第二 銲塾343皆為中央型鮮塾，故該些第二銲線332 i於該 些第一銲線331，藉由該線凍結元件35〇包覆該些第二 銲線332在該第二晶片34〇上之懸空部位，以避免晶片 上沖線或/及碰觸晶片邊緣。因此，該背對背堆疊之多 晶片封裝構造300除了可使用相同種類之晶片來降低 晶片之製造成本與管控成本之外，並可解決銲線長短不 一造成的封裝缺陷。 16 Γ353664 以上所述，僅是本發明的較佳實施例而已，教非對 本發明作任何形式上的限制，本發明技術方案範圚當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的住何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：一種習知背對背堆疊之多晶片封裝構造之裁面 示意圖。 第2圖：依據本發明之第一具體實施例，一種背對背堆 疊之多晶片封裝構造之截面示意圖。 第3圖：依據本發明之第一具體實施例，該背對背堆疊 之多晶片封裝構造中一第二晶片之第二主動面示 意圖。 第4圖：依據本發明之第一具體實施例，該背對背堆疊 之多晶片封裝構造中已設置第二晶片並形成有線 /東结元件之基板上表面示意圖。 第5 A至5 Η圖：依據本發明之第一具體實施例，該背 對背堆疊之多晶片封裝構造在製程中該基板截面 示意圖。 第6圖：依據本發明之第二具體實施例，另一種背對背 堆疊之多晶片封裝構造截面示意圖。 17 1353664In a second embodiment of the present invention, another back-to-back stacked multi-chip package structure is disclosed. Referring to FIG. 6, the back-to-back stacked multi-chip package structure 300 mainly includes a substrate 310 and a ''chip. 320, a plurality of first bonding wires 331, a second wafer 340, a plurality of second bonding wires 3 3 2, at least one wire freezing component 350 and a molding compound 360. The substrate 3 10 has a wire slot 3 13 for supply. A few of the weld lines 3 3 1 passed. The first wafer 3 2 is disposed on the base 3 3 1 , and has a plurality of first pads 323. In the present embodiment, the multi-chip package structure 3 of the back-to-back stack may further include a plurality of C-shaped crystal tapes 380' to adhere to one of the first active surfaces 320 of the first wafer 320 to the substrate. The first bonding wires 3 3 are electrically connected to the first pads 323 of the first wafer 320 of the first chip 320 to the substrate 310 . The second wafer 340 is disposed on the first wafer 320 in a back-to-back stacking manner and has a plurality of second pads 343 located on a second active surface of the second wafer 340. Central area of 341. The second bonding wires 323 are electrically connected to the second pads 343 of the second wafer 340 to the substrate 310. The line segment is adhered to the second active surface 341 15 1353664 of the second wafer 340. Referring to FIG. 6 again, in the embodiment, the wire freezing component 350 can include a wire pier 351 and a wire covering material 352, wherein the wire pier 351 is located below the second bonding wires 332. For supporting the second bonding wires 332 and defining a partial line segment of the second bonding wires 332 covered by the covering material 352, the second bonding wires 3 3 2 can be completely avoided. The possibility of two wafers 3 40 and limits the formation area of the covering material 52. Preferably, the line sign 35 1 may be a LOC (Lead-On-Chip) type of adhesive tape, which is preset to the second before the second wire 332 is formed. On wafer 340. The wire covering material 352 can be a liquid epoxy resin. The wire pier 35 1 is capable of effectively confining the wire-bonding element 3 5 〇 of the wire-wrapping material 3 5 2 forming region ‘to avoid overflow diffusion of the wire-covering material 3 52 . The molding compound 360 seals the first bonding wires 33, the second bonding wires 332, the first wafer 32, the second wafer 34, and the wire freezing member 350. The back-to-back stacked multi-chip package structure φ φ may further include a plurality of external terminals 3 7 接合 bonded to the substrate 310. Referring to FIG. 6 , since the first bonding pads 323 and the second bonding pads 343 are both central type, the second bonding wires 332 i are borrowed from the first bonding wires 331 . The wire freezing component 35 〇 covers the floating portions of the second bonding wires 332 on the second wafer 34 to avoid punching or/and touching the edge of the wafer. Therefore, the back-to-back stacked multi-chip package structure 300 can use the same kind of wafers to reduce the manufacturing cost and the control cost of the wafer, and can solve the package defects caused by the length of the bonding wires. The above is only a preferred embodiment of the present invention, and the teachings of the present invention are not limited thereto. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. The simple modifications, equivalent changes and modifications of the present invention are still within the scope of the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a conventional multi-chip package structure of a back-to-back stack. Figure 2 is a cross-sectional view showing a multi-chip package structure of a back-to-back stack in accordance with a first embodiment of the present invention. Figure 3: In accordance with a first embodiment of the present invention, a second active surface of a second wafer in the multi-chip package construction of the back-to-back stack is shown. Fig. 4 is a schematic view showing the upper surface of a substrate in which a second wafer is formed and a wired/east junction element is formed in the multi-chip package structure of the back-to-back stack according to the first embodiment of the present invention. 5A to 5: A cross-sectional view of the substrate in the process of the multi-chip package construction of the back-to-back stack in accordance with the first embodiment of the present invention. Figure 6 is a cross-sectional view showing another multi-chip package structure of a back-to-back stack in accordance with a second embodiment of the present invention. 17 1353664

【主要元件符號說明】 100 背對背堆疊. 多晶 片封裝構造 110 基板 111 上 表面 112 113 打線槽孔 120 第一晶片 121 第 一主動面 122 123 中央銲墊 131 第一銲線 132 第 二銲線 140 第—晶片 141 第 二主動面 142 143 周邊銲塾 160 模封膠體 170 外接端子 200 背對背堆疊. 之多晶 片封裝構造 210 基板 211 上 表面 212 213 打線槽孔 214 第 一接指 215 220 第—晶片 22 1 第 一主動面 222 223 第—銲墊 231 第—銲線 232 第 二銲線 240 第二晶片 241 第 二主動面 242 243 第二銲墊 250 線凍結元件 260 模封膠體 261 上 模流通道 262 270 外接端子 300 背對背堆疊 之多晶 片封裝構造 3 10 基板 313 打 線槽孔 320 第一日 y 321 第 ^ 日日月 一主動面 323 下表面 第一背面 第二背面 下表面 第二接指 第一背面 第二背面 下模流通道 第一銲墊 18 1353664 331 第一銲線 332 第二銲線 340 第二晶片 341 第二主動面 343第二銲墊 350 線凍結元件 351 線墩 352 覆線物質 360 模封膠體 370 外接端子 3 80 LOC黏晶膠帶[Main component symbol description] 100 Back-to-back stacking. Multi-chip package structure 110 substrate 111 upper surface 112 113 wire slot 120 first wafer 121 first active surface 122 123 central pad 131 first bonding wire 132 second bonding wire 140 — wafer 141 second active surface 142 143 peripheral solder fillet 160 mold seal 170 external terminal 200 back-to-back stack. Multi-chip package structure 210 substrate 211 upper surface 212 213 wire slot 214 first finger 215 220 first wafer 22 1 First active surface 222 223 first-pad 231 first-bonding wire 232 second bonding wire 240 second wafer 241 second active surface 242 243 second bonding pad 250 wire freezing element 260 molding compound 261 upper molding flow channel 262 270 External terminal 300 Back-to-back stacked multi-chip package structure 3 10 Substrate 313 Wire slot 320 First day y 321 The second day of the day, the active surface 323, the lower surface, the first back, the second back, the second surface, the second finger, the first back Second back lower mold flow channel first pad 18 1353664 331 first bond wire 332 A second bonding wire 340 of the second wafer 341 active surface 343 of the second pad 350 line 351 line elements pier freeze-wire 352 molded encapsulant material 360 external connection terminal 370 3 80 LOC die-tape

1919

Claims (1)

1353664 “年5/日修 、申請專利範圍： 、-種背對背堆疊之多晶片封I構造，包含 一基板； :第—晶片，係設置於該基板上並具有複數個第一銲墊； 複數個第一銲線’係電性連接該第一晶片之該些第一銲 墊至該基板； 二第二晶片，係以背對背堆疊方式設置於該第一晶片上 並具有複數個第二銲墊； 複數個第二輝線，係電性連接該第二晶片之該些第 墊至該基板； 至少-線康結元件，係包覆該些第二銲線之一局部線段 並黏附至該第二晶片之一主動面上；以及 -模封膠體’至少形成於該基板上，藉以密封該此第一 銲線、該些第二銲線、該第一晶 乐一曰曰片U及該 線凍結元件； 其中’該些第-銲塾與該些第二銲塾皆為中央型鲜塾， 以使該些第二銲線長於該些第一銲線； 其中’該線凍結元件係包含有一線墩以及一覆線物質， 其中該線墩係位於料第二料之下方心支樓該些 第二録線並定義該些第二銲線被該覆線物質包覆之局部 線段° 2、如申請專利範圍第i項所述之背對背堆疊之多晶片封裝 構造，其中該第一晶片與該第二晶片係為實質相同之晶 片。 θ 20 1353664 3、 如申請專利範圍帛1項所述之背對背堆疊之多晶片封裝 構造，其中該線凍結元件係為液態塗佈之固化膠體。 4、 如中請專利範圍第1項所述之背對背堆疊之多晶片封裝 構造，其中該線凍結元件係為複數條狀，並沿著該些第 二銲墊之排列方向黏附至該第二晶片之一主動面上。 5、 如申請專利範圍第4項所述之背對背堆疊之多晶片封裝 構造，其中s玄基板係具有一打線槽孔，以供該些第—銲 線之通過，並且該些線凍結元件係不覆蓋該些第二銲 墊，以使該些線凍結元件在條與條之間係形成有一上模 流通道。 6、 如申請專利範圍第5項所述之背對背堆疊之多晶片封裝 構造，其中由該些條狀線凍結元件形成之該上模流通道 係具有一間隙，其係不小於該打線槽孔之寬度。 7、 如申請專利範圍第丨項所述之背對背堆疊之多晶片封裝 構造，其中該些線凍結元件係不覆蓋至該第一晶片與該 第二晶片之側面以及該基板之一上表面。 8、 如申請專利範圍第1項所述之背對背堆疊之多晶片封裝 構造，其中該線墩係為LOC(Lead-0n_Chip，引腳在晶片 上型式）黏晶膠帶。 9、 如申請專利範圍第丨項所述之背對背堆疊之多晶片封裝 構造’其中該覆線物質係為液態環氧樹脂。 1 0、如申請專利範圍第j項所述之背對背堆疊之多晶片封 裝構造’另包含有複數個LOC黏晶膠帶，以黏著該第_ 晶片之一主動面至該基板。 21 1353664 U、如申請專利範圍第1項所述之背對背堆疊之多曰片封 裝構造，另包含有複數個外接端子，其係接合該基板之 —下表面。 12、 如中請專利範圍第n項所述之背對背堆疊之多晶片封 裝構造，其中該些外接端子係包含複數個銲球。 13、 -種背對背堆疊之多晶片封裝構造之製造方法，包含 以下步騾： 提供一基板； 〇又置一第一晶片於該基板上，該笛 B Li〆 ^ 4弟一晶片係具有複數個 第一銲墊； 形成複數個第一銲線’以電性連接該第一晶片之該些第 一銲墊至該基板； 以背對背堆疊方式設置一第-曰 瓦y叭。又1 弟一日日片於該第一晶片上，該 第二晶片係具有複數個第二銲墊； 形成複數個第二銲線，以電性連接該第二晶片之該些第 二銲墊至該基板，其中，該些第一銲墊與該些第二銲墊 皆為中央型銲墊，以使該些第二銲線备於該些第一銲線； 形成至少一線凍結元件，其係包覆該些第二銲線之一局 琿線K並黏附至該第二晶片之一主動面上，其中該線凍 結元件係包含有一線墩以及一覆線物質，其中該線墩係 位於該些第二銲線之下方，用以支撐該些第二銲線並定 義該些第二銲線被該覆線物質包覆之局部線段；以及 形成—模封膠體，以密封該些第一銲線、該些第二銲線、 該第一晶片、一第二晶片以及該線凍結元件。 22 1353664 14、 如申請專利範圍第13項所述之背對背堆疊之多晶 裝構造之製造方法’其中該第一晶片與該第二二曰係工 實質相同之晶片，並使該第一晶片盥 ·" -、邊弟二晶片為同中 心地完全重疊。 15、 如申請專利範圍第13項所述之背對背堆疊之多晶片、 裝構造之製造方法，其中該線凍結元封 τ你為液態塗佈之 固化膠體’以液態塗晝方式黏附至該 不~ B日片並加以孰 化。 16、如申請專利範圍第13項所述之背對背堆疊之多晶片 裝構造之製造方法，其中該線;東結元件係為複^狀封 並沿著該些第二銲墊之排列方向黏附至該第二晶片之— 主動面上。 17、 如申請專利範圍第16項所述之背對背堆疊之多晶片封 裝構造之製造方法，其中該基板係具有一打線糟孔以 供該呰第一銲線之通過，並且該些線凍結元件係不覆蓋 該些第二銲墊，以使該些線凍結元件在條與條之間係形 成有一上模流通道。 18、 如申請專利範圍第13項所述之背對背堆疊之多晶片封 裝構造之製造方法’另包含之步驟有：設置複數個外接 端子’以接合該基板之一下表面。 231353664 "Annual 5/day repair, patent application scope: - a multi-chip package I structure stacked back-to-back, comprising a substrate; a first wafer disposed on the substrate and having a plurality of first pads; a plurality of The first bonding wire is electrically connected to the first pads of the first wafer to the substrate; the second wafer is disposed on the first wafer in a back-to-back stacking manner and has a plurality of second pads; a plurality of second illuminating wires electrically connecting the pads of the second wafer to the substrate; at least a wire bonding component covering a partial line segment of the second bonding wires and adhering to the second wafer An active surface; and a mold encapsulant ' is formed at least on the substrate, thereby sealing the first bonding wire, the second bonding wires, the first crystal fiber U and the wire freezing component Wherein the 'the first and the second welding borings are both central squeegees, so that the second bonding wires are longer than the first bonding wires; wherein the wire freezing component comprises a wire pier And a covered material, wherein the line is located in the second The second line of the lower branch of the heart and defines a partial line segment of the second wire covered by the wire covering material. 2. The multi-chip package structure of the back-to-back stack as described in claim i, The first wafer and the second wafer are substantially identical wafers. θ 20 1353664 3. The multi-chip package structure of the back-to-back stack according to claim 1, wherein the wire freezing component is liquid coating 4. The multi-chip package structure of the back-to-back stack according to claim 1, wherein the line freeze element is in a plurality of strips and adheres to the arrangement direction of the second pads to 5. The multi-chip package structure of the back-to-back stack according to claim 4, wherein the s-substrate has a wire slot for the first wire bond. Passing, and the line freezing elements do not cover the second pads, so that the line freezing elements form an upper mold flow channel between the strips. 6. As described in claim 5 a multi-chip package structure stacked back-to-back, wherein the upper mold flow channel formed by the strip line freezing elements has a gap which is not less than a width of the wire slot. 7. The multi-chip package structure of the back-to-back stack, wherein the line freeze elements do not cover the sides of the first wafer and the second wafer and the upper surface of the substrate. 8. As described in claim 1 The back-to-back stacked multi-chip package structure, wherein the line is a LOC (Lead-0n_Chip, pin-on-wafer type) die-bonding tape. 9. The multi-chip package of the back-to-back stack as described in the scope of the patent application. Constructing 'where the overlying material is a liquid epoxy resin. 100. The multi-chip package structure of the back-to-back stack as described in the scope of claim j' further includes a plurality of LOC adhesive tapes to adhere to the first _ One of the wafers has an active surface to the substrate. 21 1353664 U. The multi-slice package structure of the back-to-back stack of claim 1, further comprising a plurality of external terminals that engage the lower surface of the substrate. 12. The multi-chip package structure of back-to-back stacking as described in claim n, wherein the external terminals comprise a plurality of solder balls. 13. A method of fabricating a multi-chip package structure stacked back-to-back, comprising the steps of: providing a substrate; and placing a first wafer on the substrate, the wafer has a plurality of wafers a first pad is formed to electrically connect the first pads of the first wafer to the substrate; and a first-side stack is disposed in a back-to-back stack. And the first wafer is on the first wafer, the second wafer has a plurality of second pads; forming a plurality of second bonding wires to electrically connect the second pads of the second wafer To the substrate, wherein the first pads and the second pads are both central pads, such that the second wires are prepared on the first wires; and at least one wire freezing member is formed. Attaching one of the second bonding wires to the active surface of the second wafer, wherein the wire freezing component comprises a wire pier and a wire covering material, wherein the wire pier is located Below the second bonding wires, for supporting the second bonding wires and defining local wire segments of the second bonding wires covered by the covering material; and forming a molding compound to seal the first wires a bonding wire, the second bonding wires, the first wafer, a second wafer, and the wire freezing member. 22 1353664. The method of manufacturing a back-to-back stacked polymorph structure as described in claim 13 wherein the first wafer and the second die are substantially identical in the wafer, and the first wafer is · " -, the two brothers of the two brothers completely overlap in the same center. 15. The method for manufacturing a multi-wafer and package structure of the back-to-back stack according to claim 13 wherein the line freezes the seal τ and the liquid-coated solidified gel adheres to the liquid coating method. B-day film and smashed. The manufacturing method of the multi-chip package structure of the back-to-back stack according to claim 13 , wherein the wire; the east junction component is a composite seal and adheres to the arrangement direction of the second pads The second wafer - the active surface. 17. The method of fabricating a back-to-back stacked multi-chip package structure according to claim 16, wherein the substrate has a wire hole for passage of the first wire bonding wire, and the wire freezing component is The second pads are not covered such that the line freezing elements form an upper mold flow channel between the strips. 18. The method of fabricating a back-to-back stacked multi-chip package structure as described in claim 13 further comprising the step of: providing a plurality of external terminals to engage a lower surface of the substrate. twenty three
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TWI382506B (en) * 2009-09-24 2013-01-11 Powertech Technology Inc Method and structure of multi-chip stack having central pads with upward active surfaces
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