TWI362727B - Window bga package and method for fabricating the same - Google Patents

Window bga package and method for fabricating the same Download PDF

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Publication number
TWI362727B
TWI362727B TW097120892A TW97120892A TWI362727B TW I362727 B TWI362727 B TW I362727B TW 097120892 A TW097120892 A TW 097120892A TW 97120892 A TW97120892 A TW 97120892A TW I362727 B TWI362727 B TW I362727B
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TW
Taiwan
Prior art keywords
wafer
die
substrate
grid array
ball grid
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Application number
TW097120892A
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Chinese (zh)
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TW200952132A (en
Inventor
Chin Ti Chen
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Powertech Technology Inc
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Priority to TW097120892A priority Critical patent/TWI362727B/en
Publication of TW200952132A publication Critical patent/TW200952132A/en
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Publication of TWI362727B publication Critical patent/TWI362727B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

Disclosed are a window BGA package and a method for fabricating the same. The package primarily comprises a substrate, a chip, a die-attach material, a plurality of bonding wires electrically connecting the chip with the substrate, an encapsulant encapsulating the chip, and a plurality of external terminals below the substrate. The substrate has a die-attach dent on which the die-attach material is formed and a slot for the bonding wires passing through. The chip is aligned with the die-attach dent and disposed on the substrate. In the step of adhesive diffusion, the die-attach dent limits the spread shape of the die-attach material so that the die-attach material is filled in the gap between the sides of the chip and the peripheries of the die-attach dent. Accordingly, the package has a reduced thickness and can avoid crack and delamination at chip sides.

Description

1.362.727 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種半導體裝置,特別係有關於一 種窗口型球栅陣列封裝構造及其製造方法。 [先前技術】1.362.727 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a window type ball grid array package structure and a method of fabricating the same. [Prior technology]

在小多半導體裝置之封裝類型中,窗口型球栅陣列 封裝構造(WBGA,Window Ball Grid Array)是將用以承 載晶片之基板開設有一貫通之槽孔,以便於銲線穿過槽 孔,以電性連接基板與在其上方之晶片,並將如銲球之 外接端子接合至基板之下方,以使窗口型球栅陣列封裝 構造可對外電性接合。一旦利用液態或膠稠態之黏晶材 料將晶片黏貼於基板上,而在黏晶的昇溫與施壓過程 中,黏晶材料將具有流動性而發生溢膠,又當黏晶材料 流佈覆蓋至晶片之銲墊則會導致無法打線。故目前窗口 型球柵陣列封裝構造只能使用黏晶膠帶(tape)代替液態 或膠稠態之黏晶材料,以避免產生溢膠,但成本較高。 而且,晶片被黏晶膠帶所黏接的區域僅為晶片主動面且 平面狀,容易受到應力影響而在晶片側面產生分層或是 碎裂之Μ題,致使傳 '统的f 口型球栅睁列封裝構造之^ 賴度及品質受到影響。 請參閱第i圖所示’一種習知窗口型球柵陣列封裝 構造1〇〇主要包含一基板110、一晶片12〇、一黏晶膠 帶⑴、複數個銲線14〇、—封膠體15Q以及複數個外 接端子160。該基板110具有一内表面iu、一外表面 5 1362727 112以及一貫穿該内表面111至該外表面112之槽孔 114。該晶片120係具有一主動面121以及複數個在該 主動面1 2 1上的銲墊1 24。該黏晶膠帶1 3 0係黏貼該晶 片120之該主動面121與該基板11〇之該内表面in,In a package type of a small multi-semiconductor device, a window ball grid array structure (WBGA) is a slot in which a substrate for carrying a wafer is opened to facilitate a wire pass through the slot. The substrate and the wafer above it are electrically connected, and a solder ball external terminal is bonded under the substrate to make the window type ball grid array package structure electrically connectable. Once the wafer is adhered to the substrate by using a liquid or gel-bonded viscous material, the viscous material will have fluidity and overflow during the temperature rise and pressure application of the viscous crystal, and the viscous material will be covered by the flow of the viscous material. Wafer pads on the wafer can cause wire to be broken. Therefore, the current window type ball grid array package structure can only use the adhesive tape (tape) instead of the liquid or colloidal bonded crystal material to avoid overflow, but the cost is high. Moreover, the area where the wafer is bonded by the adhesive tape is only the active surface of the wafer and is flat, which is susceptible to stress and causes delamination or chipping on the side of the wafer, resulting in a f-type ball grid. The dependence and quality of the package structure are affected. Please refer to FIG. 1 ''A conventional window type ball grid array package structure 1 〇〇 mainly includes a substrate 110, a wafer 12 〇, a die bonding tape (1), a plurality of bonding wires 14 〇, a sealing body 15Q, and A plurality of external terminals 160. The substrate 110 has an inner surface iu, an outer surface 5 1362727 112, and a slot 114 extending through the inner surface 111 to the outer surface 112. The wafer 120 has an active surface 121 and a plurality of pads 1 24 on the active surface 112. The adhesive tape 130 is adhered to the active surface 121 of the wafer 120 and the inner surface in of the substrate 11

以使該晶片120係設置於該基板110上。並在黏晶後顯 露於該槽孔114。該晶片120之該主動面121上係形成 有一鈍化層125。該些銲線140係通過該槽孔114並電 性連接該些銲墊124至該基板11〇。該封膠體15〇係密 封該晶片120與該些銲線140。該些外接端子ι6〇係設 置於該基板110之該外表面112。請參閱第2圖的放大 圖所示’該黏晶膠帶1 3 0僅局部黏貼該晶片1 2〇之該主 動面1 2 1上之純化層1 25(passivation layer),故在封勝 過程與熱循環試驗中產生之熱應力容易導致由該晶片 1 20的側面產生該鈍化層125的分層與剝離或是造成晶 片側面的碎裂問題。The wafer 120 is placed on the substrate 110. And exposed to the slot 114 after the adhesion. A passivation layer 125 is formed on the active surface 121 of the wafer 120. The bonding wires 140 pass through the slots 114 and electrically connect the pads 124 to the substrate 11A. The encapsulant 15 is used to seal the wafer 120 and the bonding wires 140. The external terminals ι6 are disposed on the outer surface 112 of the substrate 110. Referring to the enlarged view of FIG. 2, the adhesive layer 1300 is only partially adhered to the passivation layer of the active surface 1 2 1 of the wafer 1 2 ,, so the sealing process is The thermal stress generated in the thermal cycle test tends to cause delamination and peeling of the passivation layer 125 from the side of the wafer 120 or a problem of chipping on the sides of the wafer.

【發明内容】 有繁於此,本發明之主要目的係在於提供一種窗口 里求柵陣列封裝構造及其製造方法,能降低整個封裝的 厚度,並能有效解決傳統窗口型球柵陣列封裝構造在晶 ϋ面產生分層、剝離或是晶片側面的碎裂問題。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明所揭示之—種窗口型球柵陣列 封裝構造,主要包含一某 一篦一曰 匕a暴板 第日日片、一黏晶材料、 複數個第一銲線、一封膠體以及複數個外接端子。哕美 6 1362727 板係具有一内表面、一外表面、一形成在該内表面之黏 β曰凹陷以及一槽孔’該槽孔係貫穿該外表面至該黏晶凹 5亥第—晶片係對準於該黏晶凹陷而設置於該基板之 該内表面上’該第—晶片係具有一第一主動面、一第一 背面以及複數個在該第一主動面與該第一背面之間之 側面。該黏晶材料係形成於該黏晶凹陷内以黏接該第— 曰曰片之該第一主動面’該黏晶凹陷係限制該黏晶材料的 形狀’以使該黏晶材料填入該第一晶片之該些侧面與該 黏晶凹陷邊緣之間的縫隙,而局部覆蓋至該第一晶片之 6亥些側面。該些第一銲線係穿過該槽孔並電性連接該第 晶片至該基板。該封膠體係形成於該基板之該内表面 上並填滿該槽孔,以密封該第一晶片與該些第一銲線。 °亥些外接端子係設置於該基板之該外表面。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之窗口型球栅陣列封裝構造中,該第一晶片 '、口更具有一覆蓋於該第一主動面之鈍化層,該鈍化層 係元全嵌埋於該黏晶凹陷内,以使該鈍化層之周邊側緣 被該黏晶材料密封。 在則述之窗口型球柵陣列封裝構造中,該黏晶凹陷 的/罙度係可大於該黏晶材料與該鈍化層之厚度總合但 小於兮贫 ^弟一晶片之厚度,以使該第一晶片係局部嵌埋於 該黏晶凹陷内。 在前述之窗口型球栅陣列封裝構造中,該黏晶凹陷 7 1362727 之邊緣係可位於該第一晶 該些側面。 片之外但緊鄰該第 一晶片之 在前述之窗口型球柵陣列封 a ^ ^ 农傅&中,該黏晶材料 係可更擴散到該槽孔内。 在前述之窗口型球柵陣列 j打衮構造中,該黏晶材料 係可更密封該些第一銲線在該第—曰 竹 日日月之一端0 在前述之窗口型球柵陣列封裝構造中,該第一SUMMARY OF THE INVENTION In view of the above, the main object of the present invention is to provide a window array layout structure and a manufacturing method thereof, which can reduce the thickness of the entire package, and can effectively solve the traditional window type ball grid array package structure. The wafer surface creates delamination, peeling, or chipping on the sides of the wafer. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the invention, a window type ball grid array package structure mainly comprises a certain 曰匕 a 暴 a storm board first day film, a viscous material, a plurality of first bonding wires, a colloid and a plurality An external terminal.哕美6 1362727 The plate has an inner surface, an outer surface, a viscous β 曰 recess formed on the inner surface, and a slot through the outer surface to the viscous cavity Arranging on the inner surface of the substrate in alignment with the die recess, the first wafer has a first active surface, a first back surface, and a plurality of between the first active surface and the first back surface The side. The viscous material is formed in the viscous recess to adhere the first active surface of the first ridge sheet, and the viscous recess defines a shape of the viscous material to fill the viscous material a gap between the sides of the first wafer and the recessed edge of the die, and partially covering the sides of the first wafer. The first bonding wires pass through the slot and electrically connect the first wafer to the substrate. The encapsulation system is formed on the inner surface of the substrate and fills the slot to seal the first wafer and the first bonding wires. The external terminals are disposed on the outer surface of the substrate. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing window type ball grid array package structure, the first wafer ', the port further has a passivation layer covering the first active surface, and the passivation layer is completely embedded in the die recess, so that The peripheral side edge of the passivation layer is sealed by the die bonding material. In the window type ball grid array package structure described above, the thickness of the viscous recess may be greater than the thickness of the viscous material and the passivation layer but less than the thickness of the wafer. The first wafer is partially embedded in the die-forming recess. In the foregoing window type ball grid array package structure, the edge of the die recess 7 1362727 may be located on the first crystal side. Outside of the sheet but in close proximity to the first wafer, in the aforementioned window type ball grid array a ^ ^ 傅 傅 &, the viscous material can diffuse into the slot. In the foregoing window type ball grid array j snagging structure, the viscous material material can seal the first bonding wires at one end of the first 曰 日 日 日 日 日 in the aforementioned window type ball grid array package structure In the first

係可具有複數個形成於該第一 乐 王動面之第一銲墊,其传 對準於該槽孔内,以^ _ b ' 供。亥些第一銲線之接合。 在前述之窗口型球栅陣 日士 + ^ e j对裝構造中,該基板係可 具有一階梯狀缺口,盆 八係形成在該外表面與該槽孔之侧 邊0 在前述之窗口型球栅陣列封敦構造中該些外接端 子係可包含複數個銲球。 在前述之·窗口型球柵陣列封裝構造中,可另包含— 第二晶片,其係以背對背堆疊方式設置於該第一晶片之 第一背面上並具有複數個第二銲墊。 在刖述之® 口型球栅陣列封裝構造中,可另包含複 數個第二銲線,其係電性連接該些第二銲墊至該基板。 在前述的窗口型球柵陣列封裝構造中,該封膠體係 可覆蓋該第一晶片之該第—背面。 本發明還揭不前述的窗口型球柵陣列封裝構造之製 程,主要步驟包含:首先,提供一基板,該基板係具有 一内表面、一外表面、—形成在該内表面之黏晶凹陷以 8 1362727 槽孔,該槽孔係貫穿該外表面至該黏晶㈣,並於 凹陷内形成一黏晶材料。接著,設置一第 及 該黏晶 _ _ i 一弟一晶 片 板 ,該第-晶片係對準該黏晶凹陷I暫時性㈣於該基 之該内表面,其中該第-晶片係具有—第一主動面、 該第-主動面。在暫時性黏晶後,打線形成L:第 銲線,該些第一銲線係穿過該槽孔並電性連接該第 之 晶 片 至 該 基板。接 著 , 進行一黏晶擴散步驟,以 施 壓 於 該 第 —— 晶 片,該黏 晶 凹 陷係限制該黏晶材料的形 狀 ? 以 使 該 黏 晶 材料擴散並填入該第一晶片之該些側 面 與 該 黏 晶 陷 邊緣之間 的 縫 隙’而局部覆蓋至該第一 晶 片 之 該 些 側 面 。之後, 形 成 一封膠體於該基板之該内 表 面 上 M- 填 滿 該 槽孔,以 密 封 該些第一晶片與該些第一 銲 線 0 最 後 > 設 置複數個 外 接 端子於該基板之該外表面 0 一弟一月叫μ久複致個在該第—主動面與該第一背面 之間之側面,其中該黏晶材料係暫時性黏 a …蝴UI尘琢珊陣 列封裝構造及其製造方法,冑以下優點與功效: 一、 利用基板内表面形成有黏晶凹陷且—曰 ^ ^ Λ 布 日日片係局部 嵌埋於該黏晶凹陷,以降低整個封裝的厚度。 二、 藉由黏晶材料填滿該晶凹陷與該第—晶片又^門 隙缝,並局部覆蓋至該第一晶片之側面,提供; 面的黏晶區域,以增強黏晶強度。 三、 藉由該黏晶材料密封該第一晶 片之鈍化層的周邊側 緣,以減輕該第一晶片受到的 j的應力,以避免晶片鈍 9 1362727 化層的分層剝離,並能避免該第一晶片之側面 碎裂。 四、 藉由該黏晶材料密封第一銲線在該第一晶片 端’以防止該些第一銲線因封膠過程中受模流 造成沖線或斷線之問題。 五、 利用該基板之階梯狀缺口低於該基板之外表面 供較低的打線區域’能使用線徑較小的銲線作 接合’以降低銲線外露的風險。 【實施方式】 依據本發明之第一具體實施例,一種窗口型球 列封裝構造舉例說明於第2圖之截面示意圖。 請參閱第2圖所示’該窗口型球柵陣列封裝構违 主要包含一基板21 〇、一第一晶片220、一黏晶 230、複數個第一銲線240、一封膠體250以及複 外接端子260。該基板210係具有一内表面211、 表面212、一形成在該内表面211之黏晶凹陷213 一槽孔214’該槽孔214係貫穿該外表面212至該 凹陷213。該内表面211係為該基板21〇不外露於 膠體250之一表面,以供設置該第一晶片22〇 ;該 面212係為外露於該封膠體250之一表面,以供設 些外接端子260»該槽孔214係可為中央槽孔,用 露該第一晶片220之複數個第一銲墊224,並供該 一銲線240之通過。在本實施例中,該基板2 1 0係 有一階梯狀缺口 2 1 5,其係形成在該外表面2 1 2與 產生 之一 影響 以提 打線 柵陣 200 材料 數個 一外 以及 黏晶 該封 外表 置該 以顯 些第 可具 該槽 10 1362727 孔2 14之側邊,用以降低該些第一銲線240之 體而言,如第2圖所示,該基板210更具有複 於該外表面212之外接墊 217以及複數個 216。更具體而言,該些第一接指216係形成 狀缺口 215並可排列於該階梯狀缺口 215,以 一銲線240電性連接。該些外接墊2 1 7 —般係 球墊’該些外接墊2 1 7係可為矩陣排列或多 列’以供接合該些外接端子260。該基板210 一防焊層218,其係形成於該外表面212但顯 接墊2 1 7。在本實施例中,該防焊層2 1 8更顯 一接指216以形成該階梯狀缺口 215。通常該 係為一種線路基板,例如印刷電路板或陶瓷基 請參閱第2圖所示,該第一晶片220係對 晶凹陷213而設置於該基板210之該内表面2 第一晶片220係具有一第一主動面22卜一第一 以及複數個在該第一主動面22 1與該第一背面 之側面2 2 3。具體而言,該第一晶片2 2 〇之尺 小於該黏晶凹陷2 1 3,該第一晶片2 2 0係以該 面221朝向該基板210之方式局部容置於該 2 1 3内。該黏晶凹陷2 1 3之邊緣2丨3 a係可位 晶片220之外但緊鄰該第一晶片220之該些侧 故一縫隙S係形成在該些側面223與該黏晶凹 邊緣2 1 3 A之間。該第一晶片2 2 〇形成於該第 221之該些第一銲墊224係對準於該槽孔214 π 弧南。具 數個形成 第一接指 於該階梯 供該些第 為圓形接 排周邊排 可另具有 露該些外 露該些第 基板210 .板。 準於該黏 1 1上,該 背面222 222之間 寸係可略 第一主動 黏晶凹陷 於該第一 丨面223, 陷213之 一主動面 内,以供 1362727 該些第一銲線240之接合。在本實施例中,該 墊224係位於該第一主動面221之中央區域, 一銲墊224為中央銲墊。該些第—銲墊224係 晶片220内部積體電路之對外電極,該些第一 之材質係可為铭、銅或銘合金。在本實施例吟 圖之放大圖所示,該第一晶片220係可更具有 該第一主動面221之鈍化層225,其中該鈍化 顯露該些第一銲墊224 ^該鈍化層225係可選 胺(PI, Poly imide)、笨基環丁, Benzocyclobutene)與石夕化物之其中之一,其中 可包括氧化矽或氮化矽。 請再參閱第2圖所示,該黏晶材料2 3 〇係 黏晶凹陷2 1 3内以黏接該第一晶片22〇之該第 221,該黏晶凹陷213係限制該黏晶材料23〇 以使該黏晶材料230填入該第一晶片220之 223與該黏晶凹陷213之邊緣213a之間的縫 局P覆蓋至该第一晶片220之該些側面223, 黏晶材料23 〇之黏貼面積並使黏晶區域為非 截•面),故能加強該第一晶片220與該基板 著力。較佳地,該黏晶凹陷2 1 3的深度D係可 :材料23 〇與該鈍化層225之厚度了總合但小 晶j 220之厚度,以使該第一晶片22〇係局部 黏θ曰凹陷2 1 3内,故能降低整個封裝的厚度。 該黏晶材料230之厚度是指該黏晶材料23〇由 些第一銲 即該些第 為該第一 •銲墊224 7 ,如第2 一覆蓋於 層22 5係 自聚亞醯 缔(BCB, 該矽化物 形成於該 一主動面 的形狀, 該些側面 隙S,而 以增加該 产面(如u 2 1 0之黏 大於該黏 於該第一 嵌埋於該 在此所指 該保護層 12 L362727 225至該黏晶凹陷213之底面的最短距離。較佳地,該 第一晶片220之該鈍化層225係完全嵌埋於該黏晶凹陷 2 1 3内,以使該鈍化層225之周邊側緣被該黏晶材料23 〇 密封,以避免該鈍化層225由該第一晶片22〇產生分層 或剝離。該黏晶材料 230係可為 B階黏膠(B_stage adhesive),具有多階段固化特性,以調整在該第—曰曰片 220之該些側面223之覆蓋效果。 請再參閱第2圖所示,該些第一銲線240係穿過該 槽孔214並電性連接該第一晶片220之該些第一鲜塾 2 24至該基板2 1 〇之該些第一接指2 1 6,達到該第—晶 片2 2 0與該基板2 1 0之間之電性互連。該些第—辉線 240係可為打線形成,該些第一銲線240之材質係可為 金或銅等導電材料。由於該些第一接指2丨6係位於該階 梯狀缺口 215,使得該基板210與該第一晶片22〇具有 較短的打線高度差,降低該些第一銲線240之弧高,故 能採用較細的銲線實現打線接合。請再參閱第2圖所 示,該黏晶材料230係可更擴散到該槽孔214内。較佳 地,該黏晶材料230經黏晶擴散而可更密封該些第一銲 線240在該第—晶片22〇之一端,以防止沖線與銲線斷 路。 凊參閱第2圖所示,該封膠體25〇係形成於該基板 2 1〇之該内表面211上並填滿該槽孔214,以密封該第 一晶片220與該些第一銲線24〇。在本實施例中,該封 膠體2 5 0係可覆蓋該第一晶片2 2 〇之該第一背面2 2 2。 13 1362727 在不同實施例中,該封豚 膠體250係可顯露該第一晶片 220之該第一背面222,以描 u Λ Μ増加散熱效果。(圖中未繪出) 請再參閲第2圖所矛 # 下’該些外接端子260係設置於 該基板210之s玄外表 212之該些外接墊217,以供作 為該窗口型球栅陣列封爭 · ^ . 裝構造200之輸入端及/或輸出 端’以便與外界裝置(如冰p 1外。卩印刷電路板)形成電性連接 關係。該些外接端子26η及 ^ „ 00係可包含複數個銲球、金屬 球、錫膏、接觸墊或接觸針。The system may have a plurality of first pads formed on the first movement surface, which are aligned in the slots and provided by ^ _ b '. The joint of the first welding wire. In the aforementioned window type ball grid array, the substrate system may have a stepped notch, and the basin is formed on the outer surface and the side of the slot 0 in the aforementioned window type ball. The external terminals in the gate array seal structure may include a plurality of solder balls. In the foregoing window type ball grid array package structure, a second wafer may be further disposed on the first back surface of the first wafer and provided with a plurality of second pads in a back-to-back stacking manner. In the description of the articulated ball grid array package structure, a plurality of second bonding wires may be further included, which electrically connect the second pads to the substrate. In the aforementioned window type ball grid array package configuration, the encapsulation system can cover the first back side of the first wafer. The present invention also discloses the process of the window type ball grid array package structure. The main steps include: firstly, providing a substrate having an inner surface, an outer surface, and a die-forming recess formed on the inner surface 8 1362727 a slot extending through the outer surface to the die (4) and forming a die-forming material in the recess. Next, a first and a die plate are disposed, the first wafer is aligned with the die recess I temporarily (four) on the inner surface of the substrate, wherein the first wafer has a An active surface, the first active surface. After the temporary adhesion, the wires are formed into L: the first bonding wires, and the first bonding wires are passed through the slots and electrically connected to the first wafer to the substrate. Next, performing a die-diffusion step to apply pressure to the first wafer, the die-forming recess restricting the shape of the die-bonding material, so that the die-bonding material diffuses and fills the sides of the first wafer And a gap between the edge of the sticky edge and partially covering the sides of the first wafer. Thereafter, a colloid is formed on the inner surface of the substrate to fill the slot to seal the first wafer and the first bonding wires. Finally, a plurality of external terminals are disposed on the substrate. The outer surface 0, a younger brother, is called a long time in the side between the first active surface and the first back surface, wherein the viscous material is temporarily viscous a... The manufacturing method, the following advantages and effects: First, the use of the inner surface of the substrate to form a sticky crystal depression and - 曰 ^ ^ Λ 日 日 日 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部2. Filling the recesses with the first wafer by the die-bonding material and partially covering the side of the first wafer to provide a surface of the die to enhance the bond strength. 3. Sealing the peripheral side edge of the passivation layer of the first wafer by the die bonding material to reduce the stress of the first wafer, so as to avoid delamination of the wafer blunt 9 1362727 layer, and avoiding the The side of the first wafer is broken. 4. Sealing the first bonding wire at the first wafer end by the die bonding material to prevent the first bonding wires from being damaged or broken due to the mold flow during the sealing process. 5. The stepped notch of the substrate is lower than the outer surface of the substrate for the lower wire-bonding area 'the wire can be joined using a smaller wire diameter' to reduce the risk of wire exposure. [Embodiment] According to a first embodiment of the present invention, a window type ball-column package structure is illustrated in a cross-sectional view of Fig. 2. Referring to FIG. 2, the window type ball grid array package structure mainly comprises a substrate 21 〇, a first wafer 220, a die bond 230, a plurality of first bond wires 240, a gel body 250, and a complex external connection. Terminal 260. The substrate 210 has an inner surface 211, a surface 212, and a slotted hole 214' formed in the inner surface 211. The slot 214 extends through the outer surface 212 to the recess 213. The inner surface 211 is such that the substrate 21 is not exposed on one surface of the colloid 250 for providing the first wafer 22; the surface 212 is exposed on one surface of the encapsulant 250 for providing external terminals. The slot 214 can be a central slot, and a plurality of first pads 224 of the first wafer 220 are exposed and passed through the wire 240. In this embodiment, the substrate 210 is provided with a stepped notch 2 15 , which is formed on the outer surface 2 1 2 and generates an influence on the wire grid array 200 material and a plurality of layers. The outer surface of the sealing plate is disposed to show the side of the hole 2 14 of the groove 10 1362727 for reducing the body of the first bonding wire 240. As shown in FIG. 2, the substrate 210 is further provided. The outer surface 212 is externally connected to the pad 217 and a plurality of 216. More specifically, the first fingers 216 are formed into a notch 215 and can be arranged in the stepped notch 215 to be electrically connected by a bonding wire 240. The external pads 2 17 are generally ball pads. The external pads 2 17 can be arranged in a matrix or in multiple columns to engage the external terminals 260. The substrate 210 is a solder mask 218 formed on the outer surface 212 but having a pad 2 17 . In the present embodiment, the solder resist layer 2 18 is further provided with a finger 216 to form the stepped notch 215. Generally, the system is a circuit substrate, such as a printed circuit board or a ceramic base. As shown in FIG. 2, the first wafer 220 is provided on the inner surface 2 of the substrate 210 by the recess 213. The first wafer 220 has A first active surface 22 is first and a plurality of first active surface 22 1 and a side surface 2 2 3 of the first back surface. Specifically, the first wafer 2 2 is smaller than the die recess 2 1 3 , and the first wafer 220 is partially accommodated in the 2 1 3 with the surface 221 facing the substrate 210. The edge 2 丨 3 a of the viscous recess 2 1 3 is outside the alignable wafer 220 but adjacent to the sides of the first wafer 220. A slit S is formed on the side surface 223 and the viscous concave edge 2 1 Between 3 A. The first pads 224 formed on the first die 221 are aligned with the slots 214 π arc south. The plurality of first substrates are formed on the steps for the first circular rows of peripheral rows to additionally expose the first substrate 210. Between the back surface 222 222, the first active adhesive crystal is recessed in the active surface of one of the first surface 223 and the recess 213 for the first bonding wire 240 of 1362727. Engagement. In this embodiment, the pad 224 is located in a central region of the first active surface 221, and a pad 224 is a center pad. The first pads 224 are external electrodes of the integrated circuit inside the wafer 220, and the first materials may be Ming, copper or alloy. In the enlarged view of the embodiment, the first wafer 220 may further have a passivation layer 225 of the first active surface 221, wherein the passivation reveals the first pads 224. The passivation layer 225 is One of amine (PI, Poly imide), Benzocyclobutene, and lithium, which may include cerium oxide or cerium nitride. Referring to FIG. 2 again, the viscous material 2 3 is in the viscous recess 2 1 3 to adhere the 221 of the first wafer 22, and the viscous recess 213 restricts the viscous material 23 So that the die bonding material 230 fills the seam P between the 223 of the first wafer 220 and the edge 213a of the die recess 213 to cover the side faces 223 of the first wafer 220, and the die bonding material 23 The adhesion area is made and the die-bonded area is non-cutting, so that the first wafer 220 and the substrate can be strengthened. Preferably, the depth D of the die recess 2 1 3 is such that the material 23 总 is combined with the thickness of the passivation layer 225 but the thickness of the small crystal j 220 is such that the first wafer 22 is locally adhered to the θ. The depression is within 2 1 3, so the thickness of the entire package can be reduced. The thickness of the die-bonding material 230 means that the die-bonding material 23 is made of a first welding wire, that is, the first electrode pad 224 7 , such as the second layer covering the layer 22 5 from the poly-Asian BCB, the telluride is formed in the shape of the active surface, the side gaps S, to increase the mating surface (eg, the adhesion of u 2 1 0 is greater than the adhesion of the first embedded in the Preferably, the passivation layer 225 of the first wafer 220 is completely embedded in the die recess 21 1 3 to make the passivation layer. The peripheral side edge of 225 is sealed by the die bonding material 23 to prevent the passivation layer 225 from being layered or peeled off from the first wafer 22. The die bonding material 230 may be a B-stage adhesive. A multi-stage curing characteristic is provided to adjust the covering effect on the side faces 223 of the first cymbal sheet 220. Referring to FIG. 2 again, the first bonding wires 240 pass through the slot 214 and are electrically charged. The first squeezing 2 24 of the first wafer 220 is connected to the first fingers 2 1 6 of the substrate 2 1 An electrical interconnection between the first wafer 220 and the substrate 210. The first filaments 240 may be formed by wire bonding, and the first bonding wires 240 may be made of gold or copper. Since the first fingers 2丨6 are located in the stepped notch 215, the substrate 210 and the first wafer 22〇 have a shorter wire height difference, and the arc height of the first bonding wires 240 is lowered. Therefore, the wire bonding can be achieved by using a thin wire bonding wire. Please refer to FIG. 2 again, the die bonding material 230 can be more diffused into the slot 214. Preferably, the die bonding material 230 is bonded. Diffusion can further seal the first bonding wires 240 at one end of the first wafer 22 to prevent the wire and the wire from being broken. Referring to FIG. 2, the sealing body 25 is formed on the substrate 2 The inner surface 211 of the first surface 211 is filled with the slot 214 to seal the first wafer 220 and the first bonding wires 24 〇. In this embodiment, the sealing body 250 can cover the first surface. a first back surface of the wafer 2 2 2 2 2 13 13362727 In various embodiments, the stylus colloid 250 can reveal the first wafer 220 A back surface 222 is used to describe the heat dissipation effect (not shown). Please refer to FIG. 2 for the spear #下下. The external terminals 260 are disposed on the substrate 212 of the substrate 210. The external pads 217 are used as the window type ball grid array to encapsulate the input and/or output ' of the structure 200 to form electrical properties with external devices (eg, ice p1, 卩 printed circuit boards). The external terminals 26n and 00 00 may comprise a plurality of solder balls, metal balls, solder pastes, contact pads or contact pins.

因此#由該點晶凹㉜2 i 3之設計有效控制該黏晶 材料230之黏晶擴散,以局部覆蓋至該第一晶片22〇之 該些侧Φ 223 ’有效增加黏晶面積與改變為非平面黏晶 區域,故能減少整個封裝的厚度並增強黏晶強度,以避 免該鈍化層225由該第一晶片22〇產生分層剝離,並能 避免該第一晶片220之該些側面223產生碎裂損傷。此 外,藉由該黏晶凹陷2 1 3控制該黏晶材料2 3 0不致擴散 到該基板21 0之邊緣’以使該封膠體25〇能完全密封該 黏晶材料23 0,確保良好的水氣抵抗能力。尤佳地該 黏晶材料23 0可更密封該些第一銲線240在該第一晶片 220之一端,以防止該些第一銲線24〇因封膠過程中受 模流影響造成沖線或斷線之問題。 本發明進一步說明前述窗口型球柵陣列封裴構造之 製造方法例舉說明於第3圖之製造流程方塊圖與第4八 至4E圖之製程中元件截面示意圖。 請參閱第第3圖所示,該窗口型球柵陣列封 1 I構造 1362727 之製程主要包含以下步驟:「提供基板」之步驟1、「暫 時性黏晶」步驟2、「電性連接」步驟3、「黏晶擴散」 步驟4、「形成封膠體」之步驟5以及「設置外接端子」 步驟6’並配合第4A至4E圖說明如后。 •首先,執行步驟丨。如第4A圖所示,提供該基板210, 該基板210之該内表面211已形成有該黏晶凹陷213以 及該槽孔2 1 4,該槽孔2 1 4係貫穿該外表面2丨2至該黏 晶凹陷2 1 3,並在該黏晶凹陷2丨3内形成該黏晶材料 230。其中,該黏晶凹陷213之底面可不設有線路層, 以利機械式形成該黏晶凹陷2 1 3時不會破壞該基板2 1 〇 之内部線路結構。較佳地,該黏晶材料2 3 〇係可為多階 k固化的膠稠態膠體,在形成於該基板2丨〇時,該黏晶 材料230係具有較佳流動性,故能以網版印刷(screen printing)或鋼版印刷(stencil printing)之方式形成於該 黏晶凹陷213。該黏晶材料23〇係不填滿該黏晶凹陷 2 1 3,以顯露該槽孔2丨4。該黏晶材料23 〇係可與該基 板210之該内表面211為共平面或略高於該内表面 21卜該基板210之該些第一接指216與該些外接墊217 係為同一線路層。該基板21〇可另具有一防焊層218, 其係形成於該外表面212。該防焊層218更顯露該些外 接塾217’該防焊層218係可更構成一階梯狀缺口 215 以顯露該些第一接指2 1 6。 接著’執行步驟2。如第4B圖所示,利用該黏晶材 料230之黏著使該第一晶片22〇對準該黏晶凹陷213並 15 、性黏貼於該基板2 1 0之該内表面2丨丨。該第一晶片 係些微嵌陷於該黏晶凹陷2 1 3内,並使該黏晶材料 23〇 了 . 過度變形與不改變溢谬範圍。其中該黏晶材料 2 係暫時性黏者該第一晶片220之該第一主動面 1該第一晶片220之第一銲墊224係對準於該槽孔 曰内。具體而言,步驟2需預烤該基板21〇,使該黏 曰材料23 0在室溫達到半固化狀態並具有熱結合之黏 十生 > ' 以供黏著該第一晶片22〇。此時,利用黏晶溫度調 整該黏晶材料230在較低的流動性,故具有不易塌散的 卜形進而避免該黏晶材料230流佈覆蓋至該些第一銲 墊224而造成無法打線之問題。接著,執行步驟3。如 第4 C圖所示,打線形成該些第一銲線2 4 〇通過該槽孔 2 14,以電性連接該第一晶片22〇之該些第一銲墊224 至該基板210之該些第—接指216。 接著,執行步驟4。如第4D圖所示,利用加溫與加 壓方式施加於該第一晶片22〇,以使該黏晶材料23〇擴 散,並使該第一晶片220更嵌陷於該黏晶凹陷213内。 此步驟中的加熱溫度與壓力係應高於「暫時性黏晶」步 驟2中之知作條件。各 曰μ …^ 片220往該黏晶凹陷 21 ^於溫度提高會使該點晶材料230且有較 佳流Γ,然而該黏晶凹陷213係限制該黏晶材料-的形狀,以使該黏晶材料 22。之該些側面223 ”V 並填八該第-晶片 Μ如第2圖妬 。〜黏日日凹陷213邊緣之間的縫隙 S(如第2圖所示),更 I復显芏0亥第一晶片22〇之該 16 1362727 些側面223 °由於該黏晶材料230係在形成該些第一銲 線240後才會產生擴張變形,故即使該黏晶材料230產 〜第一銲線240仍不會造成無法打線之問 題,甚至有助於該些第一銲線240的固定。例如在步驟 孩黏晶材料230 #可更擴散到該槽孔2 1 4 内°亥黏BB特料230係可包覆該些第一銲線240之一 端’*該黏日m材料23〇固化之後便能固定封住該些第一 桿線2 4 〇之—端’以避免在後續封膠過程中產生沖線。 在本實施例中’該黏晶材料23 0之固化係可執行於黏晶, 擴散步驟4同時進行或在黏晶擴散步驟4之後,或在步 驟5中元成此外,請參閱第2及3圖所示,更具體地, 在黏晶擴散步驟4中’該第一晶片220之該鈍化層225 係完全嵌埋於該黏晶凹陷2丨3内,以使該鈍化層225之 周邊側緣被該黏晶材料23〇密封。 之後’執行步驟5。如第4E圖所示,以轉移模封 (transfer molding)技術形成該封膠體25〇,該封膠體250 形成在該基板2 1 0之該内表面2丨丨上並填滿該槽孔 214,以密封該第一晶片22〇與該些第一銲線24〇。由 於该黏晶凹陷2 1 3能限制該黏膠材料2 3 〇之形狀,不致 往s亥基板210之周邊擴散,故該封膠體25〇可完全密封 該黏晶材料23 0。最後’執行步驟6,可利用回焊技術 使該些外接端子260設置於該些外接墊217,以製成如 第2圖所示之窗口型球柵陣列封裝構造2〇〇。在不同實 施例中,該窗口型球柵陣列封裝構造2 〇 〇之製造方法可 17 1*362727 另包含一第二晶片(圖中未繪出)之設置步驟,以背 堆疊方式將該第二晶片設置於該第一晶片22〇之 背面222上。 依據本發明之第二具體實施例,另一種窗口型 陣列封裝構造舉例說明於第5圖之截面示意圖,其 架構係與第一具體實施例相同,但可堆疊更 ’ 日日门 請參閱第5圖所示’該窗口型球栅陣列封裝構造 主要包含一基板310、一第一晶片320、_黏晶 3 3〇、複數個第一銲線341、一封膠體35〇以及複 外接端子360。該基板310係具有一内表面311、 表面312、一形成在該内表面311之黏晶凹陷313 —槽孔3 1 4,該槽孔3 1 4係貫穿該外表面3丨2至該 凹陷313。該基板310係可具有一階梯狀缺口 315 係形成在該外表面3 1 2與該槽孔3 1 4之側邊。在本 例中’該外表面3 1 2位於該階梯狀缺口 3 1 5之兩側 形成有複數個第一接指316,該内表面311在該黏 陷3 1 3之外係可形成有複數個第二接指3丨9。而該 3 1 0係可為多層印刷電路板,以使該些第一接指31 該些第二接指319電性連接至該外表面312之複數 接墊3 1 7。該第一晶片3 2 0係對準於該黏晶凹陷3 1 設置於該基板310之該内表面311上,該第一晶片 係具有一第一主動面321、一第一背面322以及複 在β亥第一主動面321與該第一背面322之間之 323。s青參閱第5圖所不’該黏晶材料330係形成 對背 第一 球柵 基本 〇 300 材料 數個 一外 以及 黏晶 ,其 實施 係可 晶凹 基板 6與 個外 3而 320 數個 側面 於該 18 1362727 黏晶凹陷3 1 3内以黏接該第一晶片320之該第一主動面 3 2 1,該黏晶凹陷3 1 3係限制該黏晶材料3 3 0的形狀, 以使該黏晶材料33 0填入該第一晶片320之該些側面 3 2 3與該黏晶凹陷3 1 3之邊緣3 1 3 A之間的縫隙,而局 部覆蓋至該第一晶片320之該些侧面323,故該第一晶 片3 20係局部嵌埋於該黏晶凹陷3 1 3内,以降低整個封 裝的厚度。 請參閱第5圖所示,該第一晶片320係可具有複數 個形成於該第一主動面321之第一銲墊324,其係對準 於該槽孔3 1 4内。該些第一銲線3 4 1係穿過該槽孔3 1 4 並電性連接該第一晶片320之該些第一銲墊324至該基 板310之該些第一接指316。在本實施例中,該窗口型 球柵陣列封裝構造300可另包含一第二晶片370,其係 具有一第二主動面371以及一相對之第二背面372,該 第二晶片3 70係以背對背堆疊方式設置於該第一晶片 320之第一背面322上,即該第二晶片370之該第二背 面3 72係貼設於該第一晶片320之該第一背面322,而 使該第二主動面371係為朝上。該第二晶片370更具有 複數個第二銲墊374,其係形成於該第二主動面371。 在本實施例中,該第二晶片3 70與該第一晶片3 20係可 為實質相同之晶片,例如晶片尺寸、電性功能與銲墊配 置位置皆相同,故該些第二銲墊374亦為中央銲墊,藉 以能減少晶片種類以降低晶片之製造成本與管理成 本。藉由複數個第二銲線342電性連接該些第二銲墊 19 1362727 374至該基板310之該些第二接指319,達到該第二晶 片370與該基板310之電性互連。該封膠體35〇係形成 於該基板310之該内表面311上並填滿該槽孔314,以 密封該第一晶片320、該第二晶片370、該些第一銲線 341與該些第二銲線342。該些外接端子36〇係設置於 該基板3 1 0之該外表面3 1 2之該些外接墊3 1 7,以供對 外接合。Therefore, the design of the dot recess 322 i 3 effectively controls the diffusion of the die crystal of the die bond material 230 to partially cover the sides Φ 223 of the first wafer 22 to effectively increase the die area and change to a non- The planar die-bonding region can reduce the thickness of the entire package and enhance the bond strength, so as to prevent the passivation layer 225 from being delaminated from the first wafer 22, and avoiding the side faces 223 of the first wafer 220. Fragmentation damage. In addition, the die-bonding material 2 3 3 is controlled to not diffuse to the edge of the substrate 21 0 by the die-forming recess 2 1 3 so that the sealant 25 can completely seal the die-bonding material 23 0, ensuring good water. Gas resistance. More preferably, the die bonding material 230 can seal the first bonding wires 240 at one end of the first wafer 220 to prevent the first bonding wires 24 from being damaged by the mold flow during the sealing process. Or the problem of disconnection. The present invention further illustrates a manufacturing method of the window type ball grid array sealing structure as exemplified in the manufacturing flow block diagram of Fig. 3 and the cross-sectional view of the components in the processes of Figs. 4-8E. Referring to FIG. 3, the process of the window type ball grid array 1 1 structure 1362727 mainly includes the following steps: Step 1 of "providing the substrate", "Step 2", "Electrical connection" step 3. "Crystal Diffusion" Step 4, "Forming the Encapsulant" Step 5 and "Setting the External Terminal" Step 6' and the following description with reference to Figures 4A to 4E. • First, perform the steps丨. As shown in FIG. 4A, the substrate 210 is provided. The inner surface 211 of the substrate 210 has been formed with the die-shaped recess 213 and the slot 2 1 4 , and the slot 2 1 4 extends through the outer surface 2 丨 2 The viscous material 230 is formed in the viscous recess 2 2 3 and in the viscous recess 2 丨 3 . Wherein, the bottom surface of the viscous recess 213 may not be provided with a circuit layer, so that the internal structure of the substrate 2 1 不会 is not damaged when the viscous recess 2 1 3 is mechanically formed. Preferably, the viscous material 2 3 lanthanide can be a multi-stage k-cured colloidal colloid. When formed on the substrate 2, the viscous material 230 has better fluidity, so A mode of screen printing or stencil printing is formed in the die-forming recess 213. The die-bonding material 23 does not fill the die-forming recess 2 1 3 to reveal the slot 2丨4. The die bond material 23 can be coplanar or slightly higher than the inner surface 211 of the substrate 210. The first fingers 216 of the substrate 210 and the external pads 217 are in the same line. Floor. The substrate 21A may further have a solder resist layer 218 formed on the outer surface 212. The solder resist layer 218 further exposes the outer turns 217'. The solder resist layer 218 can further form a stepped notch 215 to expose the first fingers 2 16 . Then go to step 2. As shown in FIG. 4B, the first wafer 22 is aligned with the die recess 213 by the adhesion of the die bonding material 230, and is adhered to the inner surface 2 of the substrate 210. The first wafer is slightly embedded in the viscous recess 2 1 3 and causes the viscous material 23 to collapse. Excessive deformation does not change the overflow range. The first bonding pad 224 of the first wafer 220 is temporarily aligned with the first bonding surface of the first wafer 220. The first bonding pad 224 of the first wafer 220 is aligned in the slot. Specifically, in step 2, the substrate 21 is pre-baked so that the adhesive material 30 0 is semi-cured at room temperature and has a heat-bonding adhesion > ' for adhering the first wafer 22 〇. At this time, the viscosity of the die-bonding material 230 is adjusted to be low in fluidity, so that the die-shaped material is not easily collapsed, and the flow of the die-bonding material 230 is prevented from covering the first pads 224, thereby failing to wire. problem. Then, go to step 3. As shown in FIG. 4C, the first bonding wires 24 are formed by the wires, and the first pads 224 of the first wafer 22 are electrically connected to the substrate 210. These are the first fingers 216. Then, step 4 is performed. As shown in Fig. 4D, the first wafer 22 is applied by heating and pressing to diffuse the die bonding material 23, and the first wafer 220 is more embedded in the die recess 213. The heating temperature and pressure system in this step should be higher than the known conditions in the "temporary viscous crystal" step 2. Each of the 曰 ... ^ 220 220 220 220 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The die bond material 22. The side faces 223"V and fills the first wafer-like wafer as shown in Fig. 2. The gap S between the edges of the sticky sunday recess 213 (as shown in Fig. 2) is more complex. A wafer 22 of the 16 1362727 side faces 223 ° is not deformed due to the formation of the first bonding wires 240 because the die bonding material 230 is formed, so even if the die bonding material 230 is produced to the first bonding wire 240 It will not cause the problem of inability to wire, and even help to fix the first wire 240. For example, in the step, the child bonding material 230 # can be more diffused into the slot 2 1 4 The one end of the first bonding wire 240 can be coated with the end of the first bonding wire 240. After the curing, the material can be fixed and sealed to the end of the first wire 2 to avoid the subsequent sealing process. In the present embodiment, the curing of the die bonding material 230 can be performed on the die bond, the diffusion step 4 is performed simultaneously or after the die diffusion step 4, or in the step 5, in addition, please refer to 2 and 3, more specifically, in the die diffusion step 4, the passivation layer 225 of the first wafer 220 is completely embedded in the paste. The recess is 2丨3 so that the peripheral side edge of the passivation layer 225 is sealed by the die bonding material 23. Then 'Step 5 is performed. As shown in FIG. 4E, the seal is formed by transfer molding technique. The colloid 250 is formed on the inner surface 2 of the substrate 210 and fills the slot 214 to seal the first wafer 22 and the first bonding wires 24 . The viscous recess 2 1 3 can limit the shape of the adhesive material 2 3 ,, and does not spread to the periphery of the s-substrate 210, so the sealant 25 〇 can completely seal the viscous material 23 0. Finally, step 6 is performed. The external terminals 260 can be disposed on the external pads 217 by reflow soldering to form a window type ball grid array package structure 2 as shown in Fig. 2. In various embodiments, the window type The manufacturing method of the ball grid array package structure 可 17 1*362727 further includes a setting step of a second wafer (not shown), and the second wafer is disposed on the first wafer 22 in a back stacking manner. On the back side 222. According to the second embodiment of the present invention, another window type The column package structure is illustrated in the cross-sectional view of FIG. 5, and its architecture is the same as that of the first embodiment, but can be stacked more. Please refer to FIG. 5 for the day-to-day gate. The window type ball grid array package structure mainly includes a substrate 310, a first wafer 320, a die bond 3 3 , a plurality of first bond wires 341, a gel 35 〇 and a complex external terminal 360. The substrate 310 has an inner surface 311, a surface 312, and a A die-forming recess 313 is formed in the inner surface 311 - a slot 3 1 4 , and the slot 3 14 extends through the outer surface 3 丨 2 to the recess 313 . The substrate 310 may have a stepped notch 315 formed on the side of the outer surface 31 and the slot 3 1 4 . In this example, the outer surface 3 1 2 is formed on the two sides of the stepped notch 3 1 5 with a plurality of first fingers 316, and the inner surface 311 can be formed with a plurality of the outer surface of the adhesive layer 3 1 3 The second finger is 3丨9. The 301 may be a multi-layer printed circuit board, such that the second fingers 319 of the first fingers 31 are electrically connected to the plurality of pads 317 of the outer surface 312. The first wafer 306 is disposed on the inner surface 311 of the substrate 310. The first wafer has a first active surface 321 , a first back surface 322 , and a reticle 323 between the first active surface 321 and the first back surface 322. s Qing refers to Figure 5, which does not. The viscous material 330 forms a plurality of outer and first slabs of the first spheroidal material, and a plurality of viscous crystals. The implementation of the opaque substrate 6 and the outer 3 and 320 The first active surface 3 1 1 of the first wafer 320 is adhered to the surface of the 18 1362727 viscous recess 3 1 3 , and the viscous recess 3 3 3 limits the shape of the viscous material 330 The viscous material 33 0 is filled into the gap between the side faces 3 2 3 of the first wafer 320 and the edge 3 1 3 A of the die recess 3 1 3 to partially cover the first die 320 The side surfaces 323 are partially embedded in the die recesses 31 to reduce the thickness of the entire package. Referring to FIG. 5, the first wafer 320 can have a plurality of first pads 324 formed on the first active surface 321 which are aligned in the slots 31. The first bonding wires 314 are passed through the slots 3 1 4 and electrically connected to the first pads 324 of the first wafer 320 to the first fingers 316 of the substrate 310. In this embodiment, the window type ball grid array package structure 300 may further include a second wafer 370 having a second active surface 371 and an opposite second back surface 372. The back-to-back stacking manner is disposed on the first back surface 322 of the first wafer 320, that is, the second back surface 720 of the second wafer 370 is attached to the first back surface 322 of the first wafer 320, so that the first The two active faces 371 are upwards. The second wafer 370 further has a plurality of second pads 374 formed on the second active surface 371. In this embodiment, the second wafer 370 and the first wafer 306 can be substantially the same wafer, for example, the wafer size, the electrical function and the pad arrangement position are the same, so the second pads 374 It is also a central solder pad, which can reduce the type of wafer to reduce the manufacturing cost and management cost of the wafer. Electrically interconnecting the second pads 370 to the substrate 310 by electrically connecting the second pads 19 1362727 374 to the second contacts 319 of the substrate 310. The encapsulant 35 is formed on the inner surface 311 of the substrate 310 and fills the slot 314 to seal the first wafer 320, the second wafer 370, the first bonding wires 341 and the first Second weld line 342. The external terminals 36 are disposed on the outer pads 3 1 2 of the outer surface 3 1 2 of the substrate 310 for external bonding.

藉由該黏晶凹陷3 13以限制該黏晶材料33〇之形 狀,使戎黏晶材料3 3 0延伸並局部覆蓋至該第一晶片 320之該些側面323而不會溢膠至該基板31〇之該内表 面3 1 1之周邊’以避免溢膠污染該些第二接指3 1 9,故 該窗口型球柵陣列封裝構造3〇〇不需在該内表面3ΐι 留溢膠容許誤差,藉此縮小整個封裝的尺寸。因此,該 由口 I球柵陣列封裝構造3 〇〇不僅具有減少整個封裝The die-forming recess 3 13 is used to limit the shape of the die-bonding material 33, so that the die-bonding material 310 extends and partially covers the side faces 323 of the first wafer 320 without overflowing the substrate. 31周边 The periphery of the inner surface 3 1 1 'to avoid overflowing the second fingers 3 1 9 , so the window type ball grid array package structure 3 〇〇 does not need to allow glue on the inner surface 3 ΐ The error, thereby reducing the size of the entire package. Therefore, the port I ball grid array package structure 3 〇〇 not only has the entire package reduced

的厚度及增強黏晶強度以避免晶片分層剝離之功效 可縮小整個封裝的尺寸。 以上所述,僅县土 1 疋本發明的較佳實施例而已,並非 本發明作任何形式 Λ上的限制’本發明技術方案範圍當 所附申請專利範圍 田偎 固马丰。任何熟悉本專業的技術人員 利用上述揭示的枯你 技術内容作出些許更動或修飾為 變化的等效實施例,彳 1彳'-凡是未脫離本發明技術方案的由 容,依據本發明的括你I 节妁内 的技術實質對以上實施例所作的任〃 單修改、等同變化盥收私 間 一 U飾’均仍屬於本發明技術方 範圍内。 系的 20 圖··為習知窗口型球柵陣列封裝構造及其局部放大 的戴面示意圖。 1圖:為依據本發明第一具體實施例的一種窗口型球 柵陣列封裝構造及其特徵局部放大的截面示意 圖。 3圖:為依據本發明第—具體實施例的該窗口型球柵 陣列封裝構造之製程之主要流程方塊圖。 4 a 至4E圖.為依據本發明第一具體實施例的在該 囪口型球栅陣列封裝構造之製程中元件截面 示意圖。 5圖:為依據本發明第二具體實施例的另一種窗口型 球拇陣列封裝構造之截面示意圖。 &要元件符號說明】 第a曰片之側面與黏晶凹陷邊緣之間的縫隙 黏晶凹陷的深度 黏晶材料與鈍化層的厚度總合 提供基板之步驟 暫時性黏晶之步驟 電性連捿之步驟 黏晶擴散之步驟 形成封膠體之步驟 設置外接端子之步驟 ® 口型球柵陣列封裝構造The thickness and enhanced bond strength to avoid delamination of the wafer can reduce the size of the entire package. In the above, only the preferred embodiment of the present invention is not limited to the present invention. Any technical scope of the present invention is stipulated in the appended patent application. Any person skilled in the art can make a few changes or modify the equivalent embodiments by using the above-mentioned technical content, and the present invention does not deviate from the technical solution of the present invention. It is still within the scope of the technical scope of the present invention to make any modifications to the above embodiments, and equivalent changes to the above-mentioned embodiments. The figure 20 is a conventional window type ball grid array package structure and a partially enlarged surface view thereof. 1 is a partially enlarged cross-sectional schematic view showing a window type ball grid array package structure and its features in accordance with a first embodiment of the present invention. 3 is a block diagram showing the main flow of the process of the window type ball grid array package structure according to the first embodiment of the present invention. 4a to 4E are schematic cross-sectional views showing the components in the process of the gate-type ball grid array package structure in accordance with the first embodiment of the present invention. Figure 5 is a cross-sectional view showing another window type ball thumb array package structure in accordance with a second embodiment of the present invention. & description of the component symbol] The gap between the side of the a-thick film and the edge of the viscous recessed surface, the depth of the viscous crystal recess and the thickness of the passivation layer provide the step of the substrate, the step of temporarily bonding the crystal Step of the step of forming the sealant to form the sealant. Step of setting the external terminal.

110基板 111内表面 112 114槽孔 12 0晶片 121主動面 124 125鈍化層 130黏晶膠帶 140 150封膠體 160外接端子 200窗口型球柵陣列封裝構造 2 1 0基板 211内表面 212 2 13黏晶凹陷 2 13 A邊緣 214槽孔 215階梯狀缺口 2 1 6第一接指 217外接墊 218 220第一晶片 221第一主'動面 222 2 2 3側面 224第一鮮塾 225 2 3 0黏晶材料 240第一銲線 250 260外接端子 300窗口型球柵陣列封裝構造 310基板 3 11内表面 312 3 13黏晶凹陷 313A邊緣 3 14槽孔 3 1 5階梯狀缺口 316第一接指 320第一晶片 3 23側面 3 3 0黏晶材料 3 1 7外接塾 32 1第一主動面 324第一銲塾 341第一銲線 3 19 322 342 外表面 銲墊 銲線 外表面 防焊層 第一背面 鈍化層 封膠體 外表面 第二接指 第一背面 第二銲線 350封膠體 360外接端子 370第二晶片 371第二主動面 372第二背面 22 1362727 374第二銲墊110 substrate 111 inner surface 112 114 slot 12 0 wafer 121 active surface 124 125 passivation layer 130 adhesive tape 140 150 sealant 160 external terminal 200 window type ball grid array package structure 2 1 0 substrate 211 inner surface 212 2 13 die crystal Recess 2 13 A edge 214 slot 215 stepped notch 2 1 6 first finger 217 outer pad 218 220 first wafer 221 first main 'moving surface 222 2 2 3 side 224 first fresh 塾225 2 3 0 Material 240 first bonding wire 250 260 external terminal 300 window type ball grid array package structure 310 substrate 3 11 inner surface 312 3 13 sticky crystal recess 313A edge 3 14 slot 3 1 5 stepped notch 316 first finger 320 first Wafer 3 23 side 3 3 0 adhesive material 3 1 7 external 塾 32 1 first active surface 324 first solder 341 first bonding wire 3 19 322 342 outer surface soldering wire outer surface solder mask first passivation Layer seal outer surface second finger first back second bond wire 350 sealant 360 external terminal 370 second wafer 371 second active surface 372 second back surface 22 1362727 374 second solder pad

Claims (1)

1362727 十、申請專利範圍: Μ年z月7曰修正本 - —·. ,1 1、 一種® ό型球柵陣列封裝構造,包含: -基板’係具有-内表面、一外表面、—形成在該内表 面之黏晶凹陷以及一槽孔,該槽孔係貫穿該外表面至該 黏晶凹陷; 一第一晶片,係對準於該黏晶凹陷而設置於該基板之該 内表面,該第一晶片係具有一第一主動面、一第一背面 以及複數個在該第一主動面與該第一背面之間之側面; 一黏晶材料,係形成於該黏晶凹陷内以黏接該第一晶片 之該第一主動面,該黏晶凹陷係限制該黏晶材料的形 狀以使。玄黏曰曰材才斗填入該第—晶片之胃些側面與該黏 晶凹陷邊緣之間的缝隙,而局部覆蓋至該第一晶片之該 些侧面; 複數個第一銲線,係穿過該槽孔並電性連接該第一晶片 至該基板; 封膠體’係、形成於該基板之該内表面上並填滿該槽 孔,以密封該第一晶片與該些第一銲線;以及 複數個外接端子’係設置於該基板之該外表面; 其中該第一晶片具有—覆蓋於該第—主動面之純化 層,該鈍化層係完全嵌埋於該黏晶凹陷内,以使該鈍化 層之周邊側緣被該黏晶材料密封。 2、 如申請專利範圍第丨項所述之窗口型球栅陣列封裝構 造,其中該黏晶凹陷的深度係大於該黏晶材料與該鈍化 層之厚度總合但小於該第一晶片之厚度,以使該第一曰 24 1362727 3 ' 4、 5 ' 6、 7、 8、 9、 片係局部嵌埋於該黏晶凹陷内。 如申請專利範圍第1項 項所述之由口型球柵陣列封 造’其中該黏晶凹陷之邊 襄構 心瓊緣係位於該第一晶片之 鄰該第一晶片之該些側面❶ 一緊 如申請專利範圍第1 項所述之由口型球柵陣列封 造’/、中該黏晶材料係更擴散到該槽孔内。 、 如申》月專利範圍第4項所述之窗口型球柵陣列封 造,其中該黏晶材料係、更密封該些卜銲線在:曰 片之一端。 晶 如申請專利範圍第丨項所述之窗口型球柵陣列 造’其中該第-晶片係'具有複數個形成於該第—主^ 之第-銲墊,其係對準於該槽孔内,以供該些第= 之接合。 綷線 如申請㈣㈣第丨項所述之“㈣柵陣列 造,其中該基板係具有一階梯狀缺口,其係形成在: 表面與該槽孔之側邊。 x 如申請專利範圍第丨項所述之窗口型球栅陣列封 造,其中该些外接端子係包含複數個銲球。 如申請專利範圍第丨項所述之窗口型球柵陣 造,另包含一第二晶4,其係以背對背堆疊方式設置於 該第一晶片之第一背面上並具有複數個第二銲墊。、 、如申請專利範圍第9項所述之窗口型球柵陣列封裝構 造’另包含複數個第二銲線,其係電性連接該此: ~ ^ -韓 墊至該基板。 25 10 11、如申請專利範圍第1 造,_列封裝構 12 _ ㈣膠體係覆蓋該第U之該第-背面。 、—㈣口型球柵㈣料構造之製造方法 以下步驟: |包含 艰成在該 該外表面 材料; 陷並暫時 係具有一 主動面與 時性黏著 性連接該 提供一基板,係具有-内表面、—外表面、一 内表面之黏晶凹陷以及一槽孔,該槽孔係貫穿 至該黏晶凹陷,並於該黏晶凹陷内形成一黏晶 設置-第-晶片’該第一晶片係對準該黏晶凹 性黏貼於該基板之該内表面,其中該第—晶片 第主動®、一第一冑面以及複數個在該第— 該第-月面之間之側面’其中該黏晶材料係暫 該第一晶片之該第一主動面; 打線形成複數個第一銲線,係穿過該槽孔並電 第一晶片至該基板; 進行一黏晶擴散步驟,以施壓於該第一晶片,該黏晶凹 陷係限制該黏晶材料的形狀,以使該黏晶材料擴散並填 入該第一晶片之該些側面與該黏晶凹陷邊緣之間的縫 隙,而局部覆蓋至該第一晶片之該些側面,其中該第一 晶片係更具有一覆蓋於該第一主動面之鈍化層,並且在 該黏晶擴散步驟中,該鈍化層係完全嵌埋於該黏晶凹陷 内’以使該鈍化層之周邊側緣被該黏晶材料密封; 形成一封膠體’係形成於該基板之該内表面上並填滿該 槽孔,以密封該些第一晶片與該些第一銲線;以及 設置複數個外接端子,係設置於該基板之該外表面。 26 Ϊ362727 】3、如_請專利蔚R # 造之製1方、、苐12項所述之窗口型球柵陣列封裝構 料與該:化層法之:中該黏晶凹陷的深度係大於該黎晶材 使該笛_曰 度總合但小於該第一晶片之厚度,以 5 曰曰片係局部嵌埋於該黏晶凹陷内。 Ή請專利範園第12項所述之窗口型球柵陣列封 造之製造方法,甘士 構 其中該黏晶凹陷之邊緣係位於該第—曰 片之外但緊鄰該第-晶片之該些側面。 aa 15、 如中請專利11圍第12項所述之窗口型球柵陣列封裝槿 造之製造方法’其中在該黏晶擴散步驟中,該材 係更擴散到該槽孔内。 材514 16、 如申請專利_第15項所述之窗口型球栅陣列封 造之製造方法,其中該黏晶材料係更密封該些第 在該第一晶片之一端。 、” 17、 如申請專利範圍第12項所述之窗口型球柵陣列封裝構 造之製造方法’其中該第—晶片係具有複數個形成:該 第-主動面之第-銲勢,其係對準於該槽孔内,以 些第一銲線之接合。 八Μ 18、 如申請專利範圍第12項所述之窗口型球栅陣列封 造之製造方法’另包含之步驟為:以背對背堆疊方式設 置一第二晶片於該第一晶片之第—背面上。 271362727 X. Patent application scope: Μ年z月7月曰 Revised--·., 1 1. A ό-type ball grid array package structure, comprising: - the substrate 'has an inner surface, an outer surface, a die-forming recess on the inner surface and a slot extending through the outer surface to the die-forming recess; a first wafer disposed on the inner surface of the substrate in alignment with the die-forming recess; The first wafer has a first active surface, a first back surface, and a plurality of sides between the first active surface and the first back surface; a die-bonding material is formed in the die-forming recess to adhere The first active surface of the first wafer is connected to the shape of the die-bonding material. The viscous coffin is filled into the gap between the side of the stomach of the first wafer and the edge of the viscous recess, and partially covers the sides of the first wafer; a plurality of first bonding wires are threaded through Passing through the slot and electrically connecting the first wafer to the substrate; the encapsulant is formed on the inner surface of the substrate and filling the slot to seal the first wafer and the first bonding wires And a plurality of external terminals are disposed on the outer surface of the substrate; wherein the first wafer has a purification layer covering the first active surface, the passivation layer is completely embedded in the die recess, The peripheral side edge of the passivation layer is sealed by the die bonding material. 2. The window type ball grid array package structure of claim 2, wherein the depth of the viscous recess is greater than a thickness of the viscous material and the passivation layer but less than a thickness of the first wafer, The first 曰 24 1362727 3 ' 4, 5 ' 6, 7, 8, 9, and the fading system are partially embedded in the viscous recess. The edge ball grid array is sealed as described in claim 1 wherein the edge of the die-shaped recess is located on the side of the first wafer adjacent to the first wafer. Immediately as described in claim 1 of the patent application, the die-shaped ball grid array is encapsulated '/, and the die-bonding material is more diffused into the slot. The window type ball grid array package according to item 4 of the patent application scope of the present invention, wherein the die bonding material system further seals the plurality of bonding wires at one end of the cymbal sheet. A window type ball grid array according to the above-mentioned claim, wherein the first wafer system has a plurality of first pads formed on the first main gate, which are aligned in the slots For the joining of the first =. The 綷 line is as described in (4) (4) (4) Grid array, wherein the substrate has a stepped notch formed on the surface and the side of the slot. x As claimed in the scope of the patent application The window type ball grid array is encapsulated, wherein the external terminals comprise a plurality of solder balls. The window type ball grid array according to the scope of claim 2, further comprising a second crystal 4 The back-to-back stacking method is disposed on the first back surface of the first wafer and has a plurality of second solder pads. The window type ball grid array package structure as described in claim 9 further includes a plurality of second solders. The wire is electrically connected to the substrate: ~ ^ - Han pad to the substrate. 25 10 11. As claimed in the first paragraph, the package structure 12 _ (4) The glue system covers the first-back side of the U-th. - (4) mouth-shaped ball grid (four) material structure manufacturing method the following steps: | contains the outer surface material; the trapping and temporary system has an active surface and a time-adhesive connection to provide a substrate, which has - Surface, outer surface, inner surface a die-forming recess and a slot, the slot penetrates into the die-forming recess, and a die-forming device is formed in the die-forming recess - the first wafer is aligned with the die-bonded paste On the inner surface of the substrate, wherein the first wafer first active surface, a first first surface, and a plurality of sides between the first and the first moon surface, wherein the die bonding material is temporary to the first wafer The first active surface; forming a plurality of first bonding wires through the slot and electrically discharging the first wafer to the substrate; performing a die diffusion step to apply pressure to the first wafer, the die bonding The recesses limit the shape of the die-bonding material such that the die-bonding material diffuses and fills a gap between the sides of the first wafer and the edge of the die-forming recess, and partially covers the first wafer a side surface, wherein the first wafer system further has a passivation layer covering the first active surface, and in the die diffusion step, the passivation layer is completely embedded in the die hole recess to make the passivation layer The peripheral side edges are sealed by the die-bonding material; forming a colloid Forming on the inner surface of the substrate and filling the slot to seal the first wafer and the first bonding wires; and providing a plurality of external terminals disposed on the outer surface of the substrate. Ϊ 362727 】 3, such as _ please patent 蔚 R # 造造一方, 苐12 items of the window type ball grid array package material and the: layer method: the depth of the viscous recess is greater than the Li Jing material makes the flute _ 总 总 但 但 但 但 但 但 但 总 总 总 总 总 总 总 总 总 总 总 总 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 窗口 窗口 窗口 窗口 窗口 窗口 窗口 专利 窗口 窗口 专利 专利 窗口The manufacturing method of the seal, wherein the edge of the viscous depression is located outside the first slab but adjacent to the sides of the first wafer. aa 15. The window described in Item 12 of Patent 11 A method of manufacturing a ball grid array package, in which the material is more diffused into the slot. The method of manufacturing a window type ball grid array package according to claim 15, wherein the die bonding material further seals the ends of the first wafer. The manufacturing method of the window type ball grid array package structure according to claim 12, wherein the first wafer system has a plurality of formations: a first-welding potential of the first-active surface, which is a pair In the slot, the first bonding wire is bonded. The manufacturing method of the window type ball grid array sealing according to claim 12 of the patent application's further includes the steps of: stacking back to back A second wafer is disposed on the first back surface of the first wafer.
TW097120892A 2008-06-05 2008-06-05 Window bga package and method for fabricating the same TWI362727B (en)

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