1337401 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種多晶片堆疊組合，特別係有關 於一種多晶片層疊之側立表面接合構造，可運用於高密 度3 D晶片堆疊。 【先前技術】 隨著半導體裝置微小化與高容量的發展趨勢，複數 個半導體晶片可以縱向3 D堆疊。以往的晶片堆疊可為 背面朝向基板之方式逐一往上疊合，以打線達到晶片與 基板電性連接，在晶片堆疊與打線，重覆循環進行。故 這樣堆疊的生產效率較差且厚度較高，晶片堆疊層數越 多，則堆疊製程愈繁瑣耗時。此外，在多晶片堆疊區域 的周邊要預留打線連接空間，以設置打線接指。 本國發明專利公告480629號「雙晶圓封裝方法」揭 示一種雙晶片構裝體，在晶圓階段將兩個晶片面對面先 疊合，再側立表面接合至基板之技術。該雙晶片構襞體 係包含有面對面疊合第一晶片、第二晶片以及複數個銲 料凸塊。其中，該些銲料凸塊係位在兩晶片之主動面之 間，以電性連接兩晶片之銲墊。該雙晶片構裝體可側立 表面接合至一印刷電路板，由於雙晶片構裝體之側面面 積小且已為切割單離，無法預先銲設突出之凸塊，故該 雙晶片構裝體之表面接合方式是在印刷電路板上設置 另一銲料凸塊，熔接至該雙晶片構裝體之銲料凸塊並銲 接印刷電路板之連接墊。該雙晶片構裝體之側面放置於 突出之銲料凸塊，會有位移與空焊的問題。過於下壓該 雙晶片構裝體，則突出受壓迫的銲料凸塊會有橋接與污 染問題。 ^ 【發明内容】 本發明之主要目的係在於提供一種多晶片層疊之側 立表面接合構造，一晶片載體上之導體柱插接入晶片組 側面顯露之銲料凸i鬼’以增加晶片組焊接強度，避免回 銲時晶片組位移。因此’在晶片組之表面接合側面不需 設置突出之銲料凸塊，以消除習知晶片組在側立表面接 合時產生之鲜料橋接與污染問題。 本發明之次一目的係在於提供一種多晶片層叠之側 立表面接合構造，晶片組以其複數個晶片之一側面作為 表：接合’晶片組之外接點係為嵌埋之銲料凸塊，符合 先完成晶片堆疊，再以一次表面接合達到電性連接至晶 片栽體的要求。此外，在晶片堆叠時不會有銲料凸塊掉 落與污染問題。 个锭月心另一目的係在於提供一種多晶片層叠之側 表面接。構造，有利於晶片載體之導體柱穿刺入晶片 組之嵌埋銲料凸塊，以便在回銲時定位該晶片組。 本t月的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明’ 一種多晶片層疊之側立表面 接合構造主要包含一晶片載體以及至少一晶片組。該晶片 載體係具有複數個表面突出之導體柱。該晶片組係包含面對 貝古_资 ^ —弟—晶片與一第二晶片以及複數個銲料凸瑰，該 1337401 . 第一=片係、具有複數㈣-銲塾，該第二晶片係具有複數個 第一銲墊，該些銲料凸塊係連接該些第一銲墊與該些第二銲 ，並且外露於該晶片組之—晶片側面。其中該晶片組之該 晶片側^系表面接合於該晶片^，並使該些導體柱插接於 該些銲料凸塊内。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之多晶片層疊之侧立表面接合構造t ，每— 導體柱可具有一穿刺尖端。 在則述之多晶片層疊之側立表面接合構造中，該晶 片組可另包含面對面貼合之一第三晶片與第四晶片，該第三 晶片係具有複數個第三銲墊，該第四晶片係具有複數個第四 銲墊，並以複數個銲料凸塊連接該些第三銲墊與該些第四銲 墊並且外露於該晶片組之該晶片側面，並且該第三晶片之背 面係疊合在該第二晶片之背面。 在前述之多晶片層疊之側立表面接合構造中，該歧 導雜柱之炫點係可高於該些銲料凸塊之回銲溫度。 在則述之多晶片層疊之側立表面接合構造中，該杜 導體柱係可為錐形柱體。 在别述之多晶片層疊之侧立表面接合構造中，該先匕 導體柱係可為電鍵形成或是由一銅箔蝕刻形成之金屬枉 體。 在前述之多晶片層叠之側立表面接合構造中，該此 導體柱係可為打線形成之結球&塊。 7 1337401 , 在前述之多晶片層疊之側立表面接合構造中，該第 一晶片與第二晶片之間係可形成有一填充膠。 在前述之多晶片層疊之側立表面接合構造中，可另 包含有一密封膠，其係形成於該晶片組之該晶片側面之周 緣。 在前述之多晶片層疊之側立表面接合構造中，該第 一晶片與該第二晶片可為同尺寸，依晶片堆疊數量而使該晶 片組之該晶片側面之面積增加，以接近為正方形。 【實施方式】 依據本發明之第一具體實施例，揭示一種多晶片層 疊之側立表面接合構造。請參閱第1及2圖所示，一種 多晶片層疊之側立表面接合構造 1 〇〇主要包含一晶片 載體1 1 0以及至少一晶片組1 20。該晶片載體1 1 0在一 供多晶片堆疊接合之表面接合區内係具有複數個連接 墊1 1 1。複數個表面突出之導體柱Π 2係設置於該些連 接墊1 1 1。該晶片載體1 1 0係可為一印刷電路板、一導 線架或一電路薄膜。依用途區分，該晶片載體1 1 0係為 一記憶卡基板、一記憶體模組基板、一 BGA封裝基板、 一主機板或一手機通訊板等等。而該些導體柱1 1 2係形 成於該些連接墊111上且突出於該晶片載體110之表面 接合區，用以電性連接該晶片組1 2 0。 該晶片組1 2 0係包含面對面貼合之一第一晶片1 2 1 與一第二晶片1 2 2以及複數個銲料凸塊1 3 0。該第一晶 片 121 係具有複數個位於主動面邊緣之第一銲墊 8 1337401 . 1 2 1 A，該第二晶片1 2 2亦具有複數個位於主動面 第二銲墊122A。該第一晶片121之主動面與第 1 22之主動面之間係可形成有一填充膠1 40，例 樹脂（epoxy)，以增加結合強度及加強該些銲料凸 之密封保護。 在本實施例中，該第一晶片1 21與該第二晶 係為低腳數之積體電路晶片，所稱「低腳數」是 晶片之銲墊121A或122A的數量是小於一百， 第一晶片1 2 1與該第二晶片1 22可為快閃記憶類 動態隨機存取記憶體晶片或邏輯晶片。該些銲 130係連接該些第一銲墊121A與該些第二銲墊 並且如第3圖所示，該些銲料凸塊1 3 0係外露於 晶片1 2 1與該第二晶片1 22之一晶片側面1 20B 之晶片側面1 20B係包含所有晶片的在其主動面 之間之一側面以及密封膠1 40之厚度，對應於該 體110之表面接合區。 其中，該晶片組1 20之該晶片側面1 20B係表 於該晶片載體1 1 〇，並使該些導體柱Η 2插接於 料凸塊1 3 0内，以增加該晶片組1 2 0之焊接強度 晶片載體1 1 〇可利用該些嵌埋之銲料凸塊1 3 0側 結合至該晶片載體1 1 0，符合先完成晶片堆疊， 次表面接合達到電性連接至晶片載體的要求。此 晶片堆疊時不會有銲料凸塊掉落與污染問題。此 晶片組1 2 0係以側立方式表面接合，能增加晶片 邊緣之 二晶片 如環氧 塊130 片122 相每一 例如該 :晶片、 料凸塊 1 22A。 該第一 。所稱 與背面 晶片載 面接合 該些銲 。故該 向覆晶 再以一 外，在 外，該 堆疊數 9 1337401 4- 量與統一晶片組之高度。 通常該晶片載體11 〇上該些導體柱1 i 2之熔點係可 高於該些銲料凸塊1 3 0之回銲溫度，以使該些導趙桂 1 1 2具有回銲該些銲料凸塊1 3 〇時之插接能力。 較佳地，該第一晶片121與該第二晶片122可為同尺 寸，依晶片堆疊數置而使該a曰片組1 2 0之s玄晶片側面1 2 〇 b 之面積增加，以接近為正方形，可以方便地利用習知的點晶 吸嘴吸附該晶片組1 20 ’進行表面接合之前的定位作業，壓 接至該晶片載體1 1 0。上述晶片堆疊數量增加的實施方法 為’面對面貼合兩晶片之後，再進行晶背對晶背之晶片級黏 接’在本實施例中，即是利用一黏晶層1 2 〇 A黏接相接面 對面晶片組之晶片背面。在本實施例中，為達到正方开/ 或接近正方形之晶片側面120B，該晶片組no包含有 四組面對面貼合之晶片組，可另包含面對面貼合之—第 二晶片123與一第四晶片124’該第三晶片in係具有 複數個第三銲墊123A ’該第四晶片124係具有複數個 第四銲墊1 24A ’並以複數個銲料凸塊1 3〇連接該些第 三銲堅123與該些第四輝塾124並且外露於該晶片組 120之晶片側面120B。利用一黏晶層u〇A之黏貼，使 該第三晶片123之背面疊合在該第二晶片122之背面。 同樣地’可另包含面對面貼合之一第五晶片1 25與—第 六晶片1 2 6以及面對面貼合之一第七晶片】2 7與一第八 晶片1 28。並以嵌埋在第五晶片1 25與第六晶片i 26之 間之鲜料凸塊1 3 0連接第五晶片i 25之複數個第五銲墊 10 I3374Q1 125A與第六晶片126之複數個第六銲墊ι26Α β _黏晶 層1 2 Ο Α黏接第五晶片1 2 5之背面與第四晶片1 2 4之背 面。以嵌埋在第七晶片1 2 7與第八晶片1 28之間之銲料 凸塊130連接第七晶片127之複數個第七銲墊127A與 第八晶片1 2 8之複數個第八銲整1 2 8 A。 較佳地，每一導體柱11 2可具有一穿刺尖端丨〖3。本發 明之多晶片層疊之側立表面接合構造之製造流程中在 • 表面接合步驟中係包含有一黏晶步驟與一回銲步驟。如 第5圖所示，在黏晶步驟時，該晶片組i 2〇之晶片側面1 2〇b 係往該晶片載體11 0壓合，施予該晶片組j 2〇之黏晶溫度與 黏晶壓力，會使該些銲料凸塊1 3〇軟化，該些導體柱丨]3之 泫些穿刺尖端113可稍插入至該些銲料凸塊13〇，達到回銲 前之定位效果。在本實施例中，該些導體柱i丨2係可為錐 形柱體，如圓錐體或方錐體。在回銲步驟中，該些銲料 凸塊130熔化並沿著該些導體柱112銲接至該些連接墊 φ 111，達到多晶片組之側立表面接合。 再如第1圖所示，在一具體結構中，該多晶片層疊 之側立表面接合構造！ 〇〇係可另包含有一密封膠！ ， 其係形成於該晶片組1 2〇之該晶片側面！ 2〇B之周緣， 使該晶片組120更為穩固結合於該晶片載體】"，並可 避免外界水氣或污染物侵入表面接合之間隙。 如第4圖所示，繪示該多晶片層疊之側立表面接合 構造1 〇〇之實施流程示意圖。首先，提供一第一晶片 12丨，在其主動面之銲墊上設置複數個銲料凸塊13〇。BRIEF DESCRIPTION OF THE DRAWINGS 1. Field of the Invention The present invention relates to a multi-wafer stack assembly, and more particularly to a multi-wafer stacking side-surface bonding structure that can be used for high density 3D wafer stacking. [Prior Art] With the trend toward miniaturization and high capacity of semiconductor devices, a plurality of semiconductor wafers can be stacked in a vertical 3D. The conventional wafer stack can be stacked one by one in such a manner that the back side faces the substrate, and the wafer is electrically connected to the substrate by wire bonding, and the wafer is stacked and wired, and the cycle is repeated. Therefore, the stacking process is inferior in production efficiency and the thickness is high. The more the number of stacked layers of the wafer, the more complicated and time-consuming the stacking process. In addition, a wire bonding space is reserved around the multi-wafer stacking area to set the wire bonding fingers. The "Double Wafer Packaging Method" of the National Invention Patent Publication No. 480629 discloses a two-wafer structure in which two wafers are stacked face to face in the wafer stage, and the side surface is bonded to the substrate. The dual wafer structure includes a first wafer, a second wafer, and a plurality of solder bumps stacked face to face. Wherein, the solder bumps are located between the active faces of the two wafers to electrically connect the pads of the two wafers. The bimorph structure can be joined to a printed circuit board by a side surface. Since the side surface area of the bimorph structure is small and the cut is detached, the protruding bump cannot be soldered in advance, so the bimorph structure The surface bonding is performed by disposing another solder bump on the printed circuit board, soldering the solder bump to the bimorph structure, and soldering the connection pads of the printed circuit board. The side of the bimorph structure is placed on the protruding solder bumps, which causes displacement and void soldering problems. If the bimorph structure is depressed too much, the stressed solder bumps will have bridging and contamination problems. SUMMARY OF THE INVENTION The main object of the present invention is to provide a multi-wafer laminated side surface bonding structure, a conductor post on a wafer carrier is inserted into the solder bump exposed on the side of the wafer group to increase the soldering strength of the wafer set. To avoid displacement of the wafer set during reflow. Therefore, no protruding solder bumps are required on the surface bonding side of the wafer set to eliminate the problem of bridging and contamination of the conventional wafer set when the side surface is joined. A second object of the present invention is to provide a multi-wafer laminated side-surface bonding structure in which a wafer set is represented by one side of a plurality of wafers: the bonding 'outside of the wafer set is an embedded solder bump, which is in accordance with The wafer stack is completed first, and then the surface bonding is performed to achieve the electrical connection to the wafer carrier. In addition, there is no solder bump drop and contamination problems when the wafer is stacked. Another purpose of the ingot is to provide a side surface connection of a multi-wafer stack. The structure facilitates penetration of the conductor posts of the wafer carrier into the embedded solder bumps of the wafer set to position the wafer set during reflow. The purpose of this month and the resolution of its technical problems are achieved by the following technical solutions. According to the present invention, a multi-wafer laminated side surface bonding structure mainly comprises a wafer carrier and at least one wafer group. The wafer carrier has a plurality of conductor posts with surface protrusions. The chip set includes a face-to-face and a second wafer and a plurality of solder bumps, the 1734401. The first = film, having a plurality (four)-weld, the second chip has And a plurality of first solder pads connecting the first pads and the second solders and exposed to the wafer side of the wafer set. The wafer side surface of the wafer set is bonded to the wafer, and the conductor posts are inserted into the solder bumps. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the aforementioned side wafer bonding structure t of the multi-wafer stack, each of the conductor posts may have a puncture tip. In the side-surface bonding structure of the multi-wafer stack described above, the wafer set may further comprise a third wafer and a fourth wafer facing each other, the third wafer having a plurality of third pads, the fourth The wafer has a plurality of fourth pads, and the third pads and the fourth pads are connected by a plurality of solder bumps and exposed on the side of the wafer of the wafer set, and the back surface of the third wafer is Superposed on the back side of the second wafer. In the aforementioned side wafer bonding configuration of the multi-wafer stack, the dazzle of the parasitic pillars may be higher than the reflow temperature of the solder bumps. In the side-surface bonding structure of the multi-wafer stack described above, the pillar column can be a tapered cylinder. In the side-surface bonding structure of the multi-wafer lamination described above, the pre-conducting conductor post may be formed of a bond or a metal body formed by etching a copper foil. In the aforementioned side wafer bonding structure of the multi-wafer stack, the conductor post may be a ball forming & block formed by wire bonding. 7 1337401, in the side wafer bonding structure of the multi-wafer stack described above, a filling glue may be formed between the first wafer and the second wafer. In the side wafer bonding structure of the multi-wafer stack described above, a sealant may be further included on the periphery of the wafer side of the wafer set. In the above-described multi-wafer laminated side-surface bonding structure, the first wafer and the second wafer may be the same size, and the area of the wafer side of the wafer group is increased to be approximately square according to the number of wafer stacks. [Embodiment] According to a first embodiment of the present invention, a side-surface joining structure of a multi-wafer stack is disclosed. Referring to Figures 1 and 2, a multi-wafer laminated side surface bonding structure 1 〇〇 mainly includes a wafer carrier 110 and at least one wafer set 120. The wafer carrier 110 has a plurality of pads 1 1 1 in a surface bond region for multi-wafer stack bonding. A plurality of surface-constructed conductor posts 2 are disposed on the plurality of connection pads 1 1 1 . The wafer carrier 110 can be a printed circuit board, a wire frame or a circuit film. According to the use, the wafer carrier 110 is a memory card substrate, a memory module substrate, a BGA package substrate, a motherboard or a mobile communication board, and the like. The conductor posts 112 are formed on the connection pads 111 and protrude from the surface landing area of the wafer carrier 110 for electrically connecting the chip set 120. The wafer set 120 includes a first wafer 1 2 1 and a second wafer 1 2 2 and a plurality of solder bumps 130 that face-to-face. The first wafer 121 has a plurality of first pads 8 1337401 . 1 2 1 A at the edge of the active surface, and the second wafer 12 2 also has a plurality of active pads second pads 122A. An adhesive 134, such as an epoxy, may be formed between the active surface of the first wafer 121 and the active surface of the first 22 to increase the bonding strength and enhance the sealing protection of the solder bumps. In this embodiment, the first wafer 126 and the second crystal system are low-numbered integrated circuit chips, and the number of "low-foot counts" is that the number of solder pads 121A or 122A of the wafer is less than one hundred. The first wafer 1 21 and the second wafer 1 22 may be flash memory type dynamic random access memory chips or logic chips. The solder pads 130 are connected to the first pads 121A and the second pads. As shown in FIG. 3 , the solder bumps 1 3 0 are exposed on the wafer 1 21 and the second wafer 1 22 . The wafer side 1 20B of one of the wafer sides 1 20B includes the side of one of the wafers between its active faces and the thickness of the sealant 140, corresponding to the surface landing zone of the body 110. The wafer side 1 20B of the chip set 120 is attached to the wafer carrier 1 1 〇, and the conductor posts 2 are inserted into the material bumps 130 to increase the chip set 1 2 0 The solder strength wafer carrier 1 1 can be bonded to the wafer carrier 110 using the embedded solder bumps 130 side, in accordance with the requirements of completing the wafer stacking and subsurface bonding to electrically connect to the wafer carrier. This wafer is stacked without solder bumps and contamination problems. The wafer set 120 is surface-bonded in a side-by-side manner, and the two wafers, such as the epoxy block 130, each of which can be added to the edge of the wafer, such as the wafer, the bump 1 22A. The first. The welds are said to be bonded to the back wafer carrier. Therefore, the number of stacks is 9 1337401 4- and the height of the unified wafer set. Generally, the melting point of the conductive pillars 1 i 2 on the wafer carrier 11 can be higher than the soldering temperature of the solder bumps 130, so that the conductive electrodes 1123 have reflow solder bumps. Block 1 3 插 plug-in capability. Preferably, the first wafer 121 and the second wafer 122 may be the same size, and the area of the side of the a wafer group 1 2 0 增加 晶片 增加 增加 , , , , , , , In the case of a square, the positioning operation before the surface bonding of the wafer set 1 20 ′ can be conveniently performed by a conventional dot crystal nozzle, and crimped to the wafer carrier 1 10 . The method for increasing the number of wafer stacks described above is to perform the wafer-level bonding of the crystal back to the crystal back after the two wafers are face-to-face bonded. In this embodiment, a bonded layer of 1 2 〇A is used. The back side of the wafer facing the face wafer group. In this embodiment, in order to achieve a square open/or nearly square wafer side 120B, the wafer set no includes four sets of face-to-face bonded wafer sets, which may further comprise face-to-face bonding - second wafer 123 and a fourth The wafer 124' has a plurality of third pads 123A. The fourth wafer 124 has a plurality of fourth pads 1 24A ′ and connects the third pads with a plurality of solder bumps 13 〇 The stiffener 123 and the fourth radiant 124 are exposed to the wafer side 120B of the wafer set 120. The back surface of the third wafer 123 is superposed on the back surface of the second wafer 122 by adhesion of a bonding layer u〇A. Similarly, a fifth wafer 256 and a sixth wafer 126 and a face-to-face one of the seventh wafers 27 and an eighth wafer 1 28 may be additionally provided face to face. And connecting the plurality of fifth pads 10 I3374Q1 125A and the sixth wafer 126 of the fifth wafer i 25 with the fresh bumps 1 300 interposed between the fifth wafer 152 and the sixth wafer i 26 The sixth solder pad ι26 Α β _ the adhesive layer 1 2 Ο Α is bonded to the back surface of the fifth wafer 1 2 5 and the back surface of the fourth wafer 1 2 4 . The plurality of eighth solder pads 127A and the eighth wafers 1 2 8 of the seventh wafer 127 are connected by a solder bump 130 embedded between the seventh wafer 127 and the eighth wafer 128. 1 2 8 A. Preferably, each conductor post 11 2 can have a puncture tip 丨3. In the manufacturing process of the multi-wafer laminated side-surface bonding structure of the present invention, the surface bonding step includes a die bonding step and a reflow step. As shown in FIG. 5, in the die bonding step, the wafer side surface 1 2〇b of the wafer set i 2〇 is pressed against the wafer carrier 110, and the die bonding temperature and viscosity of the wafer set j 2〇 are applied. The crystal pressure causes the solder bumps to soften, and the puncture tips 113 of the conductor posts 3 can be slightly inserted into the solder bumps 13 to achieve the positioning effect before reflow. In this embodiment, the conductor posts i丨2 may be tapered cylinders such as cones or square cones. In the reflow step, the solder bumps 130 are melted and soldered along the conductor posts 112 to the pads φ 111 to achieve side surface bonding of the multi-wafer stack. Further, as shown in Fig. 1, in a specific configuration, the multi-wafer laminated side surface joint structure is constructed! The enamel can also contain a sealant! It is formed on the side of the wafer of the wafer set 1 2〇! The periphery of 2〇B enables the wafer set 120 to be more firmly bonded to the wafer carrier, and the outside water vapor or contaminant can be prevented from intruding into the gap of the surface joint. As shown in Fig. 4, a schematic flow diagram of the implementation of the side-surface bonding structure 1 of the multi-wafer stack is shown. First, a first wafer 12 is provided, and a plurality of solder bumps 13 are provided on the pads of the active surface.
II 1337.401, 之後，提供一第二晶片1 22，並在該第二晶片1 22 有第二銲墊122A之主動面塗施上一填充膠140。名 將該第一晶片12〗具有該些銲料凸塊130之主動面 至該第二晶片1 2 2，該填充膠1 4 0使該第一晶片1 該第二晶片1 2 2為面對面覆晶黏貼。再將複數個如 面對面貼合之晶片組疊合，直到所需要的晶片 12 0B之厚度，該晶片側面120B面積約為正方形。 將該晶片組1 20之晶片側面1 20B，以研磨盤1 0加 磨成一可顯露該些銲料凸塊1 3 0之平整平面。另， 供之一晶片載體 110，其表面設置有複數個導 1 1 2。之後，進行一表面接合步驟，以結合該晶片细 與該晶片載體1 1 0，其中每一導體柱Η 2係插接對 於每一銲料凸塊1 3 0，用以增加晶片組焊接強度。 在本發明之第二具體實施例，揭示另一種多晶 疊之側立表面接合構造。請參閱第6圖係為繪示另 多晶片層疊之側立表面接合構造200之戴面示意I 多晶片層疊之側立表面接合構造200具有與第一 例不同的導體柱形狀。主要包含一晶片載體2 1 0以 少一晶片組220。該晶片載體2 1 0係具有複數個表 出之導體柱212，其係設置於在一表面接合區内之 個連接墊2 1 1。在本實施例中，該些導體柱2 1 2係 電鍍形成或是由一銅箔蝕刻形成之金屬柱體。 該晶片組220係包含面對面貼合之一第一晶片 與一第二晶片222以及複數個銲料凸塊230，該第 形成 ^著， 疊壓 21與 上述 側面 接著 以研 所提 體柱 .120 應入 片層 一種 。該 實施 及至 面突 複數 可為 22 1 一晶 12 1337401 片 2 2 1 係且古·, τ八有複數個位於其主動面邊緣之第一銲墊 221Α，該 Μ -曰 u ^ 一 bb片2 2 2係具有複數個位於其主動面邊緣 之第二鮮塾 » ^该些銲料凸塊230係連接該些第一 銲塾221A应兮砂哲_ Λ - ^二第_•鲜塾222A並且外露於該晶片組II 1337.401, after which a second wafer 1 22 is provided, and a filler 140 is applied to the active surface of the second wafer 122 having the second pad 122A. The first wafer 12 has the active surface of the solder bumps 130 to the second wafer 1 2 2, and the filling paste 140 causes the first wafer 1 and the second wafer 1 2 2 to be face-to-face flip-chip stickers. . A plurality of face-to-face wafers are then laminated until the desired thickness of the wafer 120B, which is approximately square. The wafer side 1 20B of the wafer set 120 is ground to a flattening plane that exposes the solder bumps 130. In addition, a wafer carrier 110 is provided, the surface of which is provided with a plurality of conductors 112. Thereafter, a surface bonding step is performed to bond the wafer to the wafer carrier 110, wherein each conductor post 2 is interposed for each solder bump 130 to increase the wafer set soldering strength. In a second embodiment of the invention, another side stacking surface construction of the polycrystalline stack is disclosed. Referring to Fig. 6, there is shown a side view of a side-surface joining structure 200 in which a plurality of wafers are stacked. The multi-wafer laminated side-surface joining structure 200 has a conductor post shape different from that of the first example. It mainly comprises a wafer carrier 210 with at least one wafer set 220. The wafer carrier 210 has a plurality of conductor posts 212, which are disposed in a connection pad 2 1 1 in a surface joint region. In this embodiment, the conductor posts 2 1 2 are plated or formed of a metal foil formed by etching a copper foil. The wafer set 220 includes a first wafer and a second wafer 222 and a plurality of solder bumps 230 that are surface-to-face bonded. The first layer is formed, and the layer 21 and the side surface are subsequently formed by the substrate. Enter a layer of one. The implementation and the facet complex number can be 22 1 a crystal 12 1337401 piece 2 2 1 system and the ancient ·, τ eight has a plurality of first pads 221 位于 at the edge of the active face, the Μ -曰u ^ a bb piece 2 The 2 2 series has a plurality of second fresh enamels located at the edges of the active faces thereof. ^ The solder bumps 230 are connected to the first solder dies 221A and should be exposed to the sand zh _ Λ - ^ 二第_•鲜塾222A and exposed On the chipset
2 2 0 之一曰 y I 曰曰側面220B。在該第一晶片221之主動面與 該第二晶片 2之主動面之間可形成有一填充膠240, 以嵌埋該些録刹_儿& β，Λ ^ , 科凸塊2 3 0。其中，該晶片組2 2 0之該晶 a 片側面2 2 Ο B係|人 W *表面接合於該晶片載體2 1 0，並使該些 導體柱2 1 2插接於該些銲料凸塊230内。 。月再，閱第6圖，在本實施例中，該晶片組2 2 〇另 匕3有面對面貼合之一第三晶片223與第四晶片224，該第 三晶片223係具有複數個第三銲墊223a，該第四晶片224 係具有複數個第四銲墊224A，並以複數個銲料凸塊23〇連 接忒些第二如墊223A與該些第四銲墊223B並且外露於該 晶片組220之該晶片側面22〇B。並且，利用一黏晶層22〇a • 使該第三晶片223之背面係疊合在該第二晶片222之背面。 藉此，擴大該晶片側面220B之面積’以利該晶片組22〇之 黏晶取放與壓合，並增加晶片堆叠數量。 此外，該多晶片層疊之側立表面接合構造2 〇 〇可另 包含一密封膠250,其係形成於該晶片組22〇之該晶片側 面2 20B之周緣。 在本發明之第二具體實施例，如第7圖所示，揭示 另一種多晶片層疊之側立表面接合構造’主要元件大體 與第二具體實施例相同，相同圖號的元件不再詳細贅 13 1337401 0 述。該多晶片層疊之側立表面接合構造主要包含一晶片 載體210’以及至少一晶片組22〇。該晶片載體21〇，係具有複 數個表面突出之導體柱2 1 3。在本實施例中，該些導體柱 2 1 3係可為打線形成之結球凸塊。 。玄b曰片組2 2 0係包含面對面貼合之一第一晶片2 2 1與一 第二晶片222以及複數個銲料凸塊230 ’該第一晶片221係 具有複數個第一銲墊221 A，該第二晶片222係具有複數個 第一 ~塾222A’該些銲料凸塊230係連接該些第一銲塾 221A與該些第二銲墊222A並且外露於該晶片組22〇之一晶 片側面220B。在該第一晶片221與該第二晶片222之間可 形成有一填充膠240，以嵌埋該些銲料凸塊230。在本實施 例中，該晶片組220係另包含面對面貼合之一第三晶片223 與一第四晶片224，其晶片疊合方式如同第一晶片221與第 一晶片 222。 其中’該晶片組220之該晶片側面22〇B係表面接合於該 晶片載體2 1 0,，並使該些導體柱2丨3插接於該些銲料凸塊 230内。因此，該多晶片層疊之側立表面接合構造能增加 δ玄晶片組2 2 0之焊接強度，避免回銲時該晶片組2 2 〇發 生位移，並能消除習知晶片組在側立表面接合時產生之 銲料橋接與污染問題。 較佳地’多晶片層疊之側立表面接合構造可另包含一 密封膠250’，可為一點塗膠體，其係形成於該晶片組22〇之 該晶片側面220Β之周緣並密封該些晶片221、222、223與 224之其餘側面’以防止水氣侵入晶片間疊合間隙並電性絕 14 1337401 » 緣與保護該些晶片221、222、223與224。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：依據本發明之第一具體實施例，一種多晶片層 疊之側立表面接合構造之截面示意圖。 第2圖：依據本發明之第一具體實施例，該多晶片層疊 之側立表面接合構造在表面接合之前主要元 件分離之截面示意圖。 第3圖：依據本發明之第一具體實施例，該多晶片層疊 之側立表面接合構造之晶片組之晶片側面之 示意圖。 第4圖：依據本發明之第一具體實施例，該多晶片層叠 之側立表面接合構造之實施流程示意圖。 第5圖：依據本發明之第一具體實施例，該多晶片層疊 之側立表面接合構造在回銲前達到定位狀態 之裁面示意圖。 第6圖：依據本發明之第二具體實施例，繪示另一種導 15 1337401. 體柱形狀之一種多晶片層疊之側立表面接合 構造之載面示意圖。 第7圖：依據本發明之第三具體實施例，繪示另一種導 體柱形狀之一種多晶片層疊之側立表面接合 構造之截面示意圖。 【主要元件符號說明】 10 研磨盤 1 〇〇多晶片層疊之側立表面接合構造 110 晶片載體 111連接墊 112 導體柱 113 穿刺尖踹 120 晶片組 120A黏晶層 120B 晶片侧面 121 第一晶片 121 A第一銲墊 122 第二晶片 1 22A第二銲墊 123 第三晶片 123A第三銲墊 124 第四晶片 1 24A第四銲塾 125 第五晶片 125A第五銲墊 126 第六晶片 126A第六銲墊 127 第七晶片 1 27A第七銲塾 128 第八晶片 1 28A第八銲塾 130 銲料凸塊 14〇填充膠 150 密封膠 200 多晶片層疊之側立表面接合構造 210 晶片載體 2 1 〇 ’晶片載體 211 連接墊 212 導體柱 213導體柱 220 晶片組 220A黏晶層 220E 丨晶片命丨面 16 1337,401, 221第一晶片 222第二晶片 230銲料凸塊 221A第一銲墊 222A第二銲墊 240填充膠 250密封膠2 2 0 One 曰 y I 曰曰 Side 220B. A filling glue 240 may be formed between the active surface of the first wafer 221 and the active surface of the second wafer 2 to embed the recording electrodes θ, Λ ^ , and the bumps 203. The surface of the wafer 2 2 Ο B system | human W * surface is bonded to the wafer carrier 2 1 0, and the conductor posts 2 1 2 are inserted into the solder bumps. Within 230. . Further, in the sixth embodiment, in the embodiment, the wafer set 2 2 and the other 3 have face-to-face bonding one of the third wafer 223 and the fourth wafer 224, and the third wafer 223 has a plurality of third The pad 223a has a plurality of fourth pads 224A, and is connected to the second pads 223A and the fourth pads 223B by a plurality of solder bumps 23B and exposed to the chip set. 220 of the wafer side 22 〇 B. Moreover, the back surface of the third wafer 223 is superposed on the back surface of the second wafer 222 by using a die bond layer 22A. Thereby, the area of the wafer side surface 220B is enlarged to facilitate the pick-and-place bonding of the wafer group 22 and increase the number of wafer stacks. In addition, the multi-wafer laminated side surface bonding structure 2 〇 〇 may further comprise a sealant 250 formed on the periphery of the wafer side surface 20 20B of the wafer set 22 . In the second embodiment of the present invention, as shown in FIG. 7, the side member of the multi-wafer stack is disclosed. The main components are substantially the same as those of the second embodiment, and the components of the same figure are no longer detailed. 13 1337401 0 Description. The multi-wafer stacked side landing surface bonding configuration primarily comprises a wafer carrier 210' and at least one wafer set 22A. The wafer carrier 21 is a conductor post 2 1 3 having a plurality of surface protrusions. In this embodiment, the conductor posts 2 1 3 may be ball bumps formed by wire bonding. . The first wafer 221 has a plurality of first pads 221 A. The first wafer 221 has a plurality of first pads 221 A. The first wafer 221 has a plurality of first pads 221 A. The second wafer 222 has a plurality of first 塾 222A'. The solder bumps 230 are connected to the first solder pads 221A and the second pads 222A and exposed to the wafer set 22 Side 220B. A filling paste 240 may be formed between the first wafer 221 and the second wafer 222 to embed the solder bumps 230. In the present embodiment, the wafer set 220 further includes a third wafer 223 and a fourth wafer 224 which are surface-to-face bonded, and the wafers are stacked in the same manner as the first wafer 221 and the first wafer 222. The wafer side 22B of the wafer set 220 is surface-bonded to the wafer carrier 210, and the conductor posts 2丨3 are inserted into the solder bumps 230. Therefore, the multi-wafer lamination side-side surface bonding structure can increase the welding strength of the δ 玄 晶片 wafer group 220, avoid the displacement of the wafer group 2 2 回 during reflow, and can eliminate the bonding of the conventional wafer group on the side vertical surface. The resulting solder bridging and contamination problems. Preferably, the multi-wafer laminated side-surface bonding structure may further comprise a sealant 250', which may be a one-coat gel, which is formed on the periphery of the wafer side 220 of the wafer set 22 and seals the wafers 221 The remaining sides of 222, 223 and 224 'to prevent moisture from intruding into the inter-wafer stacking gap and electrically insulating the wafers 221, 222, 223 and 224. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a side-surface joining structure of a multi-wafer laminate in accordance with a first embodiment of the present invention. Figure 2 is a schematic cross-sectional view showing the separation of major components prior to surface bonding in accordance with a first embodiment of the present invention. Figure 3 is a schematic illustration of the wafer side of the wafer set of the side-surface bonded construction of the multi-wafer stack in accordance with a first embodiment of the present invention. Fig. 4 is a flow chart showing the implementation of the side-surface joining structure of the multi-wafer stack according to the first embodiment of the present invention. Fig. 5 is a schematic view showing the face of the multi-wafer laminate in a positional state before reflowing, in accordance with a first embodiment of the present invention. Fig. 6 is a schematic view showing the surface of a multi-wafer laminated side-surface joining structure of a body column shape according to a second embodiment of the present invention. Figure 7 is a cross-sectional view showing a side-surface joining structure of a multi-wafer laminate of another shape of a conductor post in accordance with a third embodiment of the present invention. [Main component symbol description] 10 grinding disc 1 〇〇 multi-wafer laminated side surface bonding structure 110 wafer carrier 111 connection pad 112 conductor post 113 puncture tip 120 wafer group 120A die layer 120B wafer side 121 first wafer 121 A First pad 122 second wafer 1 22A second pad 123 third wafer 123A third pad 124 fourth wafer 1 24A fourth pad 125 fifth wafer 125A fifth pad 126 sixth wafer 126A sixth solder Pad 127 seventh wafer 1 27A seventh soldering pad 128 eighth wafer 1 28A eighth soldering pad 130 solder bump 14 〇 filling glue 150 sealing paste 200 multi-wafer laminated side surface bonding structure 210 wafer carrier 2 1 〇 'wafer Carrier 211 connection pad 212 conductor post 213 conductor post 220 wafer set 220A die bond layer 220E die wafer die face 16 1337, 401, 221 first die 222 second die 230 solder bump 221A first pad 222A second pad 240 filling glue 250 sealant
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