TWI453881B - Package structure and method of forming same - Google Patents

Package structure and method of forming same Download PDF

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Publication number
TWI453881B
TWI453881B TW101100274A TW101100274A TWI453881B TW I453881 B TWI453881 B TW I453881B TW 101100274 A TW101100274 A TW 101100274A TW 101100274 A TW101100274 A TW 101100274A TW I453881 B TWI453881 B TW I453881B
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Taiwan
Prior art keywords
substrate
package structure
electrical contacts
conductive element
pads
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TW101100274A
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Chinese (zh)
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TW201330203A (en
Inventor
詹前峰
林畯棠
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矽品精密工業股份有限公司
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Priority to TW101100274A priority Critical patent/TWI453881B/en
Priority to CN2012100155802A priority patent/CN103199076A/en
Publication of TW201330203A publication Critical patent/TW201330203A/en
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Publication of TWI453881B publication Critical patent/TWI453881B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/17104Disposition relative to the bonding areas, e.g. bond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
    • H01L2924/1461MEMS

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  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

封裝結構及其製法Package structure and its manufacturing method

本發明係有關於一種封裝結構及其製法,尤指一種具有高密度的輸入/輸出端之封裝結構及其製法。The present invention relates to a package structure and a method of fabricating the same, and more particularly to a package structure having a high density of input/output terminals and a method of fabricating the same.

隨著半導體晶片的封裝技術愈趨進步,電子產品的尺寸愈趨輕薄短小,及高效能晶片的需求隨之上升,又高效能晶片的輸入/輸出(I/O)端的數量也變得愈來愈多,造成輸入/輸出(I/O)端之間的間距愈來愈小,亦即金屬凸塊也必須隨之縮小,而晶片接合(die bonding)的困難度也愈來愈高。As the packaging technology of semiconductor wafers has advanced, the size of electronic products has become thinner and lighter, and the demand for high-performance chips has increased. The number of input/output (I/O) terminals of high-efficiency chips has also become more and more popular. The more the spacing between the input/output (I/O) terminals, the smaller the metal bumps have to be, and the more difficult the die bonding is.

請參閱第1A、1B與1B’圖,係習知晶片接合之作法的剖視圖,其中,第1B’圖係為第1B圖的另一情況。Referring to Figures 1A, 1B and 1B', there is shown a cross-sectional view of a conventional wafer bonding process, wherein the 1B' diagram is another example of Figure 1B.

如第1A圖所示,提供高效能之第一晶片11與第二晶片12,其表面分別具有複數第一電性接點111與第二電性接點121,且各該第二電性接點121上係形成有金屬凸塊13。As shown in FIG. 1A, the first wafer 11 and the second wafer 12 are provided with high efficiency, and the surface has a plurality of first electrical contacts 111 and second electrical contacts 121, respectively, and each of the second electrical contacts A metal bump 13 is formed on the dot 121.

如第1B與1B’圖所示,開始進行晶片接合製程,即以該金屬凸塊13對應接合於該第二電性接點121,但由於該第一電性接點111與第二電性接點121之間的間距狹小,因此即使對位上僅有些許偏差,即有可能形成假銲點或是銲點受到應力集中的影響而斷裂,引起信賴性(reliability)問題,如第1B圖所示;或者,銲點錯位,而造成錯誤的接合結果,如第1B’圖所示。As shown in FIGS. 1B and 1B', the wafer bonding process is started, that is, the metal bumps 13 are correspondingly bonded to the second electrical contacts 121, but the first electrical contacts 111 and the second electrical regions are The spacing between the contacts 121 is narrow, so even if there is only a slight deviation in the alignment, it is possible to form a dummy solder joint or the solder joint is broken by the stress concentration, causing a problem of reliability, such as FIG. 1B. As shown; or, the solder joints are misaligned, resulting in erroneous bonding results, as shown in Figure 1B'.

因此,如何避免上述習知技術中之種種問題,俾解決晶片接合時的對位問題,進而提升封裝結構的信賴性,實已成為目前亟欲解決的課題。Therefore, how to avoid the various problems in the above-mentioned prior art, to solve the alignment problem at the time of wafer bonding, and to improve the reliability of the package structure has become a problem to be solved at present.

有鑒於上述習知技術之缺失,本發明提供一種封裝結構,係包括:第一基板,係具有複數第一銲墊;第二基板,係具有複數第二銲墊;以及第一導電元件,係對應連接各該第二銲墊與各該第一銲墊,且該第一導電元件的平面投影寬度小於該第一銲墊的平面投影寬度。In view of the above-mentioned prior art, the present invention provides a package structure comprising: a first substrate having a plurality of first pads; a second substrate having a plurality of second pads; and a first conductive element Correspondingly connecting each of the second pads and each of the first pads, and a planar projection width of the first conductive element is smaller than a planar projection width of the first pad.

本發明復提供另一種封裝結構,係包括:第一基板,係具有複數第一銲墊及複數第一電性接點;第二基板,係具有複數第二銲墊及複數第二電性接點;第一導電元件,係對應連接各該第二銲墊與各該第一銲墊;以及第二導電元件,係對應連接各該第一電性接點與各該第二電性接點,其中,該第一導電元件係大於第二導電元件。The present invention further provides another package structure, comprising: a first substrate having a plurality of first pads and a plurality of first electrical contacts; and a second substrate having a plurality of second pads and a plurality of second electrical contacts a first conductive element correspondingly connecting each of the second pads and each of the first pads; and a second conductive element correspondingly connecting the first electrical contacts and each of the second electrical contacts Wherein the first conductive element is greater than the second conductive element.

本發明復提供一種封裝結構之製法,係包括:提供一具有複數第一銲墊的第一基板與具有複數第二銲墊的第二基板,於各該第二銲墊上具有第一導電元件,且該第一導電元件的平面投影寬度小於該第一銲墊的平面投影寬度;以及令各該第二銲墊藉由該第一導電元件對應電性連接各該第一銲墊。The invention provides a method for manufacturing a package structure, comprising: providing a first substrate having a plurality of first pads and a second substrate having a plurality of second pads, wherein each of the second pads has a first conductive element; The planar projection width of the first conductive component is smaller than the planar projection width of the first bonding pad; and the second bonding pads are electrically connected to the first bonding pads by the first conductive component.

本發明復提供另一種封裝結構之製法,係包括:提供一具有複數第一銲墊及第一電性接點的第一基板與具有複數第二銲墊及第二電性接點的第二基板,且於各該第二銲墊上具有第一導電元件,各該第一電性接點或第二電性接點上具有第二導電元件;連接該第一基板與第二基板,僅使該第二銲墊上之第一導電元件接觸該第一銲墊;回銲該第一導電元件,使該第一導電元件連接該第一銲墊,藉由該第一導電元件提供一拉力,使該第一基板與第二基板相對地移動;以及藉由該第二導電元件連接該第一電性接點與第二電性接點,以使該第一基板電性連接至該第二基板。The invention provides a method for fabricating another package structure, comprising: providing a first substrate having a plurality of first pads and a first electrical contact; and a second substrate having a plurality of second pads and a second electrical contact a substrate, and each of the second pads has a first conductive element, each of the first electrical contacts or the second electrical contacts has a second conductive element; connecting the first substrate and the second substrate, only The first conductive element on the second bonding pad contacts the first bonding pad; reflowing the first conductive element to connect the first conductive element to the first bonding pad, and the first conductive element provides a pulling force The first substrate is opposite to the second substrate; and the first electrical contact and the second electrical contact are connected by the second conductive component to electrically connect the first substrate to the second substrate .

由上可知,因為本發明係於待接合之兩基板上巧妙設計銲墊與其對應之導電元件,俾使於合理對位偏離範圍內,藉由該導電元件與銲墊的作用力而自動對位與校正位置,減少接合對位之偏移,並增進封裝結構的可靠度,進而可利用低精度的接合機台實現高精度的接合,以減少設備成本的支出。It can be seen from the above that, because the invention is skillfully designed on the two substrates to be joined, the solder pads and their corresponding conductive elements are designed to be automatically aligned by the force of the conductive elements and the pads within a reasonable deviation range. By correcting the position, reducing the offset of the joint alignment, and improving the reliability of the package structure, high-precision bonding can be realized by using a low-precision bonding machine to reduce the cost of equipment.

以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「平面」、「凸」、「頂」、「凹」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "flat", "convex", "top", "concave" and "one" as used in this specification are for convenience only and are not intended to be limiting. The scope of the invention can be implemented, and the change or adjustment of the relative relationship is also considered to be within the scope of the invention.

請參閱第2A至2D圖,係本發明之封裝結構及其製法的剖視圖,其中,第2A’至2D’圖分別係第2A至2D圖的局部俯視圖,第2A”圖係第2A圖之第一基板的俯視圖,第2A-1、2A-2、2A-3與2A-4圖係第2A圖的不同實施態樣。2A to 2D are cross-sectional views showing a package structure and a method of manufacturing the same according to the present invention, wherein the 2A' to 2D' drawings are partial top views of the 2A to 2D drawings, respectively, and the 2A" figure is the 2Ath drawing. A top view of a substrate, 2A-1, 2A-2, 2A-3, and 2A-4 are different embodiments of FIG. 2A.

首先,如第2A與2A’圖所示,提供第一基板21與第二基板22,該第一基板21係具有複數第一銲墊211、複數第一電性接點212及形成於該第一電性接點212上的第二導電元件24,該第二基板22係具有複數第二銲墊221、複數第二電性接點222及形成於該第二銲墊221上之第一導電元件23,且該第一導電元件23的連接該第二銲墊221部份之平面投影寬度D小於該第一銲墊211的平面投影寬度L,且該第一導電元件23之平面投影寬度大於該第二導電元件24之平面投影寬度;其中,該第一導電元件23與第二導電元件24可為銲球,該第一基板21與第二基板22可各別為半導體晶圓、半導體晶片、玻璃基板、矽基板或封裝基板,該第一導電元件23之寬度係較佳大於該第二導電元件24之寬度,該第一導電元件23之熔點係較佳大於或等於該第二導電元件24之熔點。First, as shown in FIGS. 2A and 2A', a first substrate 21 and a second substrate 22 are provided. The first substrate 21 has a plurality of first pads 211, a plurality of first electrical contacts 212, and is formed in the first substrate a second conductive member 24 on the second substrate 22, the second substrate 22 has a plurality of second pads 221, a plurality of second electrical contacts 222, and a first conductive layer formed on the second pad 221 The planar projection width D of the portion of the first conductive member 23 connected to the second pad 221 is smaller than the planar projection width L of the first pad 211, and the planar projection width of the first conductive member 23 is greater than The planar projection width of the second conductive component 24; wherein the first conductive component 23 and the second conductive component 24 can be solder balls, and the first substrate 21 and the second substrate 22 can be semiconductor wafers and semiconductor wafers, respectively. The width of the first conductive element 23 is preferably greater than the width of the second conductive element 24, and the melting point of the first conductive element 23 is preferably greater than or equal to the second conductive element. The melting point of 24.

於本實施例中,該第一導電元件23與第二導電元件24為無鉛銲錫;於其他實施例中,該第一導電元件23可以是無鉛銲錫,該第二導電元件24可以是具有一層無鉛銲錫層與其上之一層銅導電柱之金屬凸塊,且該第二導電元件24之無鉛銲錫層之熔點較佳者係大於或等於第一導電元件23之熔點;接著,進行初步的對位步驟,該第一導電元件23接觸到該第一基板21之第一銲墊211,於此情況下,該第一導電元件23並未經過回銲之步驟,此時當機台之精度較低時,會造成中間之該第二導電元件24無法準確地對準該第二電性接點222,此時該第一基板21與第二基板22並無法完全對齊。In this embodiment, the first conductive element 23 and the second conductive element 24 are lead-free solder; in other embodiments, the first conductive element 23 may be lead-free solder, and the second conductive element 24 may have a layer of lead-free solder. a solder bump and a metal bump of a layer of copper conductive pillars thereon, and a melting point of the lead-free solder layer of the second conductive component 24 is preferably greater than or equal to a melting point of the first conductive component 23; and then, a preliminary alignment step is performed The first conductive element 23 contacts the first pad 211 of the first substrate 21. In this case, the first conductive element 23 does not undergo a reflow process, when the precision of the machine is low. The second conductive element 24 in the middle cannot be accurately aligned with the second electrical contact 222. At this time, the first substrate 21 and the second substrate 22 are not completely aligned.

第2A’圖所示係為第2A圖於該第一銲墊211區域的俯視圖,該第一銲墊211上更具有一定位標記2110。於本實施例中,該第一銲墊211為金屬材質,可以為鎳、鎳/金、銅、鋁、錫/銀、錫/鉛、錫/銀/銅等單層或多層金屬合金結構,該第一銲墊211可以是經由電鍍、無電電鍍、濺鍍、印刷或其他相似之方式形成,該定位標記2110為設置於該第一銲墊211中的十字形之缺口,該定位標記2110亦可以是介電層材質或是與該第一銲墊211不同材質之金屬層,以作為該第一基板21與第二基板22接合時之定位使用。另外,如第2A”圖所示,係為該第一基板21的俯視圖,該第一銲墊211係可分佈於該第一基板21的角落處,於本實施例中,該第一銲墊211分別設置該第一基板21之四角落處,以於該第一基板21與第二基板22發生X-Y軸之偏移或角度旋轉偏移時,可以進行後續之自動對位而提供該第一基板21與第二基板22相對位置偏移的回正,且該等第二導電元件24係可矩陣排列於該第一基板21的中心處。於其他實施例中(未圖示),該第一基板21與第二基板22係為晶圓,具有複數個晶片單元設至於晶片設置區中,而銲墊係設置於晶圓之非晶片設置區。2A' is a plan view of the second pad 211 in the region of the first pad 211, and the first pad 211 further has a positioning mark 2110. In the embodiment, the first pad 211 is made of a metal material, and may be a single layer or a plurality of metal alloy structures such as nickel, nickel/gold, copper, aluminum, tin/silver, tin/lead, tin/silver/copper. The first pad 211 may be formed by electroplating, electroless plating, sputtering, printing, or the like. The positioning mark 2110 is a cross-shaped notch disposed in the first pad 211, and the positioning mark 2110 is also It may be a dielectric layer material or a metal layer different from the first pad 211 for use as a positioning when the first substrate 21 and the second substrate 22 are joined. In addition, as shown in FIG. 2A, the first substrate 21 is a top view of the first substrate 21, and the first pad 211 is distributed at a corner of the first substrate 21. In this embodiment, the first pad 211 is respectively disposed at four corners of the first substrate 21, so that when the first substrate 21 and the second substrate 22 are offset by an XY axis or an angular rotation offset, the subsequent automatic alignment can be performed to provide the first The substrate 21 and the second substrate 22 are offset from each other, and the second conductive elements 24 are matrix-arranged at the center of the first substrate 21. In other embodiments (not shown), the first A substrate 21 and a second substrate 22 are wafers, and a plurality of wafer units are disposed in the wafer setting area, and the pads are disposed in the non-wafer setting area of the wafer.

接著,如第2B至2D與2B’至2D’圖所示,藉由回銲或熱處理以熔化該第一導電元件23,該第一導電元件23逐漸熔融成液體後,並連接至該第一銲墊211時,因該第一導電元件23上與第一銲墊211之潤濕(wetting)而使該第一導電元件23逐漸覆蓋整個該第一銲墊211,如第2C圖所示。之後,如第2D圖所示,該第一導電元件23全部覆蓋於該第一銲墊211,由於該第一導電元件23的內聚力,因而提供一拉力,同時帶動該第一基板21與第二基板22水平相對移動直至對齊彼此,藉由此拉力將原本該第一基板21與第二基板22的X-Y軸偏移或角度旋轉偏移之位置拉回至該第二導電元件24能到達預定接合之位置,且該第一導電元件23的高度因熔化而降低,使得該第二導電元件24對齊並對應連接該第二電性接點222,最終完成兩基板的自對準(self-align)與接合,而成為一封裝結構。Next, as shown in FIGS. 2B to 2D and 2B' to 2D', the first conductive member 23 is melted by reflow or heat treatment, and the first conductive member 23 is gradually melted into a liquid, and is connected to the first When the pad 211 is soldered, the first conductive element 23 gradually covers the entire first pad 211 due to the wetting of the first conductive element 23 and the first pad 211, as shown in FIG. 2C. Then, as shown in FIG. 2D, the first conductive element 23 entirely covers the first pad 211. Due to the cohesive force of the first conductive element 23, a pulling force is provided, and the first substrate 21 and the second substrate are driven. The substrates 22 are horizontally moved relative to each other until they are aligned with each other, thereby pulling back the position where the XY axis offset or the angular rotation of the first substrate 21 and the second substrate 22 are originally pulled back to the second conductive element 24 to reach a predetermined joint. The position of the first conductive element 23 is lowered by melting, so that the second conductive element 24 is aligned and correspondingly connected to the second electrical contact 222, thereby completing the self-alignment of the two substrates. With the joint, it becomes a package structure.

要注意的是,本發明之實施除了第2A圖之態樣外,亦可變換該第一導電元件23與第二導電元件24的位置,如第2A-1圖所示;或者,該第二基板22上可具有複數微機電(MEMS)元件25,如第2A-2圖所示;或者,該第一基板21可形成有複數貫穿通孔210與複數凸部213,令各該第一銲墊211位於各該凸部213之頂面上,且該第一基板21上並設有封蓋該通孔210並電性連接第一基板21的半導體晶片26,且該第二基板22係為透明材質所構成,如第2A-3圖所示;或者,該第一基板21可形成有複數凹部214,以令各該第一銲墊211設置於各該凹部214上,因此在該第一基板21與第二基板22對位後,且該第一導電元件23的高度因熔化而降低,回銲後之該第一基板21與第二基板22間之高度與原先未進行回銲之高度相比,下沉約8%~75%,使得該第二導電元件24對齊並對應連接該第二電性接點222,最終完成兩基板的自對準(self-align)與接合,該凹部結構能增加自對準之準確性以及降低整體封裝結構之體積,如第2A-4圖所示。It is to be noted that the implementation of the present invention may also change the position of the first conductive element 23 and the second conductive element 24, as shown in FIG. 2A-1, in addition to the aspect of FIG. 2A; or, the second The substrate 22 may have a plurality of micro-electromechanical (MEMS) devices 25 as shown in FIG. 2A-2. Alternatively, the first substrate 21 may be formed with a plurality of through vias 210 and a plurality of protrusions 213 for each of the first pads. The pad 211 is located on the top surface of each of the protrusions 213, and the first substrate 21 is provided with a semiconductor wafer 26 that covers the through hole 210 and is electrically connected to the first substrate 21, and the second substrate 22 is The transparent material is formed as shown in FIG. 2A-3; or the first substrate 21 may be formed with a plurality of recesses 214, so that the first pads 211 are disposed on the recesses 214, and thus the first After the substrate 21 and the second substrate 22 are aligned, the height of the first conductive element 23 is lowered by melting, and the height between the first substrate 21 and the second substrate 22 after reflowing is not the height of the original reflow soldering. In contrast, the sinking is about 8% to 75%, so that the second conductive element 24 is aligned and correspondingly connected to the second electrical contact 222, and finally two Self-alignment plate (self-align) engages with the recessed portion to increase the accuracy of the self-aligned structure and reduce the overall volume of the package, as shown on FIG. 2A-4.

此外,第2A’圖所示者係該第一銲墊211與第一導電元件23處的俯視圖,此處顯示該第一銲墊211中復包括一定位標記2110,該定位標記2110係可呈十字形的缺口,但該定位標記2110亦可呈L字形、圓形、矩形或五角形的缺口,如第3A至3D圖所示;又該第二銲墊221係可呈矩形、八角形、圓形或長條膠囊形,如第4A至4D圖所示,當然,該第二銲墊221亦可呈橢圓形(未圖示此情況)。In addition, FIG. 2A is a top view of the first pad 211 and the first conductive element 23, where the first pad 211 is further included with a positioning mark 2110, and the positioning mark 2110 can be presented. a cross-shaped notch, but the positioning mark 2110 may also have an L-shaped, circular, rectangular or pentagonal notch, as shown in FIGS. 3A to 3D; and the second bonding pad 221 may be rectangular, octagonal, or circular. The shape of the shape or the length of the capsule is as shown in Figures 4A to 4D. Of course, the second pad 221 may also have an elliptical shape (not shown).

綜上所述,相較於習知技術,由於本發明係於待接合之兩基板上巧妙設計銲墊與其對應之導電元件,俾使於合理對位偏離範圍內,藉由該導電元件與銲墊的作用力而自動對位與校正位置(進行平移或旋轉),減少接合對位之偏移,並增進封裝結構的可靠度,進而可利用低精度的接合機台實現高精度的接合,以減少設備成本的支出。In summary, the present invention is based on the two substrates to be joined, and the solder pads and their corresponding conductive elements are skillfully designed to be within a reasonable range of deviation, by the conductive elements and soldering. The force of the pad automatically aligns and corrects the position (translating or rotating), reduces the offset of the joint alignment, and improves the reliability of the package structure, thereby enabling high-precision bonding using a low-precision bonding machine. Reduce equipment costs.

上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

11...第一晶片11. . . First wafer

111...第一電性接點111. . . First electrical contact

12...第二晶片12. . . Second chip

121...第二電性接點121. . . Second electrical contact

13...金屬凸塊13. . . Metal bump

21...第一基板twenty one. . . First substrate

210...通孔210. . . Through hole

211‧‧‧第一銲墊211‧‧‧First pad

2110‧‧‧定位標記2110‧‧‧ Positioning Mark

213‧‧‧凸部213‧‧‧ convex

214‧‧‧凹部214‧‧‧ recess

212‧‧‧第一電性接點212‧‧‧First electrical contact

22‧‧‧第二基板22‧‧‧second substrate

221‧‧‧第二銲墊221‧‧‧Second pad

222‧‧‧第二電性接點222‧‧‧Second electrical contacts

23‧‧‧第一導電元件23‧‧‧First conductive element

24‧‧‧第二導電元件24‧‧‧Second conductive element

25‧‧‧微機電元件25‧‧‧Microelectromechanical components

26‧‧‧半導體晶片26‧‧‧Semiconductor wafer

D,L‧‧‧平面投影寬度D, L‧‧‧ Planar projection width

第1A、1B與1B’圖係習知晶片接合之作法的剖視圖,其中,第1B’圖係為第1B圖的另一情況;1A, 1B, and 1B' are cross-sectional views showing a conventional wafer bonding method, wherein the 1B' diagram is another example of FIG. 1B;

第2A至2D圖係本發明之封裝結構及其製法的剖視圖,其中,第2A’至2D’圖分別係第2A至2D圖的局部俯視圖,第2A”圖係第2A圖之第一基板的俯視圖,第2A-1、2A-2、2A-3與2A-4圖係第2A圖的不同實施態樣;2A to 2D are cross-sectional views showing a package structure and a method of manufacturing the same according to the present invention, wherein the 2A' to 2D' drawings are partial top views of the 2A to 2D drawings, respectively, and the 2A" figure is the first substrate of the 2Ath drawing. In the top view, the 2A-1, 2A-2, 2A-3, and 2A-4 diagrams are different embodiments of FIG. 2A;

第3A至3D圖係本發明之封裝結構之第一銲墊的不同實施態樣;以及3A to 3D are different embodiments of the first pad of the package structure of the present invention;

第4A至4D圖係本發明之封裝結構之第二銲墊的不同實施態樣。4A through 4D are different embodiments of the second pad of the package structure of the present invention.

21...第一基板twenty one. . . First substrate

211...第一銲墊211. . . First pad

2110...定位標記2110. . . Positioning mark

212...第一電性接點212. . . First electrical contact

22...第二基板twenty two. . . Second substrate

221...第二銲墊221. . . Second pad

222...第二電性接點222. . . Second electrical contact

23...第一導電元件twenty three. . . First conductive element

24...第二導電元件twenty four. . . Second conductive element

Claims (25)

一種封裝結構,係包括:第一基板,係具有複數第一銲墊;第二基板,係具有複數第二銲墊及微機電元件;以及第一導電元件,係對應連接各該第二銲墊與各該第一銲墊,且該第一導電元件的平面投影寬度小於該第一銲墊的平面投影寬度。 A package structure includes: a first substrate having a plurality of first pads; a second substrate having a plurality of second pads and microelectromechanical components; and a first conductive component correspondingly connecting the second pads And each of the first pads, and a planar projection width of the first conductive element is smaller than a planar projection width of the first pad. 一種封裝結構,係包括:第一基板,係具有複數第一銲墊及複數第一電性接點;第二基板,係具有複數第二銲墊及複數第二電性接點;第一導電元件,係對應連接各該第二銲墊與各該第一銲墊;以及第二導電元件,係對應連接各該第一電性接點與各該第二電性接點,其中,該第一導電元件係大於第二導電元件,且該第二導電元件之熔點大於該第一導電元件之熔點。 A package structure includes: a first substrate having a plurality of first pads and a plurality of first electrical contacts; and a second substrate having a plurality of second pads and a plurality of second electrical contacts; the first conductive And the second conductive pad is connected to each of the first electrical contact and each of the second electrical contacts, wherein the first A conductive element is greater than the second conductive element, and the second conductive element has a melting point greater than a melting point of the first conductive element. 如申請專利範圍第1項所述之封裝結構,其中,該第一基板上並具有複數第一電性接點及形成於該第一電性接點上的第二導電元件,該第二基板上並具有複數第二電性接點,使各該第一電性接點係藉由該第二導電元件對應電性連接各該第二電性接點。 The package structure of claim 1, wherein the first substrate has a plurality of first electrical contacts and a second conductive component formed on the first electrical contact, the second substrate And having a plurality of second electrical contacts, wherein each of the first electrical contacts is electrically connected to each of the second electrical contacts by the second conductive component. 如申請專利範圍第1項所述之封裝結構,其中,該第一基板上形成有複數第一電性接點,該第二基板上並形成有複數第二電性接點及形成於該第二電性接點上的第二導電元件,使各該第二電性接點係藉由該第二導電元件對應電性連接各該第一電性接點。 The package structure of claim 1, wherein the first substrate is formed with a plurality of first electrical contacts, and the second substrate is formed with a plurality of second electrical contacts and formed on the second substrate The second conductive component on the two electrical contacts is such that each of the second electrical contacts is electrically connected to each of the first electrical contacts by the second conductive component. 如申請專利範圍第2項所述之封裝結構,其中,該第一導電元件的平面投影寬度小於該第一銲墊的平面投影寬度。 The package structure of claim 2, wherein the planar projection width of the first conductive element is smaller than a planar projection width of the first pad. 如申請專利範圍第1或2項所述之封裝結構,其中,該第一導電元件係為銲塊。 The package structure of claim 1 or 2, wherein the first conductive element is a solder bump. 如申請專利範圍第2、3或4項所述之封裝結構,其中,該第二導電元件係為銲塊。 The package structure of claim 2, 3 or 4, wherein the second conductive element is a solder bump. 如申請專利範圍第1或2項所述之封裝結構,其中,該第一基板係為半導體晶圓、半導體晶片、玻璃基板或封裝基板,且該第二基板係為半導體晶片或封裝基板。 The package structure according to claim 1 or 2, wherein the first substrate is a semiconductor wafer, a semiconductor wafer, a glass substrate or a package substrate, and the second substrate is a semiconductor wafer or a package substrate. 如申請專利範圍第1或2項所述之封裝結構,其中,該第二銲墊係呈矩形、八角形、圓形、長條膠囊形或橢圓形。 The package structure of claim 1 or 2, wherein the second pad is rectangular, octagonal, circular, elongated, or elliptical. 如申請專利範圍第1或2項所述之封裝結構,其中,該第一銲墊中復包括一定位標記。 The package structure of claim 1 or 2, wherein the first pad further comprises a positioning mark. 如申請專利範圍第10項所述之封裝結構,其中,該定位標記係呈L字形、圓形、多邊形或十字形的缺口。 The package structure of claim 10, wherein the positioning mark is an L-shaped, circular, polygonal or cross-shaped notch. 如申請專利範圍第1或2項所述之封裝結構,其中, 該第一基板係形成有複數貫穿通孔與複數凸部,令各該第一銲墊位於各該凸部之頂面上,且該第一基板上並設有封蓋該通孔並電性連接第一基板的半導體晶片。 The package structure as described in claim 1 or 2, wherein The first substrate is formed with a plurality of through holes and a plurality of protrusions, wherein each of the first pads is located on a top surface of each of the protrusions, and the first substrate is provided with a cover and electrically connected A semiconductor wafer connected to the first substrate. 如申請專利範圍第1或2項所述之封裝結構,其中,該第一基板係形成有複數凹部,以令各該第一銲墊設置於各該凹部上。 The package structure of claim 1 or 2, wherein the first substrate is formed with a plurality of recesses so that each of the first pads is disposed on each of the recesses. 一種封裝結構之製法,係包括:提供一具有複數第一銲墊的第一基板與具有複數第二銲墊及微機電元件的第二基板,於各該第二銲墊上具有第一導電元件,且該第一導電元件的平面投影寬度小於該第一銲墊的平面投影寬度;以及令各該第二銲墊藉由該第一導電元件對應電性連接各該第一銲墊。 A method for fabricating a package structure includes: providing a first substrate having a plurality of first pads and a second substrate having a plurality of second pads and microelectromechanical elements, wherein each of the second pads has a first conductive element; The planar projection width of the first conductive component is smaller than the planar projection width of the first bonding pad; and the second bonding pads are electrically connected to the first bonding pads by the first conductive component. 如申請專利範圍第14項所述之封裝結構之製法,其中,該第一導電元件係為銲球。 The method of fabricating a package structure according to claim 14, wherein the first conductive element is a solder ball. 如申請專利範圍第14項所述之封裝結構之製法,其中,該第一基板上並具有複數第一電性接點及形成於該第一電性接點上的第二導電元件,該第二基板上並具有複數第二電性接點,使各該第一電性接點係藉由該第二導電元件對應電性連接各該第二電性接點。 The method of manufacturing the package structure of claim 14, wherein the first substrate has a plurality of first electrical contacts and a second conductive component formed on the first electrical contact, the first The second substrate has a plurality of second electrical contacts, and the first electrical contacts are electrically connected to the second electrical contacts by the second conductive elements. 如申請專利範圍第14項所述之封裝結構之製法,其中,該第一基板上形成有複數第一電性接點,該第二基板上並形成有複數第二電性接點及形成於該第二電 性接點上的第二導電元件,使各該第二電性接點係藉由該第二導電元件對應電性連接各該第一電性接點。 The method of manufacturing a package structure according to claim 14, wherein the first substrate is formed with a plurality of first electrical contacts, and the second substrate is formed with a plurality of second electrical contacts and formed on the second substrate The second electricity The second conductive component on the contact is electrically connected to each of the first electrical contacts by the second conductive component. 如申請專利範圍第16或17項所述之封裝結構之製法,其中,該第二導電元件係為銲球。 The method of fabricating a package structure according to claim 16 or 17, wherein the second conductive element is a solder ball. 如申請專利範圍第14項所述之封裝結構之製法,其中,該第二銲墊係呈矩形、八角形、圓形、長條膠囊形或橢圓形。 The method of manufacturing a package structure according to claim 14, wherein the second pad is rectangular, octagonal, circular, elongated, or elliptical. 如申請專利範圍第14項所述之封裝結構之製法,其中,該第一銲墊中復包括一定位標記。 The method of manufacturing a package structure according to claim 14, wherein the first pad further comprises an alignment mark. 如申請專利範圍第20項所述之封裝結構之製法,其中,該定位標記係呈L字形、圓形、多邊形或十字形的缺口。 The method of manufacturing a package structure according to claim 20, wherein the positioning mark is an L-shaped, circular, polygonal or cross-shaped notch. 一種封裝結構之製法,係包括:提供一具有複數第一銲墊及第一電性接點的第一基板與具有複數第二銲墊及第二電性接點的第二基板,且於各該第二銲墊上具有第一導電元件,各該第一電性接點或第二電性接點上具有第二導電元件,且該第二導電元件之熔點大於該第一導電元件之熔點;連接該第一基板與第二基板,僅使該第二銲墊上之第一導電元件接觸該第一銲墊;回銲該第一導電元件,使該第一導電元件連接該第一銲墊,藉由該第一導電元件提供一拉力,使該第一基板與第二基板相對地移動;以及藉由該第二導電元件連接該第一電性接點與第二 電性接點,以使該第一基板電性連接至該第二基板。 A method for fabricating a package structure includes: providing a first substrate having a plurality of first pads and first electrical contacts; and a second substrate having a plurality of second pads and second electrical contacts, and The second conductive pad has a first conductive element, and each of the first electrical contact or the second electrical contact has a second conductive component, and a melting point of the second conductive component is greater than a melting point of the first conductive component; Connecting the first substrate and the second substrate, only the first conductive element on the second bonding pad contacts the first bonding pad; reflowing the first conductive element to connect the first conductive element to the first bonding pad, Providing a pulling force to move the first substrate and the second substrate relative to each other; and connecting the first electrical contact and the second by the second conductive element Electrical contacts are electrically connected to the second substrate. 如申請專利範圍第22項所述之封裝結構之製法,其中,且該第一導電元件的平面投影寬度小於該第一銲墊的平面投影寬度。 The method of fabricating a package structure according to claim 22, wherein a planar projection width of the first conductive element is smaller than a planar projection width of the first pad. 如申請專利範圍第14或22項所述之封裝結構之製法,其中,該第一基板係形成有複數凹部,以令各該第一銲墊設置於各該凹部上。 The method of fabricating a package structure according to claim 14 or claim 22, wherein the first substrate is formed with a plurality of recesses so that each of the first pads is disposed on each of the recesses. 如申請專利範圍第22項所述之封裝結構之製法,其中,該第一導電元件之平面投影寬度大於該第二導電元件之平面投影寬度。The method of fabricating a package structure according to claim 22, wherein a plane projection width of the first conductive element is greater than a plane projection width of the second conductive element.
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