TWI609471B - Semiconductor packaging assembly and its fabricating method - Google Patents
Semiconductor packaging assembly and its fabricating method Download PDFInfo
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- TWI609471B TWI609471B TW105141612A TW105141612A TWI609471B TW I609471 B TWI609471 B TW I609471B TW 105141612 A TW105141612 A TW 105141612A TW 105141612 A TW105141612 A TW 105141612A TW I609471 B TWI609471 B TW I609471B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明係有關於半導體晶片封裝領域，特別係有關於一種半導體封裝組合及其製造方法。 The present invention relates to the field of semiconductor chip packaging, and more particularly to a semiconductor package combination and a method of fabricating the same.
傳統地，複數個半導體封裝構造係以側對側(side-by-side)並排接合於一電路板。為了在電路板上接合更多數量的半導體封裝構造，有人提出封裝堆疊(Package-On-Package,POP)技術，即將複數個半導體封裝構造逐一往上縱向堆疊在一電路板，以達到立體封裝(3D packaging)形態。 Traditionally, a plurality of semiconductor package structures are side-by-side bonded to a circuit board side by side. In order to bond a larger number of semiconductor package structures on a circuit board, a package-on-package (POP) technology has been proposed, in which a plurality of semiconductor package structures are vertically stacked one by one on a circuit board to achieve a three-dimensional package ( 3D packaging) form.
早期的封裝堆疊組合中，頂層半導體封裝構造與底層半導體封裝構造的電性耦合係經由一中介基板(interposer substrate)，故有封裝堆疊成本高與封裝堆疊製程繁瑣之問題。在近期的封裝堆疊組合中，底層半導體封裝構造內直接設置凸塊或銲球等中介導體，以減少一次的中介基板之接合步驟。然而，在中介導體的已知形成過程中，中介導體係先被模封膠體所密封，之後再利用雷射鑽孔或是圖案化孔蝕刻方式以露出中介導體的接合表面，不論是雷射鑽孔的逐一鑽孔操作或是包含於圖案化孔蝕刻的曝光顯影都會增加封裝堆疊成本。此外，中介導體的接合表 面也可能遭受到孔形成污染的膠體殘留，雷射鑽孔的能量過大也會造成中介導體的損傷與變形，皆不利於中介導體對頂層半導體封裝構造的接合。 In the early package stack assembly, the electrical coupling between the top-level semiconductor package structure and the underlying semiconductor package structure is via an interposer substrate, so that the cost of the package stack is high and the package stack process is cumbersome. In a recent package stack assembly, an intermediate conductor such as a bump or a solder ball is directly disposed in the underlying semiconductor package structure to reduce the bonding step of the interposer at one time. However, in the known formation process of the intermediate conductor, the intermediate guiding system is first sealed by the molding compound, and then the laser drilling or patterning hole etching is used to expose the bonding surface of the intermediate conductor, whether it is a laser drill or not. Hole-by-hole drilling operations or exposure developments included in patterned hole etching increase the cost of package stacking. In addition, the bonding table of the intermediate conductor The surface may also suffer from colloidal residue that is contaminated by the holes. Excessive energy of the laser drilling hole may also cause damage and deformation of the intermediate conductor, which is not conducive to the bonding of the intermediate conductor to the top semiconductor package structure.
為了解決上述之問題，本發明之主要目的係在於提供一種半導體封裝組合及其製造方法，用以簡化封裝堆疊製程。 In order to solve the above problems, the main object of the present invention is to provide a semiconductor package assembly and a method of fabricating the same to simplify the package stacking process.
本發明之次一目的係在於提供一種半導體封裝組合及其製造方法，用以消除被模封中介導體的孔形成污染、損傷與變形，加強了頂層半導體封裝構造與底層半導體封裝構造的電性耦合強度，進而實現了先封裝堆疊再表面接合至電路板之封裝堆疊製程。 A second object of the present invention is to provide a semiconductor package assembly and a manufacturing method thereof for eliminating contamination, damage and deformation of a hole of a molded intermediate conductor, and enhancing electrical coupling between a top semiconductor package structure and an underlying semiconductor package structure. The strength, in turn, enables a package stacking process in which the package is first packaged and then surface bonded to the board.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種半導體封裝組合，包含一第一基板、一第一晶片、複數個中介導體以及一第一封膠體。該第一晶片係設置於該第一基板上，該第一晶片係具有一面向該第一基板之主動面以及一相對遠離該主動面之背面。該些中介導體係電耦合至該第一基板並配置在該第一晶片之周邊，該些中介導體之一第一設置高度係不小於該第一晶片之一第二設置高度。該第一封膠體係形成於該第一基板上，用以至少密封該第一晶片之局部與每一之該些中介導體之局部。其中，經由只蝕刻該第一封膠體之化學閃蝕方式，藉以形成該第一封膠體之一表面，其係顯露每一之該些中介導體之殘留部位與該第一晶片之該背面。 The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a semiconductor package assembly comprising a first substrate, a first wafer, a plurality of intermediate conductors and a first encapsulant. The first wafer is disposed on the first substrate, and the first wafer has an active surface facing the first substrate and a back surface opposite to the active surface. The interposer system is electrically coupled to the first substrate and disposed at a periphery of the first wafer, and a first set height of the one of the interposing conductors is not less than a second set height of one of the first wafers. The first encapsulation system is formed on the first substrate to seal at least a portion of the first wafer and a portion of each of the interposer conductors. The surface of the first encapsulant is formed by the chemical flashing method of etching only the first encapsulant, which exposes the residual portion of each of the interposer and the back surface of the first wafer.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。 The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述半導體封裝組合中，具體地可另包含複數個外接端子，係設置於該第一基板之一底面。 In the foregoing semiconductor package assembly, specifically, a plurality of external terminals may be further disposed on a bottom surface of the first substrate.
在前述半導體封裝組合中，較佳地該第一封膠體由該第一基板至該表面之厚度係不大於該些中介導體之該第一設置高度，亦不大於該第一晶片之該第二設置高度，以確保該些中介導體與該第一晶片之局部顯露。 Preferably, in the foregoing semiconductor package assembly, the thickness of the first encapsulant from the first substrate to the surface is not greater than the first set height of the intermediate conductors, and is not greater than the second height of the first wafer. The height is set to ensure that the intermediate conductors and portions of the first wafer are exposed.
在前述半導體封裝組合中，具體地另包含複數個覆晶凸塊，其係接合該第一晶片至該第一基板。 In the foregoing semiconductor package assembly, specifically, a plurality of flip chip bumps are further included, which bond the first wafer to the first substrate.
在前述半導體封裝組合中，具體地該些中介導體係包含複數個迴焊固定於該第一基板上之銲球。 In the foregoing semiconductor package combination, specifically, the interposer system includes a plurality of solder balls fixed on the first substrate by reflow soldering.
在前述半導體封裝組合中，具體地可另包含一頂封裝件，係疊置於該第一封膠體上，該頂封裝件係包含一第二晶片以及複數個接合端，其中該些中介導體之該些殘留部位係接合至對應之該些接合端。 In the foregoing semiconductor package assembly, specifically, a top package may be further disposed on the first encapsulant, the top package includes a second wafer and a plurality of bonding ends, wherein the intermediate conductors The residual portions are joined to the corresponding joint ends.
在前述半導體封裝組合中，更具體地該頂封裝件係另包含一第二基板以及一第二封膠體，該第二晶片係設置於該第二基板上，該第二封膠體係形成於該第二基板上，以密封該第二晶片，並且該些接合端係構成於該第二基板之一外表面，該些中介導體係直接焊接於該些接合端。 In the foregoing semiconductor package assembly, more specifically, the top package further includes a second substrate and a second encapsulant, the second wafer is disposed on the second substrate, and the second encapsulation system is formed on the The second substrate is sealed to seal the second wafer, and the bonding ends are formed on an outer surface of the second substrate, and the intermediate guiding systems are directly soldered to the bonding ends.
藉由上述的技術手段，本發明可以達成封裝堆疊製 程的簡化。 By the above technical means, the present invention can achieve package stacking Simplification of the process.
H1‧‧‧第一設置高度 H1‧‧‧ first set height
H2‧‧‧第二設置高度 H2‧‧‧Second setting height
100‧‧‧半導體封裝組合 100‧‧‧Semiconductor package combination
110‧‧‧第一基板 110‧‧‧First substrate
111‧‧‧底面 111‧‧‧ bottom
120‧‧‧第一晶片 120‧‧‧First chip
121‧‧‧主動面 121‧‧‧Active surface
122‧‧‧背面 122‧‧‧Back
130‧‧‧中介導體 130‧‧‧Intermediary conductor
131‧‧‧殘留部位 131‧‧‧Residual parts
140‧‧‧第一封膠體 140‧‧‧First gel
141‧‧‧表面 141‧‧‧ surface
150‧‧‧外接端子 150‧‧‧External terminals
160‧‧‧覆晶凸塊 160‧‧‧Flip-coated bumps
170‧‧‧頂封裝件 170‧‧‧ top package
171‧‧‧第二晶片 171‧‧‧second chip
172‧‧‧接合端 172‧‧‧ joint end
173‧‧‧第二基板 173‧‧‧second substrate
174‧‧‧第二封膠體 174‧‧‧Second seal
175‧‧‧外表面 175‧‧‧ outer surface
176‧‧‧銲線 176‧‧‧welding line
第1圖：依據本發明之一具體實施例，一種半導體封裝組合之截面示意圖。 1 is a cross-sectional view of a semiconductor package assembly in accordance with an embodiment of the present invention.
第2A至2E圖：依據本發明之一具體實施例，繪示該半導體封裝組合之製程中各主要步驟之元件截面圖。 2A to 2E are cross-sectional views showing the main steps of the process of the semiconductor package assembly in accordance with an embodiment of the present invention.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。 The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之一具體實施例，一種半導體封裝組合100舉例說明於第1圖之截面示意圖以及第2A至2E圖繪示其製程中各主要步驟之元件截面圖。一種半導體封裝組合100係包含一第一基板110、一第一晶片120、複數個中介導體130以及一第一封膠體140，以至少構成為封裝堆疊組合之底封裝件。 In accordance with an embodiment of the present invention, a semiconductor package assembly 100 is illustrated in cross-sectional view in FIG. 1 and in FIGS. 2A-2E to illustrate cross-sectional views of elements in various steps of the process. A semiconductor package assembly 100 includes a first substrate 110, a first wafer 120, a plurality of intermediate conductors 130, and a first encapsulant 140 to form at least a bottom package of the package stack assembly.
如第1及2D圖所示，該第一晶片120係設置於該第一基板110上。該第一基板110係為一積體電路載板，具體可為一印 刷電路板、一軟性電路板、一陶瓷線路基板或一導線架；在本實施例中，該第一基板110係為一印刷電路板。該第一晶片120係為一具有積體電路之主動元件，該第一晶片120係具有一面向該第一基板110之主動面121以及一相對遠離該主動面121之背面122，該第一晶片120之積體電路係製作成該主動面121。在本實施例中，具體地另包含複數個覆晶凸塊160，其係接合該第一晶片120至該第一基板110，以達到電性耦合與機械固定。 As shown in FIGS. 1 and 2D, the first wafer 120 is disposed on the first substrate 110. The first substrate 110 is an integrated circuit carrier, and specifically can be a printed The circuit board, a flexible circuit board, a ceramic circuit substrate or a lead frame; in the embodiment, the first substrate 110 is a printed circuit board. The first wafer 120 is an active component having an integrated circuit. The first wafer 120 has an active surface 121 facing the first substrate 110 and a back surface 122 opposite to the active surface 121. The first wafer The integrated circuit of 120 is fabricated as the active surface 121. In this embodiment, a plurality of flip-chip bumps 160 are specifically included to bond the first wafer 120 to the first substrate 110 to achieve electrical coupling and mechanical fixation.
該些中介導體130係電耦合至該第一基板110並配置在該第一晶片120之周邊，該些中介導體130係可為銲球、縱向銲線或柱狀凸塊。在本實施例中，具體地該些中介導體130係包含複數個迴悍固定於該第一基板110上之銲球，故可經由化學閃蝕程度來控制該些中介導體130顯露於該第一封膠體140之顯露表面面積。此外，該些中介導體130之一第一設置高度H1係不小於該第一晶片120之一第二設置高度H2(如第2A圖所示)，用以確保在該第一晶片120之該背面112顯露於該第一封膠體140時，該些中介導體130必然會有顯露表面。 The interposer conductors 130 are electrically coupled to the first substrate 110 and disposed at the periphery of the first wafer 120. The interposer conductors 130 may be solder balls, longitudinal bonding wires or stud bumps. In this embodiment, the intermediate conductors 130 include a plurality of solder balls fixed on the first substrate 110, so that the intermediate conductors 130 can be controlled by the first degree of chemical flashing. The exposed surface area of the encapsulant 140. In addition, a first set height H1 of the one of the intermediate conductors 130 is not less than a second set height H2 of the first wafer 120 (as shown in FIG. 2A) to ensure the back surface of the first wafer 120. When the first encapsulant 140 is exposed, the interposer conductors 130 must have a exposed surface.
該第一封膠體140係形成於該第一基板110上，用以至少密封該第一晶片120之局部與每一之該些中介導體130之局部。該第一封膠體140係具體可為一模封環氧化合物(Epoxy Molding Compound,EMC)，以電絕緣地密封保護該第一晶片120與該些中介導體130之底部。其中，經由只蝕刻該第一封膠體140之化學閃蝕(chemical flash-etching)方式，藉以形成該第一封膠體 140之一表面141，其係顯露每一之該些中介導體130之殘留部位131與該第一晶片120之該背面122。上述「化學閃蝕」係為使用化學蝕刻液的淺度全面蝕刻，並且只有蝕刻該第一封膠體140而不蝕刻該些中介導體130與該第一晶片120，所使用的化學蝕刻液係可為硝酸(HNO3)與硫酸(H2SO4)之混合溶液。在化學閃蝕流程之後，該第一封膠體140由該第一基板110至該表面141之厚度係不大於該些中介導體130之該第一設置高度H1，亦不大於該第一晶片120之該第二設置高度H2，以確保該些中介導體130與該第一晶片120之局部顯露。在本實施例中，具體地該半導體封裝組合100係可另包含複數個外接端子150，例如銲球，係設置於該第一基板110之一底面111。 The first encapsulant 140 is formed on the first substrate 110 for sealing at least a portion of the first wafer 120 and a portion of the interposer conductors 130. The first encapsulant 140 is specifically an Epoxy Molding Compound (EMC), which is electrically insulated to protect the bottom of the first wafer 120 and the intermediate conductors 130. The surface 141 of the first encapsulant 140 is formed by the chemical flash-etching method of etching the first encapsulant 140, and the remaining portions of the interposer 130 are exposed. 131 and the back surface 122 of the first wafer 120. The above "chemical flashing" is a shallow overall etching using a chemical etching solution, and only the first sealing body 140 is etched without etching the intermediate conductor 130 and the first wafer 120, and the chemical etching liquid system used may be used. It is a mixed solution of nitric acid (HNO 3 ) and sulfuric acid (H 2 SO 4 ). After the chemical flashover process, the thickness of the first encapsulant 140 from the first substrate 110 to the surface 141 is not greater than the first set height H1 of the intermediate conductors 130, and is not greater than the first wafer 120. The second height H2 is set to ensure that the intermediate conductors 130 and portions of the first wafer 120 are exposed. In this embodiment, the semiconductor package assembly 100 may further include a plurality of external terminals 150, such as solder balls, disposed on a bottom surface 111 of the first substrate 110.
在本實施例中，該半導體封裝組合100係可另包含一頂封裝件170，係疊置於該第一封膠體140上，該頂封裝件170係包含一第二晶片171以及複數個接合端172，其中該些中介導體130之該些殘留部位131係接合至對應之該些接合端172。該些接合端172具體可為外接墊。 In this embodiment, the semiconductor package assembly 100 can further include a top package 170 disposed on the first encapsulant 140. The top package 170 includes a second wafer 171 and a plurality of bonding ends. 172, wherein the residual portions 131 of the intermediate conductors 130 are bonded to the corresponding joint ends 172. The joint ends 172 may specifically be external pads.
在本實施例中，更具體地該頂封裝件170係另包含一第二基板173以及一第二封膠體174，該第二晶片171係設置於該第二基板173上，該第二封膠體174係形成於該第二基板173上，以密封該第二晶片171，並且該些接合端172係構成於該第二基板173之一外表面175，該些中介導體130係直接焊接於該些接合端172。可藉由複數個銲線176電性連接該第二晶片171與該第二基板173。然 而，非限定地，該頂封裝件170之具體結構係可相同於本發明之一封裝堆疊組合之底封裝件。 In this embodiment, the top package 170 further includes a second substrate 173 and a second encapsulant 174. The second wafer 171 is disposed on the second substrate 173. The second encapsulant is disposed on the second substrate 173. 174 is formed on the second substrate 173 to seal the second wafer 171, and the bonding ends 172 are formed on an outer surface 175 of the second substrate 173. The intermediate conductors 130 are directly soldered to the second substrate 173. Engaged end 172. The second wafer 171 and the second substrate 173 can be electrically connected by a plurality of bonding wires 176. Of course However, without limitation, the specific structure of the top package 170 may be the same as the bottom package of one of the package stack assemblies of the present invention.
本發明更揭示一種半導體封裝組合100之製造方法，並說明如後。 The present invention further discloses a method of fabricating a semiconductor package assembly 100 and is described below.
如第2A圖所示，首先，提供一第一基板110，該第二基板110係具有一底面111。之後，可利用覆晶接合方式，設置一第一晶片120於該第一基板110上，該第一晶片120係具有一面向該第一基板110之主動面121以及一相對遠離該主動面121之背面122。此外，電耦合複數個中介導體130至該第一基板110並配置在該第一晶片120之周邊，該些中介導體130之一第一設置高度H1係不小於該第一晶片120之一第二設置高度H2。上述電耦合該些中介導體130之步驟係具體地包含迴焊該些中介導體130，以形成複數個固定於該第一基板110上之銲球。 As shown in FIG. 2A, first, a first substrate 110 is provided, and the second substrate 110 has a bottom surface 111. Then, a first wafer 120 is disposed on the first substrate 110 by using a flip chip bonding method. The first wafer 120 has an active surface 121 facing the first substrate 110 and a relatively distant active surface 121. Back 122. In addition, the plurality of intermediate conductors 130 are electrically coupled to the first substrate 110 and disposed at the periphery of the first wafer 120. The first set height H1 of the one of the intermediate conductors 130 is not less than one of the first wafers 120. Set the height H2. The step of electrically coupling the intermediate conductors 130 specifically includes reflowing the intermediate conductors 130 to form a plurality of solder balls fixed on the first substrate 110.
如第2B圖所示，以模封方式形成一第一封膠體140於該第一基板110上，用以密封該第一晶片120與該些中介導體130。在本步驟中，該第一封膠體140係可完全密封該第一晶片120與該些中介導體130。 As shown in FIG. 2B, a first encapsulant 140 is formed on the first substrate 110 by sealing to seal the first wafer 120 and the interposer conductors 130. In this step, the first encapsulant 140 can completely seal the first wafer 120 and the interposer conductors 130.
如第2C圖所示，在一選置步驟中，在上述形成該第一封膠體140之步驟之後與一閃蝕步驟之前，可設置複數個外接端子150至該第一基板110之一底面111。 As shown in FIG. 2C, in an optional step, after the step of forming the first encapsulant 140 and before the flashing step, a plurality of external terminals 150 may be disposed to one of the bottom surfaces 111 of the first substrate 110.
如第2D圖所示，經由只蝕刻該第一封膠體140之化學閃蝕方式，形成該第一封膠體140之一表面141，並使該第一封膠 體140僅密封該第一晶片120之局部與每一之該些中介導體130之局部，該表面141係顯露每一之該些中介導體130之殘留部位131與該第一晶片120之該背面122。 As shown in FIG. 2D, one surface 141 of the first encapsulant 140 is formed by chemical etching only etching the first encapsulant 140, and the first encapsulant is formed. The body 140 only seals a portion of the first wafer 120 and a portion of the plurality of intermediate conductors 130. The surface 141 exposes each of the residual portions 131 of the intermediate conductors 130 and the back surface 122 of the first wafer 120. .
如第2E圖所示，並請配合參閱第1圖，本發明之製造方法係可另包含：疊置一頂封裝件170於該第一封膠體140上，該頂封裝件170係包含一第二晶片171以及複數個接合端172，其中該些中介導體130之該些殘留部位131係接合至對應之該些接合端172。在本實施例中，該頂封裝件170係另包含一第二基板173以及一第二封膠體174，該第二晶片171係設置於該第二基板173上，該第二封膠體174係形成於該第二基板173上，以密封該第二晶片171，並且該些接合端172係構成於該第二基板173之一外表面175，該些中介導體130係直接悍接於該些接合端172。 As shown in FIG. 2E, and referring to FIG. 1 , the manufacturing method of the present invention may further include: stacking a top package 170 on the first encapsulant 140, the top package 170 includes a first The two wafers 171 and the plurality of bonding ends 172, wherein the residual portions 131 of the intermediate conductors 130 are bonded to the corresponding bonding ends 172. In this embodiment, the top package 170 further includes a second substrate 173 and a second encapsulant 174. The second wafer 171 is disposed on the second substrate 173, and the second encapsulant 174 is formed. The second substrate 173 is sealed on the second substrate 173, and the bonding ends 172 are formed on the outer surface 175 of the second substrate 173. The intermediate conductors 130 are directly connected to the bonding ends. 172.
因此，本發明提供一種半導體封裝組合100及其製造方法，用以簡化封裝堆疊製程。 Accordingly, the present invention provides a semiconductor package assembly 100 and a method of fabricating the same to simplify a package stacking process.
以上所揭露的僅為本發明實施例，不以此來限定本發明之權利範圍，因此依本發明權利要求所作的等同變化，仍屬本發明所涵蓋的範圍。 The above disclosure is only the embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes made in the claims of the present invention are still within the scope of the present invention.
100‧‧‧半導體封裝組合 100‧‧‧Semiconductor package combination
110‧‧‧第一基板 110‧‧‧First substrate
111‧‧‧底面 111‧‧‧ bottom
120‧‧‧第一晶片 120‧‧‧First chip
121‧‧‧主動面 121‧‧‧Active surface
122‧‧‧背面 122‧‧‧Back
130‧‧‧中介導體 130‧‧‧Intermediary conductor
131‧‧‧殘留部位 131‧‧‧Residual parts
140‧‧‧第一封膠體 140‧‧‧First gel
141‧‧‧表面 141‧‧‧ surface
150‧‧‧外接端子 150‧‧‧External terminals
160‧‧‧覆晶凸塊 160‧‧‧Flip-coated bumps
170‧‧‧頂封裝件 170‧‧‧ top package
171‧‧‧第二晶片 171‧‧‧second chip
172‧‧‧接合端 172‧‧‧ joint end
173‧‧‧第二基板 173‧‧‧second substrate
174‧‧‧第二封膠體 174‧‧‧Second seal
175‧‧‧外表面 175‧‧‧ outer surface
176‧‧‧銲線 176‧‧‧welding line
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| TW201344818A (en) * | 2012-04-16 | 2013-11-01 | Taiwan Semiconductor Mfg | Semiconductor device package structure and methods for forming the same |
| TW201622018A (en) * | 2014-12-03 | 2016-06-16 | 台灣積體電路製造股份有限公司 | Integrated circuit package pad and methods of forming |
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| TW201344818A (en) * | 2012-04-16 | 2013-11-01 | Taiwan Semiconductor Mfg | Semiconductor device package structure and methods for forming the same |
| TW201622018A (en) * | 2014-12-03 | 2016-06-16 | 台灣積體電路製造股份有限公司 | Integrated circuit package pad and methods of forming |
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