TWI244190B - Substrate for IC package - Google Patents

Abstract

A substrate for flip chip package has an upper surface and a lower surface. The lower surface has two vertical fringes and an inclined edge, wherein the inclined edge is formed at a broken corner between two vertical fringes. The substrate includes a plurality of connecting traces, each has an inner finger on the upper surface and an outer terminal on the lower surface. One of the plurality of connecting traces has an outer terminal adjacent to the inclined edge so as to have a length accorded with those of the other connecting traces to lessen signal skew.

Description

1244190

[Technical field to which the invention belongs] The present invention relates to an integrated circuit package substrate, and more particularly, to an integrated circuit package substrate for reducing signal delay. [Previous technology] In the field of integrated circuit packaging, various integrated circuits are first fabricated on a semiconductor wafer, and then the wafer is mounted on a substrate and electrically connected, and then the wafer is sealed with a sealing compound or a shell to Get proper package protection. At present, integrated circuit packaging substrates are formed by cutting a substrate strip and have a square f or rectangular shape, such as a ball grid array packaging substrate (BGA substrate). With the development of high-frequency integrated circuits, the circuit design in the substrate is more Significantly important 'Once the difference in the length of the circuit inside the substrate is too large, there will be a problem of too large difference in energy loss and resistance. A Chinese Patent Bulletin No. 531816 "Substrate for semiconductor packaging structure" does not disclose a substrate for integrated circuit packaging. The main system of the substrate is rectangular and has a plurality of wires. A plurality of strip-shaped metal strips are arranged at the corner of the main body. In order to strengthen the substrate structure, a solder-proof green paint covers and protects the metal strips. The ball pad of one of the wires is adjacent to the corner of the substrate body, so it has a long length, resulting in excessive energy loss and impedance difference. ^

Please refer to FIG. 1. A conventional integrated circuit package substrate 丨 () has a top surface including a sticky crystal region HQ and a bottom surface 120, and the top surface is used for sticking a wafer in the sticky crystal region 丨丨 θ, the lower surface 1 2 0 series can be used to implant a plurality of solder balls in the packaging process for surface bonding, the substrate 丨 〇 ^ ^ 3 has a plurality of conductive lines WO A i AO, as a chip and The internal connection path of the solder ball (or eight external connection elements), each connection line ^^ or surface 1244190 V. Description of the invention (2) 140 has an inner finger end 131, 141 and an under The terminals 120 and 132 are connected to the outside of the surface 120. The fingers 131 are electrically connected to the wafer (not shown in the figure) on the sticky crystal region 110, and the corresponding upper and lower surfaces are obtained by using the corresponding vias 1 3 3 and 143. For electrical continuity, one of the conductive lines 丨 30 external terminals 132 are adjacent to the edge of the substrate. With the complexity of the wiring, at least one of the other conductive lines 140 external terminals 142 are adjacent to the corner of the substrate. Therefore, the conductive line 140 is longer than the conductive line 130 The length of the conductive line 14 of the connection substrate corner 习 may be more than 1.5 times longer than the length of the conductive line 130. Therefore, the conductive line 14 may have a large energy loss and impedance difference. High-frequency integrated circuit calculates ^ time or signal delay. [Summary of the Invention] The main object of the present invention is to provide an integrated circuit package substrate including a plurality of conductive lines. The lower surface of the substrate has at least two vertical edges, and a gap is formed between the two edges. Angled hypotenuse, & the outer end of the one lead line is adjacent to the notched hypotenuse, so that the length of the lead line does not exceed the length of the other lead lines by a factor of two, in order to reduce the The difference in impedance reduces the occurrence of signal delays. A second object of the present invention is to provide an integrated circuit packaging substrate. A beveled edge is formed between two vertical edges of the lower surface of the substrate, so that one of the outer ends of the conductive lines can be adjacent to the other. The beveled bevel and edge, and the upper surface of the substrate contains a glue zone, the sealant area is provided with a -corner beveled edge, and the beveled edge of the lower surface is parallel to the beveled edge. To improve the structural strength of the substrate at the corners.

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The substrate and the integrated circuit package substrate of the present invention, the substrate has an upper surface and at least the surface / and the substrate includes at least a first conductive line to a first-conductor line, wherein the lower surface is Containing an edge and a second edge that are perpendicular to each other, a notched hypotenuse is formed at the first edge and the second private pole, and the hypotenuse should be at an angle with one of the upper surface.隅 It is preferable that the hypotenuse is parallel. The first conductive line has a first inner finger end on the upper surface and a first external end on the lower surface, and the first external end is adjacent to the first Edge, and the second circuit has a second inner finger end on the upper surface and a first, outer ^ 'a outer first end on the lower surface adjacent to the hypotenuse, so that the y first The length of the two lead lines does not exceed the length of the first lead line 1.2 It is preferred that the first lead line has a consistent length with the first lead line to reduce the second lead line Energy loss and impedance difference. [Embodiment] With reference to the drawings, the present invention will be described by the following embodiments. According to a specific embodiment of the present invention, please refer to FIGS. 2 and 3, a integrated circuit package substrate 200 is provided with an upper surface 210 and a lower surface 220. The upper surface 210 is used for mounting a chip 310. In this embodiment, the upper surface 2 10 of the substrate defines a sticky crystal region 211 and a sealant region 212 containing the adhesive. ^ See 211. The lower surface 220 of the substrate is used as an external surface bonding, where The lower surface 220 includes a first edge 221 and a second edge 22 22 perpendicular to each other. A notch beveled edge 223 is formed between the first edge 221 and the second edge 222. Preferably, The sealing area 2 1 2

1244190 V. Description of the invention (4) A corner beveled edge 213, the notch beveled edge 223 is parallel to the corner beveled edge 21 3 'to improve the corner structure strength of the substrate 200 and reduce warpage after packaging In this embodiment, the beveled edge 2 1 3 of the glue sealing area 2 1 2 is a glue injection inlet of a glue 330. In addition, the substrate 200 includes at least one first conductive line 23 ° and at least one first conductive line 2 40. The first conductive line 2 30 has a first surface 210 on the upper surface 210. The inner finger end 2 31 and a first external end 232 on the lower surface 22 o, the first conductive line 2 30 is connected to at least a first via 233 (first via), so that the first inner The finger end 231 and the first external terminal 232 are formed on the upper and lower surfaces of the substrate 2000. The first / external terminal 232 is adjacent to the first edge mi, and the second conductive line 24 also has a The second inner finger end 24m of the upper surface 21 and a second external end 242 on the lower surface 220 are connected to at least a second via 243 (fecond via). The second external end 242 is adjacent to the defect. The angled beveled edge 223, preferably, the distance between the second external end 242 and the notched beveled edge 223 does not exceed the distance between the first external end 232 and the first edge 221. In addition, the first guide, line 2 The length of 40 does not exceed the first conductive line M. The length of the second conductive line 240 is preferably the same as the length of the second conductive line 240 to reduce the energy of the second conductive line 240: '篦: t-resistance difference' In this embodiment, $ First lead connection line 230 Second == One connection line 24 ◦ It is a signal transmission line, which makes the substrate 20 months ^, used for horse frequency integrated circuit packaging, and it is not easy to have signal delay (signai is usually measured on the substrate Upper surface 21 G and lower surface 220, ^ solder mask 25 ° to protect the first conductive line 2 30 and 1244190 V. Description of the invention (5) The second conductive line 240 but the first inner finger end is exposed 231, the second inner finger terminal 241, the first external terminal 232 and the second external terminal 242. Furthermore, please refer to FIG. 3, in a integrated circuit package structure using the above-mentioned substrate 2000, a chip 310 series The die-bonding region 211 provided on the upper surface of the substrate 2000 is 200. In this embodiment, a bonding wire 320 formed by wire bonding is connected to the first pad 200 by the bonding pad of the wafer 310. An inner finger end 231 and the second inner finger end 241 electrically connect the chip 310 to the substrate 200, or the chip 310 is The flip chip and inner lead bonding (ILB) technology can be used to electrically connect to the substrate 200 with other conventional conductive elements. In addition, a colloidal 330 can be provided on the Lu substrate 2 using stamping technology 2 On the sealant area 2 1 2 of 0 0, preferably, during the compression molding process, the sealant body 330 is injected and re-cured from the corner and beveled edge 2 13 of the sealant area 212, and the substrate 2 is used. The hypotenuse hypotenuse 2 23 is parallel to the hypotenuse hypotenuse 2 1 3. Under a shorter moment, the waste rubber that is removed except the sealing compound 3330 and the substrate 4 can be reduced. Damage, and can reduce the curvature of the substrate 2000 at the corner. In this embodiment, the substrate 200 is a ball grid array package substrate, the first external terminal 232 and the second external terminal 242 The plurality of solder balls 340 are bonded to the first external terminal 232 and the second external terminal 242 on the lower surface 220 of the substrate. Therefore, the integrated circuit package substrate of the present invention can greatly balance the connection. The difference in the length of the circuit to improve the digital signal and analog signal of the overall integrated circuit package structure The scope of protection of the present invention shall be determined by the scope of the attached patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention belong to the present invention. protected range.

1244190

[Brief description of the diagram] G: a partial schematic diagram of the τ surface of the mounting substrate; A, ^ ^ χ is one of the specific embodiments, a partial schematic diagram of the lower surface of the integrated circuit package substrate, and Figure 3: basis The cross-section of a board of the present invention after packaging is partially shown in a specific embodiment, and the integrated circuit packaging base is intended. Simple explanation of component symbols 1 0 0 substrate 130 lead line 1 31 inner finger end 140 lead line 141 inner finger end 200 base plate 211 sticky crystal area 2 2 0 lower surface 223 notch beveled edge 230 first lead line 231 first Inner finger end 240 Second conductive line 241 Second inner finger end 2 5 0 Anti-glow layer 3 1 0 Chip 340 Solder ball 11 〇Crystal region 1 3 2 External end 14 2 External end 21 0 Upper surface 21 2 Sealant Zone 2 21 First edge 232 First external end 242 Second external end 320 Welding wire 120 Lower surface 133 Via hole 143 Via hole 21 3 beveled edge 222 Second edge 233 First via hole 243 Second via hole 330 Seal colloid

Claims (1)

1244190 VI. Scope of patent application [Scope of patent application, the second leading edge and the first end with a close neighbor pass through the 2, middle and side, 3, the middle, 4, the middle, 5, the middle, 6, and the middle via) An integrated circuit package substrate having a top surface and the substrate system including at least a first surface connection line, wherein a conductive line and at least a -second-second edge, at: the first side of each other ; The length of the straight-first-side-first connection line does not exceed the length of the integrated circuit package substrate described in item 1 above, which is equal to the sealing area, which has -angle Its system: The hypotenuse of the lower surface is parallel. The corner of the sealing area of the integrated circuit package substrate described in item 2 of the dry circuit is the entrance for glue injection. Shen Shen: The integrated circuit package substrate described in item 1 of 7 Ganwei has a length equal to that of the first conductive line. m—i The integrated circuit package substrate described in item 1 of Qianwei, where i is a signal transmission line by the agency and the second lead line. & 一 = & t The integrated circuit package substrate described in item 1 of the yoke enclosure, the first conductive line of which is connected to at least one first via (first 〇 as described in item 6 of the Shenyan patent stem enclosure). Integrated circuit package substrate Page 14 1244190 Liushenqing Patent Scope = At least the second conductive line is connected—the second via hole (―Middle 8 of this; with 1: the integrated circuit package substrate described above, which is as claimed in Decay brakes] The 2nd—the external end is a ball receiving pad. The integrated circuit packaging substrate described in item 1 of the 2nd technical example, the distance between the end of the M section ^ and the hypotenuse is not more than the The first external post, 4, the distance of the first edge. 10 ,: a kind of integrated circuit package structure, including: contains; ϊϊ η: the upper surface and-the lower surface, and the substrate is in the table below; is the second The lead line is virtual at the first edge: the first edge and the second edge, and there is a -inner finger end on the upper surface and -in 1 outer end, the first outer end is Adjacent to the first side; end 2 ,; the second lead line has-on the upper surface: inside the near beveled edge, the first outer lead line is adjacent to the lead line, and the length of the two ::: guide The length of the connection line does not exceed the first-Japanese sheet, which is provided on the upper surface of the substrate; and a plurality of conductive elements, which are connected to the chip. The first inner finger end of the first lead and the second inner finger end of the second lead line. Youlu π, the integrated circuit package as described in item 10 of the scope of patent application, the surface of the frame is defined by a Sealing zone, the sealing zone has-steep angle bevel ', is parallel to the beveled edge of the lower surface. 1244190 VI. The scope of patent application for the integrated circuit package structure described in the patent scope, The gel is provided on the sealing area of the substrate. The integrated circuit package structure described in item 12 of the patent range, and the sealing system seals the wafer. 2 in; 13 ' The integrated circuit packaging structure of the factory, the beveled corner of the sealing area in the factory is the injection inlet. "Two please = the integrated circuit packaging structure described in No. 10 ', with the-lead The line has the same length as the lead line «2 in; the 10th, the integrated circuit packaging structure described in the circuit, the circuit. The lead line is a signal transmission line 17 7. If the scope of patent application ^ The first-conductor line is connected at least by the connection,-product via). Connected with a second via (second 19, such as the scope of the patent application, where the integrated circuit packaging structure of the first external terminal blood, the above description), ^, such as the patent, please refer to the patent standard ^ # 9— # W 为 接Ball ball. It also includes a plurality of solder balls, hair; the integrated circuit package structure, ball pad. 〃 f, the connection on the lower surface of the substrate 21, such as the scope of the patent application No. 10, ten, The structure of the integrated circuit packaging structure of jinjin, page 16 1244190 6. The scope of patent application where the distance between the second external terminal and the beveled edge is not more than the distance between the first external terminal and the first edge. ^ 1 p. 17