TWI345297B - Pop (package-on-package) device protecting soldered joints between external leads - Google Patents

Description

1*345297 ' IX. Description of the Invention: [Technical Field] The present invention relates to a lead frame-based POP device, and in particular to a semiconductor package for protecting solder joints between external pins Stacking level [Prior technology] In recent years, high-tech electronic products have continuously introduced more human-friendly electronic products, resulting in products that are lighter and thinner. Therefore, a combination of semiconductor components is to form a plurality of half-pieces for vertical 3D stacking. Meets the requirements of small surface bonding area and component setting, which is called a semiconductor package stacking frame-based POP device. Among them, the stackable semi-conducting member uses the lead frame as the wafer carrier, which is the lowest cost. It is soldered and stacked on the outer lead of the piece (sealing body), and the circuit is connected in series 'but the outer pin is soldered. The prior art semiconductor sealing structure 100 mainly includes a first semiconductor package, a second package 120 stacked on the first semiconductor package 11A. . The first semiconductor package " and the second package 120 are both lead frame substrates, and the inner packaged wafer can be recalled or double data speed (DDR) dynamic random access memory increases the capacity of the memory Or add application features. The first semi-conducting body 110 includes a first sealing body u i , a plurality of first outer pins i 丨 3 of a first wafer and a lead frame. Among them, the stacking group; there is about - ^ construction. , the function is more, the trend. The conductor package is still in the form of a density element (lead body package element extends the element to achieve the L ° package stack and at least the semiconductor package semiconductor package is a flash memory body, the body package 1 1 2 and the first outer 6 1345297, pin 11 3 series can be soldered to a circuit board 1 4 利用 using a solder 丨 5 〇. The usual lead frame products can be TSOP, QFP, TQFP, etc. The second semiconductor package 12 包含 includes a second encapsulant 1 2 1 , a second chip 1 22 and a plurality of second outer leads 123 of a lead frame, wherein the second outer leads 123 of the second semiconductor package 120 are exposed to the second encapsulant 1 2 , about an I-shaped leg, which is straight and substantially perpendicular to the marking surface on the second encapsulant 121, and is connected to the first outer lead 113 of the first semiconductor package n〇 by the soldering substance 130. a section. Since the solder joints between the first outer leads 113 and the second outer leads 123 (ie, the position of the solder material 13〇) are formed independently, it is easy to be in a temperature cycling test. Fracture. Tested and studied between the outer pins The breakage of the solder joint is caused by the coefficient of thermal expansion of the component material. CTEmismatch. Although different material suppliers have different material properties with different models, for example, the first semiconductor package 丨The thermal expansion coefficients of the sealants ill and 121 of the second semiconductor package 120 are about 10 ppm wide C when the temperature is lower than the glass transition temperature (Tg), about 36 ppm / C when the glass transition temperature (Tg) is still The glass transition temperature of the sealant is generally about 120 ° C; and the general lead frame (ie, the outer leads 113 and 123) is made of metal or alloy material. The iron-nickel alloy Alloy 42 is taken as an example, and the thermal expansion coefficient is about 4.3 ppm/°C ^ Therefore, the higher the temperature of the semiconductor package stack assembly 100, the greater the volumetric thermal expansion of the sealants 1 and 121 'the greater the difference in the amount of expansion from the outer leads 113 and 123'. The sealant 111 The contact interface with 121 generates the stress of pulling the 7 1-345297, the second pin 123 (as shown in Fig. 1), so that some of the solder joints of the second pins 1 23 are excessively concentrated. Stress, especially the second The side edge of the pin 1 23 has a problem of solder joint breakage. SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor package stack assembly structure for protecting solder joints between external pins, and to enable external pins. The stress of the solder joint is dispersed, thereby avoiding the occurrence of solder joint breakage due to the difference in thermal expansion coefficient between the sealant and the lead frame. In addition, the electrical short circuit between the pins can be prevented. The second object of the present invention is to provide a protection. The semiconductor package stacking structure of the solder joints between the outer leads can absorb the difference in thermal expansion coefficient between the sealant and the lead frame and act on the stress of the solder joint between the outer leads. A further object of the present invention is to provide a semiconductor package stack assembly structure for protecting solder joints between external pins, which can cover solder joints between the outer leads, help to conduct heat, and can maintain heat at high temperatures. Electrical connection between the pins. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a semiconductor package stack assembly structure for protecting solder joints between external pins mainly comprises a first semiconductor package, at least a second semiconductor package, a solder material, and a non-conductive paste. The first semiconductor package includes a first encapsulant, at least one first outer chip sealed to the first wafer of the first encapsulant, and a lead frame, wherein the first outer leads are Extending from the side of the first sealant and exposing. The second semiconductor package is bonded to 8

I34529T, in the first semiconductor package, the second semiconductor package comprises a second encapsulant, at least one second chip sealed on the second encapsulant and a plurality of second outer leads of a lead frame, The second outer leads extend from the sides of the second encapsulant and are exposed. The solder material is soldered to the end faces of the second outer leads and a portion corresponding to the first outer leads. The non-conductive adhesive is formed on the end faces of the second outer leads of the second semiconductor package along the side of the first encapsulant of the first semiconductor package to connect the second outer leads. The solder material is coated. In order to achieve the stress dispersion of the solder joints between the external pins and prevent short circuits. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing semiconductor package stack assembly configuration, the dielectric paste can be low modulus to absorb stress between the first outer leads and the second outer leads. In the foregoing semiconductor package stack assembly construction, the dielectric coating system may be a thermal conductive silicone. In the foregoing semiconductor package stack assembly configuration, the second encapsulant may be laminated to contact the first encapsulant. In the foregoing semiconductor package stack assembly configuration, the dielectric coating may partially or completely seal the solder material. In the foregoing semiconductor package stack assembly structure, the dielectric coating system 1*345297 is a semiconductor package stack for protecting solder joints between external pins according to an embodiment of the present invention. Combined construction. A semiconductor package stack assembly structure for protecting solder joints between external pins mainly includes a first semiconductor package 21, at least a second

The semiconductor package 220, the solder material 230, and the dielectric paste 24". The first semiconductor package 210 and the second semiconductor isolation member 22 may be a single chip package or a multi-chip package. As shown in Fig. 3, in the present embodiment, the first semiconductor package 21A and the second semiconductor package are both thin single-profile packages (TS〇P) of a single wafer. The first semiconductor package 2H) includes a first encapsulant 211, a first wafer 212 sealed to the first colloid 211, and a plurality of first outer leads 213 of a lead frame, wherein the first wafer The active surface of the 212 is provided with a first pad 216 ′ and the active surface of the first wafer 212 is adhered to the sealed region of the first outer leads 213 of the lead frame by the adhesive 217 Duan Zhi

The lower surface 'the other splicing element formed by the plurality of wires" is the first electrode 212 of the first wafer 212 to the first outer pin 213 of the lead frame 213 bonding wire 2 1 5 as the electrical bonding pad 2 1 6 electrically connected to the upper surface of the encapsulated section. The first encapsulant 21 1 is formed in a step to seal the first wafer 2 i 2 , and the encapsulated segments 2 1 3 of the first outer leads 2 1 3 are bound by the first encapsulant 2 11 In the side extension embodiment, the first outer leads 2丨3 are sea for surface bonding to a circuit board 250, and generally the circuit board 250 can be a motherboard and memorized in an encapsulation. Step the first wire 2 1 5 and. The first outer leads are extended and exposed. In this gull lead, solder 260 is soldered. The body module carrier board 'displays 10 1-3452971 card carrier board, this memory card substrate or mobile phone communication board and so on. The second semiconductor package "220" is bonded to the first semiconductor package 21" to form a package stacking person, - a woman, a female

The composition of the whistle, the multi-layer TSOP stack structure. The second semiconductor device ” & & & τ 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 220 Second outer leads 223, wherein the second outer leads 223 extend from the sides of the second sealant 221

dew. Preferably, the second outer pins 223 can be vertical type j-type legs, so that the second outer pins 221 >*山&, ~ Ή 223 can be utilized The solder material 230 is soldered to one of the first outer leads 213 as shown in the enlarged view of FIG. 3). As shown in FIG. 3, in a specific embodiment, the second semiconductor package 22 further includes a host a > a die bond 227 and a plurality of second bond wires 225. The adhesive 227 adheres the second 222 to the second outer lead 223 or the wafer holder (not shown) of the lead frame. The second bonding wires 2 25 are electrically connected to the plurality of second pads 226 of the second 222 222 to the corresponding second outer pins 223 . The package pattern of the second semiconductor package can be the same as the first semiconductor package 21 _ except for the side extension pins. The same as 0, except for 220, the memory is not the same as the memory. The first wafer and the second wafer 222 are bulk wafers, such as flash memory or dynamic random access memory, which increase the memory capacity without increasing the surface bonding area. The first encapsulant 211 and the second encapsulant 221 are Epoxy Molding Compound (EMC) 〇 π 1345297 * The bottom surface of the second encapsulant 221 is laminated to the first encapsulant 2 11 The top surface to reduce the height of the stack. In addition, the soldering material 23 〇# 4 # and the end surface 224 of the second outer lead 223 and the section 214 corresponding to the first outer outer corner 213 are electrically connected. Some second outer pins? The force leg 213 and the second outer pins 223. The solder material 23 0 is a fusible miscible g 綷 conductive metal such as tin-lead or a lead-free solder.

As shown in FIG. 3, the dielectric adhesive 24 is formed along the side of the first encapsulant 211 of the first semiconductor package 210 to form the first semiconductor package 220. An end surface 224 of the second outer lead 223. In this embodiment, the dielectric adhesive 24 can be agglomerate to connect the second outer leads 223 and cover the solder material 230, thereby dispersing between the outer leads 213 and 223. The solder joint (i.e., the position of the solder material 230) is subjected to a difference in thermal expansion coefficient to prevent breakage of the solder joint of the outer lead. Wherein, the difference in thermal expansion coefficient is a difference between the thermal expansion coefficients of the outer leads 2 1 3 and 223 of the wire frame and the sealants 2 1 1 and 221 . In the present embodiment, the dielectric paste 240 is partially sealable on the outer side of the recording material 203. However, the viscosity and application amount of the dielectric coating are adjustable to change to the appropriate coating area and coating shape, as shown in Fig. 5 'in different embodiments' a dielectric chamber wins 240A and can be partially Sealing the inner side of the solder material 230 (as shown in FIG. 5); a dielectric adhesive 24〇B and completely sealing the recording material and having a thin cover thickness (as shown in FIG. 5) a dielectric adhesive 240C and can completely seal the solder material 230 and have a thickness of 12 1-345297. (With the thickness of the cover layer (as shown in FIG. 5, preferably, the dielectric adhesive 240 The low-modulus, the first-outer pins 213 and the second outer leads 223 can be absorbed to increase the stress, and the semiconductor package is improved. The combination of anti-dropping and anti-thermal cycling combines the impact. Therefore, the semiconductor package stacking structure has a problem of solder joint breakage between the two hot-shock pins, thereby improving the reliability of the product.

The dielectric adhesive 24 can be a thermal conductive silicone, and its thermal conductivity should be:, and even higher than the first sealing body 211 or the second sealing body 22, to help dissipate heat. Thermal Conduction As shown in the figure, a half-package stack assembly structure 200 for protecting solder joints between external pins mainly comprises a first semiconductor package: 2 10, at least one second semiconductor package 22, solder material, and non-conductive Squeegee 240'. Except for the non-conductive rubber coating 24, the shape of which is slightly different from that of the above embodiment, the other elements may be the same, and the same drawing numbers are used. The first semiconductor package 21 includes a first outer package 213' for: sealing the first encapsulant 2" of the wafer, and a lead frame can be soldered to a circuit board 25 by solder 260. . The second semiconductor package 220 is bonded to the first semiconductor package 2 1 , and the second semiconductor package 22 includes a second encapsulant 221 for sealing the wafer and a plurality of lead frames. The second outer bow is 223. The solder material 23 is soldered to the end faces of the second outer leads and to a section corresponding to the first outer pins 213. The non-conductive adhesive 240 is formed on the end surface of the outer electrode 223 along the side of the first seal 13 11 of the first semiconductor package 21, and covers the solder material 230. Borrow and prevent short circuits. Preferably, the non-conductive series is not dispersed in different external pins.

1-345297. The second semiconductor package 220 is connected to the second outer leads 223 to achieve a solder joint between the outer leads. The non-conductive adhesive 240 is the same as the second outer lead 223. Can achieve results. The above description is only a preferred embodiment of the present invention, and the present invention is not limited to any form, and the scope of the technical scope of the present invention is subject to the scope of the appended claims. Any person skilled in the art can use the technical content of the above-mentioned disclosure to make some equivalents or modifications to the equivalent embodiment, but without departing from the technical solution of the present invention, the above embodiments are made according to the technical essence of the present invention. The singularity of the singular changes and modifications are still within the scope of the technical scope of the present invention. [Simplified description of the drawings] FIG. 1 : Conventional semiconductor package stacking assembly structure before the schematic diagram 2: conventional semiconductor package stack A partial side view of a combined construction. FIG. 3 is a schematic diagram of a semiconductor package stack assembly structure for protecting external solder joints according to an embodiment of the present invention. FIG. 4 is a view of an embodiment of the present invention. A partial side view of a semiconductor package assembly structure. Figure 5: According to the embodiment of the present invention, it is shown that the semi-conducting and the second force-packing strips are not equivalent. Fig. 6 shows the partial cross-section enlarged view of the different coating patterns of the dielectric coating of the stacked composite structure. Another partial side view of a semiconductor package stack assembly structure for protecting solder joints between external pins according to an embodiment of the present invention. [Main Component Symbol Description] 111 First Sealant 113 First Outer Pin 12 1 second sealing body 123 second outer pin

100 semiconductor package stack assembly structure 110 first semiconductor package 112 first wafer 120 second semiconductor package 122 second wafer 130 solder material 150 solder 2 11 first seal body 213 first outer pin 2 1 5 first bond wire 21 7 adhesive 221 second sealant 223 second outer lead 225 second bond wire 227 adhesive paste 240 dielectric adhesive 240B dielectric adhesive 140 circuit board 200 semiconductor package stack assembly structure 210 first semiconductor package 21 2 first wafer 214 outer pin segment 216 first pad 220 second semiconductor package 222 second wafer 224 second outer pin end surface 226 second pad 230 solder material 240A dielectric glue 15 1345297 glue 240C dielectric coating 240' dielectric 250 circuit board 260 solder

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Claims (1)

P345297 X. Patent application scope: 1. Recording between protective outer pins, including: Anvil's Fengconductor package stacking assembly-the first semiconductor package, which is sealed in the first-sealed kick body _ a sealant, at least a plurality of first-outer pins, wherein: ^ and a side of the ferrule of the lead frame extend and are exposed; ^ the foot is formed by the first at least one second semiconductor package, Attached to the device, the second semiconductor guide (4), the first +-conductor seal comprises at least a second wafer of the == sealant and a plurality of second external chats of the lead frame, wherein ~ ±xmm - two first outer leads extending from the side of the first encapsulant and exposed; splicing material, which is soldered to the second 帛 - outer pin - region ^ ^ end face and corresponding Dielectric coating, which is the first sealing material of the first + conductor package, and (4) formed on the second outer leads of the second semiconductor package to connect The second outer leads cover the solder material. \如_Please patent scope! The semiconductor package stack assembly of claim 7, wherein the dielectric paste is low modulus to absorb stress between the first outer leads and the second outer leads. 3. The semiconductor package stack assembly structure of claim 2, wherein the dielectric coating is a thermal conductive silicone. 4. The semiconductor package stack assembly structure of claim </RTI> wherein the second sealant system is laminated to contact the first sealant. 17. The semiconductor package stack assembly of claim 1, wherein the dielectric coating partially seals the semi-finished material of the detailed reference substance β s month patent scope item 1 θ π V $ k ' wherein the dielectric coating completely seals the solder material. The semiconductor package stacking structure described in claim i is wherein the dielectric coating is in the form of a mass. 'As described in the scope of patent application 帛1, Gan b K + conductor package stacking structure, wherein the dielectric coating is a strip