CN102856268A - First packaged and then etched packaging structure with multiple chips normally installed and without base islands and preparation method of structure - Google Patents
First packaged and then etched packaging structure with multiple chips normally installed and without base islands and preparation method of structure Download PDFInfo
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- CN102856268A CN102856268A CN2012101407783A CN201210140778A CN102856268A CN 102856268 A CN102856268 A CN 102856268A CN 2012101407783 A CN2012101407783 A CN 2012101407783A CN 201210140778 A CN201210140778 A CN 201210140778A CN 102856268 A CN102856268 A CN 102856268A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a first packaged and then etched packaging structure with multiple chips normally installed and base islands buried and a preparation method of the structure. The structure comprises base islands (1) and pins (2), wherein a plurality of chips (4) are arranged on the front faces of the base islands (1); the front faces of the chips (4) and the front faces of the pins (2) are connected by metal wires (5); plastic package materials (6) are arranged in the surrounding regions of the base islands (1) and the pins (2) and outside the chips (4) and the metal wires (5); small holes (7) are formed on the surfaces of the plastic package materials (6) on the lower parts of the pins (2); the small holes (7) are communicated with the backs of the pins (2); metal balls (9) are arranged in the small holes (7); and the metal balls (9) are contacted with the backs of the pins (2). The packaging structure and the preparation method have the following beneficial effects that the preparation cost is reduced; the safety and reliability of the packaging body are improved; environmental pollution is reduced; and design and preparation of high-density circuits are truly achieved.
Description
Technical field
The present invention relates to a kind of multi-chip formal dress and encapsulate first after etching without basic island encapsulating structure and manufacture method thereof.Belong to the semiconductor packaging field.
Background technology
The manufacturing process flow of traditional high-density base board encapsulating structure is as follows:
Step 13, finish follow-up load, routing, seal, the concerned process steps such as cutting.
Above-mentioned traditional high-density base board encapsulating structure has the following disadvantages and defective:
1, many glass fiber materials of one deck, same also many costs of layer of glass;
2, because must use glass fibre, so with regard to the about thickness space of 100 ~ 150 μ m of many layer of glass thickness;
3, glass fibre itself is exactly a kind of foaming substance, so easily because the time of placing and environment suck moisture and moisture, directly have influence on security capabilities or the reliability step of reliability;
4, the fiberglass surfacing coating the about Copper Foil metal layer thickness of 50 ~ 100 μ m of one deck, and the etching of metal level circuit and circuit distance is also because the characteristic of etching factor can only accomplish that (etching factor: the ability of preferably manufacturing is the thickness that etched gap approximately is equal to etched object for the etched gap of 50 ~ 100 μ m, referring to Figure 38), so the design of accomplishing high-density line and manufacturing that can't be real;
5, because must use the Copper Foil metal level, and the Copper Foil metal level is the mode that the employing high pressure is pasted, so the thickness of Copper Foil is difficult to be lower than the thickness of 50 μ m, otherwise just is difficult to operation such as out-of-flatness or Copper Foil breakage or Copper Foil extension displacement etc.;
6, also because whole baseplate material is to adopt glass fiber material, thus significantly increased thickness 100 ~ 150 μ m of glass layer, can't be real accomplish ultra-thin encapsulation;
7, the traditional glass fiber is sticked on the technology of Copper Foil because material property difference very large (coefficient of expansion) easily causes stress deformation in the operation of adverse circumstances, directly has influence on precision and element and substrate adherence and reliability that element loads.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, provide a kind of multi-chip formal dress to encapsulate first after etching without basic island encapsulating structure and preparation method thereof, its technique is simple, need not use glass layer, reduce cost of manufacture, improved the safety and reliability of packaging body, reduced the environmental pollution that glass fiber material brings, and the metal substrate line layer adopts is electro-plating method, can really accomplish the Design and manufacture of high-density line.
The object of the present invention is achieved like this: a kind of multi-chip formal dress encapsulates first after etching without basic island encapsulating structure, it comprises pin, described pin front is provided with a plurality of chips by conduction or non-conductive bonding material, be connected with metal wire between described a plurality of chip front side and the pin front, zone between described pin and the pin, the zone on pin top, the zone of pin bottom and chip and metal wire all are encapsulated with plastic packaging material outward, offer aperture on the plastic packaging material at the described pin back side, described aperture is connected with the pin back side, be provided with Metal Ball in the described aperture, described Metal Ball contacts with the pin back side.
A kind of multi-chip formal dress encapsulates first after etching without the manufacture method of basic island encapsulating structure, said method comprising the steps of:
The photoresistance film that can carry out exposure imaging is sticked respectively at front and the back side at the metal substrate of finishing preplating copper material film;
Utilize exposure imaging equipment that step 3 is finished the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the positive follow-up needs of metal substrate;
In step 4, electroplate the inert metal line layer in the zone of the positive removal of metal substrate part photoresistance film;
Multilayer or single-layer metal line layer on the inert metal plated surface in step 5, metallic circuit layer namely form corresponding pin top at metal substrate after electroplating and finishing;
Remove the photoresistance film of metallic substrate surfaces;
Pin top front face coated with conductive or nonconducting bonding material in step 6 formation;
A plurality of chips are implanted on pin top in step 8;
Between chip front side and pin front, carry out the operation of bonding metal wire;
The positive plastic packaging material that adopts of metal substrate in the step 10 is carried out plastic packaging;
The photoresistance film that can carry out exposure imaging is sticked respectively at front and the back side at the metal substrate of finishing plastic packaging work;
Part photoresistance film is removed at step 13, the metal substrate back side
Utilize exposure imaging equipment that step 12 is finished the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics that carry out chemical etching to expose the follow-up needs in the metal substrate back side;
The metal substrate back side in the step 13 is finished the zone of exposure imaging and carry out chemical etching;
Step 15, plated metal line layer
Multilayer or single-layer metal line layer on inert metal line layer plated surface namely form corresponding pin bottom at metal substrate after metal plating is finished;
Remove the photoresistance film of metallic substrate surfaces;
Adopt plastic packaging material to carry out plastic packaging at the metal substrate back side in the step 10 six;
The surface of sealing in advance plastic packaging material at the metal substrate back side needs follow-up zone of planting Metal Ball to carry out perforate, specifically carries out perforate at the pin back side;
Carry out the cleaning of oxidation material, grease material at metal substrate back side plastic packaging material tapping, can carry out the coating of coat of metal simultaneously;
The plastic-sealed body tapping is implanted into Metal Ball at the metal substrate back side, and Metal Ball is contacted with the back side of pin;
Also can carry out the operation of bonding metal wire between described step 10 seven chips fronts and the chip front side.
In the described step 10 nine metal substrate back side plastic packaging material tapping cleaned and carry out simultaneously the coat of metal coating.
Cross-over connection has passive device between described pin and the pin, and described passive device is connected across between pin front and the pin front or is connected across between the pin back side and the pin back side.
Described pin has multi-turn.
Described pin comprises pin top, pin bottom and intermediate barrier layers, and described pin top and pin bottom form by the single or multiple lift metal plating, and described intermediate barrier layers is nickel dam or titanium layer or copper layer.
Compared with prior art, the present invention has following beneficial effect:
1, the present invention does not need to use glass layer, so can reduce the cost that glass layer brings;
2, the present invention does not need to use the foaming substance of glass layer, so the grade of reliability can improve again, relatively will improve the fail safe of packaging body;
3, the present invention does not use the glass layer material, so just can reduce the environmental pollution that glass fiber material brings;
What 4, two-dimensional metallic substrate circuit layer of the present invention adopted is electro-plating method, and the gross thickness of electrodeposited coating is about 10 ~ 15 μ m, and the gap between circuit and the circuit can reach the following gap of 25 μ m easily, so can accomplish veritably the technical capability of pin circuit tiling in the high density;
5, two-dimensional metallic substrate of the present invention is the metal level galvanoplastic because of what adopt, so the technique than glass fibre high pressure Copper Foil metal level is come simply, and do not have metal level because high pressure produces bad or puzzled that metal level out-of-flatness, metal level breakage and metal level extend and be shifted;
6, two-dimensional metallic substrate circuit layer of the present invention is to carry out metal plating on the surface of metal base, so the material characteristic is basic identical, so the internal stress of coating circuit and metal base is basic identical, can carries out easily the rear engineering (such as the surface mount work of high temperature eutectic load, high temperature tin material scolder load and high temperature passive device) of adverse circumstances and be not easy to produce stress deformation.
Description of drawings
Fig. 1 ~ Figure 21 is that multi-chip formal dress of the present invention encapsulates first after etching without each operation schematic diagram of basic island encapsulating structure embodiment 1 manufacture method.
Figure 22 (A) encapsulates first after etching without the structural representation of basic island encapsulating structure embodiment 1 for multi-chip formal dress of the present invention.
Figure 22 (B) is the vertical view of Figure 22 (A).
Figure 23 (A) encapsulates first after etching without the structural representation of basic island encapsulating structure embodiment 2 for multi-chip formal dress of the present invention.
Figure 23 (B) is the vertical view of Figure 23 (A).
Figure 24 (A) encapsulates first after etching without the structural representation of basic island encapsulating structure embodiment 3 for multi-chip formal dress of the present invention.
Figure 24 (B) is the vertical view of Figure 24 (A).
Figure 25 (A) encapsulates first after etching without the structural representation of basic island encapsulating structure embodiment 4 for multi-chip formal dress of the present invention.
Figure 25 (B) is the vertical view of Figure 25 (A).
Figure 26 ~ Figure 37 is the manufacturing process flow diagram of traditional high-density base board encapsulating structure.
Figure 38 is the etching situation schematic diagram of fiberglass surfacing Copper Foil metal level.
Wherein:
Conduction or non-conductive bonding material 2
Coat of metal 7
Inert metal line layer 13
Embodiment
It is as follows without basic island encapsulating structure and manufacture method thereof that a kind of multi-chip formal dress of the present invention encapsulates first after etching:
Embodiment one: single basic island individual pen pin
See Figure 22 (A) and Figure 22 (B), Figure 22 (A) multi-chip formal dress of the present invention encapsulates first after etching without the structural representation of basic island encapsulating structure embodiment 1.Figure 22 (B) is the vertical view of Figure 22 (A).Can be found out by Figure 22 (A) and Figure 22 (B); multi-chip formal dress of the present invention encapsulates first after etching without basic island encapsulating structure; it comprises pin 1; described pin 1 front is provided with a plurality of chips 3 by conduction or non-conductive bonding material 2; described a plurality of chip 3 positive with pin 1 front between and be connected with metal wire 4 between chip 3 fronts and chip 3 fronts; zone between described pin 1 and the pin 1; the zone on pin 1 top; the zone of pin 1 bottom and chip 3 and the metal wire 4 outer plastic packaging materials 5 that all are encapsulated with; offer aperture 6 on the plastic packaging material 5 at described pin 1 back side; described aperture 6 is connected with pin 1 back side; be provided with Metal Ball 8 in the described aperture 6; be provided with coat of metal 7 between described Metal Ball 8 and pin 1 back side; described Metal Ball 8 adopts tin or tin alloy material; described pin 2 is by pin top; intermediate barrier layers and pin bottom form; pin top and pin bottom form by the single or multiple lift metal plating, and intermediate barrier layers is nickel dam or titanium layer or copper layer.
Its manufacture method is as follows:
Referring to Fig. 1, get the suitable metal substrate of a slice thickness, the material of metal substrate can be carried out conversion according to function and the characteristic of chip, such as: copper material, iron material, ferronickel material, zinc-iron material etc.
Referring to Fig. 2, at metallic substrate surfaces plating one deck copper material film, purpose is to do the basis for follow-up plating.(mode of plating can adopt chemical plating or metallide).
Referring to Fig. 3, stick respectively the photoresistance film that can carry out exposure imaging at front and the back side of the metal substrate of finishing preplating copper material film, to protect follow-up electroplated metal layer process operation, the photoresistance film can be that dry type photoresistance film also can be wet type photoresistance film.
Referring to Fig. 4, utilize exposure imaging equipment that step 3 is finished the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the positive follow-up needs of metal substrate.
Referring to Fig. 5, in step 4, electroplate the inert metal line layer in the zone of the positive removal of metal substrate part photoresistance film, as the barrier layer of subsequent etch work, inert metal can adopt nickel material or titanium material or copper material, and plating mode can make electroless plating or metallide mode.
Referring to Fig. 6, multilayer or single-layer metal line layer on the inert metal line layer plated surface in step 5, the metallic circuit layer namely forms corresponding pin top at metal substrate after electroplating and finishing, described metallic circuit layer can adopt one or more in silver, aluminium, copper, nickel gold and the NiPdAu, and plating mode can be that electroless plating also can be the mode of metallide.
Referring to Fig. 7, remove the photoresistance film of metallic substrate surfaces, adopt chemical medicinal liquid mode softening and that adopt high pressure water jets to remove to remove the photoresistance film.
Referring to Fig. 8, at pin top front face coated with conductive or the nonconducting bonding material that step 6 forms, purpose be for behind the follow-up implanted chip with the engaging of pin.
Referring to Fig. 9, implant a plurality of chips on the pin top of step 8.
Referring to Figure 10, between chip front side and pin front, carry out the operation of bonding metal wire, the material of described metal wire adopts gold, silver, copper, aluminium or the material of alloy, shape wiry can be thread also can be banded.
Referring to Figure 11, the positive plastic packaging material that adopts of the metal substrate in the step 10 is carried out plastic packaging, the plastic packaging mode can adopt mould encapsulating mode, spraying equipment spraying method or use the pad pasting mode.Described plastic packaging material can adopt packing material or without the epoxy resin of packing material.
Referring to Figure 12, stick respectively the photoresistance film that can carry out exposure imaging at front and the back side of the metal substrate of finishing plastic packaging work, the photoresistance film can be that dry type photoresistance film also can be wet type photoresistance film.
Part photoresistance film is removed at step 13, the metal substrate back side
Referring to Figure 13, utilize exposure imaging equipment that step 12 is finished the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics that carry out chemical etching to expose the positive follow-up needs of metal substrate.
Referring to Figure 14, the metal substrate back side in the step 13 to be finished the zone of exposure imaging and carry out chemical etching, chemical etching is until till the inert metal line layer, etching solution can adopt copper chloride or iron chloride.
Step 15, plated metal line layer
Referring to Figure 15, multilayer or single-layer metal line layer on the inert metal plated surface, namely form corresponding pin bottom at metal substrate after metal plating is finished, the coating kind can be copper nickel gold, copper nickeline, porpezite, gold or copper etc., and electro-plating method can be electroless plating or metallide.
Referring to Figure 16, remove the photoresistance film of metallic substrate surfaces, adopt chemical medicinal liquid mode softening and that adopt high pressure water jets to remove to remove the photoresistance film.
Referring to Figure 17, adopt plastic packaging material to carry out plastic packaging at the metal substrate back side in the step 10 six, the plastic packaging mode can adopt the spraying method of mould encapsulating mode, spraying equipment or use the pad pasting mode.Described plastic packaging material can adopt packing material or without the epoxy resin of packing material.
Referring to Figure 18, the surface of sealing in advance plastic packaging material at the metal substrate back side needs follow-up zone of planting Metal Ball to carry out perforate, specifically carries out perforate at the pin back side, can adopt the method for dry laser sintering or wet chemistry corrosion to carry out perforate.
Referring to Figure 19, carry out the cleaning of oxidation material, grease material at metal substrate back side plastic packaging material tapping, can carry out the coating of coat of metal simultaneously, coat of metal adopts oxidation-resistant material.
Referring to Figure 20, the plastic-sealed body tapping is implanted into Metal Ball at the metal substrate back side, Metal Ball is contacted with the back side of pin, can adopt conventional ball attachment machine or adopt the metal paste printing can form orbicule again after high-temperature digestion, the material of Metal Ball can be pure tin or ashbury metal.
Referring to Figure 21, step 2 ten is finished the semi-finished product of planting ball carry out cutting operation, make and originally integrate in array aggregate mode and to contain more than cuttings of plastic-sealed body module of chip independent, make the multi-chip formal dress and encapsulate first after etching without basic island encapsulating structure, can adopt conventional diamond blade and conventional cutting equipment to get final product.
Embodiment 2: without basic island individual pen pin passive device
Referring to Figure 23 (A) and Figure 23 (B), Figure 23 (A) multi-chip formal dress of the present invention encapsulates first after etching without the structural representation of basic island encapsulating structure embodiment 3.Figure 23 (B) is the vertical view of Figure 23 (A).Can be found out by Figure 23 (A) and Figure 23 (B), the difference of embodiment 2 and embodiment 1 only is: pass through conduction bonding material cross-over connection passive device 9 between described pin 1 and the pin 1, described passive device 9 can be connected across between pin 1 front and pin 1 front, also can be connected across between pin 1 back side and pin 1 back side.
Embodiment 3: single basic island multi-circle pin
Referring to Figure 24 (A) and Figure 24 (B), Figure 24 (A) multi-chip formal dress of the present invention encapsulates first the structural representation of the base island embedded encapsulating structure embodiment 3 of after etching.Figure 24 (B) is the vertical view of Figure 24 (A).Can be found out by Figure 24 (A) and Figure 24 (B), embodiment 3 only is with the difference of embodiment 1: described pin 1 has multi-turn.
Embodiment 4: single basic island multi-circle pin passive device
Referring to Figure 25 (A) and Figure 25 (B), Figure 25 (A) multi-chip formal dress of the present invention encapsulates first after etching without the structural representation of basic island encapsulating structure embodiment 4.Figure 25 (B) is the vertical view of Figure 25 (A).Can be found out by Figure 25 (A) and Figure 25 (B), embodiment 4 only is with the difference of embodiment 2: described pin 1 has multi-turn.
Claims (7)
1. a multi-chip formal dress encapsulates first after etching without basic island encapsulating structure, it is characterized in that it comprises pin (1), described pin (1) is positive to be provided with a plurality of chips (3) by conduction or non-conductive bonding material (2), described a plurality of chip (3) positive with pin (1) front between be connected with metal wire (4), zone between described pin (1) and the pin (1), the zone on pin (1) top, the outer plastic packaging material (5) that all is encapsulated with of the zone of pin (1) bottom and chip (3) and metal wire (4), offer aperture (6) on the plastic packaging material (5) at described pin (1) back side, described aperture (6) is connected with pin (1) back side, be provided with Metal Ball (8) in the described aperture (6), described Metal Ball (8) contacts with pin (1) back side.
2. a multi-chip formal dress as claimed in claim 1 encapsulates first the manufacture method of the base island embedded encapsulating structure of after etching, said method comprising the steps of:
Step 1, get metal substrate
Step 2, the pre-copper facing of metallic substrate surfaces
Step 3, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked respectively at front and the back side at the metal substrate of finishing preplating copper material film;
Step 4, the positive part photoresistance film of removing of metal substrate
Utilize exposure imaging equipment that step 3 is finished the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the positive follow-up needs of metal substrate;
Step 5, plating inert metal line layer
In step 4, electroplate the inert metal line layer in the zone of the positive removal of metal substrate part photoresistance film;
Step 6, plated metal line layer
Multilayer or single-layer metal line layer on the inert metal line layer plated surface in step 5, metallic circuit layer namely form corresponding pin top at metal substrate after electroplating and finishing;
Step 7, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 8, coating bonding material
Pin top front face coated with conductive or nonconducting bonding material in step 6 formation;
Step 9, load
A plurality of chips are implanted on pin top in step 8;
Step 10, routing
Between chip front side and pin front, carry out the operation of bonding metal wire;
Step 11, seal
The positive plastic packaging material that adopts of metal substrate in the step 10 is carried out plastic packaging;
Step 12, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked respectively at front and the back side at the metal substrate of finishing plastic packaging work;
Part photoresistance film is removed at step 13, the metal substrate back side
Utilize exposure imaging equipment that step 12 is finished the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics that carry out chemical etching to expose the follow-up needs in the metal substrate back side;
Step 14, chemical etching
The metal substrate back side in the step 13 is finished the zone of exposure imaging and carry out chemical etching;
Step 15, plated metal line layer
Multilayer or single-layer metal line layer on the inert metal plated surface namely form corresponding pin bottom at metal substrate after metal plating is finished;
Step 10 six, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10 seven, seal
Adopt plastic packaging material to carry out plastic packaging at the metal substrate back side in the step 10 six;
Step 10 eight, plastic packaging material surface perforate
The surface of sealing in advance plastic packaging material at the metal substrate back side needs follow-up zone of planting Metal Ball to carry out perforate, specifically carries out perforate at the pin back side;
Step 10 nine, cleaning
Carry out the cleaning of oxidation material, grease material at metal substrate back side plastic packaging material tapping, can carry out the coating of coat of metal simultaneously;
Step 2 ten, plant ball
The plastic-sealed body tapping is implanted into Metal Ball at the metal substrate back side, and Metal Ball is contacted with the back side of pin;
Step 2 11, cutting finished product
Step 2 ten is finished the semi-finished product of planting ball carry out cutting operation, make and originally integrate in array aggregate mode and to contain more than cuttings of plastic-sealed body module of chip independent, make the multi-chip formal dress and encapsulate first after etching without basic island encapsulating structure, can adopt conventional diamond blade and conventional cutting equipment to get final product.
3. a kind of multi-chip formal dress according to claim 2 encapsulates first after etching without the manufacture method of basic island encapsulating structure, it is characterized in that: cross-over connection has passive device (9) between described pin (1) and the pin (1), and described passive device (9) is connected across between pin (1) front and pin (1) front or is connected across between pin (1) back side and pin (1) back side.
4. one of them described a kind of multi-chip formal dress encapsulates first after etching without the manufacture method of basic island encapsulating structure according to claim 2 ~ 3, it is characterized in that described pin (1) has multi-turn.
5. the manufacture method of the base island embedded encapsulating structure of encapsulation after the first etching of a kind of multi-chip formal dress according to claim 2 is characterized in that: carry out the operation of bonding metal wire in the described step 10 seven between chip (3) front and chip (3) front.
6. a kind of multi-chip formal dress according to claim 2 encapsulates first after etching without the manufacture method of basic island encapsulating structure, it is characterized in that: the nine pairs of metal substrate back side of described step 10 plastic packaging material tapping cleans and carries out simultaneously the coat of metal coating.
7. a kind of multi-chip formal dress according to claim 1 encapsulates first after etching without basic island encapsulating structure, it is characterized in that: described pin (1) comprises pin top, pin bottom and intermediate barrier layers, described pin top and pin bottom form by the single or multiple lift metal plating, and described intermediate barrier layers is nickel dam or titanium layer or copper layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210140778.3A CN102856268B (en) | 2012-05-09 | 2012-05-09 | First packaged and then etched packaging structure with multiple chips normally installed and without base islands and preparation method of structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| US20080054418A1 (en) * | 2006-09-06 | 2008-03-06 | Advanced Semiconductor Engineering, Inc. | Chip carrier with signal collection tape and fabrication method thereof |
| TW200939421A (en) * | 2008-03-11 | 2009-09-16 | Powertech Technology Inc | Multi-window ball grid array package |
| US20090283884A1 (en) * | 2008-05-16 | 2009-11-19 | Samsung Techwin Co., Ltd. | Lead frame, semiconductor package including the same, and method of manufacturing the lead frame and the semiconductor package |
| CN102376672A (en) * | 2011-11-30 | 2012-03-14 | 江苏长电科技股份有限公司 | Foundation island-free ball grid array packaging structure and manufacturing method thereof |
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| US20080054418A1 (en) * | 2006-09-06 | 2008-03-06 | Advanced Semiconductor Engineering, Inc. | Chip carrier with signal collection tape and fabrication method thereof |
| TW200939421A (en) * | 2008-03-11 | 2009-09-16 | Powertech Technology Inc | Multi-window ball grid array package |
| US20090283884A1 (en) * | 2008-05-16 | 2009-11-19 | Samsung Techwin Co., Ltd. | Lead frame, semiconductor package including the same, and method of manufacturing the lead frame and the semiconductor package |
| CN102376672A (en) * | 2011-11-30 | 2012-03-14 | 江苏长电科技股份有限公司 | Foundation island-free ball grid array packaging structure and manufacturing method thereof |
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