CN102723289A - Normal chip single-faced three-dimensional circuit manufacture method by encapsulation prior to etching and normal chip single-faced three-dimensional circuit encapsulation structure - Google Patents

Normal chip single-faced three-dimensional circuit manufacture method by encapsulation prior to etching and normal chip single-faced three-dimensional circuit encapsulation structure Download PDF

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Publication number
CN102723289A
CN102723289A CN2012101900126A CN201210190012A CN102723289A CN 102723289 A CN102723289 A CN 102723289A CN 2012101900126 A CN2012101900126 A CN 2012101900126A CN 201210190012 A CN201210190012 A CN 201210190012A CN 102723289 A CN102723289 A CN 102723289A
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metal substrate
metal
pin
green lacquer
chip
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CN2012101900126A
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CN102723289B (en
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王新潮
李维平
梁志忠
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

The invention relates to a normal chip single-faced three-dimensional circuit manufacture method by encapsulation prior to etching. The method includes: taking a metal substrate; preplating copper to the metal substrate surface; coating with green paint; partially removing the green paint on the front of the metal substrate; electroplating inert a metal circuit layer; electroplating a metal circuit layer; coating with green paint; partially removing the green paint on the front of the metal substrate; electroplating a metal circuit layer; coating with green paint; partially removing the green paint on the front of the metal substrate; coating a circuit screen plate; performing metallization pretreatment; removing the circuit screen plate; electroplating metal circuit layer; coating bonding material; mounting a chip; performing metal circuit bonding; encapsulating; partially removing the green paint on the back of the metal substrate; performing chemical etching; electroplating a metal circuit layer; coating with green paint; reserving holes on the green paint; cleaning; attaching balls; and cutting finished products. The normal chip single-faced three-dimensional circuit manufacture method by encapsulation prior to etching has the advantages that manufacture cost is lowered, safety and reliability of encapsulation are enhanced, environmental pollution is reduced, and design and manufacture of high density circuit are really achieved.

Description

The three-dimensional circuit of chip formal dress single face is honored as a queen earlier and is lost manufacturing approach and encapsulating structure thereof
Technical field
The present invention relates to the three-dimensional circuit of a kind of chip formal dress single face be honored as a queen earlier erosion manufacturing approach and encapsulating structure thereof, belong to the semiconductor packaging field.
Background technology
The manufacturing process flow of traditional high-density base board encapsulating structure is as follows:
Step 1, referring to Figure 85, get the substrate that a glass fiber material is processed,
Step 2, referring to Figure 86, perforate on desired position on the glass fiber substrate,
Step 3, referring to Figure 87, at the back side of glass fiber substrate coating one deck Copper Foil,
Step 4, referring to Figure 88, insert conductive materials in the position of glass fiber substrate punching,
Step 5, referring to Figure 89, at positive coating one deck Copper Foil of glass fiber substrate,
Step 6, referring to Figure 90, the coating photoresistance film on glass fiber substrate surface,
Step 7, referring to Figure 91, the photoresistance film is carried out exposure imaging in the position of needs windows,
Step 8, referring to Figure 92, the part that completion is windowed is carried out etching,
Step 9, referring to Figure 93, the photoresistance film of substrate surface is divested,
Step 10, referring to Figure 94, carry out the coating of anti-welding lacquer (being commonly called as green lacquer) on the surface of copper foil circuit layer,
Step 11, referring to Figure 95, need carry out load and the zone of routing bonding of back operation at anti-welding lacquer and window,
Step 12, referring to Figure 96, electroplate in the zone that step 11 is windowed, form Ji Dao and pin relatively,
Step 13, accomplish follow-up load, routing, seal, concerned process steps such as cutting.
Above-mentioned traditional high-density base board encapsulating structure exists following deficiency and defective:
1, many glass fiber materials of one deck, same also many costs of layer of glass;
2, because must use glass fiber, so with regard to many thickness space of about 100 ~ 150 μ m of layer of glass thickness;
3, glass fiber itself is exactly a kind of foaming substance, so easily because time of placing and environment suck moisture and moisture, directly have influence on the security capabilities of reliability or the grade of reliability;
4, the fiberglass surfacing Copper Foil metal layer thickness of about 50 ~ 100 μ m of one deck that has been covered; And the etching of metal level circuit and circuit distance also because the etched gap that the characteristic of etching factor can only be accomplished 50 ~ 100 μ m (referring to Figure 97; Best making ability is that etched gap is equal to the thickness that is etched object approximately), so the design of accomplishing high-density line and manufacturing that can't be real;
5, because must use the Copper Foil metal level, and the Copper Foil metal level is the mode that the employing high pressure is pasted, so the thickness of Copper Foil is difficult to be lower than the thickness of 50 μ m, otherwise just is difficult to operation like out-of-flatness or Copper Foil breakage or Copper Foil extension displacement or the like;
6, also because the whole base plate material is to adopt glass fiber material, thus significantly increased thickness 100 ~ 150 μ m of glass layer, can't be real accomplish ultra-thin encapsulation;
7, the traditional glass fiber stick on Copper Foil technology because material property difference very big (coefficient of expansion) causes stress deformation easily in the operation of adverse circumstances, directly have influence on precision and element and substrate adherence and reliability that element loads.
Summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, provide the three-dimensional circuit of a kind of chip formal dress single face to be honored as a queen earlier and lose manufacturing approach and encapsulating structure thereof, its technology is simple; Need not use glass layer; Reduce manufacturing cost, improved the fail safe and the reliability of packaging body, reduced the environmental pollution that glass fiber material brings; And the metal substrate line layer adopts is electro-plating method, can really accomplish the design and the manufacturing of high-density line.
The objective of the invention is to realize like this: the three-dimensional circuit of a kind of chip formal dress single face erosion manufacturing approach of being honored as a queen earlier, it comprises following processing step:
Step 1, get metal substrate
Step 2, metallic substrate surfaces preplating copper material
Electroplate one deck copper material film in metallic substrate surfaces,
Step 3, green lacquer coating
Accomplish the metal substrate front and the back side of preplating copper material film in step 2 and carry out the lining of green lacquer,
Step 4, the positive green lacquer of part of removing of metal substrate
Utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 3 is accomplished green lacquer coating;
Step 5, plating inert metal line layer
The graphics field of windowing has been accomplished in step 4 metal substrate front has electroplated upward inert metal line layer,
Step 6, plated metal line layer
Inert metal line layer surface metal plated line layer in step 5,
Step 7, green lacquer coating
Accomplish the metal substrate front of plated metal line layer in step 6 and carry out the lining of green lacquer once more,
Step 8, the positive green lacquer of part of removing of metal substrate
Utilize exposure imaging equipment to carry out graph exposure, develop and window in the metal substrate front that step 7 is accomplished green lacquer coating, exposing the graphics field that the positive follow-up needs of metal substrate are electroplated,
Step 9, plated metal line layer
The graphics field of windowing has been accomplished in step 8 metal substrate front has electroplated upward metallic circuit layer,
Step 10, green lacquer coating
Accomplish the metal substrate front of plated metal line layer in step 9 and carry out the lining of green lacquer once more,
Step 11, the positive green lacquer of part of removing of metal substrate
Utilize exposure imaging equipment to carry out graph exposure, develop and window in the metal substrate front that step 10 is accomplished green lacquer coating, exposing the graphics field that the positive follow-up needs of metal substrate are electroplated,
Step 12, be covered with the circuit web plate
Be covered with the circuit web plate in the metal substrate front,
Step 13, metallization pre-treatment
The metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing has been accomplished in step 11 metal substrate front,
Step 14, remove the circuit web plate
The circuit web plate that metal substrate front in the step 12 is covered with removes,
Step 15, plated metal line layer
Upward metallic circuit layer is electroplated in the positive zone of accomplishing the pre-treatment of plated metal line layer of step 13 metal substrate; After electroplating and accomplish, said metallic circuit layer promptly forms the top of pin or Ji Dao and pin or Ji Dao, pin and static release ring relatively in the metal substrate front
Step 10 six, coating bonding material
When step 15 only forms pin top relatively, at pin top coated with conductive or nonconducting bonding material; When Ji Dao that relatively forms when step 15 and pin top or Ji Dao, pin and static release ring top, at basic island top front face coated with conductive or nonconducting bonding material,
Step 10 seven, load
On conduction that step 10 six pins or basic island top front face apply or non-conductive bonding material, carry out the implantation of chip,
Step 10 eight, metal wire bonding
Between chip front side and pin front, carry out the operation of bonding metal wire,
Step 10 nine, seal
The plastic packaging material operation is sealed in metal substrate front behind the step 10 eight completion load routings,
The green lacquer of part is removed at step 2 ten, the metal substrate back side
Utilize exposure imaging equipment that the green lacquer of metal substrate back side coating is carried out graph exposure, develops and windows, exposing the graphics field that the follow-up needs in the metal substrate back side carry out chemical etching,
Step 2 11, chemical etching
The graphics field of windowing is accomplished at the metal substrate back side in the step 2 ten carries out chemical etching,
Step 2 12, plated metal line layer
Accomplish the inert metal line layer surface of exposing after the chemical etching in step 2 11 and carry out the plating of metallic circuit layer; After electroplating and accomplish, the metallic circuit layer promptly forms the bottom of pin or Ji Dao and pin or Ji Dao, pin and static release ring relatively at the metal substrate back side
Step 2 13, green lacquer coating
The lining of green lacquer is carried out at the metal substrate back side in that step 2 12 is accomplished the plated metal line layer;
Step 2 14, the surperficial perforate of green lacquer
The follow-up perforate operation that will plant the metal ball zone is carried out on green lacquer surface in step 2 13 metal substrate back side coatings,
Step 2 15, cleaning
The green lacquer tapping in the step 2 14 metal substrate back sides is cleaned
Step 2 16, plant ball
The aperture of crossing cleaning at step 2 ten Five Classics is implanted into metal ball,
Step 2 17, cutting finished product
Step 2 16 is accomplished the semi-finished product of planting ball carry out cutting operation; Make originally to integrate and to contain more than cuttings of plastic-sealed body module of chip independent, make the three-dimensional circuit of chip formal dress single face and be honored as a queen earlier and lose the encapsulating structure finished product with array aggregate mode.
The three-dimensional circuit of a kind of chip formal dress single face is honored as a queen earlier and is lost the encapsulating structure of manufacturing approach, and it comprises pin, and said pin front is provided with chip through conduction or non-conductive bonding material; Be connected with metal wire between said chip front side and the pin front; The zone between zone, pin and the pin of said pin periphery and the zone of pin bottom are encapsulated with green lacquer, and the zone on said pin top and chip and metal wire are encapsulated with plastic packaging material outward, offer aperture on the green lacquer surface of said pin bottom; Said aperture is connected with the pin back side; Be provided with metal ball in the said aperture, said metal ball contacts with the pin back side
The green lacquer tapping in 15 pairs of metal substrate back sides of said step 2 cleans and carries out the coat of metal lining simultaneously.
Said encapsulating structure comprises Ji Dao, and this moment, chip was arranged at front, basic island through conduction or non-conductive bonding material.
Said Ji Dao has single or a plurality of.
Be provided with static release ring between said Ji Dao and the pin, be connected through metal wire between said static release ring front and the chip front side.
Compared with prior art, the present invention has following beneficial effect:
1, the present invention need not use glass layer, so can reduce the cost that glass layer brings;
2, the present invention does not use the foaming substance of glass layer, so the grade of reliability can improve again, the fail safe to packaging body will improve relatively;
3, the present invention need not use the glass layer material, so just can reduce the environmental pollution that glass fiber material brings;
What 4,3-dimensional metal substrate circuit layer of the present invention was adopted is electro-plating method; And the gross thickness of electrodeposited coating is about 10 ~ 15 μ m; And the gap between circuit and the circuit can reach the gap below the 25 μ m easily, so can accomplish the technical capability of pin circuit tiling in the high density veritably;
5,3-dimensional metal substrate of the present invention is the metal level galvanoplastic because of what adopt; So the technology than glass fiber high pressure Copper Foil metal level is come simply, and do not have metal level because high pressure produces bad or puzzled that metal level out-of-flatness, metal level breakage and metal level extend and be shifted;
6,3-dimensional metal substrate circuit layer of the present invention is to carry out metal plating on the surface of metal base; So the material characteristic is basic identical; So the internal stress of coating circuit and metal base is basic identical, can carries out the back engineering (like the surface mount work of high temperature eutectic load, high temperature tin material scolder load and high temperature passive device) of adverse circumstances easily and be not easy to produce stress deformation.
Description of drawings
Fig. 1 ~ Figure 27 is honored as a queen earlier for the three-dimensional circuit of chip formal dress single face of the present invention and loses each operation sketch map of manufacturing approach embodiment one.
Figure 28 is honored as a queen earlier for the three-dimensional circuit of chip formal dress single face of the present invention and loses the structural representation of encapsulating structure embodiment one.
Figure 29 ~ Figure 55 is honored as a queen earlier for the three-dimensional circuit of chip formal dress single face of the present invention and loses each operation sketch map of manufacturing approach embodiment two.
Figure 56 is honored as a queen earlier for the three-dimensional circuit of chip formal dress single face of the present invention and loses the structural representation of encapsulating structure embodiment two.
Figure 57 ~ Figure 83 is honored as a queen earlier for the three-dimensional circuit of chip formal dress single face of the present invention and loses each operation sketch map of manufacturing approach embodiment three.
Figure 84 is honored as a queen earlier for the three-dimensional circuit of chip formal dress single face of the present invention and loses the structural representation of encapsulating structure embodiment three.
Figure 85 ~ Figure 96 is each operation sketch map of the manufacturing process flow of traditional high-density base board encapsulating structure.
Figure 97 is the etching situation sketch map of fiberglass surfacing Copper Foil metal level.
Wherein:
Metal substrate 1
Copper material film 2
Green lacquer 3
Inert metal line layer 4
Metallic circuit layer 5
Circuit web plate 6
Metallization preprocessing layer 7
Conduction or non-conductive bonding material 8
Chip 9
Metal wire 10
Plastic packaging material 11
Aperture 12
Coat of metal 13
Metal ball 14
Pin 15
Base island 16
Static release ring 17.
Embodiment
The three-dimensional circuit of the chip formal dress single face of the present invention erosion manufacturing approach of being honored as a queen earlier comprises following processing step:
Embodiment one, no Ji Dao
Step 1, get metal substrate
Referring to Fig. 1, get the suitable metal substrate of a slice thickness, the material of said metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper material, iron material, ferronickel material or zinc-iron material etc.;
Step 2, metallic substrate surfaces preplating copper material
Referring to Fig. 2, electroplate one deck copper material film in metallic substrate surfaces, purpose is to do the basis for follow-up plating, the mode of said plating can adopt chemical plating or metallide;
Step 3, green lacquer coating
Referring to Fig. 3, accomplish the metal substrate front and the back side of preplating copper material film in step 2 and carry out the lining of green lacquer, to protect follow-up electroplated metal layer process operation;
Step 4, the positive green lacquer of part of removing of metal substrate
Referring to Fig. 4, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 3 is accomplished green lacquer coating;
Step 5, plating inert metal line layer
Referring to Fig. 5; The graphics field of windowing has been accomplished in step 4 metal substrate front electroplated upward inert metal line layer; As the barrier layer of subsequent etch operation, said inert metal wiring material layer adopts nickel, titanium or copper etc., and said plating mode adopts chemical plating or metallide mode;
Step 6, plated metal line layer
Referring to Fig. 6; Inert metal line layer surface metal plated line layer in step 5; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Step 7, green lacquer coating
Referring to Fig. 7, accomplish the metal substrate front of plated metal line layer in step 6 and carry out the lining of green lacquer once more, to protect follow-up electroplated metal layer process operation;
Step 8, the positive green lacquer of part of removing of metal substrate
Referring to Fig. 8, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 7 is accomplished green lacquer coating;
Step 9, plated metal line layer
Referring to Fig. 9; The graphics field of windowing has been accomplished in step 8 metal substrate front electroplated upward metallic circuit layer; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Step 10, green lacquer coating
Referring to Figure 10, accomplish the metal substrate front of plated metal line layer in step 9 and carry out the lining of green lacquer once more, to protect follow-up electroplated metal layer process operation;
Step 11, the positive green lacquer of part of removing of metal substrate
Referring to Figure 11, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 10 is accomplished green lacquer coating;
Step 12, be covered with the circuit web plate
Referring to Figure 12, be covered with the circuit web plate in the metal substrate front, the covering of circuit web plate is follow-up need not carry out metallized zone;
Step 13, metallization pre-treatment
Referring to Figure 13, the metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing has been accomplished in step 11 metal substrate front, said metallization pre-treatment mode can adopt modes such as coating, sprinkling, printing, showering or immersion;
Step 14, remove the circuit web plate
Referring to Figure 14, the circuit web plate that metal substrate front in the step 12 is covered with removes;
Step 15, plated metal line layer
Referring to Figure 15; Upward metallic circuit layer is electroplated in the positive zone of accomplishing the pre-treatment of plated metal line layer of step 13 metal substrate; After electroplating and accomplish, said metallic circuit layer promptly forms the top of pin relatively in the metal substrate front; Said metallic circuit layer can be a single or multiple lift, and said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Step 10 six, coating bonding material
Referring to Figure 16, at pin top front face coated with conductive or the nonconducting bonding material that step 15 relatively forms, purpose is to implant engaging of back and pin for follow-up chip;
Step 10 seven, load
Referring to Figure 17, on conduction that step 10 six pin top front face apply or non-conductive bonding material, carry out the implantation of chip;
The chip implantation can have single or a plurality of, when being a plurality of as if the chip of implanting, and the follow-up metal wire bonding operation that also will carry out between chip front side and the chip front side;
Step 10 eight, metal wire bonding
Referring to Figure 18, between chip front side and pin front, carry out the operation of bonding metal wire, the material of said metal wire adopts gold, silver, copper, aluminium or alloy material, the shape of metal wire can be thread also can be banded;
Step 10 nine, seal
Referring to Figure 19; The plastic packaging material operation is sealed in metal substrate front behind the step 10 eight completion load routings; The mode of sealing of plastic packaging material can adopt mould encapsulating mode, spraying method or brush coating mode, and said plastic packaging material can adopt packing material or not have the epoxy resin of packing material;
The green lacquer of part is removed at step 2 ten, the metal substrate back side
Referring to Figure 20, utilize exposure imaging equipment that the green lacquer of metal substrate back side coating is carried out graph exposure, develops and windows, to expose the graphics field that the follow-up needs in the metal substrate back side carry out chemical etching;
Step 2 11, chemical etching
Referring to Figure 21, the graphics field of windowing to be accomplished at the metal substrate back side in the step 2 ten carry out chemical etching, chemical etching is till the position of inert metal line layer, and etching liquid medicine can adopt copper chloride or iron chloride;
Step 2 12, plated metal line layer
Referring to Figure 22; Accomplish the inert metal line layer surface of exposing after the chemical etching in step 2 11 and carry out the plating of metallic circuit layer; After electroplating and accomplish, the metallic circuit layer promptly forms the bottom of pin relatively at the metal substrate back side; Said metallic circuit layer can be a single or multiple lift, and said metallic circuit layer material adopts copper nickel gold, copper nickeline, porpezite, gold or copper etc., and said electro-plating method can be electroless plating or metallide;
Step 2 13, green lacquer coating
Referring to Figure 23, carry out the lining of green lacquer at the metal substrate back side that step 2 12 is accomplished the plated metal line layer;
Step 2 14, the surperficial perforate of green lacquer
Referring to Figure 24, carry out the follow-up perforate operation that will plant the metal ball zone on the green lacquer surface of step 2 13 metal substrate back side coatings, said perforate mode can adopt dry laser sintering or wet chemistry corroding method;
Step 2 15, cleaning
Referring to Figure 25, the green lacquer tapping in the step 2 14 metal substrate back sides is cleaned to remove oxidation material or organic substance etc., can carry out the lining of coat of metal simultaneously, coat of metal adopts oxidation inhibitor;
Step 2 16, plant ball
Referring to Figure 26; The aperture of crossing cleaning at step 2 ten Five Classics is implanted into metal ball; Metal ball contacts with the back side of pin; The said ball mode of planting can adopt conventional ball attachment machine or adopt the paste printing after high-temperature digestion, can form orbicule again, and the material of metal ball can be pure tin or ashbury metal;
Step 2 17, cutting finished product
Referring to Figure 27; Step 2 16 is accomplished the semi-finished product of planting ball carry out cutting operation; Make originally to integrate and to contain more than cuttings of plastic-sealed body module of chip independent, make the three-dimensional circuit of chip formal dress single face and be honored as a queen earlier and lose the encapsulating structure finished product with array aggregate mode.
The encapsulating structure of embodiment one is following:
Referring to Figure 28, the three-dimensional circuit of the chip formal dress single face of the present invention erosion encapsulating structure of being honored as a queen earlier, it comprises pin 15; Said pin 15 fronts are provided with chip 9 through conduction or non-conductive bonding material 8; Said chip 9 positive with pin 15 fronts between be connected with metal wire 10, the zone between peripheral zone, pin 15 and the pin 15 of said pin 15 and the zone of pin 15 bottoms are encapsulated with green lacquer 3, the zone on said pin 15 tops and chip 9 and metal wire 10 are encapsulated with plastic packaging materials 11 outward; Offer aperture 12 on green lacquer 3 surfaces of said pin 15 bottoms; Said aperture 12 is connected with pin 15 back sides, is provided with metal ball 14 in the said aperture 12, and said metal ball 14 contacts with pin 15 back sides; Be provided with coat of metal 13 between the said metal ball 14 and pin 15 back sides, said coat of metal 13 is an oxidation inhibitor.
Embodiment two, Ji Dao is arranged
Step 1, get metal substrate
Referring to Figure 29, get the suitable metal substrate of a slice thickness, the material of said metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper material, iron material, ferronickel material or zinc-iron material etc.;
Step 2, metallic substrate surfaces preplating copper material
Referring to Figure 30, electroplate one deck copper material film in metallic substrate surfaces, purpose is to do the basis for follow-up plating, the mode of said plating can adopt chemical plating or metallide;
Step 3, green lacquer coating
Referring to Figure 31, accomplish the metal substrate front and the back side of preplating copper material film in step 2 and carry out the lining of green lacquer, to protect follow-up electroplated metal layer process operation;
Step 4, the positive green lacquer of part of removing of metal substrate
Referring to Figure 32, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 3 is accomplished green lacquer coating;
Step 5, plating inert metal line layer
Referring to Figure 33; The graphics field of windowing has been accomplished in step 4 metal substrate front electroplated upward inert metal line layer; As the barrier layer of subsequent etch operation, said inert metal wiring material layer adopts nickel, titanium or copper etc., and said plating mode adopts chemical plating or metallide mode;
Step 6, plated metal line layer
Referring to Figure 34; Inert metal line layer surface metal plated line layer in step 5; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Step 7, green lacquer coating
Referring to Figure 35, accomplish the metal substrate front of plated metal line layer in step 6 and carry out the lining of green lacquer once more, to protect follow-up electroplated metal layer process operation;
Step 8, the positive green lacquer of part of removing of metal substrate
Referring to Figure 36, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 7 is accomplished green lacquer coating;
Step 9, plated metal line layer
Referring to Figure 37; The graphics field of windowing has been accomplished in step 8 metal substrate front electroplated upward metallic circuit layer; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Step 10, green lacquer coating
Referring to Figure 38, accomplish the metal substrate front of plated metal line layer in step 9 and carry out the lining of green lacquer once more, to protect follow-up electroplated metal layer process operation;
Step 11, the positive green lacquer of part of removing of metal substrate
Referring to Figure 39, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 10 is accomplished green lacquer coating;
Step 12, be covered with the circuit web plate
Referring to Figure 40, be covered with the circuit web plate in the metal substrate front, the covering of circuit web plate is follow-up need not carry out metallized zone;
Step 13, metallization pre-treatment
Referring to Figure 41, the metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing has been accomplished in step 11 metal substrate front, said metallization pre-treatment mode can adopt modes such as coating, sprinkling, printing or showering;
Step 14, remove the circuit web plate
Referring to Figure 42, the circuit web plate that metal substrate front in the step 12 is covered with removes;
Step 15, plated metal line layer
Referring to Figure 43; Upward metallic circuit layer is electroplated in the positive zone of accomplishing the pre-treatment of plated metal line layer of step 13 metal substrate; After electroplating and accomplish, said metallic circuit layer promptly forms the top of Ji Dao and pin relatively in the metal substrate front; Said metallic circuit layer can be a single or multiple lift, and said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Step 10 six, coating bonding material
Referring to Figure 44, at basic island top front face coated with conductive or the nonconducting bonding material that step 15 relatively forms, purpose is to implant engaging of back and pin for follow-up chip;
Step 10 seven, load
Referring to Figure 45, on conduction that step palmityl island top front face applies or non-conductive bonding material, carry out the implantation of chip;
The chip implantation can have single or a plurality of, when being a plurality of as if the chip of implanting, and the follow-up metal wire bonding operation that also will carry out between chip front side and the chip front side;
Step 10 eight, metal wire bonding
Referring to Figure 46, between chip front side and pin front, carry out the operation of bonding metal wire, the material of said metal wire adopts gold, silver, copper, aluminium or alloy material, the shape of metal wire can be thread also can be banded;
Step 10 nine, seal
Referring to Figure 47; The plastic packaging material operation is sealed in metal substrate front behind the step 10 eight completion load routings; The mode of sealing of plastic packaging material can adopt mould encapsulating mode, spraying method or brush coating mode, and said plastic packaging material can adopt packing material or not have the epoxy resin of packing material;
The green lacquer of part is removed at step 2 ten, the metal substrate back side
Referring to Figure 48, utilize exposure imaging equipment that the green lacquer of metal substrate back side coating is carried out graph exposure, develops and windows, to expose the graphics field that the follow-up needs in the metal substrate back side carry out chemical etching;
Step 2 11, chemical etching
Referring to Figure 49, the graphics field of windowing to be accomplished at the metal substrate back side in the step 2 ten carry out chemical etching, chemical etching is till the position of inert metal line layer, and etching liquid medicine can adopt copper chloride or iron chloride;
Step 2 12, plated metal line layer
Referring to Figure 50; Accomplish the inert metal line layer surface of exposing after the chemical etching in step 2 11 and carry out the plating of metallic circuit layer; After electroplating and accomplish, the metallic circuit layer promptly forms the bottom of Ji Dao and pin relatively at the metal substrate back side; Said metallic circuit layer can be a single or multiple lift, and said metallic circuit layer material adopts copper nickel gold, copper nickeline, porpezite, gold or copper etc., and said electro-plating method can be electroless plating or metallide;
Step 2 13, green lacquer coating
Referring to Figure 51, carry out the lining of green lacquer at the metal substrate back side that step 2 12 is accomplished the plated metal line layer;
Step 2 14, the surperficial perforate of green lacquer
Referring to Figure 52, carry out the follow-up perforate operation that will plant the metal ball zone on the green lacquer surface of step 2 13 metal substrate back side coatings, said perforate mode can adopt dry laser sintering or wet chemistry corroding method;
Step 2 15, cleaning
Referring to Figure 53, the green lacquer tapping in the step 2 14 metal substrate back sides is cleaned to remove oxidation material or organic substance etc., can carry out the lining of coat of metal simultaneously, coat of metal adopts oxidation inhibitor;
Step 2 16, plant ball
Referring to Figure 54; The aperture of crossing cleaning at step 2 ten Five Classics is implanted into metal ball; Metal ball contacts with the back side of pin; The said ball mode of planting can adopt conventional ball attachment machine or adopt the paste printing after high-temperature digestion, can form orbicule again, and the material of metal ball can be pure tin or ashbury metal;
Step 2 17, cutting finished product
Referring to Figure 55; Step 2 16 is accomplished the semi-finished product of planting ball carry out cutting operation; Make originally to integrate and to contain more than cuttings of plastic-sealed body module of chip independent, make the three-dimensional circuit of chip formal dress single face and be honored as a queen earlier and lose the encapsulating structure finished product with array aggregate mode.
The encapsulating structure of embodiment two is following:
Referring to Figure 56; The three-dimensional circuit of the chip formal dress single face of the present invention erosion encapsulating structure of being honored as a queen earlier; It comprises basic island 16 and pin 15, and 16 fronts, said basic island are provided with chip 9 through conduction or non-conductive bonding material 8, said chip 9 positive with pin 15 fronts between be connected with metal wire 10; The zone between zone, pin 15 and the pin 15 between zone, basic island 16 and the pin 15 of 16 peripheries, said basic island and the zones of basic island 16 and pin 16 bottoms are encapsulated with green lacquer 3; Be encapsulated with plastic packaging material 11 outside the zone on said basic island 16 and pin 15 tops and chip 9 and the metal wire 10, offer aperture 12 on green lacquer 3 surfaces of said pin 15 bottoms, said aperture 12 is connected with pin 15 back sides; Be provided with metal ball 14 in the said aperture 12; Said metal ball 14 contacts with pin 15 back sides, is provided with coat of metal 13 between the said metal ball 14 and pin 15 back sides, and said coat of metal 13 is an oxidation inhibitor.
Embodiment three, basic island static release ring is arranged
Step 1, get metal substrate
Referring to Figure 57, get the suitable metal substrate of a slice thickness, the material of said metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper material, iron material, ferronickel material or zinc-iron material etc.;
Step 2, metallic substrate surfaces preplating copper material
Referring to Figure 58, electroplate one deck copper material film in metallic substrate surfaces, purpose is to do the basis for follow-up plating, the mode of said plating can adopt chemical plating or metallide;
Step 3, green lacquer coating
Referring to Figure 59, accomplish the metal substrate front and the back side of preplating copper material film in step 2 and carry out the lining of green lacquer, to protect follow-up electroplated metal layer process operation;
Step 4, the positive green lacquer of part of removing of metal substrate
Referring to Figure 60, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 3 is accomplished green lacquer coating;
Step 5, plating inert metal line layer
Referring to Figure 61; The graphics field of windowing has been accomplished in step 4 metal substrate front electroplated upward inert metal line layer; As the barrier layer of subsequent etch operation, said inert metal wiring material layer adopts nickel, titanium or copper etc., and said plating mode adopts chemical plating or metallide mode;
Step 6, plated metal line layer
Referring to Figure 62; Inert metal line layer surface metal plated line layer in step 5; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Step 7, green lacquer coating
Referring to Figure 63, accomplish the metal substrate front of plated metal line layer in step 6 and carry out the lining of green lacquer once more, to protect follow-up electroplated metal layer process operation;
Step 8, the positive green lacquer of part of removing of metal substrate
Referring to Figure 64, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 7 is accomplished green lacquer coating;
Step 9, plated metal line layer
Referring to Figure 65; The graphics field of windowing has been accomplished in step 8 metal substrate front electroplated upward metallic circuit layer; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Step 10, green lacquer coating
Referring to Figure 66, accomplish the metal substrate front of plated metal line layer in step 9 and carry out the lining of green lacquer once more, to protect follow-up electroplated metal layer process operation;
Step 11, the positive green lacquer of part of removing of metal substrate
Referring to Figure 67, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 10 is accomplished green lacquer coating;
Step 12, be covered with the circuit web plate
Referring to Figure 68, be covered with the circuit web plate in the metal substrate front, the covering of circuit web plate is follow-up need not carry out metallized zone;
Step 13, metallization pre-treatment
Referring to Figure 69, the metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing has been accomplished in step 11 metal substrate front, said metallization pre-treatment mode can adopt modes such as coating, sprinkling, printing, showering or immersion;
Step 14, remove the circuit web plate
Referring to Figure 70, the circuit web plate that metal substrate front in the step 12 is covered with removes;
Step 15, plated metal line layer
Referring to Figure 71; Upward metallic circuit layer is electroplated in the positive zone of accomplishing the pre-treatment of plated metal line layer of step 13 metal substrate; After electroplating and accomplish, said metallic circuit layer promptly forms the top of Ji Dao, pin and static release ring relatively in the metal substrate front; Said metallic circuit layer can be a single or multiple lift, and said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Step 10 six, coating bonding material
Referring to Figure 72, at basic island top front face coated with conductive or the nonconducting bonding material that step 15 relatively forms, purpose is to implant engaging of back and pin for follow-up chip;
Step 10 seven, load
Referring to Figure 73, on conduction that step palmityl island top front face applies or non-conductive bonding material, carry out the implantation of chip;
The chip implantation can have single or a plurality of, when being a plurality of as if the chip of implanting, and the follow-up metal wire bonding operation that also will carry out between chip front side and the chip front side;
Step 10 eight, metal wire bonding
Referring to Figure 74; Carrying out the operation of bonding metal wire between chip front side and the pin front and between chip front side and the static release ring; The material of said metal wire adopts gold, silver, copper, aluminium or alloy material, the shape of metal wire can be thread also can be banded;
Step 10 nine, seal
Referring to Figure 75; The plastic packaging material operation is sealed in metal substrate front behind the step 10 eight completion load routings; The mode of sealing of plastic packaging material can adopt mould encapsulating mode, spraying method or brush coating mode, and said plastic packaging material can adopt packing material or not have the epoxy resin of packing material;
The green lacquer of part is removed at step 2 ten, the metal substrate back side
Referring to Figure 76, utilize exposure imaging equipment that the green lacquer of metal substrate back side coating is carried out graph exposure, develops and windows, to expose the graphics field that the follow-up needs in the metal substrate back side carry out chemical etching;
Step 2 11, chemical etching
Referring to Figure 77, the graphics field of windowing to be accomplished at the metal substrate back side in the step 2 ten carry out chemical etching, chemical etching is till the position of inert metal line layer, and etching liquid medicine can adopt copper chloride or iron chloride;
Step 2 12, plated metal line layer
Referring to Figure 78; Accomplish the inert metal line layer surface of exposing after the chemical etching in step 2 11 and carry out the plating of metallic circuit layer; After electroplating and accomplish, the metallic circuit layer promptly forms the bottom of Ji Dao, pin and static release ring relatively at the metal substrate back side; Said metallic circuit layer can be a single or multiple lift, and said metallic circuit layer material adopts copper nickel gold, copper nickeline, porpezite, gold or copper etc., and said electro-plating method can be electroless plating or metallide;
Step 2 13, green lacquer coating
Referring to Figure 79, carry out the lining of green lacquer at the metal substrate back side that step 2 12 is accomplished the plated metal line layer;
Step 2 14, the surperficial perforate of green lacquer
Referring to Figure 80, carry out the follow-up perforate operation that will plant the metal ball zone on the green lacquer surface of step 2 13 metal substrate back side coatings, said perforate mode can adopt dry laser sintering or wet chemistry corroding method;
Step 2 15, cleaning
Referring to Figure 81, the green lacquer tapping in the step 2 14 metal substrate back sides is cleaned to remove oxidation material or organic substance etc., can carry out the lining of coat of metal simultaneously, coat of metal adopts oxidation inhibitor;
Step 2 16, plant ball
Referring to Figure 82; The aperture of crossing cleaning at step 2 ten Five Classics is implanted into metal ball; Metal ball contacts with the back side of pin; The said ball mode of planting can adopt conventional ball attachment machine or adopt the paste printing after high-temperature digestion, can form orbicule again, and the material of metal ball can be pure tin or ashbury metal;
Step 2 17, cutting finished product
Referring to Figure 93; Step 2 16 is accomplished the semi-finished product of planting ball carry out cutting operation; Make originally to integrate and to contain more than cuttings of plastic-sealed body module of chip independent, make the three-dimensional circuit of chip formal dress single face and be honored as a queen earlier and lose the encapsulating structure finished product with array aggregate mode.
The encapsulating structure of embodiment three is following:
Referring to Figure 84; The three-dimensional circuit of the chip formal dress single face of the present invention erosion encapsulating structure of being honored as a queen earlier; It comprises basic island 16 and pin 15; Be provided with static release ring 17 between said basic island 16 and the pin 15,16 fronts, said basic island are provided with chip 9 through conduction or non-conductive bonding material 8, said chip 9 positive with pin 15 fronts between and be connected with metal wire 10 between chip 9 fronts and the static release ring 17; The zone between zone, pin 15 and the pin 15 between zone, basic island 16 and the pin 15 of 16 peripheries, said basic island and the zones of basic island 16 and pin 15 bottoms are encapsulated with green lacquer 3; Be encapsulated with plastic packaging material 11 outside the zone on said basic island 16 and pin 15 tops and chip 9 and the metal wire 10, offer aperture 12 on green lacquer 3 surfaces of said pin 15 bottoms, said aperture 12 is connected with pin 15 back sides; Be provided with metal ball 14 in the said aperture 12; Said metal ball 14 contacts with pin 15 back sides, is provided with coat of metal 13 between the said metal ball 14 and pin 15 back sides, and said coat of metal 13 is an oxidation inhibitor.

Claims (6)

1. the three-dimensional circuit of the chip formal dress single face erosion manufacturing approach of being honored as a queen earlier is characterized in that said method comprises following processing step:
Step 1, get metal substrate
Step 2, metallic substrate surfaces preplating copper material
Electroplate one deck copper material film in metallic substrate surfaces,
Step 3, green lacquer coating
Accomplish the metal substrate front and the back side of preplating copper material film in step 2 and carry out the lining of green lacquer,
Step 4, the positive green lacquer of part of removing of metal substrate
Utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 3 is accomplished green lacquer coating;
Step 5, plating inert metal line layer
The graphics field of windowing has been accomplished in step 4 metal substrate front has electroplated upward inert metal line layer,
Step 6, plated metal line layer
Inert metal line layer surface metal plated line layer in step 5,
Step 7, green lacquer coating
Accomplish the metal substrate front of plated metal line layer in step 6 and carry out the lining of green lacquer once more,
Step 8, the positive green lacquer of part of removing of metal substrate
Utilize exposure imaging equipment to carry out graph exposure, develop and window in the metal substrate front that step 7 is accomplished green lacquer coating, exposing the graphics field that the positive follow-up needs of metal substrate are electroplated,
Step 9, plated metal line layer
The graphics field of windowing has been accomplished in step 8 metal substrate front has electroplated upward metallic circuit layer,
Step 10, green lacquer coating
Accomplish the metal substrate front of plated metal line layer in step 9 and carry out the lining of green lacquer once more,
Step 11, the positive green lacquer of part of removing of metal substrate
Utilize exposure imaging equipment to carry out graph exposure, develop and window in the metal substrate front that step 10 is accomplished green lacquer coating, exposing the graphics field that the positive follow-up needs of metal substrate are electroplated,
Step 12, be covered with the circuit web plate
Be covered with the circuit web plate in the metal substrate front,
Step 13, metallization pre-treatment
The metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing has been accomplished in step 11 metal substrate front,
Step 14, remove the circuit web plate
The circuit web plate that metal substrate front in the step 12 is covered with removes,
Step 15, plated metal line layer
Upward metallic circuit layer is electroplated in the positive zone of accomplishing the pre-treatment of plated metal line layer of step 13 metal substrate; After electroplating and accomplish, said metallic circuit layer promptly forms the top of pin or Ji Dao and pin or Ji Dao, pin and static release ring relatively in the metal substrate front
Step 10 six, coating bonding material
When step 15 only forms pin top relatively, at pin top coated with conductive or nonconducting bonding material; When Ji Dao that relatively forms when step 15 and pin top or Ji Dao, pin and static release ring top, at basic island top front face coated with conductive or nonconducting bonding material,
Step 10 seven, load
On conduction that step 10 six pins or basic island top front face apply or non-conductive bonding material, carry out the implantation of chip,
Step 10 eight, metal wire bonding
Between chip front side and pin front, carry out the operation of bonding metal wire,
Step 10 nine, seal
The plastic packaging material operation is sealed in metal substrate front behind the step 10 eight completion load routings,
The green lacquer of part is removed at step 2 ten, the metal substrate back side
Utilize exposure imaging equipment that the green lacquer of metal substrate back side coating is carried out graph exposure, develops and windows, exposing the graphics field that the follow-up needs in the metal substrate back side carry out chemical etching,
Step 2 11, chemical etching
The graphics field of windowing is accomplished at the metal substrate back side in the step 2 ten carries out chemical etching,
Step 2 12, plated metal line layer
Accomplish the inert metal line layer surface of exposing after the chemical etching in step 2 11 and carry out the plating of metallic circuit layer; After electroplating and accomplish, the metallic circuit layer promptly forms the bottom of pin or Ji Dao and pin or Ji Dao, pin and static release ring relatively at the metal substrate back side
Step 2 13, green lacquer coating
The lining of green lacquer is carried out at the metal substrate back side in that step 2 12 is accomplished the plated metal line layer;
Step 2 14, the surperficial perforate of green lacquer
The follow-up perforate operation that will plant the metal ball zone is carried out on green lacquer surface in step 2 13 metal substrate back side coatings,
Step 2 15, cleaning
The green lacquer tapping in the step 2 14 metal substrate back sides is cleaned
Step 2 16, plant ball
The aperture of crossing cleaning at step 2 ten Five Classics is implanted into metal ball,
Step 2 17, cutting finished product
Step 2 16 is accomplished the semi-finished product of planting ball carry out cutting operation; Make originally to integrate and to contain more than cuttings of plastic-sealed body module of chip independent, make the three-dimensional circuit of chip formal dress single face and be honored as a queen earlier and lose the encapsulating structure finished product with array aggregate mode.
2. be honored as a queen earlier encapsulating structure of erosion manufacturing approach of the three-dimensional circuit of chip formal dress single face according to claim 1; It is characterized in that: it comprises pin (15); Said pin (15) is positive to be provided with chip (9) through conduction or non-conductive bonding material (8); Said chip (9) positive with pin (15) front between be connected with metal wire (10); The zone between zone, pin (15) and the pin (15) of said pin (15) periphery and the zone of pin (15) bottom are encapsulated with green lacquer (3); The zone on said pin (15) top and chip (9) and metal wire (10) are outer to be encapsulated with plastic packaging material (11), offers aperture (12) on green lacquer (3) surface of said pin (15) bottom, and said aperture (12) is connected with pin (15) back side; Be provided with metal ball (14) in the said aperture (12), said metal ball (14) contacts with pin (15) back side.
3. the three-dimensional circuit of a kind of chip formal dress single face according to claim 1 erosion manufacturing approach of being honored as a queen earlier, it is characterized in that: the green lacquer tapping in 15 pairs of metal substrate back sides of said step 2 cleans and carries out the coat of metal lining simultaneously.
4. the three-dimensional circuit of a kind of chip formal dress single face according to claim 2 is honored as a queen earlier and is lost the encapsulating structure of manufacturing approach; It is characterized in that: said encapsulating structure comprises Ji Dao (16), and chip this moment (9) is arranged at Ji Dao (16) front through conduction or non-conductive bonding material (8).
5. the three-dimensional circuit of a kind of chip formal dress single face according to claim 4 is honored as a queen earlier and is lost the encapsulating structure of manufacturing approach, and it is characterized in that: said Ji Dao (16) has single or a plurality of.
6. the three-dimensional circuit of a kind of chip formal dress single face according to claim 4 is honored as a queen earlier and is lost the encapsulating structure of manufacturing approach; It is characterized in that: be provided with static release ring (17) between said Ji Dao (16) and the pin (15), said static release ring (17) positive with chip (9) front between be connected through metal wire (10).
CN2012101900126A 2012-06-09 2012-06-09 Manufacture method of normal chip single-faced three-dimensional circuit by manufactured by encapsulation prior to etching and normal chip single-faced three-dimensional circuit encapsulation structure Active CN102723289B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103400773A (en) * 2013-08-06 2013-11-20 江苏长电科技股份有限公司 Packaging-prior-to-etching passive device type three-dimensional system-level metal circuit board structure and process method thereof
CN103400772A (en) * 2013-08-06 2013-11-20 江苏长电科技股份有限公司 Packaging-prior-to-etching chip-normally-bonded type three-dimensional system-level metal circuit board structure and process method thereof
CN103515249A (en) * 2013-08-06 2014-01-15 江苏长电科技股份有限公司 Firstly-packaged secondly-etched three-dimensional system level chip front-installed bump packaged structure and technology method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004327903A (en) * 2003-04-28 2004-11-18 Dainippon Printing Co Ltd Resin sealed semiconductor device and its manufacturing method
CN1691314A (en) * 2004-04-21 2005-11-02 美龙翔微电子科技（深圳）有限公司 Flip ball grid array packaging base plate and making technique thereof
CN101840901A (en) * 2010-04-30 2010-09-22 江苏长电科技股份有限公司 Lead frame structure of static release ring without paddle and production method thereof
CN102005432A (en) * 2010-09-30 2011-04-06 江苏长电科技股份有限公司 Packaging structure with four pin-less sides and packaging method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004327903A (en) * 2003-04-28 2004-11-18 Dainippon Printing Co Ltd Resin sealed semiconductor device and its manufacturing method
CN1691314A (en) * 2004-04-21 2005-11-02 美龙翔微电子科技（深圳）有限公司 Flip ball grid array packaging base plate and making technique thereof
CN101840901A (en) * 2010-04-30 2010-09-22 江苏长电科技股份有限公司 Lead frame structure of static release ring without paddle and production method thereof
CN102005432A (en) * 2010-09-30 2011-04-06 江苏长电科技股份有限公司 Packaging structure with four pin-less sides and packaging method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103400773A (en) * 2013-08-06 2013-11-20 江苏长电科技股份有限公司 Packaging-prior-to-etching passive device type three-dimensional system-level metal circuit board structure and process method thereof
CN103400772A (en) * 2013-08-06 2013-11-20 江苏长电科技股份有限公司 Packaging-prior-to-etching chip-normally-bonded type three-dimensional system-level metal circuit board structure and process method thereof
CN103515249A (en) * 2013-08-06 2014-01-15 江苏长电科技股份有限公司 Firstly-packaged secondly-etched three-dimensional system level chip front-installed bump packaged structure and technology method thereof
CN103515249B (en) * 2013-08-06 2016-02-24 江苏长电科技股份有限公司 First be honored as a queen and lose three-dimensional systematic chip formal dress bump packaging structure and process
CN103400773B (en) * 2013-08-06 2016-06-08 江阴芯智联电子科技有限公司 First it is honored as a queen and loses passive device three-dimensional systematic metal circuit board structure and process
CN103400772B (en) * 2013-08-06 2016-08-17 江阴芯智联电子科技有限公司 First it is honored as a queen and loses chip formal dress three-dimensional systematic metallic circuit plate structure and process

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