TWI355726B - Semiconductor package enhancing variation of movab - Google Patents

Abstract

Disclosed is a semiconductor package enhancing variation of movability at external ball terminals. A chip is disposed on a substrate by a die-bonding adhesive. The substrate has at least a stepwise groove on its carrying substrate so that the thickness of the substrate is gradually thinned toward a direction away from a central line of the chip. Additionally, the die-bonding adhesive fills in the stepwise groove. Accordingly, the die-bonding adhesive has a greater thickness as closer to side(s) of the chip. Under the conditions not to change product appearance, dimensions and thickness and the bonding plane for external ball terminals, some of the external ball terminals far away from the central line of the chip possess a better enhanced movability with respect to the chip. The ones of the external ball terminals located at side(s) or corner(s) of the semiconductor package can absorb more serious stress without breakage or ball dropping. Moreover, the stepwise groove offer a lager accommodation for the die-bonding adhesive to reduce die-bonding adhesive bleeding contamination.

Description

13^55726 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device using a semiconductor package technology, and more particularly to a semiconductor package structure having a movable gain variation of an external ball point to increase the temperature Product reliability for cycle test performance. [Prior Art] The semiconductor package structure of the semiconductor package is different in the semiconductor package structure, and there are various package types. The so-called ball (four) column division (four) • coffee y, inspection) package structure, is set on the bottom of the product, for example, a small ball reflow to form a ball point (generally called solder ball or solder ball). The external ball point should be formed on the same bonding plane and have an appropriate enough number to be used as an input/output connection L (i/〇 connecting terminal) of the semiconductor package structure, so as to be electrically connected to the external printed circuit board during operation. Relationship to meet the needs of high-density surface bonding. Usually the bonding plane is the exposed surface of the substrate. In the semiconductor packaging process, the substrate can be subjected to various heat treatments such as baking curing of the adhesive paste, curing of the sealant, and reflow of the external ball point. And when the m-body seal structure is used for calculation or thermal cycle test (TCT), due to the difference in coefficient of thermal expansion (CTE) mismatch, the semiconductor package structure and the external printed circuit board will Thermal stress is generated, which is particularly likely to act on the periphery of the substrate or the corners of the substrate and the circumscribing ball adjacent to the edge of the wafer, resulting in warpage of the substrate and cracking of the solder ball, resulting in low product reliability. In addition, in the dr〇p test, the circumscribing ball point (or edge ball and corner 6 6557% croquet) located at the periphery or corner of the substrate is susceptible to impact stress and falling off the ball. As shown in FIG. 1 , a conventional semiconductor package structure 100 is a window type ball grid array type mainly comprising a substrate 11 , a die bond 12 , a wafer 130 , and a plurality of first rows of external ball points. Ι4〇 and a plurality of second row of external ball points 150. The substrate 11 has a package surface m, an exposed surface 112, and a through-hole 115 as a window. The exposed surface 112 of the substrate 11 is formed with a solder mask layer 117 which exposes a plurality of internal fingers 116 and a plurality of external pads 118 for bonding a plurality of electrical connection elements 16 And the external ball points 140, 150. The adhesive layer 120 is formed on the package surface η of the substrate 并 and adheres to the wafer 130 so that the wafer 13 can be disposed on the substrate 11 。. The active surface of the wafer 130 has a plurality of pads 132. The plurality of electrical connection elements 160 (such as wire bonds formed by wire bonding) can be connected to the pads 132 through the through slots 115. The internal fingers 116 electrically interconnect the wafer 130 with the substrate 11. A glue body 17 is disposed on the package surface 111 of the substrate 110 and the through hole 11 5 in a stamper φ manner to: seal the wafer 130 and the electrical connection elements i 6 〇 . The first row of external ball points 140 are disposed on the exposed surface 112 of the substrate 1 (), and the second row of external ball points 15 are disposed on the exposed surface 112 of the substrate 11 The outer pads 118 are further away from the through slots 115 with respect to the first row of external ball points 14〇, so the center point distances of the second row of external ball points 15〇 are (distance hits (3) hits point, DNP) is greater than the center point distance of the first row of external ball points 14〇. Therefore, the second row of external ball points 15 is adjacent to the edge of the substrate u 7 7 1355726 or the corners to become a stress concentration. However, in the curing of the above-mentioned adhesive glue 丨2〇, the curing of the sealant 丄7〇, the first row of the external ball point 14〇 and the second row of the external ball point 150 are re-welded or It is the subsequent thermal cycle test and the actual product calculation, etc., there will be heat treatment, the difference in thermal expansion coefficient between the materials will cause thermal stress, or impact stress will be generated in the fall test, these stresses will be applied to the first row of circumscribed balls Point 1 50 causes breakage and ball drop problems, affecting the quality of electrical connections. In addition, the substrate 11 is susceptible to warpage problems. A portion of the circumscribing ball 14 〇 or 15 邻近 adjacent to the corner U 131 of the wafer also has a problem of breakage and drop. In addition, during the temperature rise and pressure application of the viscous crystal, the viscous gel 12 has fluidity and is prone to λ. overflow or creeping. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a semiconductor package structure in which an external ball point has a movable gain variation, and the appearance of the product is 'size and thickness' and the joint plane of the external ball point. The closer the 'adhesive knee' is closer to the edge of the substrate, the greater the thickness, so that the external ball point farther away from the -h line of the wafer can produce a larger movable gain variation with respect to the wafer, so the semiconductor package is constructed An external ball point at its edge or corner can withstand greater stress without breaking or dropping the ball. A second object of the present invention is to provide an external ball point having a movable "semiconductor package structure" capable of providing a thicker adhesive layer at the side corners of the wafer, which can reduce the application of the side edge of the wafer to the external ball point. The stress of the invention avoids the occurrence of breakage of the external ball point. A further object of the present invention is to provide a semiconductor package structure in which the external ball point has a movable change of 8 13*55726, and the stepped groove of the substrate is used to provide the die-bonding crystal. The object of the present invention and the technical problem of the present invention are achieved by the following technical solutions. According to the present invention, a semiconductor package structure having a movable gain variation of an external ball point mainly comprises a a substrate, a die bond adhesive, a wafer, a plurality of first row of external ball points, and a plurality of second row of external ball points. The substrate has a package surface and an exposed surface, wherein the package surface comprises a die bond The adhesive layer is formed on the surface of the package of the substrate. The wafer is aligned with the die bond region and is provided by the adhesive bond material. On the package surface of the substrate, the first rows of external ball points are disposed on the exposed surface of the substrate, and the second rows of external ball points are disposed on the exposed surface of the substrate, and relative to the The first row of external ball points is further away from the center line of the die bonding region, wherein the substrate further has at least one stepped groove formed on the surface of the package such that the thickness of the substrate in the stepped groove is The stepped thinning is generated in a direction away from the center line of the viscous crystal region, and the viscous gel material is filled in the stepped groove. The object of the present invention and solving the technical problem thereof can be further realized by the following technical measures. In the foregoing semiconductor package structure, the second row of external ball points can be aligned within the coverage area of the stepped groove. In the foregoing semiconductor package structure, the second row of external ball points are Two adjacent symmetrical parallel edges may be adjacent to the stepped recess. In the foregoing semiconductor package construction, the second row of circumscribing points may be adjacent to the periphery of the stepped recess. 9 13.55726 In the foregoing semiconductor package structure, the substrate has a first substrate thickness on the first row of external ball points by the stepped groove, and the substrate has one on the second row of external ball points. The thickness of the second substrate, wherein the thickness of the second substrate is less than the thickness of the first substrate. In the foregoing semiconductor package structure, the wafer system may have a side corner contacting the adhesive, which is associated with the substrate. The arrangement direction of the second row of circumscribed balls is substantially parallel, and the stepped groove has an edge outside the die bond region and parallel to the side corner. In the foregoing semiconductor package structure, the die bond The thickness of the material between the side edges to the second row of external ball points may be greater than the thickness of the substrate between the side edges to the second row of external ball points. The middle portion may further comprise a plurality of electrical connecting elements electrically connecting the wafer to the substrate. In the semiconductor package structure described above, the electrical connecting elements may comprise a plurality of bonding wires. In the foregoing semiconductor package structure, the substrate may have a through hole extending through the package surface and the exposed surface for the passage of the electrical connection elements. In the semiconductor package structure described above, a gel may be further formed on the surface of the package and the through-hole. In the foregoing semiconductor package construction, a second wafer may be further disposed on the wafer back to back. In the semiconductor package construction described above, the substrate may have a plurality of internal layers formed on the surface of the package and outside the stepped grooves. 13*55726 fingers 216 and the outer pads 218 are reserved for subsequent bonding of conductive elements such as bonding wires or solder balls. Preferably, the substrate 210 can be a printed circuit board having a single layer of circuitry to save the cost of the substrate 21 .

In addition, as shown in FIGS. 2 and 5, the substrate 21 further has at least one stepped recess 214 formed on the package surface 211 such that the thickness of the substrate in the stepped recess 214 is far away. The direction of the center line of the die-bonding region 213 is stepped and thinned. The method of forming the stepped recess 214 can be achieved by lamination using a plurality of sub-substrates of different opening sizes. In addition, the present invention does not limit the number of the stepped recesses 214. In this embodiment, the two sides of the substrate 210 each have a stepped recess 214. The adhesive layer 220 is formed on the package surface 21 of the substrate 21, preferably, the material of the adhesive material 220 may be selected from liquid epoxy, B-stage colloid or other Ft-curable The die-bonding material may be pre-formed on the substrate 21 () before or during the wafer armoring process, and the method is a liquid coating such as spot coating or printing. As shown in Figs. 3 and 4, the wafer 23G is aligned with the die attach region 213 and is disposed on the package surface 211 of the substrate 21 by the die attach adhesive 220. In the embodiment t, the wafer has a plurality of solder pads 232 located on the active surface, which may be arranged in a single row or in a double row in a central region of the active surface. The adhesive layer 220 is adhered to the active surface of the wafer 23 and the fresh slabs 232 are aligned in the through slots 215. In addition, as shown in FIGS. 3 and 4, the wafer 230 may have a side edge 231 contacting the adhesive bonding material 22, which is substantially flat with the arrangement direction of the second row of external ball points 25A. 12 13*55726 row 'and the stepped groove 214 has an edge 214A that is positioned outside the die bond region 213 and parallel to the side corner 231, thereby increasing the adhesive bond 220 from the side The corners 231 to the thicknesses of the second row of external ball points 25 ' are used to alleviate the stress of the side edges 23 1 of the wafer 230 on the second row of circumscribing points 250. As shown in Figures 2 and 4, the first row of external ball points 240 are disposed on the outer pads 218 of the exposed surface 212 of the substrate 210. The second row of external ball points 250 are disposed on the outer pads 218 of the exposed surface 212 of the substrate 210, and are further away from the center of the die bonding region 213 with respect to the first row of external ball points 24 line. That is, according to the center line distance or the distance from neutral point (DNP) of the substrate 21, the external ball point can be divided into a plurality of first row of external ball points 24〇 and a plurality of second row of external ball points. 250. In a cross-sectional structure, the second row of circumscribed ball points 25 is farther away from the substrate 210. Specifically, the first row of external ball points 240 and the second row of external ball points 25 may include a metal ball, a tin φ paste, a contact pad or a contact pin, so the semiconductor package structure 200 can be The first row of external ball points 240 and the second row of external ball points 250 are joined to an external printed circuit board (not shown). One or more rows of external ball points may be disposed between the first row of external ball points 24A and the second row of external ball points 250. Specifically, as shown in Fig. 5, the substrate 210 has a substrate thickness so which is a distance from the exposed surface 212 to the package surface 211. The stepped recess 214 causes the substrate 210 to have a first substrate thickness si on the first row of external ball points 240 to the stepped recess 214, and 13 1355726 causes the substrate 210 to be in the first The second row of spheroids 250 has a second substrate thickness s2, wherein the second substrate thickness 82 can be smaller than the first substrate thickness S1, and the first substrate thickness S1 can be smaller than the The substrate thickness S (the first substrate thickness S1 and the second substrate thickness s2 can be appropriately adjusted according to the expansion coefficient of the solder mask layer 217, the adhesive resin 220, and the sealant, in the temperature rise and fall The substrate 210 can be prevented from being warped. Specifically, the second row of external ball points 25 can be aligned within the coverage area of the stepped groove 214 and adjacent to the stepped groove 214. The two are oppositely referred to as parallel edges 214A to ensure that the shortest distance from the second row of circumscribed ball points 250 to the wafer 23〇 can be occupied by the viscous glue 22 较多 more proportions, even larger than the substrate 2 丨〇 Occupied ratio. Preferably, the second row of external ball points 25〇 The adhesive layer 22 can be adjacent to the periphery of the stepped groove 214, and the adhesive layer 22 can have a larger thickness on the second row of the outer ball points 250 to improve the stress buffering performance, so that it is susceptible to The second row of external ball points 25 concentrating can withstand large positional movement changes without falling or breaking. As shown in Figures 3 and 4, when performing the die bonding operation, the glue is first applied. The crystal glue 220 is applied to the package surface 21 of the substrate 21 in a liquid coating manner for bonding the wafer 230, and the stepped groove 214 is adjacent to the die bonding region 213' to provide the adhesion. The storage space of the crystal material 22〇 is used to reduce the overflow pollution. Therefore, the stepped groove 214 has a function of restricting the flow of the adhesive material to the substrate 21G, so that the adhesive overflow occurs. When the adhesive paste 220 is properly controlled, it does not overflow. As shown in FIG. 3, the adhesive paste 220 does not overflow to the periphery of the substrate 21 and to the pass = slot Π 55726 The electrical connection quality and durability of the structure. The third embodiment of the present invention discloses another circumscribed ball point having The semiconductor package structure of the movable dish is changed. Please refer to FIG. 7 , the semiconductor package structure mainly includes a substrate 31 〇, a viscous gel 咖 一 一 晶片 晶片 晶片 晶片 外 外 外 外 外 外 外 外 外 外 外 外 外 外 外 〇 〇 〇 〇 The second row of external ball points 350. The substrate 310 has a package surface and an exposed surface 312_', wherein the package surface 311 includes a die-bonding region 313 (as shown in FIG. 8). After. ^

The size of the crucible can be substantially equal to the wafer 330. The outer surface 312 of the substrate 310 may be formed with a solder mask layer which is a rim material to form an electrically insulating layer covering the conductive traces but exhibits a plurality of The cymbal 318 is externally connected such that the first row of circling ball points and the two first row of circling ball points 35 〇 are engageable to the circumscribed pads 318 . In addition, as shown in FIG. 7, the substrate 310 further has at least one stepped recess 14 formed on the package surface 311 to cause the substrate in the stepped recess 14 to be as far away as possible. The direction of the center line of the die-bonding zone 3 1 3

Stepped thin. The periphery of the stepped recess 314 may be slightly larger than the die attach region 313 (as shown in Fig. 8). In this embodiment, the substrate 31 further has a plurality of internal fingers 316' formed on the package surface 311 and outside the stepped grooves 314 (as shown in FIG. 8). As shown in Fig. 7, the adhesive layer 32 is formed on the cracking surface 311 of the substrate 31. The adhesive resin 32 〇 can be a liquid epoxy, a β-stage colloid or a viscous material which can be in a liquid or colloidal state at a temperature rise. Preferably, the adhesive layer 320 is a ruthenium gel which can be preformed on the substrate 310 before or during the semiconductor wafer packaging process. 17 1355726 350 is arranged in a direction that is roughly parallel. Moreover, as shown in FIGS. 7 and 8, the stepped recess 314 has an edge 314A' outside the viscous region 3 13 and parallel to the side corner 331 to thereby increase the viscous material 32. () from the side angle 331 to the second row of external drumstick shields and the thickness of the smashing point 350 to reduce the side angle of the wafer 33 3 3 3 1 to the flute - jjl.. The effect of stress on the external ball point 350 of the first row of the second row

In addition, the stepped groove 314 has a function of restricting the flow of the adhesive crystal 32 to the substrate 310. Therefore, when the sticky crystal occurs, the adhesive 32G can be appropriately controlled. It overflows to the side of the substrate 3 (as shown in FIG. 7) to ensure the quality of the semiconductor package structure 300. The present invention has been described in terms of a preferred embodiment of the invention, and is not intended to limit the invention, and is not intended to limit the invention. Any simple modifications, modifications, and modifications made herein are still within the technical scope of the present invention. [Simple diagram of the diagram] Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. Schematic diagram of a cross section of a semiconductor package structure. According to the first embodiment of the present invention,

A schematic diagram of a partially transmissive semi-conducting armored structure having a first cross section according to the first aspect of the present invention. The semiconductor package structure is constructed according to the first embodiment of the present invention. Schematic diagram of a package surface of a substrate according to a first embodiment of the present invention 19 1355726. FIG. 6 is a perspective view of a second embodiment of the present invention. FIG. 7 is a schematic cross-sectional view showing a semiconductor package structure in which an external ball point has a movable gain variation according to a third embodiment of the present invention. FIG. 8 is a third schematic view of the semiconductor package according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A perspective view of a substrate of the semiconductor package structure. [Description of main component symbols] so substrate thickness

S1 first substrate thickness S2 second substrate thickness 100 semiconductor package structure 110 substrate 111 package surface 112 exposed surface 115 through slot 116 internal finger 117 solder layer 118 external pad 120 adhesive material 130 wafer 131 side corner 132 Pad 140 First row of external ball points 150 Second row of external ball points 160 Electrical connection elements 170 Sealant 200 Semiconductor package structure 210 Substrate 211 Package surface 212 Exposed surface 213 Bonded area 214 Stepped groove 214A Edge 215 Through slot 216 Inner finger 217 welding cap layer 20 Ι3·55726

218 external pad 219 second inner finger 220 adhesive resin 230 wafer 240 first row of external ball, point 250 second row of external ball, point 260 electrical connection element 280 second wafer 290 second electrical connection element 300 semiconductor Package Structure 310 Substrate 311 Package Surface 313 Bonded Area 314 Stepped Groove 316 Inscribed Finger 317 Solder Mask Layer 320 Adhesive Tape 330 Wafer 332 Pad 340 First Row Outer Ball; Point 350 Second Row Outer Ball: Point 360 Electrical connection element 231 Side angle 270 Encapsulant 281 Pad 3 1 2 Exposed surface 3 14Α Edge 318 External pad 331 Side angle 370 Sealant 21

Claims (1)

1355726 X. Patent Application Range: A semiconductor package structure having a movable gain variation of an external ball point, comprising: a substrate having a package surface and an exposed surface, wherein the package surface comprises a die bonding region; a crystalline adhesive material is formed on the surface of the package of the substrate; a ruthenium sheet is aligned with the die-bonding region and disposed on the package surface of the substrate by the adhesive bonding material; a plurality of first rows of external connections a ball point disposed on the exposed surface of the substrate; and a plurality of second rows of external ball points disposed on the exposed surface of the substrate, and further away from the die bonding region relative to the first row of external ball points One of the center lines; Wherein the substrate further has at least one stepped groove formed on the surface of the package such that the thickness of the substrate in the stepped groove is stepped thinner away from the center line of the die bond region. And the adhesive glue is filled in the stepped groove. 2 X The semiconductor package structure having a movable gain variation, as described in claim 1, wherein the second row of circumscribed balls are aligned within the coverage area of the stepped groove. A semiconductor package structure having a movable gain variation as described in claim 2, wherein the second row of circumscribed balls are adjacent to two symmetrical parallel edges of the stepped groove. As described in the second paragraph of the patent application, the receiving point has a movable semiconductor package structure, and the φ ^ is located adjacent to the periphery of the stepped groove. . 5. As claimed in the scope of claim 苐J, the ball receiving point has a movable semiconductor package structure in which the substrate has a stepped groove in the first row of external ball points i. a first substrate thickness, and the substrate has a second substrate thickness on the second row of external ball points, wherein the second substrate thickness is less than the first substrate thickness. G. A semiconductor package structure having a movable gain variation as described in the patent application scope, wherein the wafer has a side corner contacting the adhesive paste, and is externally connected to the second rows The arrangement of the ball points is substantially parallel, and the stepped grooves have an edge outside the die bond region and parallel to the side corners. 7. The semiconductor package structure having a movable gain variation as described in claim 6 of the patent application, wherein the thickness of the adhesive material between the side edges and the second row of external ball points is Greater than the thickness of the substrate between the side edges to the second row of external ball points. 8' The semiconductor package structure having a movable gain variation as described in the first paragraph of the patent application scope' further includes a plurality of electrical connection elements' electrically connected to the wafer. 9. A semiconductor package structure having a movable gain variation as described in claim 8 of the claims, wherein the electrical connection elements comprise a plurality of bonding wires. 10. A semiconductor package having a gain variation of 23 IJ55726 as described in item 8 of the scope of the patent application. • ? ^ ?L > A # - ^ where the substrate has a through slot and is connected to the package The surface and the electrical connection elements are passed. And the road surface for the purpose of the present invention. The semiconductor package structure point of the change of the dynamic gain has a movable structure formed on the surface of the package of the substrate. ', the through hole in the hole 0 1 2, as the patent application range i i 〇 u a fan outside the ball point has Chiang The semiconductor package structure of the dynamic gain variation is stacked on the wafer back to back. The semiconductor package structure has a semiconductor package structure, wherein the substrate is: (4) & The outer ball point has a configuration, wherein the adhesive material 14, the semiconductor package of the first or u movable gain variation of the patent application is bonded to one of the active surfaces of the wafer, such as the patent scope of the fourth patent The outer ball point of the item 1 has a semiconductor package structure with a movable gain variation, wherein the die bond material is adhered to the back surface of one of the wafers. A semiconductor package structure comprising: a substrate having a package surface and an exposed surface, the package surface comprising a die-bonding region; a crystal-clear material formed on the package surface of the substrate; The wafer is aligned with the die-bonding region and is disposed at 24 by the adhesive bonding material.