L328274 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種多晶片堆疊封裝構造，特別係 有關於一種可避免基板翹曲之多晶片堆疊封裝構造。 【先前技術】 在半導體封裝領域中，由於多晶片堆疊封裝構造可 將複數個晶片可整合一封裝體内，越來越受到重視與採 用在不同的產品’通常晶片之主動面朝向同一方向地由 一基板往上縱向堆疊並電性連接至該基板，可有效縮小 封裝構造之表面接合面積（footprint)，以避免多晶片堆 疊封裝構造之尺寸過大。由於需提供更多的高度空間作 晶片堆疊’故相對使得基板越做越薄，導致在半導體封 裝製程中基板易有翹曲的問題而降低產品的良率。 請參閱第1圖所示，一種習知的多晶片堆疊封裝構 造100主要包含一基板110、一第一晶片12〇、一第二 晶片1 3 0、複數個第一銲線1 5 1、複數個第二銲線1 5 2 以及一封膠體140。該基板110係具有一第一表面ill 及一相對之第二表面112，該第一表面ill係形成有複 數個内接指113。該第一晶片120係具有一第一主動面 121、一相對之第一背面I22以及複數個形成於該第一 主動面121之第一銲墊123;同樣地，該第二晶片bo 係具有一第二主動面！31、一相對之第二背面132以及 複數個形成於該第二主動面131之第二銲墊133。該第 二晶片1 3 0之該第二背面1 3 2係黏設於該基板丨丨〇之該 6 1328274 第一表面111，並可利用該些第二銲線152電性連接該 些第二銲墊133與該基板110之該些内接搾113。並且， 該第一晶片1 20之該第一背面1 22係貼設於該第二晶片 130之該第二主動面131，且不遮蓋該些第二銲墊133, 故該第一晶片120之尺寸應小於該第二晶片130之尺 寸。通常該多晶片堆疊封裝構造1 00係為一種記憶卡裝 置，該第一晶片1 20係可為一控制器晶片，該第二晶片 130係可為一記憶體晶片。該些第一·鲜線151係連接該 第一晶片120之複數個第一銲墊123與該些内接指 113。該封膠體140係形成於該基板110之該第一表面 111，並密封該第一晶片120、該第二晶片130、該些第 一銲線151與該些第二銲線152。隨著晶片的堆疊數量 越多，在一受限的厚度要求下，相對地，該基板110會 變得更薄，故容易在半導體封裝製程中產生翹曲。 【發明内容】 本發明之主要目的係在於提供一種多晶片堆疊封裝 構造’能有效降低在多晶片堆疊封裝製程中基板之翹曲 度’並且不會增加基板之線路層數以及產品厚度，故能 提供一種能降低翹曲度之低成本基板。 本發明之次一目的係在於提供一種多晶片堆疊封裝 構造，具有低成本形成一容晶穴周邊缺口之功效》 本發明之另一目的係在於提供一種多晶片堆疊封裝 構造，能降低模封沖線並解決銲線短/斷路之問題。 本發明的目的及解決其技術問題是採用以下技術方 7 1328274 宰來實現的。依據本發明’ 一種多晶月堆豐封裝構造主 要包含一基板、一第一晶片以及一第二晶片。該基板係 具有一第一表面、一相對之第二表面、一開口朝向該第 一表面之容晶穴、複數個第一内接指及複數個第二内接 指，其中該些第一内接指係與該些第二内接指係形成於 同一線路層且外露在該第一表面，並且該容晶穴之邊緣 形成有一缺口，該些第一内接指係位於該缺口。該第一 晶片係設置於該容晶穴内並電性連接至該些第一内接 指。該第二晶片係設置於該基板之該第一表面並電性連 接至該些第二内接指，且該第二晶片係位於該第一晶片 之上方而重疊該第一晶片之至少一部位。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的多晶片堆疊封裝構造中，可另包含有一封 膠體’其係形成於該基板之該第一表面上，以密封該第 一晶片。 在前述的多晶片堆疊封裝構造中，該基板之厚度係 可超過該封谬體之一半厚度以上。 在前述的多晶片堆疊封裝構造中，該基板係可更具 有一防銲層，其係形成於該第一表向。 在前述的多晶片堆疊封裝構造中，該防銲層係可異 有一開孔’其係對準並大於該容晶穴之開口，以構成該 缺口 〇 在則述的多晶片堆疊封裝構造中，該容晶穴係可不 1-328274 貫穿至該基板之該第二表面。 在前述的多晶片堆疊封裝構造中，該基板係可 複數個外接指，其係形成於該第二表面。 在前述的多晶片堆疊封裝構造中，該些外接指 為金手指，該基板係為一記憶卡之晶片載板。 在前述的多晶片堆疊封裝構造中，該第一晶片 寸係可等於該第二晶片之尺寸。 在前述的多晶片堆疊封裝構造中，該第一晶片 寸係可小於該第二晶片之尺寸。 在前述的多晶片堆疊封裝構造中，該第二晶片 背面係可形成有一絕緣層。 在前述的多晶片堆疊封裝構造中，該絕緣層係 接黏接至該防銲層。 在前述的多晶片堆疊封裝構造中，可另包含有 個第一銲線，其係電性連接該第一晶片與該基板之 第一内接指。 在前述的多晶片堆疊封裝構造中，可另包含有 個第二銲線，其係電性連接該第二晶片與該基板之 第二内接指。 在前述的多晶片堆疊封裝構造中，可另包含有 充膠體，其係形成於該容晶穴。 在前述的多晶片堆疊封裝構造中，該填充膠體 黏著該第二晶片。 具有 係可 之尺 之尺 之一 可直 複數 該些 複數 該些 一填 係可 【實施方式】 9 1.328274 依據本發明之第一具體實施例，揭示一種多晶片堆 疊封裝構造。第2圖係為該多晶片堆疊封裝構造之截面 示意圖。第3A至3E圖係為該多晶片堆疊封裝構造於 製程中一基板之截面示意圖。 請參閱第2圖所示，一種多晶片堆疊封裝構造200 主要包含一基板210、一第一晶片220以及一第二·晶片 230。該基板210係具有一第一表面211、一相對之第 二表面212、一開口朝向該第一表面211之容晶穴213、 複數個第一内接指214及複數個第二内接指215。通常 該基板210係為一加厚的硬質印刷電路板，可為多層板 或單層板。該容晶穴213係不小於該第一晶片220之尺 寸’以供容置該第一晶片220。並且，該些第一内接指 2 1 4係與該些第二内接指2 1 5係形成於同一線路層且外 露在該第一表面211，故可減少該基板210之線路層 數，以降低基板成本。在本實施例中，該容晶穴2 1 3係 可不貫穿至該基板210之該第二表面212。此外，該容 晶穴213之底面可不需要形成有線路與内接指，能機械 性且容易地製作出該容晶穴213，而不會破壞該基板 2 1 0之内部線路。 此外，該容晶穴213之邊緣形成有一缺口 216，該 些第一内接指214係位於該缺口 216，用以容納銲線之 一端。請再參閱第2圖所示，更具體而言，該基板210 係可更具有一防銲層217，其係形成於該第一表面211 並顯露該些第二内接指2 1 5，以供打線方式與晶片電性 10 1328274 連接。該防銲層2 1 7係可具有一開孔，其係對準並略大 於該容晶穴2 1 3之開口，以構成該缺口 2 1 6，故該防銲 層217係不覆蓋該些第一内接指214。 該第—晶片220係具有一第一主動面221及一相對 之第一背面222，其中該第一主動面221係形成有複數 個第一銲墊223。可利用已知黏晶材料將該第一晶片 220之該第一背面222黏著在該基板210之容晶穴213 底部’以使該第一晶片220係設置於該容晶穴2 13内。 另可利用打線形成之複數個第一銲線25 1，以電性連接 該些第一銲墊22 3與該基板210之該些第一内接指 214，達到該第一晶片220與該基板210之電性互連。 請再參閱第2圖所示，該第二晶片230係具有一第 二主動面231及一相對之第二背面232,該第二晶片230 之該第二主動面23 1係形成有複數個第二銲墊23 3。在 本實施例中，該第二背面232係可形成有一絕緣層 234 ’ 如晶背黏著材料（Die Attach Material, DAM)，該 絕緣層23 4在加熱時產生黏著力。在適當之壓合壓力與 加熱溫度下，該絕緣層234能黏接至該基板2 1 0之該防 銲層217或其它表面’以使該第二晶片23〇係設置於該 基板210之該第一表面211上並且該第二晶片230係位 於該第一晶片220之上方而重疊該第一晶片22〇之至少 一部位，如交錯重疊或全部重疊。在本實施例中，該第 一晶片220之尺寸係可小於該第二晶片230之尺寸，故 該第二晶片230係完全重疊在該第一晶片220之上方。 11 1328274 此外，可利用複數個第二銲線2 5 2電性連接 塾23 3與該基板210之該些第二内接指215 較佳地，該多晶片堆疊封裝構造200可 填充膠體260，其係形成於該容晶穴2 1 3。 26〇係可包覆該第一晶片220與該些第一銲 以預先密封與保護該第一晶片220與該4 251 ’可避免在模封時該容晶六213内形成】 | 具體而言，該多晶片堆疊封裝構造200 —封膠體240,其係形成於該基板210之該第 上’以密封該第二晶片230與該些第二銲線 參閱第2圖所示，較佳地，該基板210之厚 該封膠體24 0之一半厚度以上，因此該基板 加厚並製成特定形狀之容晶穴213與缺口 2 馬抗翹曲性’以防止在製程中該基板210翹 品之不良率》 φ 在本實施例中，該多晶片堆疊封裝構造 一記憶卡裝置，第一晶片220係為一控制器 晶片2 3 0係為，快閃記憶體晶片，一個或複 片230可疊設在該第一晶片220上方。除此 晶片堆疊封裝構造2〇〇亦可應用在一般半 品中’例如球格陣列封裝（BGA)、平面陣列 或薄小外型尺寸封裝（TSOP)等等。 第3A至3E圖係用以說明根據本發明之 施例之該多晶片堆疊封裝構造2〇〇之製造2 該些第二銲 〇 另包含有一 該填充膠體 線251 ，藉 第一鲜線 II泡。 可另包含有 一表面21 1 252。請再 度係可超過 210能適當 16 ’藉以提 曲並降低產 200係可為 晶片，第二 數個第二晶 之外’該多 導體封裝產 封裝（lga〇 第一具體實 -法。首先， 1328274 請參閱第3A圖所示’提供一具有容晶穴 210，該基板210之第一表面211係形成有 内接指214與複數個第二内接指215，該些 214與該些第二内接指215係為同一線路層 第一表面2 1 1。該容晶穴2 1 3之一開口係朝 面2 1 1，且該容晶穴2 1 3之邊緣係形成有一 該些第一内接指214係位於該缺口 216。其 穴213之底面可不設有線路層或直接貫穿， 形成該容晶穴213時不會破壞該基板210之 構。該基板210可另具有一防辉層217，其 第一表面211’該防銲層217係顯露該些第-與該些第二内接指215並構成該缺口 216。 接著’請參閱第3 B所示，設置一第一晶 容晶穴213内，該第一晶片220之第一背面 於該基板210，其中該第一晶片220係具有 銲墊223，該些第一銲墊223係形成於該第 之一第一主動面221。並可利用打線技術形 第一銲線251連接該些第一銲墊22 3與該些 2 1 4 ’以達到該第一晶片22〇與該基板2 1 0 連接。 接著，請參閱第3 C圖所示，以點塗或網 式形成一填充膠體260於該容晶穴213内， 體260可包覆該第一晶片22〇與該些第一在 之後’請參閱第3D圖所示，設置一第 213之基板 複數個第一 第一内接指 且外露於該 向該第一表 缺口 2.1 6， 中，該容晶 以利機械式 内路線路結 係形成於該 •内接指2 1 4 片220於該 222係黏貼 複數個第一 一晶片220 成之複數個 第一内接指 之間之電性 板印刷等方 使該填充膠 F 線 251 。 二晶片.2 3 0 13 1328274 於該基板210上’該第二晶片23 0之第二主動 形成有複數個第二銲墊233，該第二晶片23〇 背面232係形成有—絕緣層234。利用該絕緣 該第二晶片230黏貼至該基板21〇之該防銲眉 設置於該基板210之該第一表面211上，並且 片230係位於該第一晶片22〇之上方而重疊該 220之至少一部位。其中該第二晶片230之尺 小於該第一晶片220之尺寸。 接著’請參閱第3 Ε圖所示，再以打線方式 數個第二銲線2 5 2，以電性連接該些第二銲墊 基板210之該些第二内接指215。最後，以模 成該封膠體240，以製成如第2圖所示之多晶 裝構造200。 因此，在上述多晶片堆疊封裝製程中，該 係為一加厚型態之基板，可在半導體封裝製程 板翹曲。此外，該些第一内接指214與該些第 215係為同一線路層且易於形成該容晶穴213 216，故可減少該基板210之線路層數進而降 本。 在本發明之第二具體實施例，揭示另一種 桑封裝構造。請參閱第4圖所示，該多晶片堆 造300主要包含一基板310、一第一晶片320 二晶片330。該基板310係具有一第—表面3 對之第二表面312、一開口朝向該第—表面3 面23 1係 之該第二 層23 4將 217，以 該第二晶 第一晶片 寸係可不 形成之複 233至該 封技術形 片堆疊封 基板210 中防止基 二内接指 與該缺口 低基板成 多晶片堆 疊封裝構 以及一第 ,1 1 ' 一相 11之容晶 14 1328274 穴313、複數個第一内接指314及複數個第二内接指 31 5’其中該些第一内接指314係與該些第二内接指315 係形成於同一線路層且外露在該第一表面311，並且該 容晶穴313之邊緣形成有一缺口 316’該些第一内接指 3 1 4係位於該缺口 3 1 6。在本實施例中，該基板3 1 0係 可更具有一防銲層317，其係形成於該第一表面311且 顯露該容晶穴313、該些第一内接指314與該些第二内 接指3 1 5。在本實施例中，該基板3 1 0係可具有複數個 外接指318，其係形成於該第二表面312。例如，該些 外接指3 1 8係可為金手指，該基板3 1 0係為一記憶卡之 晶片載板。 該第一晶片320係具有複數個第一銲墊321，該第 一晶片320係設置於該容晶穴313内並且該些第一鮮墊 3 2 1係為朝上。複數個第一銲線3 5 1係電性連接該些第 一銲墊321至該基板310之該些第一内接指314。 該多晶片堆疊封裝構造300可另包含有一填充膠體 3 60，其係形成於該容晶穴3 1 3。在本實施例中，該填 充膠體360係可為多階段固化膠體，能在A階狀態以網 板印刷方式形成於該容晶穴3 1 3，並可包覆該第一晶片 3 20與該些第一銲線351。並在塗佈之後，可預烘焙該 填充勝體360使其為B階（B-stage)狀態，具有不易塌散 的之外形，以利設置該第二晶片3 3 0。 該第二晶片330係設置於該基板310上並使該第二 晶片330之複數個第二銲墊331係為朝上，以供複數個 15 1328274 第一知線352電性連接該些第二鲜勢331至該基板 3 1 0。請再參閱第4圖所示，在本實施例中，該填充膠 體3 6 0係可黏著該第二晶片3 3 〇之背面，並使該第二晶 片330係位於該第—晶片320之上方而重疊該第一晶片 320之至少一部位。在本實施例中，該第一晶片320之 尺寸係相等於該第二晶片3 3 〇之尺寸，可皆為記憶體晶 片。 具體而言，該多晶片堆疊封裝構造300可另包含有 一封膠體340,其係形成於該基板31〇之該第一表面311 上’以密封該第二晶片33〇與該些第二銲線352。因此， 利用該容晶穴3 1 3以及該些第一内接指3 1 4係與該些第 二内接指3 1 5之配置關係，有效降低在多晶片堆疊封裝 製程中該基板310之翹曲度，並且不會增加該基板310 之線路層數。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實施 例揭露如上’然而並非用以限定本發明，任何熟悉本專 業的技術人員’在不脫離本發明技術方案範圍内，當可 和用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 各’依據本發明的技術實質對以上實施例所作的任何簡 單修改 '等同夔化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 16 1-328274 第1圖：一種習知多晶片堆疊封裝構造之截面示意圖。 第2圖：依據本發明之第一具體實施例，一種多晶片堆 疊封裝構造之截面示意圖。 第3A至3E圖：依據本發明之第一具體實施例，該多 晶片堆疊封裝構造於製程中一基板之截面示 意圖。 第4圖：依據本發明之第二具體實施例，另一種多晶片 堆疊封裝構造之截面示意圖。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-wafer stacked package structure, and more particularly to a multi-wafer stacked package structure that avoids substrate warpage. [Prior Art] In the field of semiconductor packaging, since a multi-wafer stacked package structure can integrate a plurality of wafers into a package body, more and more attention is paid to the use of different products in the same direction as the active surface of the wafer. A substrate is stacked vertically and electrically connected to the substrate, which can effectively reduce the surface footprint of the package structure to avoid excessive size of the multi-wafer stack package structure. Since more height space is required for the wafer stack, the thinner and thinner the substrate is caused, which causes the substrate to be warped in the semiconductor package process and the yield of the product is lowered. Referring to FIG. 1 , a conventional multi-wafer stacked package structure 100 mainly includes a substrate 110 , a first wafer 12 , a second wafer 1 30 , a plurality of first bonding wires 1 5 1 , and a plurality of A second bonding wire 1 5 2 and a colloid 140. The substrate 110 has a first surface ill and an opposite second surface 112. The first surface ill is formed with a plurality of internal fingers 113. The first wafer 120 has a first active surface 121, a first opposite back surface I22, and a plurality of first pads 123 formed on the first active surface 121. Similarly, the second wafer has a The second active surface! 31. An opposite second back surface 132 and a plurality of second pads 133 formed on the second active surface 131. The second back surface 1 2 2 of the second wafer 1300 is adhered to the first surface 111 of the substrate 1 , and the second bonding wires 152 can be electrically connected to the second surface 152 . The pads 133 and the inscribed pads 113 of the substrate 110. The first back surface 221 of the first wafer 1200 is attached to the second active surface 131 of the second wafer 130, and the second pads 133 are not covered. Therefore, the first wafer 120 is The size should be smaller than the size of the second wafer 130. Typically, the multi-wafer stack package structure 100 is a memory card device. The first wafer 120 can be a controller wafer, and the second wafer 130 can be a memory chip. The first fresh lines 151 are connected to the plurality of first pads 123 of the first wafer 120 and the internal fingers 113. The encapsulant 140 is formed on the first surface 111 of the substrate 110 and seals the first wafer 120, the second wafer 130, the first bonding wires 151 and the second bonding wires 152. As the number of stacked wafers increases, the substrate 110 becomes thinner under a limited thickness requirement, which tends to cause warpage in the semiconductor package process. SUMMARY OF THE INVENTION The main object of the present invention is to provide a multi-wafer stacked package structure 'effectively reducing the warpage of a substrate in a multi-wafer stack packaging process' without increasing the number of circuit layers of the substrate and the thickness of the product. A low cost substrate capable of reducing warpage is provided. A second object of the present invention is to provide a multi-wafer stack package structure having the effect of forming a peripheral notch of a cavity at a low cost. Another object of the present invention is to provide a multi-wafer stack package structure capable of reducing the die seal. Line and solve the problem of short/open circuit. The object of the present invention and solving the technical problems thereof are achieved by the following technique 7 1328274. According to the present invention, a polycrystalline moon-filled package structure mainly includes a substrate, a first wafer, and a second wafer. The substrate has a first surface, an opposite second surface, a cavity toward the first surface, a plurality of first inscribed fingers, and a plurality of second inscribed fingers, wherein the first inner portions The finger joints and the second inscribed fingers are formed on the same circuit layer and exposed on the first surface, and a gap is formed in the edge of the cavity, and the first inscribed fingers are located in the gap. The first wafer is disposed in the cavity and electrically connected to the first internal fingers. The second wafer is disposed on the first surface of the substrate and electrically connected to the second inscribed fingers, and the second wafer is located above the first wafer and overlaps at least a portion of the first wafer . The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing multi-wafer stacked package configuration, a colloid may be further included on the first surface of the substrate to seal the first wafer. In the aforementioned multi-wafer stacked package configuration, the thickness of the substrate may exceed one-half the thickness of the package. In the foregoing multi-wafer stacked package configuration, the substrate may have a solder resist layer formed in the first front direction. In the foregoing multi-wafer stacked package structure, the solder resist layer may have an opening that is aligned and larger than the opening of the cavity to form the gap in the multi-wafer stacked package structure described above. The cavity can pass through the second surface of the substrate from 1-328274. In the aforementioned multi-wafer stacked package configuration, the substrate may be a plurality of circumscribed fingers formed on the second surface. In the foregoing multi-wafer stacked package configuration, the external contacts are referred to as gold fingers, and the substrate is a wafer carrier of a memory card. In the aforementioned multi-wafer stacked package configuration, the first wafer size may be equal to the size of the second wafer. In the aforementioned multi-wafer stacked package configuration, the first wafer size may be smaller than the size of the second wafer. In the foregoing multi-wafer stacked package configuration, the second wafer back surface may be formed with an insulating layer. In the aforementioned multi-wafer stacked package configuration, the insulating layer is affixed to the solder resist layer. In the foregoing multi-wafer stack package configuration, a first bonding wire may be further included, which electrically connects the first wafer and the first inscribed finger of the substrate. In the foregoing multi-wafer stacked package structure, a second bonding wire may be further included, which electrically connects the second wafer and the second internal finger of the substrate. In the foregoing multi-wafer stack package configuration, a fill body may be further included, which is formed in the cavity. In the aforementioned multi-wafer stacked package configuration, the fill colloid adheres to the second wafer. One of the rulers having a ruler can be directly plural. The plurality of blocks can be filled. [Embodiment] 9 1.328274 According to a first embodiment of the present invention, a multi-wafer stack package structure is disclosed. Figure 2 is a schematic cross-sectional view of the multi-wafer stacked package construction. 3A to 3E are schematic cross-sectional views showing a substrate of the multi-wafer stacked package structure in the process. Referring to FIG. 2, a multi-wafer stacked package structure 200 mainly includes a substrate 210, a first wafer 220, and a second wafer 230. The substrate 210 has a first surface 211 , an opposite second surface 212 , a cavity 213 opening toward the first surface 211 , a plurality of first inscribed fingers 214 , and a plurality of second inscribed fingers 215 . . Typically, the substrate 210 is a thickened hard printed circuit board which may be a multi-layer board or a single layer board. The hole 213 is not smaller than the size of the first wafer 220 for accommodating the first wafer 220. Moreover, the first inscribed fingers 2 1 4 and the second inscribed fingers 2 15 are formed on the same circuit layer and exposed on the first surface 211 , so that the number of circuit layers of the substrate 210 can be reduced. To reduce the cost of the substrate. In this embodiment, the cavity 2 1 3 may not penetrate the second surface 212 of the substrate 210. In addition, the bottom surface of the cavity 213 does not need to be formed with a line and an internal finger, and the cavity 213 can be mechanically and easily fabricated without damaging the internal circuit of the substrate 210. In addition, the edge of the cavity 213 is formed with a notch 216, and the first inscribed fingers 214 are located at the notch 216 for receiving one end of the bonding wire. Referring to FIG. 2, more specifically, the substrate 210 may further have a solder resist layer 217 formed on the first surface 211 and expose the second inscribed fingers 2 15 to The wire is connected to the wafer electrical 10 1328274. The solder resist layer 2 17 can have an opening which is aligned and slightly larger than the opening of the cavity 2 1 3 to form the notch 2 1 6 , so the solder resist layer 217 does not cover the openings The first inscribed finger 214. The first wafer 220 has a first active surface 221 and an opposite first back surface 222. The first active surface 221 is formed with a plurality of first pads 223. The first back surface 222 of the first wafer 220 may be adhered to the bottom portion </ RTI> of the hole 213 of the substrate 210 by using a known viscous material to allow the first wafer 220 to be disposed in the cavity 2 13 . The plurality of first bonding wires 25 1 formed by wire bonding may be electrically connected to the first bonding pads 22 3 and the first inscribed fingers 214 of the substrate 210 to reach the first wafer 220 and the substrate. 210 electrical interconnection. Referring to FIG. 2 again, the second wafer 230 has a second active surface 231 and an opposite second back surface 232. The second active surface 23 1 of the second wafer 230 is formed with a plurality of Two pads 23 3 . In this embodiment, the second back surface 232 is formed with an insulating layer 234' such as a Die Attach Material (DAM), which generates an adhesive force upon heating. The insulating layer 234 can be adhered to the solder resist layer 217 or other surface of the substrate 210 at a suitable bonding pressure and heating temperature to enable the second wafer 23 to be disposed on the substrate 210. The first surface 211 and the second wafer 230 are located above the first wafer 220 and overlap at least a portion of the first wafer 22, such as staggered overlap or full overlap. In this embodiment, the size of the first wafer 220 can be smaller than the size of the second wafer 230, so that the second wafer 230 is completely overlapped above the first wafer 220. 11 1328274 In addition, a plurality of second bonding wires 252 can be electrically connected to the second internal fingers 215 of the substrate 210. Preferably, the multi-wafer stacked package structure 200 can be filled with the colloid 260. It is formed in the cavity 201 2 . The lanthanum can cover the first wafer 220 and the first solders to pre-seal and protect the first wafer 220 and the 4 251 ′ to avoid formation in the capacitor 213 during molding. The multi-wafer stack package structure 200 is formed on the first portion of the substrate 210 to seal the second wafer 230 and the second bonding wires. Referring to FIG. 2, preferably, The thickness of the substrate 210 is greater than or equal to one-half of the thickness of the encapsulant. Therefore, the substrate is thickened and formed into a specific shape of the hole 213 and the notch 2 to prevent warpage of the substrate 210 to prevent the substrate 210 from being defective in the process. In the embodiment, the multi-wafer stack package is configured as a memory card device, and the first wafer 220 is a controller wafer 203, a flash memory chip, and one or a plurality of chips 230 can be stacked. Above the first wafer 220. In addition to this, the wafer stack package structure 2 can also be applied to general semiconductors such as a ball grid array package (BGA), a planar array or a thin outline package (TSOP). 3A to 3E are diagrams for explaining the manufacture of the multi-wafer stacked package structure 2 according to the embodiment of the present invention. The second solder fillets further comprise a filled colloid line 251, which is immersed in the first fresh line II. . A surface 21 1 252 may be additionally included. Please re-expose that more than 210 can be appropriate 16 'to borrow and reduce the production of 200 series can be the wafer, the second number of second crystals outside the 'multi-conductor package production package (lga 〇 first concrete real-method. First, 1328274 Please refer to FIG. 3A to provide a cavity 210 having a first surface 211 formed with an internal finger 214 and a plurality of second internal fingers 215, the 214 and the second The inner finger 215 is the first surface 2 1 1 of the same circuit layer. One of the cavity 2 1 3 openings is directed to the face 21 1 , and the edge of the cavity 2 1 3 is formed with the first The inner finger 214 is located on the notch 216. The bottom surface of the hole 213 may not be provided with a circuit layer or directly penetrated, and the cavity 213 is formed without destroying the structure of the substrate 210. The substrate 210 may further have an anti-glare layer. 217, the first surface 211' of the solder resist layer 217 reveals the first and the second inner fingers 215 and constitutes the gap 216. Then, please refer to the third crystal, and a first crystal volume is set. In the hole 213, the first back surface of the first wafer 220 is on the substrate 210, wherein the first wafer 220 has a solder pad 223. The first pads 223 are formed on the first first active surface 221. The first bonding pads 251 can be connected to the first pads 22 3 and the 2 1 4 ′ by wire bonding technology to achieve The first wafer 22 is connected to the substrate 210. Next, as shown in FIG. 3C, a filling gel 260 is formed in the cavity 213 by spot coating or mesh, and the body 260 can cover the substrate 260. The first wafer 22 and the first ones are later, as shown in FIG. 3D, a plurality of first first inscribed fingers are disposed on the substrate of the 213th and exposed to the first table notch 2.16 The transistor is formed in the mechanical inner circuit line between the plurality of first inner fingers and the plurality of first inner fingers 220. The slab printing or the like causes the filling F line 251. The second wafer. 2 3 0 13 1328274 on the substrate 210, the second of the second wafers 23 is actively formed with a plurality of second pads 233, the second The back surface 232 of the wafer 23 is formed with an insulating layer 234. The second wafer 230 is adhered to the substrate 21 by the insulation. The first surface 211 of the substrate 210 is disposed on the first surface 211 of the substrate 210, and the sheet 230 is disposed above the first wafer 22 and overlaps at least a portion of the 220. The second wafer 230 is smaller than the first wafer 220. Dimensions. Next, please refer to FIG. 3, and then a plurality of second bonding wires 252 are electrically connected to electrically connect the second inscribed fingers 215 of the second pad substrates 210. Finally, the encapsulant 240 is molded to form a polycrystalline structure 200 as shown in Fig. 2. Therefore, in the above multi-wafer stack packaging process, the substrate is a thickened type substrate which can be warped in the semiconductor package process board. In addition, the first inscribed fingers 214 and the second layer 215 are in the same circuit layer and are easy to form the hole 213 216. Therefore, the number of circuit layers of the substrate 210 can be reduced and the cost can be reduced. In a second embodiment of the invention, another mulberry package construction is disclosed. Referring to FIG. 4, the multi-wafer stack 300 mainly includes a substrate 310, a first wafer 320, and two wafers 330. The substrate 310 has a second surface 312 of a first surface 3, and an opening 217 facing the first surface 3 of the first surface 3, 217, with the second crystal first wafer Forming a complex 233 to the sealed technical package stacking substrate 210 to prevent the base two internal fingers from forming a multi-wafer stacked package with the notched lower substrate and a first, 11 1 phase 11 of the dielectric 14 1328274 hole 313, a plurality of first inscribed fingers 314 and a plurality of second inscribed fingers 31 5 ′, wherein the first inscribed fingers 314 and the second inscribed fingers 315 are formed on the same circuit layer and exposed in the first The surface 311 and the edge of the cavity 313 are formed with a notch 316'. The first inscribed fingers 3 14 are located at the notch 3 16 . In this embodiment, the substrate 310 can further have a solder resist layer 317 formed on the first surface 311 and expose the cavity 313, the first interconnect fingers 314 and the first The second internal finger refers to 3 1 5 . In this embodiment, the substrate 310 can have a plurality of external fingers 318 formed on the second surface 312. For example, the external fingers 3 18 can be gold fingers, and the substrate 310 is a wafer carrier of a memory card. The first wafer 320 has a plurality of first pads 321 disposed in the cavity 313 and the first fresh pads 321 are facing upward. A plurality of first bonding wires 315 are electrically connected to the first bonding pads 321 to the first internal contacts 314 of the substrate 310. The multi-wafer stack package structure 300 can further include a fill colloid 3 60 formed in the cavity 31 3 . In this embodiment, the filling colloid 360 can be a multi-stage curing colloid, which can be formed in the A-stage state by screen printing on the cavity 31 and can cover the first wafer 3 20 and the Some first bonding wires 351. And after coating, the filled body 360 can be pre-baked into a B-stage state with a shape that is not easily collapsed to facilitate the setting of the second wafer 300. The second chip 330 is disposed on the substrate 310, and the plurality of second pads 331 of the second wafer 330 are upwardly connected to the plurality of 15 1328274 first wires 352 to electrically connect the second chips 352. Fresh potential 331 to the substrate 3 10 . Referring to FIG. 4 again, in the embodiment, the filling compound 360 is adhered to the back surface of the second wafer 3 3 , and the second wafer 330 is located above the first wafer 320 . At least one portion of the first wafer 320 is overlapped. In this embodiment, the size of the first wafer 320 is equal to the size of the second wafer, which may be a memory wafer. Specifically, the multi-wafer stack package structure 300 may further include a glue 340 formed on the first surface 311 of the substrate 31 to seal the second wafer 33 and the second bonding wires. 352. Therefore, the arrangement relationship between the cavity 31 3 and the first inscribed fingers 3 1 4 and the second inscribed fingers 3 15 is effective to reduce the substrate 310 in the multi-wafer stack packaging process. The degree of warpage does not increase the number of circuit layers of the substrate 310. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The present invention has been disclosed in the above preferred embodiments. However, it is not intended to limit the present invention. The skilled person's embodiments may be modified or modified to be equivalently modified by the above-mentioned technical contents without departing from the technical scope of the present invention. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; BRIEF DESCRIPTION OF THE DRAWINGS 16 1-328274 Fig. 1 is a schematic cross-sectional view showing a conventional multi-wafer stacked package structure. Figure 2 is a cross-sectional view showing a multi-wafer stack package structure in accordance with a first embodiment of the present invention. 3A to 3E are views showing a cross-sectional view of a substrate in a process in accordance with a first embodiment of the present invention. Figure 4 is a cross-sectional view showing another multi-wafer stacked package structure in accordance with a second embodiment of the present invention.
【主要元件符號說明】 100多晶片堆疊封裝構造 110基板 111第一表面 112第二表面[Main component symbol description] 100-multi-chip stacked package structure 110 substrate 111 first surface 112 second surface
113内接指 120第一晶片 123第一銲墊 130第二晶片 133第二銲墊 1 5 1第一銲線 200多晶片堆疊封 210基板 2 1 3容晶穴 216 缺口 220第一晶片 223第一銲墊 230第二晶片 121第一主動面 131第二主動面 140封膠體 152第二銲線 裝構造 211第一表面 214第一内接指 217防銲層 221第一主動面 231第二主動面 122第一背面 132第二背面 212第二表面 215第二内接指 222第一背面 232第二背面 17 1328274 233 第二銲墊 234 絕緣層 240 封膠體 251 第一銲線 252 第二銲線 260 填充膠體. 300 多晶片堆疊封裝構造 310 基板 311 第一表面 312 第二表面 3 13 容晶穴 314 第一内接指 3 15 第二内接指 3 16 缺口 3 17 防銲層 3 18 外接指 320 第一晶片 321 第一銲墊 330 第二晶片 331 第二銲墊 340 封膠體 351 第一銲線 352 第二銲線 360 填充膠體113 internal finger 120 first wafer 123 first pad 130 second wafer 133 second pad 1 5 1 first bonding wire 200 multi wafer stack sealing 210 substrate 2 1 3 cavity 216 notch 220 first wafer 223 a pad 230 second wafer 121 first active surface 131 second active surface 140 encapsulant 152 second wire bonding structure 211 first surface 214 first inscribed finger 217 solder mask 221 first active surface 231 second active surface 122 first back surface 132 second back surface 212 second surface 215 second inner finger 222 first back surface 232 second back surface 17 1328274 233 second solder pad 234 insulating layer 240 sealant 251 first bonding wire 252 second bonding wire 260 Filling colloid. 300 multi wafer stack package structure 310 substrate 311 first surface 312 second surface 3 13 cavity 314 first inner finger 3 15 second inner finger 3 16 notch 3 17 solder resist layer 3 18 external finger 320 First wafer 321 first pad 330 second wafer 331 second pad 340 sealant 351 first bond wire 352 second bond wire 360 filled with colloid
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