1307861 九、發明說明： 【發明所屬之技術領域】 本發明係有關於晶片卡，特別係有關於—種晶片尺 寸晶片卡’特別可應用在高容量之微型保全數位卡 (Micro SD card)。 【先前技術】 晶片卡（chip card)在某一程度又可稱為Ic卡或智 慧卡（smart Card) ’主要區別為記憶卡（mem〇ry card)與 微處理器卡（microprocessor card)，兩種内部皆封裝有 記憶體晶片。晶片卡尺寸從約早期的信用卡的大小往越 來越小的發展，然而記憶體的容量要求卻越來越大。 例如一種記憶卡的規格係為保全數位卡（SD card)，其尺 寸為32mmX24mmX2.1mm，内部封設有非揮發性記憶 體晶片（n〇n-v〇latile memory chip)，如快閃記憶體。在近一 代的記憶卡的規格係為微型保全數位卡（micr〇 sd card) ’其尺寸為i5mm X Umm χ imm，且記憶體容量 需求是在1GB以上，甚至於4GB或更高。其中，印 係為Secure Digital之簡寫。 在早期的保全數位卡中，複數個記憶體晶片是先行封裝 成TSOP或BGA類型的記憶體封裝件（paekage)，再表面接 CT至電路板，以上下殼體夾扣該電路板，以組成一保全數 4卡仁疋這種組合方式無法達到擴大記憶體容量與縮小晶 片卡尺寸的要求。 如第1圖所示，一種習知之晶片卡1〇〇包含一基板 5 ' 1307861 1 1 0、複數個第一層晶片1 2 0、複數個第二層晶片1 3 0、 一封膠體1 4 0以及一微處理器晶片1 5 1。由於該晶片 卡 100之接合面主要係由該基板 1 10之下表面所構 成，必須為平坦狀，無法在下表面設置任何電子元件。 該些第一層晶片1 2 0、該微處理器晶片1 5 1甚至被動 元件152皆設置於該基板110之同一上表面。該些第 二層晶片1 3 0則藉由間隔物1 7 0疊設於對應之第一層 晶片1 2 0之上，複數個銲線1 6 1與1 6 2分別電性連接 ® 該些第一層晶片120與該些第二層晶片130至該基板 1 1 0，最後並以該封膠體 1 40密封該些第一層晶片 1 20、該些第二層晶片1 3 0、微處理器晶片1 5 1與被動 元件 152。此一晶片卡 100之接合面面積約為單一第 一層晶片120之主動面121面積之五倍，整個尺寸過 大，不適用於微型晶片卡之應用。即使僅保留單一組 的第一層晶片120與第二層晶片130，晶片卡100之 $ 接合面面積亦在第一層晶片120之主動面121面積之 兩倍以上，並且其記憶體容量亦是被縮小。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提 供一種晶片尺寸晶片卡，具有卡片為晶片尺寸、多晶 片堆疊與具高記憶體容量之功效。 本發明之次一目的係在於提供一種晶片尺寸晶片 卡，能減少晶片載體之内接指數量。 本發明的目的及解決其技術問題是採用以下技術 6 :1307861 方案來實現的。本發明揭示一種晶片尺寸晶片卡，主 要包含一晶片載體、至少一微電子元件、一第一晶片、一 第二晶片以及一封膠體。該晶片載體係具有一上表面、一下 表面與一谷置孔，複數個外接觸指係形成於該下表面。該微 電子凡件係設置於該容置孔内並電性連接至該晶片載體。該 第一晶片係設置於該晶片載體之該上表面。該第二晶片係設 置於該第一晶片上。該封膠體係形成於該晶片載體上，以密 封該第一晶片與該第二晶片。其中，該晶片卡係具有一外露 該些外接觸指之接合面，並且嵌埋該微電子元件之容置孔係 被涵蓋在該第一晶片之黏晶區域内，以使該接合面之面積介 於該第一晶片之一主動面之1.0至1.5倍。 本發明的目的及解決其技術問題還可採用以下技 術措施進一步實現。 前述的晶片尺寸晶片卡，其中該容置孔係為一貫 孔，另在該晶片載體之下表面貼附有一保護膜。 前述的晶片尺寸晶片卡，其中該晶片載體係為一電 路基板’其係具有一核心層以及位於該下表面之一防 錄層，該容置孔係貫通該核心層而不連通該防銲層。 前述的晶片尺寸晶片卡，其中該晶片載體另具有一 金屬承座’其係位於該核心層與該防録層之間且對準 於該容置孔。 前述的晶片尺寸晶片卡，另包含一第一黏晶層，其 孫形成於該晶片裁體之該上表面，用以黏接該第一晶 片。 7 ‘1307861 前述的晶片尺寸晶片卡，其中該第一黏晶層係為内 含有複數個間隔球之黏膠，用以限定該第一黏晶層之 厚度並使該第一晶片平行於該晶片載體。 前述的晶片尺寸晶片卡*其中該些間隔球係為電絕 緣性。 前述的晶片尺寸晶片卡，其中該微電子元件係為一 微控制器晶片。 前述的晶片尺寸晶片卡，另包含有複數個第一銲 ® 線，其係電性連接該微電子元件與該晶片載體並被該 第一黏晶層所密封。 前述的晶片尺寸晶片卡*其中該晶片載體之該上表 面係形成有複數個第一内接指與複數個第二内接指， 該些第一内接指係位於該黏晶區域以内而被該第一黏 晶層覆蓋，該些第二内接指係位於該黏晶區域之外而被 該封膠體密封。 I 前述的晶片尺寸晶片卡’另包含有複數個第二鲜 線，以電性連接該第一晶片之銲墊至該些第二内接指。 前述的晶片尺寸晶片卡 > 另包含有複數個第三鲜 線，以電性連接該第二晶片之銲墊至該第一晶片之銲 墊。 前述的晶片尺寸晶片卡，其中該晶片卡係為記憶卡 或微處理器卡。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer card, and more particularly to a wafer size wafer card, which is particularly applicable to a high-capacity micro SD card. [Prior Art] A chip card can be called an Ic card or a smart card to some extent. The main difference is a mem〇ry card and a microprocessor card. The internal memory is packaged with a memory chip. The size of the chip card has grown from the size of the early credit card, but the capacity requirements of the memory have become larger. For example, a memory card is a SD card with a size of 32 mm X 24 mm X 2.1 mm and a non-volatile memory chip (such as a flash memory). In the recent generation, the specification of the memory card was a micro-protected digital card (micr〇 sd card) whose size was i5mm X Umm χ imm, and the memory capacity requirement was 1GB or more, or even 4GB or higher. Among them, the printing is short for Secure Digital. In the early security digital card, a plurality of memory chips were first packaged into a TSOP or BGA type memory package (paekage), and then the surface was connected to the CT to the circuit board, and the upper lower case was clamped to the circuit board to constitute The combination of a full-service 4 card kernel can not meet the requirements of expanding the memory capacity and reducing the size of the chip card. As shown in FIG. 1, a conventional wafer card 1A includes a substrate 5' 1307861 1 1 0, a plurality of first layer wafers 120, a plurality of second layer wafers 1 300, and a colloid 1 4 0 and a microprocessor chip 1 51. Since the joint surface of the wafer card 100 is mainly composed of the lower surface of the substrate 1 10, it must be flat and it is impossible to provide any electronic components on the lower surface. The first layer of wafers 120, the microprocessor chips 151 and even the passive components 152 are disposed on the same upper surface of the substrate 110. The second layer of wafers 130 are stacked on the corresponding first layer of wafers 120 by spacers 170, and the plurality of bonding lines 161 and 162 are electrically connected to each other. a first layer of the wafer 120 and the second layer of the wafer 130 to the substrate 110, and finally sealing the first layer of the wafer 110 with the encapsulant 140, the second layer of wafers 130, micro processing The wafer 1 151 and the passive component 152. The wafer card 100 has a joint area of about five times the area of the active surface 121 of the single first wafer 120. The overall size is too large to be suitable for microchip card applications. Even if only a single set of the first layer wafer 120 and the second layer wafer 130 are retained, the joint area of the wafer card 100 is more than twice the area of the active surface 121 of the first layer wafer 120, and the memory capacity thereof is also Being shrunk. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a wafer size wafer card having the functions of a wafer size, a polycrystalline wafer stack and a high memory capacity. A second object of the present invention is to provide a wafer size wafer card that reduces the number of fingers in the wafer carrier. The object of the present invention and solving the technical problems thereof are achieved by the following technique 6 : 1307861 scheme. The invention discloses a wafer size wafer card, which mainly comprises a wafer carrier, at least one microelectronic component, a first wafer, a second wafer and a gel. The wafer carrier has an upper surface, a lower surface and a valley opening, and a plurality of external contact fingers are formed on the lower surface. The microelectronic device is disposed in the receiving hole and electrically connected to the wafer carrier. The first wafer is disposed on the upper surface of the wafer carrier. The second wafer is placed on the first wafer. The encapsulation system is formed on the wafer carrier to seal the first wafer and the second wafer. Wherein the wafer card has a bonding surface exposing the external contact fingers, and the receiving hole for embedding the microelectronic component is covered in the die bonding region of the first chip so that the bonding surface area Between 1.0 and 1.5 times the active surface of one of the first wafers. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the above wafer size wafer card, wherein the receiving hole is a uniform hole, and a protective film is attached to the lower surface of the wafer carrier. The wafer-size wafer card, wherein the wafer carrier is a circuit substrate having a core layer and an anti-recording layer on the lower surface, the receiving hole penetrating the core layer without communicating the solder resist layer . The aforementioned wafer size wafer card, wherein the wafer carrier further has a metal socket 'between the core layer and the anti-recording layer and aligned with the receiving hole. The aforementioned wafer size wafer card further includes a first die layer formed on the upper surface of the wafer body for bonding the first wafer. 7 '1307861 The aforementioned wafer size wafer card, wherein the first adhesive layer is an adhesive containing a plurality of spacer balls for defining a thickness of the first adhesive layer and making the first wafer parallel to the wafer Carrier. The aforementioned wafer size wafer card* wherein the spacer balls are electrically insulative. The aforementioned wafer size wafer card, wherein the microelectronic component is a microcontroller chip. The foregoing wafer size wafer card further includes a plurality of first soldering wires electrically connected to the microelectronic component and the wafer carrier and sealed by the first die layer. In the foregoing wafer size wafer card, wherein the upper surface of the wafer carrier is formed with a plurality of first inscribed fingers and a plurality of second inscribed fingers, the first inscribed fingers are located within the die bonding region The first adhesive layer is covered, and the second inscribed fingers are located outside the bonded region and are sealed by the sealant. The foregoing wafer size wafer card ′ further includes a plurality of second fresh wires for electrically connecting the pads of the first wafer to the second internal fingers. The foregoing wafer size wafer card > further includes a plurality of third fresh wires for electrically connecting the pads of the second wafer to the pads of the first wafer. The aforementioned wafer size wafer card, wherein the wafer card is a memory card or a microprocessor card.
前述的晶片尺寸晶片卡，其中該晶片卡係為一微型 保全數位卡（Micro SD card)，其尺寸係在 15mm X 8 1307861 1 1 mm X 1 mm 〇 前述的晶片尺寸晶片卡，其中該接合面更不大於該 第一晶片之主動面之 1.2倍面積，且該第一晶片之記 憶體容量係不小於256MB。 前述的晶片尺寸晶片卡，其中該第一晶片與該第二 晶片係為同尺寸、同容量且相同銲墊排列之非揮發性 記憶體晶片。 前述的晶片尺寸晶片卡，另包含有一第三晶片，其 係疊設於該第二晶片之上。 前述的晶片尺寸晶片卡，另包含有一第四晶片，其 係疊設於該第三晶片之上。 前述的晶片尺寸晶片卡，其中該封膠體之厚度係大 於該第一晶片、該第二晶片、該第二晶片與該第四晶 片之總合厚度，且該封膠體與該晶片載體之總厚度係 不超過1.0mm。 【實施方式】 在本發明之第一具體實施例中，揭示一種晶>}尺寸 晶片卡，其晶片卡之外觀尺寸將接近晶片之尺寸，達 到真正的晶片卡微小化。如第2圖所示，一種晶片尺 寸晶片卡200主要包含一晶片載體210、至少一微電子元 件22〇、一第一晶片230、一第二晶片240以及一封膠體250。 該晶片卡2 0 0可為記憶卡或微處理器卡，在本實施例 中，是以微型保全數位卡（Micro SD card)具體例舉之。 如第2圖所示，該晶片載體210係可為一電路基板， l3〇7861 例如小型印刷電路板或是電路薄膜。該晶片載體2l〇係具有 一上表面211、一下表面212與一容置孔213〇複數個外接 觸指214係形成於該下表面2 12之一側邊；而該晶片载體2 i 〇 之上表面2 11係形成有複數個第一内接指2丨5與複數個第二 内接指216，可透過控制器等微電子元件22〇電性連接至該 些外接觸指214 〇該上表面211係定義有一形狀大致對應於 該第一晶片230之黏晶區域217»如第3圖所示’該些第一 内接指2 1 5係位於該黏晶區域217以内，以被一第一黏 籲 晶層280覆蓋（如第2圖所示），該些第二内接指216 係位於該黏晶區域217之外而被該封膠體2 5 0密封（如 苐2圖所示）。 在本實施例中’該微電子元件220係可為一微控制器 晶片（micro controller chip)。或可包含有被動元件與 邏輯元件等等。該微電子元件220係設置於該容置孔213 内並且電性連接至該晶片載體210。例如，可利用複數個 φ 第一銲線26 1、凸塊或錫膏，使該微電子元件22〇電性 連接至該晶片載體2 1 0。故該微電子元件220將嵌埋於該 晶片載體210内，不會增加該晶片卡200之厚度。在本實施 例中，該容置孔2 1 3係為一貫通該晶片載體2 1 0之上表 面2 1 1與下表面2 1 2之貫孔，故較佳地應另在該晶片 載體210之下表面212貼附有一保護膜270，以避免 該微電子元件220外露。 為第一晶片230係設置於該晶片載體210之上表面211 之上’可藉由一第一黏晶層280黏接該第一晶片230之背面 10 1307861 232’該第-晶片23G之—主動面23i上形成有複數個辉塾 心並可利用複數個第二銲線加將該第一晶片23〇之銲 墊23 3電〖生連接至該晶片載體21〇之該些第二内接指216。 在本實施例中’ 4第-晶片23G係為_非揮發性記憶體晶 I❹記㈣容量不小於25_之Μ·型快閃記 憶體晶片。 在本實施例中’該第一黏晶層28〇係形成於該晶片載體 之上表面211，其形成區域等同如第3圖所示之黏晶區 域217,用以黏接該第一晶片23〇之背面m。較佳地，該 第一黏晶@ 28〇係為内含有複數個間隔_ 281之黏 膠’用以限定該第-黏晶層28G之厚度並使該第一晶 片230平行於該晶片載體21〇。該些間隔球281係可 為電絕緣性，以避免導接該些第—銲線261。在本實施 例中，該第一黏晶層2 3 1能穷4+ # 層 版*在封該些第一銲線261，並 使該第一晶片230之背面232不會碰觸到該些第一銲 線 261。 片 230上，以在 該第一晶片240係設置於|玄第— 有限的接合面内擴充記憶體容脣 +丄^ ^ 咕 重°在本實施例中，該 第一晶片230與該第二晶片240係1 n 1承為同尺寸、同容量且相同 鮮塾排列之非揮發性記憶體晶片。 該第二晶片240係亦 具有一主動面241與一背面2叻 _ 该主動面241上形 成有複數個銲墊243。可在該第_。 〜晶片240之背面242 預形成一第二黏晶層290，以黏祕r 點接至該第一晶片230 之主動面231。如第2圖所示，+ 在本實施例中，該第 11 ；1307861 一晶片230與該第二晶片240係為同向堆疊且有些許 的位移。針對電性共用的銲墊，可利用複數個第三銲 線263電性連接該第二晶片240之銲墊243至該第一 晶片230之銲墊233，以減少該晶片載體210之第二 内接指216的數量。 該封膠體250係形成於該晶片載體210之上表面211，以 密封該第一晶片230與該第二晶片240。該封膠體250之四 周側面係為切割形成之垂直側壁並切齊於該晶片載體21 0之 籲 邊緣’而製為卡片外觀。故該晶片卡200之接合面係至少包 含有該晶片載體210之下表面212,並外露出位在下表面212 之β玄些外接觸指214(如第3圖所示）。由於嵌埋該微電子元 件220之容置孔213係包含該晶片載體210供結合該第一晶 片230之黏晶區域217内且不會增加該晶片卡200之厚度， 故該微電子元件220係内藏於該晶片載體210内且位在該第 一晶片230之下方’以使該接合面之面積係介於該第一晶片 φ 230之一主動面231之1.0至1.5倍。在本實施例中，該 晶片卡200係為一微型保全數位卡（Micr〇 sd card)， 其尺寸係在15mmXllmmXlmm。該晶片卡200扣除 如第3圖所不其下方導滑缺口與扣接缺口 ，該晶片卡 200之接合面（主要係為該晶片載體21〇之下表面212) 面積約在1 50mm2。在本實施例中，該第一晶片23〇之 主動面231之尺寸約在14.3mm X 9.0mm，其面積約在 128.7mm2。該接合面之面積約為該第一晶片23〇之主動面 231之1.16倍。故該接合面更可控制在不大於該第一晶 12 ' 1307861 片230之主動面231之ι·2倍面積。因此，整個晶片 卡200之接合面面積會接近第一晶片23〇之主動面 面積，也就是說，在一特定規格的晶片卡2〇〇有限空 間内可以封設的第一晶片23〇與第二晶片24〇的尺寸 忐更大、可堆疊的晶片數量也可以更多，以符合微小 型晶片卡具更大的記憶體容量，故提供一種晶片尺寸 與高記憶體容量之微型晶片卡2〇〇，以符合晶圓切割 效益。 籲 在本發明之第二具體實施例中，如第5圖所示，揭 示另一種晶片尺寸晶片卡3〇〇，主要包含一晶片載體 310、至少一嵌埋於該晶片載體310内之微電子元件320、一 第一晶片330、一第二晶片340以及一封膠體350，上列主 要元件大致與該第一具體實施例所述者相同。該晶片載體 31〇係具有一上表面311、一下表面312與一容置孔313,複 數個外接觸指314係形成於該下表面312，該容置孔313係 φ 用以容納該微電子元件320。在本實施例中，該容置孔3 1 3 係不貫穿該晶片栽體3 i 〇，其開口係朝向該上表面3丨i。就 該晶片載體310之具體結構而言，該晶片載體3 i 〇係為一 電路基板，例如B T基板之印刷電路板，該晶片載體 310係具有一核心層315以及位於該下表面312之一 防~層316’該容置孔313係貫通該核心層315而不 連通該防銲層3 1 6。較佳地’該晶片載體3 1 0另具有 金屬承座317，其係位於該核心層315與該防銲層 3 1 6之間且對準於該容置孔3丨3，以供該微型電子元件 13 1307861 3 2 0之黏設並能增進散熱效果。 該微電子元件320係可為一微處理器晶片，設置於該晶 片載體310之該容置孔313内。可利用複數個第一銲線如 使該微電子元件320電性連接至該晶片載體31〇。_黏晶層 儀形成於該晶片載體31G之上表面311並覆蓋該微電子元件 320 ’以使該第一晶片33〇設置在該晶片載體31〇上。並以 複數個第二銲線362電性連接在該第一晶片330主動面331 上之銲塾332至該晶片載體31卜該第二晶片3則設置在 該第-晶片330上’其中該第二晶片34〇之背面係朝向該第 一晶片330之主動面331，而呈同向堆疊之型態。形成該第 二晶片340之主動面341上的銲墊342則以複數個第三銲線 363電性連接至該晶片載體31〇。由於該微型電子元件 嵌埋於該晶片載體310，不影響該晶片卡3〇〇之厚度，故該 晶片卡300可以再往上堆疊一第三晶月37〇與一第四晶片 380。該封膠體35〇係形成於該晶片載體31〇之上表面， 以密封第一晶片330、第二晶片340、第三晶片37〇與第四 晶片380。其中，該晶片卡3〇〇係具有一外露該些外接觸指 314之接合面，其主要係由該晶片載體31〇之下表面312所 構成。由於，並且嵌埋該微電子元件32〇之容置孔3 13係被 涵蓋在該第一晶片3 3 0之黏晶區域内，以使該接合面之面積 能介於該第一晶片330之該主動面331之1·〇至1.5倍。 因此，該封膠體350之厚度係大於該第一晶片330、該第 二晶片340、該第三晶片370與該第四晶片380之總合厚度， 且該封膠體3 5 0與該晶片載體3〗〇之總厚度能控制在不超過 14 ‘1307861 1.0mm的條件。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實 施例揭露如上，然而並非用以限定本發明，任何熟悉 本項技術者，在不脫離本發明之技術範圍内，所作的 任何簡單修改、等效性變化與修飾，均仍屬於本發明 的技術範圍内。 【圖式簡單說明】 第1圖：習知一種多晶片封裝之晶片卡之截面示意圖。 第2圖：依據本發明之第一實施例，一種晶片尺寸晶 片卡之截面示意圖。 第3圖：依據本發明之第一實施例，該晶片尺寸晶片 卡之接合面示意圖。 第4圖：依據本發明之第二實施例，另一種晶片尺寸 晶片卡之截面示意圖。 【主要元件符號說明】 100 晶片卡 110 基板 120 第一層晶片 121 主動面 130 第二層晶片 140 封膠體 15 1 微處理器晶 片 152 被動元件 16 1 銲線 162 銲線 170 間隔物 200 晶片 K寸晶片 210 晶片載體 211 上表面 212 下表面 213 容置孔 214 外接觸指 215 第一内接指 15 ‘1307861The above wafer size wafer card, wherein the wafer card is a micro SD card having a size of 15 mm X 8 1307861 1 1 mm X 1 mm, the aforementioned wafer size wafer card, wherein the bonding surface It is no more than 1.2 times the area of the active surface of the first wafer, and the memory capacity of the first chip is not less than 256 MB. In the above wafer size wafer card, the first wafer and the second wafer are non-volatile memory wafers of the same size, the same capacity and the same pad arrangement. The aforementioned wafer size wafer card further includes a third wafer stacked on the second wafer. The aforementioned wafer size wafer card further includes a fourth wafer stacked on the third wafer. In the above wafer size wafer card, wherein the thickness of the sealant is greater than the total thickness of the first wafer, the second wafer, the second wafer and the fourth wafer, and the total thickness of the sealant and the wafer carrier The system does not exceed 1.0mm. [Embodiment] In a first embodiment of the present invention, a crystal wafer card is disclosed in which the size of the wafer card is close to the size of the wafer to achieve true wafer card miniaturization. As shown in FIG. 2, a wafer size wafer card 200 mainly includes a wafer carrier 210, at least one microelectronic element 22, a first wafer 230, a second wafer 240, and a colloid 250. The chip card 200 may be a memory card or a microprocessor card. In this embodiment, a micro SD card is specifically exemplified. As shown in FIG. 2, the wafer carrier 210 can be a circuit substrate, such as a small printed circuit board or a circuit film. The wafer carrier 21 has an upper surface 211, a lower surface 212 and a receiving hole 213, and a plurality of external contact fingers 214 are formed on one side of the lower surface 2 12; and the wafer carrier 2 i The upper surface 2 11 is formed with a plurality of first inscribed fingers 2丨5 and a plurality of second inscribed fingers 216, and is electrically connected to the external contact fingers 214 through a microelectronic component 22 such as a controller. The surface 211 defines a die-shaped region 217 corresponding to the first wafer 230. As shown in FIG. 3, the first inscribed fingers 2 1 5 are located within the die-bonding region 217 to be An adhesive layer 280 is covered (as shown in FIG. 2), and the second internal fingers 216 are located outside the bonded region 217 and are sealed by the sealant 250 (shown in FIG. 2). . In the present embodiment, the microelectronic component 220 can be a micro controller chip. Or it can contain passive components and logic components, and so on. The microelectronic component 220 is disposed in the receiving hole 213 and electrically connected to the wafer carrier 210. For example, the plurality of φ first bonding wires 26 1 , bumps or solder paste may be used to electrically connect the microelectronic component 22 to the wafer carrier 210. Therefore, the microelectronic component 220 will be embedded in the wafer carrier 210 without increasing the thickness of the wafer card 200. In this embodiment, the accommodating hole 2 1 3 is a through hole penetrating through the upper surface 21 1 1 and the lower surface 2 1 2 of the wafer carrier 210, so that the wafer carrier 210 should preferably be further disposed. A protective film 270 is attached to the lower surface 212 to prevent the microelectronic component 220 from being exposed. The first wafer 230 is disposed on the upper surface 211 of the wafer carrier 210. The first wafer 302 can be bonded to the back surface of the first wafer 230 by using a first bonding layer 280. The first wafer 23G is active. A plurality of radiant cores are formed on the surface 23i, and the second bonding wires of the first wafer 23 are electrically connected to the second internal contacts of the wafer carrier 21 by a plurality of second bonding wires. 216. In the present embodiment, the '4th wafer-to-wafer 23G is a non-volatile memory crystal. (4) A flash memory memory chip having a capacity of not less than 25 Å. In the present embodiment, the first bonding layer 28 is formed on the upper surface 211 of the wafer carrier, and the formation region thereof is equivalent to the bonding region 217 as shown in FIG. 3 for bonding the first wafer 23 . The back of the m m. Preferably, the first adhesive crystal layer is a plurality of adhesives _ 281 containing therein to define the thickness of the first viscous layer 28G and the first wafer 230 is parallel to the wafer carrier 21 Hey. The spacer balls 281 can be electrically insulated to avoid guiding the first bonding wires 261. In this embodiment, the first bonding layer 2 3 1 can be used to seal the first bonding wires 261, and the back surface 232 of the first wafer 230 does not touch the first bonding wires 261. The first bonding wire 261. On the sheet 230, the memory chip lip + 丄 ^ ^ 咕 is extended in the first wafer 240 in the finite joint surface. In the embodiment, the first wafer 230 and the second wafer The wafer 240 is a non-volatile memory wafer of the same size, the same capacity, and the same fresh 塾 arrangement. The second wafer 240 also has an active surface 241 and a back surface 2 _ _ the active surface 241 is formed with a plurality of pads 243. Can be in the first _. The back surface 242 of the wafer 240 is pre-formed with a second die layer 290 to be bonded to the active surface 231 of the first wafer 230. As shown in Fig. 2, in the present embodiment, the 11th; 1307861 wafer 230 and the second wafer 240 are stacked in the same direction with a slight displacement. For the electrically shared pads, a plurality of third bonding wires 263 may be electrically connected to the pads 243 of the second wafer 240 to the pads 233 of the first wafer 230 to reduce the second inner portion of the wafer carrier 210. The number of fingers 216. The encapsulant 250 is formed on the upper surface 211 of the wafer carrier 210 to seal the first wafer 230 and the second wafer 240. The four sides of the encapsulant 250 are cut to form vertical sidewalls and are aligned with the edge of the wafer carrier 21 to make a card appearance. Therefore, the bonding surface of the wafer card 200 includes at least the lower surface 212 of the wafer carrier 210, and the outer surface contact fingers 214 located at the lower surface 212 are exposed (as shown in Fig. 3). Since the accommodating hole 213 in which the microelectronic device 220 is embedded includes the wafer carrier 210 for bonding into the slab region 217 of the first wafer 230 without increasing the thickness of the wafer card 200, the microelectronic device 220 is It is embedded in the wafer carrier 210 and located below the first wafer 230 such that the area of the bonding surface is between 1.0 and 1.5 times the active surface 231 of the first wafer φ 230. In the present embodiment, the wafer card 200 is a Micr〇 sd card having a size of 15 mm×11 mm×1 mm. The wafer card 200 is deducted from the lower sliding notch and the fastening notch as shown in Fig. 3. The bonding surface of the wafer card 200 (mainly the lower surface 212 of the wafer carrier 21) has an area of about 150 mm2. In this embodiment, the active surface 231 of the first wafer 23 has a size of about 14.3 mm X 9.0 mm and an area of about 128.7 mm 2 . The area of the joint is about 1.16 times the active surface 231 of the first wafer 23 . Therefore, the joint surface can be controlled to be no more than 2 times the area of the active surface 231 of the first crystal 12 ' 1307861 sheet 230. Therefore, the bonding surface area of the entire wafer card 200 is close to the active surface area of the first wafer 23, that is, the first wafer 23 can be sealed in a limited space of a specific specification of the wafer card 2 The size of the two-chip 24〇 is larger, and the number of stackable wafers can be larger to meet the larger memory capacity of the micro-miniature wafer chuck. Therefore, a micro-wafer card with a chip size and a high memory capacity is provided. Hey, to meet wafer cutting benefits. In a second embodiment of the present invention, as shown in FIG. 5, another wafer size wafer card is disclosed, which mainly includes a wafer carrier 310 and at least one microelectronic embedded in the wafer carrier 310. Element 320, a first wafer 330, a second wafer 340, and a gel 350, the main elements listed above are substantially the same as those described in the first embodiment. The wafer carrier 31 has an upper surface 311, a lower surface 312 and a receiving hole 313. The plurality of external contacts 314 are formed on the lower surface 312, and the receiving hole 313 is φ for accommodating the microelectronic component. 320. In this embodiment, the receiving hole 3 1 3 does not penetrate the wafer carrier 3 i , and the opening thereof faces the upper surface 3丨i. In terms of the specific structure of the wafer carrier 310, the wafer carrier 3i is a circuit substrate, such as a printed circuit board of a BT substrate, the wafer carrier 310 having a core layer 315 and an anti-defense on the lower surface 312. The layer 316' receives the hole 313 through the core layer 315 without communicating the solder resist layer 3 16 . Preferably, the wafer carrier 310 has a metal socket 317 between the core layer 315 and the solder resist layer 3 16 and aligned with the receiving hole 3丨3 for the micro The electronic component 13 1307861 3 2 0 is glued and can enhance the heat dissipation effect. The microelectronic component 320 can be a microprocessor chip disposed in the receiving hole 313 of the wafer carrier 310. A plurality of first bonding wires may be utilized to electrically connect the microelectronic component 320 to the wafer carrier 31A. A viscous layerer is formed on the upper surface 311 of the wafer carrier 31G and covers the microelectronic element 320' such that the first wafer 33 is disposed on the wafer carrier 31. And a plurality of second bonding wires 362 are electrically connected to the bonding pads 332 on the active surface 331 of the first wafer 330 to the wafer carrier 31. The second wafer 3 is disposed on the first wafer 330. The back surface of the two wafers 34 is oriented toward the active surface 331 of the first wafer 330, and is stacked in the same direction. The pads 342 forming the active surface 341 of the second wafer 340 are electrically connected to the wafer carrier 31 by a plurality of third bonding wires 363. Since the microelectronic component is embedded in the wafer carrier 310 and does not affect the thickness of the wafer card 3, the wafer card 300 can be further stacked with a third crystal 37 〇 and a fourth wafer 380. The encapsulant 35 is formed on the upper surface of the wafer carrier 31 to seal the first wafer 330, the second wafer 340, the third wafer 37, and the fourth wafer 380. The wafer card 3 has a bonding surface exposing the external contact fingers 314, and is mainly composed of the lower surface 312 of the wafer carrier 31. The accommodating hole 3 13 embedded in the microelectronic device 32 is covered in the die bonding region of the first wafer 390 so that the area of the bonding surface can be between the first wafer 330 The active surface 331 is 1 to 1.5 to 1.5 times. Therefore, the thickness of the sealant 350 is greater than the total thickness of the first wafer 330, the second wafer 340, the third wafer 370, and the fourth wafer 380, and the sealant 350 and the wafer carrier 3 The total thickness of the crucible can be controlled to a condition not exceeding 14 '1307861 1.0mm. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a wafer card of a multi-chip package. Fig. 2 is a cross-sectional view showing a wafer size wafer card in accordance with a first embodiment of the present invention. Fig. 3 is a view showing the joint surface of the wafer size wafer card in accordance with the first embodiment of the present invention. Figure 4 is a cross-sectional view showing another wafer size wafer card in accordance with a second embodiment of the present invention. [Main component symbol description] 100 wafer card 110 substrate 120 first layer wafer 121 active surface 130 second layer wafer 140 encapsulant 15 1 microprocessor chip 152 passive component 16 1 bonding wire 162 bonding wire 170 spacer 200 wafer K inch Wafer 210 wafer carrier 211 upper surface 212 lower surface 213 receiving aperture 214 outer contact finger 215 first inner finger 15 '1307861
216 第二内接指 217 黏晶區域 220 微電子元件 230 第一晶片 231 主動面 232 背面 233 銲墊 240 第二晶片 241 主動面 242 背面 243 銲墊 250 封膠體 261 第一銲線 262 第二銲線 263 第三銲線 270 保護膜 280 第一黏晶層 281 間隔球 290 第二黏晶層 300 晶片尺寸晶片卡 3 10 晶片載體 311 上表面 312 下表面 313 容置孔 314 外接觸指 315 核心層 3 16 防銲層 317 金屬承座 320 微電子元件 330 第一晶片 331 主動面 332 銲墊 340 第二晶片 341 主動面 342 銲墊 350 封膠體 361 第一銲線 362 第二銲線 363 第三銲線 364 第四銲線 365 第五銲線 370 第二晶片 380 第四晶片 16216 second inner finger 217 die region 220 microelectronic component 230 first wafer 231 active face 232 back 233 pad 240 second wafer 241 active face 242 back 243 pad 250 sealant 261 first bond wire 262 second weld Line 263 third bonding wire 270 protective film 280 first bonding layer 281 spacer ball 290 second bonding layer 300 wafer size wafer card 3 10 wafer carrier 311 upper surface 312 lower surface 313 receiving hole 314 external contact finger 315 core layer 3 16 solder mask 317 metal socket 320 microelectronic component 330 first wafer 331 active surface 332 solder pad 340 second wafer 341 active surface 342 solder pad 350 sealing body 361 first bonding wire 362 second bonding wire 363 third welding Line 364 fourth bond wire 365 fifth bond wire 370 second wafer 380 fourth wafer 16