-1312970 九、發明說明： 【發明所屬之技術領域】 本發明係有關於晶片卡，特別係有關於一種隱藏微 電子元件之晶片卡，特別可應用在高容量之微型保全數位 卡（Micro SD card)。 【先前技術】 按，晶片卡（chip card)又可稱為1C卡或智慧卡 (smart card) ’主要可區別為§己憶卡（memory c arr) ) 微 _ 處理器卡（microprocessorcard)兩大類，兩種内部皆封 裝有記憶體晶片。晶片卡尺寸從約早期的信用卡的大小 往越來越小的發展，然而記憶體的容量要求卻越來越 大。例如一種記憶卡的規格係為保全數位卡（SD card)， 其尺寸為32mm X 24mm X 2.1mm，内部封設有非揮發性 記憶體晶片（non-volatile memory chip)，如NAND型快閃記 憶體。在近一代的記憶卡的規格係為微型保全數位卡 籲 （micro SD card)，或稱為 T-flash card，micro SD 卡的尺寸為 15mmX llrnmX lmm，且記憶體容量需求是在1GB以 上甚至於4GB或更南。其中’ SD係為Secure Digital 之簡寫。 在早期的保全數位卡中，複數個記憶體晶片是先行封裝 成TSOP或BGA類型的記憶體封裝件（package)，再表面接 合至一電路板’以上下殼體夾扣該電路板，以組成一保全數 位卡。但是這種組合方式無法達到擴大記憶體容量與縮小晶 片卡尺寸的要求。 5 .1312970 如第1圖所示，一種習知之晶片卡100包含一基板 11 0、複數個第一層晶片1 20、複數個第二層晶片1 3 0、 一封膠體 1 4 0以及一微處理器晶片1 5 1。由於該晶片 卡 100之接合面主要係由該基板 110之下表面所構 成，必須為平坦狀，無法在下表面設置任何電子元件。 該些第一層晶片120、該微處理器晶片151甚至被動 元件152皆設置於該基板110之同一上表面。該些第 二層晶片1 3 0則藉由間隔物1 7 0疊設於對應之第一層 籲 晶片1 2 0之上，複數個銲線1 6 1與1 6 2分別電性連接 該些第一層晶片1 20與該些第二層晶片1 3 0至該基板 1 1 0，最後並以該封膠體 1 40密封該些第一層晶片 1 2 0、該些第二層晶片1 3 0、微處理器晶片1 5 1與被動 元件 152。此一晶片卡 100之接合面面積約為單一第 一層晶片120之主動面121面積之五倍，整個尺寸過 大，不適用於微型晶片卡之應用。由於該微處理器晶 ¥ 片1 5 1與被動元件佔據了該基板1 1 0之上表面部分面 積，即使僅保留單一組的第一層晶片1 2 0與第二層晶 片130，晶片卡100之接合面面積亦在第一層晶片120 之主動面121面積之兩倍以上，並且其記憶體容量亦 是被縮小。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提 供一種晶片卡，能内藏微電子元件，使晶片卡達到高 (記憶體）容量與尺寸縮小之功效。 6 1312970 本發明之次一目的係在於提供一種晶片卡，解決晶 片卡封膠時上下模流不平衡的問題，能使封膠體填實 於晶片與晶片載體之間的間隙，以密封内藏之微電子 元件。 本發明之另一目的係在於提供一種晶片卡，能減少 晶片載體在晶片設置區外部之内接指數量並使該些内 接指密集直線排列在一有限面積内。 本發明的目的及解決其技術問題是採用以下技術 > 方案來實現的。本發明揭示一種晶片卡，主要包含一 晶片載體、至少一微電子元件、複數個間隔維持件、 一第一晶片以及一封膠體。該晶片載體係具有一上表 面與一下表面，該上表面定義有一晶片設置區，該下 表面形成有複數個外接觸指。該微電子元件係設置於 該晶片載體之該晶片設置區内並電性連接至該晶片載 體。該些間隔維持件（stand-off)係設置於該晶片載體之 g 該晶片設置區内並具有一高於該微電子元件之厚度。 該第一晶片係貼設於該些間隔維持件上。該封膠體係 形成於該晶片載體上並填入由該些間隔維持件提供之 間隙内，以密封該第一晶片與該微電子元件。其中， 該第一晶片之尺寸係對應於該晶片設置區，以使該微 電子元件内藏於該晶片載體與該第一晶片之間。 本發明的目的及解決其技術問題還可採用以下技 術措施進一步實現。 在前述的晶片卡中，該晶片設置區係佔據該晶片載 7 .1312970 體之上表面至少百分之七十以上的面積。 在前述的晶片卡中，該些間隔維持件係為矽質柱或 是$夕質條。 在前述的晶片卡中，該些間隔維持件係鄰近於該晶 片設置區之邊緣，且該第一晶片係具有複數個第一銲 墊，其係形成於該第一晶片之一主動面邊緣，以使該 些間隔維持件可供打線支撐。 在前述的晶片卡中，另包含有一模流平衡控制件， Φ 其係設置於該第一晶片之上方，以使該模流平衡控制 件至該封膠體之頂面之間隔距離不大於該晶片載體至 該第一晶片之間隔距離。 在前述的晶片卡中，另包含有複數個第一銲線，其 係電性連接該些第一銲墊與該些内接指。 在前述的晶片卡中，該微電子元件係為一微控制器 晶片。 I 在前述的晶片卡中，另包含有複數個銲線，其係電 性連接該微電子元件與該晶片載體，且該些銲線之弧 南係不超過該些間隔維持件之厚度。 在前述的晶片卡中，另包含有一第二晶片，其係堆 疊在該第一晶片之上方。 在前述的晶片卡中，另包含有一間隔片，其係設置 於該第一晶片與該第二晶片之間。 在前述的晶片卡中，該第二晶片係具有複數個第二 銲墊，其係形成於該第二晶片之一主動面邊緣，且藉 8 1312970 由複數個第二銲線電性連接該些第二銲墊至該晶片載 體。 在前述的晶片卡中，該晶片載體係為一具有黑色防 銲層之印刷電路板。 在前述的晶片卡中，該晶片卡係為記憶卡或微處理 器卡。 在前述的晶片卡中，該晶片卡係為一微型保全數位 卡（Micro SD card)，其尺寸係在 15mm X 11mm X 1mm。 1 在前述的晶片卡中，該第一晶片係為記憶體容量不 小於256MB之快閃記憶體晶片。 【實施方式】 在本發明之一具體實施例中，揭示一種隱藏微電子 元件之晶片卡。如第2圖所示，一種晶片卡200主要包 含一晶片載體2 1 0、至少一微電子元件220、複數個間 隔維持件230、一第一晶片240以及一封膠體250。該 > 晶片卡 200可為記憶卡或微處理器卡。在本實施例 中，是以微型保全數位卡（Micro SD card)具體例舉 之。此外，該晶片卡200可另包含一第二晶片270， 設置於該第一晶片240之上方，而為多晶片堆疊之型 態。 如第2圖所示，該晶片載體2 1 0係具有一上表面 211與一下表面212。如第3圖所示，該上表面211定 義有一晶片設置區213，其尺寸對應於該第一晶片 2 4 0，即為被該第一晶片 2 4 0遮蓋的區域。該下表面 9 1312970 2 1 2形成有複數個外接觸指2丨4 ;而該晶片載體2丨〇之 上表面2 11係形成有複數個内接指2 1 5，並可透過如控制器 等之微電子元件220電性連接至該些外接觸指214。如第3 圖所示，該些内接指2 1 5係位於該晶片設置區2 1 3之外的 有限空間内。較佳地，該晶片載體2丨〇係可為—具有 黑色防銲層之印刷電路板而能與該封膠體2 5 〇為同一 顏色，具有外觀的一致整體性。-1312970 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer card, and more particularly to a wafer card for hiding a microelectronic component, particularly for a high-capacity micro-satellite digital card (Micro SD card) ). [Prior Art] Press, chip card (also known as 1C card or smart card) 'mainly can be distinguished as § memory card (memory c arr) micro _ processor card (microprocessorcard) two major categories Both internal packages are packaged with a memory chip. The size of the chip card has evolved from the size of the early credit card to the smaller and smaller, but the capacity requirements of the memory have become larger. For example, a memory card is a SD card, which is 32mm X 24mm X 2.1mm, and is internally sealed with a non-volatile memory chip, such as a NAND flash memory. body. In the recent generation of memory cards, the specification is a micro SD card, or T-flash card. The size of the micro SD card is 15mmX llrnmX lmm, and the memory capacity requirement is above 1GB. 4GB or more. The 'SD' is a shorthand for Secure Digital. In the early security digital card, a plurality of memory chips were first packaged into a TSOP or BGA type memory package, and then surface-bonded to a circuit board 'the lower case clips the circuit board to form A full digital card. However, this combination cannot meet the requirements of expanding the memory capacity and reducing the size of the wafer card. 5 . 1312970 As shown in FIG. 1 , a conventional wafer card 100 includes a substrate 11 0 , a plurality of first layer wafers 1 20 , a plurality of second layer wafers 1 30 , a gel 1 4 0 , and a micro Processor chip 1 51. Since the bonding surface of the wafer card 100 is mainly composed of the lower surface of the substrate 110, it must be flat and it is impossible to provide any electronic components on the lower surface. The first layer wafer 120, the microprocessor chip 151 and even the passive component 152 are disposed on the same upper surface of the substrate 110. The second layer of the wafer 130 is stacked on the corresponding first layer of the wafer 1 2 0 by the spacer 170, and the plurality of bonding wires 161 and 162 are electrically connected to the plurality of wires. The first layer of wafers 110 and the second layer of wafers 130 to the substrate 110, and finally the first layer of wafers 120 are sealed with the encapsulants 140, and the second layers of wafers 1 3 0. The microprocessor chip 151 and the passive component 152. The wafer card 100 has a joint area of about five times the area of the active surface 121 of the single first wafer 120. The overall size is too large to be suitable for microchip card applications. Since the microprocessor wafer 151 and the passive component occupy the surface area of the upper surface of the substrate 110, even if only a single set of the first wafer 120 and the second wafer 130 are retained, the wafer card 100 The junction area is also more than twice the area of the active surface 121 of the first wafer 120, and its memory capacity is also reduced. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a wafer card capable of incorporating microelectronic components to achieve high (memory) capacity and size reduction of the wafer card. 6 1312970 A second object of the present invention is to provide a wafer card which solves the problem of unbalanced upper and lower mold flow during wafer card sealing, and enables the sealing body to be filled in the gap between the wafer and the wafer carrier to seal the built-in Microelectronic components. Another object of the present invention is to provide a wafer card which can reduce the number of fingers of the wafer carrier outside the wafer placement area and arrange the in-line fingers in a limited area. The object of the present invention and solving the technical problems thereof are achieved by the following techniques > scheme. The invention discloses a wafer card, which mainly comprises a wafer carrier, at least one microelectronic component, a plurality of spacers, a first wafer and a gel. The wafer carrier has an upper surface and a lower surface defining a wafer placement area, the lower surface being formed with a plurality of external contact fingers. The microelectronic component is disposed in the wafer placement region of the wafer carrier and electrically connected to the wafer carrier. The spacers are disposed in the wafer carrier region of the wafer carrier and have a thickness higher than the thickness of the microelectronic device. The first wafer is attached to the spacers. The encapsulation system is formed on the wafer carrier and filled into the gap provided by the spacers to seal the first wafer and the microelectronic component. The size of the first wafer corresponds to the wafer placement area such that the microelectronic component is embedded between the wafer carrier and the first wafer. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the aforementioned wafer card, the wafer mounting area occupies at least 70% of the area above the surface of the wafer carrying the 7.1312970. In the aforementioned wafer card, the spacers are enamel posts or ridge bars. In the foregoing wafer card, the spacers are adjacent to the edge of the wafer setting region, and the first wafer has a plurality of first pads formed on an active surface edge of the first wafer. So that the interval maintaining members can be supported by the wire. In the foregoing wafer card, a mold flow balance control member is further included, and Φ is disposed above the first wafer, so that the distance between the mold flow balance control member and the top surface of the sealant is not greater than the wafer The separation distance of the carrier to the first wafer. In the foregoing wafer card, a plurality of first bonding wires are further included, which electrically connect the first bonding pads and the internal connecting fingers. In the aforementioned wafer card, the microelectronic component is a microcontroller chip. In the foregoing wafer card, a plurality of bonding wires are electrically connected to the microelectronic device and the wafer carrier, and the arcs of the bonding wires do not exceed the thickness of the spacers. In the foregoing wafer card, a second wafer is further stacked on top of the first wafer. In the foregoing wafer card, a spacer is further disposed between the first wafer and the second wafer. In the foregoing wafer card, the second wafer has a plurality of second pads formed on an active surface edge of the second wafer, and electrically connected by a plurality of second bonding wires by 8 1312970 a second pad to the wafer carrier. In the aforementioned wafer card, the wafer carrier is a printed circuit board having a black solder resist. In the aforementioned wafer card, the wafer card is a memory card or a microprocessor card. In the aforementioned wafer card, the wafer card is a micro SD card having a size of 15 mm X 11 mm X 1 mm. 1 In the aforementioned wafer card, the first wafer is a flash memory chip having a memory capacity of not less than 256 MB. [Embodiment] In one embodiment of the present invention, a wafer card that hides a microelectronic component is disclosed. As shown in FIG. 2, a wafer card 200 mainly includes a wafer carrier 210, at least one microelectronic component 220, a plurality of spacers 230, a first wafer 240, and a gel 250. The > wafer card 200 can be a memory card or a microprocessor card. In the present embodiment, a micro SD card is specifically exemplified. In addition, the chip card 200 may further include a second wafer 270 disposed above the first wafer 240 in a multi-wafer stack configuration. As shown in Fig. 2, the wafer carrier 210 has an upper surface 211 and a lower surface 212. As shown in Fig. 3, the upper surface 211 defines a wafer setting area 213 having a size corresponding to the first wafer 240, i.e., an area covered by the first wafer 220. The lower surface 9 1312970 2 1 2 is formed with a plurality of external contact fingers 2丨4; and the upper surface 2 11 of the wafer carrier 2 is formed with a plurality of internal fingers 2 15 , and can pass through, for example, a controller The microelectronic component 220 is electrically connected to the external contact fingers 214. As shown in Fig. 3, the inscribed fingers 2 15 are located in a limited space outside the wafer setting area 2 1 3 . Preferably, the wafer carrier 2 can be a printed circuit board having a black solder mask and can be of the same color as the sealant, and has a uniform appearance.
如第2及3圖所示，該微電子元件22〇係設置於該 曰曰片載體210之該晶片設置區213内並電性連接至該 晶片載體2 1 0。在本實施例中，該微電子元件22〇係 可為微控制器晶片（micro controller chip)。可利用 複數個第三銲線293，使該微電子元件22〇電性連接 至該晶片載體210，而該些第三銲線293之弧高應不 超過該些間I維持件23G之厚度。此外，該微電子元 件22 0另可包含有被動元件（圖未繪出）。 再如第2及3圖所示 q ,1 ‘ Ί尔說罝 於該晶片栽體210之該晶片設置區213内並具有一高 忒微電子几件22〇之厚度，以使該微電子元件 …40壓觸。較佳地，該些間隔維持件 糸’“夕質杈或是矽質條’以減少第—24 該些間隔綞垃μ 、牛230之接合界面之内應力。As shown in Figures 2 and 3, the microelectronic component 22 is disposed in the wafer placement region 213 of the wafer carrier 210 and is electrically coupled to the wafer carrier 210. In this embodiment, the microelectronic component 22 can be a micro controller chip. The plurality of third bonding wires 293 can be used to electrically connect the microelectronic component 22 to the wafer carrier 210, and the arc height of the third bonding wires 293 should not exceed the thickness of the inter-cell I sustaining members 23G. In addition, the microelectronic element 22 0 may further comprise a passive component (not shown). Further, as shown in FIGS. 2 and 3, q, 1 ' Ί 罝 罝 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该...40 pressure touch. Preferably, the spacers 糸'" or the enamel strips" are used to reduce the internal stress of the joint interface of the spacers 24 and 230.
古玄第-曰 LI ’此W J曰240係貼設於該些間隔維持件230上。 §亥些間隔維持件 緣，且該第 該晶片設置區213之邊 Χ 晶片240係具有複數個第一銲墊242， 10 1312970 八系升7成於°玄第—晶片240之-主動面24 1邊緣，以 吏^二間隔維持件23〇可供打線支撐。利用複數個第 #線291將該些第一鮮塾242電性連接至該晶片載體210 —内接扣215。在本實施例中，該第一晶片240係為 _揮發〖生°己憶體晶片’例如記憶體容量不小於2 5 6ΜΒ 之快閃記憶體晶片。The ancient Xuan-曰 LI ’ this W J曰 240 is attached to the spacers 230. Between the plurality of spacers, the wafer 240 has a plurality of first pads 242, 10 1312970, eight liters, 70%, and the active surface 24 of the wafers 240 1 edge, with 吏 ^ 2 interval maintaining member 23 〇 for wire support. The first fresh sputum 242 is electrically connected to the wafer carrier 210 - the inner buckle 215 by a plurality of # 291. In the present embodiment, the first wafer 240 is a flash memory wafer having a memory capacity of not less than 256 Å.
=°亥封膝體2 5 0係形成於該晶片載體2丨〇上並填入由 4 —間隔維持件2 3 0提供之間隙内，以密封該第一晶 片240與該微電子元件220。通常該封膠體250係由模 封陣列處理（Map Array Process，MAP)製程製作，該封膠體 250之四周側面係為七刀㈣成之^直側壁並切齊於該晶片载 體21〇之邊緣，而製&卡片龍。通常位在該晶片載體21〇 之下表面212之該些外接觸指214係為外露，不被該封膠體 〇覆蓋，以作為對外接觸用的電極。其中，該第一晶片 之尺寸係對應於該晶片設置區2 1 3，以使該微電子 元件220内藏於該晶片載體21〇與該第一晶片24〇之 間，藉此使得該晶片卡200能達到高（記憶體）容量與尺寸 縮小之功效。 在本實施例中，該晶片卡200係為一微型保全數位 卡（Micro SD card)，其尺寸係在 15mm X llmm χ lnim。如第3圖所示，該晶片載體21〇之上表面2ιι 在扣除微型保全數位卡之導滑缺口與扣接槽，其面積 約在1 50mm2。而該晶片設置區2丨3之尺寸係對應於該 第一晶片240之主動面241，約在14 3mm χ 9 〇mm， 11 1312970 故面積約在128.7mm2。因此，該晶片設置區213係可佔 據该晶片載體210之上表面211至少百分之七十以上的面 積而成為晶片尺寸等級之晶片卡。 在本實施例中，在該第一晶片2 4 0上可另疊設至少一 第二晶片270 ’以擴充記憶體容量或增加電子功能。 另’可在第一晶片240之主動面241上設置一間隔片 280 ’以供貼設該第二晶片270，並且避免該第二晶片 _ 270壓觸至該些第一銲線291。該第二晶片270係具有 複數個第二銲墊272，其係形成於該第二晶片270之 一主動面271邊緣’且藉由複數個第二銲線292電性 連接該些第二銲墊272至該晶片載體21〇之内接指 215 ° 在本實施例中’如第3圖所示，可以增加該些内接指2 1 5 沿晶片方向之長度，該些第一銲線291之一端係連接至對應 該些内接指2 1 5之一側，該些第二銲線292之一端係連接至 φ 對應該些内接指2 1 5之另—側，藉此使得訊號相通之該些内 接指21 5可供第一銲線29 1與第二銲線292所共用連接，以 減少該些内接指215在有限面積内之設置數量。 較佳地，該晶片卡2〇〇另包含有一模流平衡控制件 260，其係設置於該第—晶片24〇之上方，以使該模流 平衡控制件260至該封膠體25〇之頂面之間隔距離s2 不大於該晶片載體21 〇至該第一晶片24〇之間隔距離 S 1，解決該晶片卡200封膠時易有上下模流不平衡的 問題，能使該封膠體25〇填實於該第—晶片24〇與該 12 1312970 晶片載體210之間的間隙，以密 220而不會有内藏氣泡。在本實 控制件260係貼附於該第_ ^ —晶片 上，且該間隔距離S2係約略等同 以上所述，僅是本發明的較佳 本發明作任何形式上的限制，雖# 施例揭露如上，然而並非用以限； 本項技術者，在不脫離本發明之^ 任何簡單修改、等效性變化與修I 的技術範圍内。 【圖式簡單說明】 第1圖：習知一種多晶片封裝之晶 第2圖：依據本發明之一實施例， 之晶片卡之截面示意圖。 第3圖：依據本發明之一實施例 體上表面示意圖。 【主要元件符號說明】 1 0 0晶片卡 110基板 120第一層晶片 130第二層晶片140封膠體 1 5 1微處理器晶片 1 6 1銲線 1 6 2銲線 2 0 0晶片卡 210晶片載體 211上表面 封内藏之微電子元件 施例中，該模流平衡 27〇之主動面271 該間隔距離S1。 實施例而已，並非對 我本發明已以較佳實 t本發明’任何熟悉 I術範圍内，所作的 争，均仍屬於本發明 片卡之截面示意圖。 一種隱藏微電子元件 ，該晶片卡之晶片載 121主動面 1 5 2被動元件 1 7 0間隔物 2 1 2下表面 13 1312970 213 晶片設置區 214 外接觸指 215 内接指 220 微電子元件 230 間隔維持件 240 第一晶片 241 主動面 242 第 一鲜塾 250 封膠體 260 模流平衡控制件 270 第二晶片 271 主動面 272 第 二鲜塾 280 間隔片 291 第一銲線 292 第二銲線 293 第三銲線 SI 間隔距離 S2 間隔距離= °Hake the knee body 250 is formed on the wafer carrier 2丨〇 and filled in the gap provided by the 4-space maintaining member 203 to seal the first wafer 240 and the microelectronic element 220. Generally, the encapsulant 250 is fabricated by a Map Array Process (MAP) process, and the side surface of the encapsulant 250 is a seven-blade (four) straight sidewall and is aligned on the edge of the wafer carrier 21 And the system & card dragon. The outer contact fingers 214, which are typically located on the lower surface 212 of the wafer carrier 21, are exposed and are not covered by the encapsulant as an electrode for external contact. The size of the first wafer corresponds to the wafer setting area 21 to enable the microelectronic element 220 to be embedded between the wafer carrier 21 and the first wafer 24, thereby making the wafer card 200 can achieve high (memory) capacity and size reduction. In this embodiment, the wafer card 200 is a micro SD card having a size of 15 mm X llmm ln lnim. As shown in Fig. 3, the upper surface 2 of the wafer carrier 21 is deducted from the sliding gap and the fastening groove of the micro-preserving digital card, and the area thereof is about 150 mm 2 . The size of the wafer setting area 2丨3 corresponds to the active surface 241 of the first wafer 240, which is about 14 3 mm χ 9 〇 mm, 11 1312970, and the area is about 128.7 mm 2 . Therefore, the wafer setting area 213 is a wafer card of a wafer size class which can occupy at least 70% of the area of the upper surface 211 of the wafer carrier 210. In this embodiment, at least one second wafer 270' may be additionally stacked on the first wafer 240 to expand the memory capacity or to increase the electronic function. Alternatively, a spacer 280 ′ may be disposed on the active surface 241 of the first wafer 240 for attaching the second wafer 270, and the second wafer _ 270 may be prevented from being pressed against the first bonding wires 291. The second wafer 270 has a plurality of second pads 272 formed on the edge ′ of the active surface 271 of the second wafer 270 and electrically connected to the second pads by a plurality of second bonding wires 292. 272 to the inner carrier of the wafer carrier 21〇 215 ° In the present embodiment, as shown in FIG. 3, the length of the inner fingers 2 1 5 in the direction of the wafer may be increased, and the first bonding wires 291 One end is connected to one side of the corresponding inner finger 2 1 5 , and one end of the second bonding wire 292 is connected to φ to the other side of the inner connecting finger 2 1 5 , thereby making the signal communicate with each other The inner connecting fingers 215 can be commonly connected to the first bonding wires 29 1 and the second bonding wires 292 to reduce the number of the inner connecting fingers 215 disposed in a limited area. Preferably, the chip card 2 further includes a mold flow balance control member 260 disposed above the first wafer 24 to make the mold flow balance control member 260 to the top of the sealant 25 The spacing distance s2 is not greater than the distance S1 from the wafer carrier 21〇 to the first wafer 24〇, and the problem of unbalanced upper and lower mold flow is easy to solve when the wafer card 200 is sealed, so that the sealing body 25〇 can be The gap between the first wafer 24 and the 12 1312970 wafer carrier 210 is filled in a dense 220 without trapping air bubbles. The actual control member 260 is attached to the first wafer, and the spacing distance S2 is approximately equivalent to the above, and is merely a limitation of any form of the preferred invention of the present invention, although #example The above disclosure is not intended to limit the scope of the invention, and the technical scope of the invention is not limited to any simple modifications, equivalent changes, and modifications. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a crystal of a multi-chip package. FIG. 2 is a schematic cross-sectional view showing a wafer card according to an embodiment of the present invention. Figure 3 is a schematic illustration of the upper surface of a body in accordance with an embodiment of the present invention. [Main component symbol description] 100 chip card 110 substrate 120 first layer wafer 130 second layer wafer 140 encapsulant 1 5 1 microprocessor chip 1 6 1 bonding wire 1 6 2 bonding wire 2 0 0 chip card 210 wafer In the embodiment of the microelectronic component embedded in the upper surface of the carrier 211, the mold flow balances the active surface 271 of the 27 该 by the distance S1. The embodiments are not intended to be exhaustive or to be construed as a part of the invention. A hidden microelectronic component, the wafer carrier of the wafer card 121 active surface 1 5 2 passive component 1 70 spacer 2 1 2 lower surface 13 1312970 213 wafer setting area 214 external contact finger 215 internal finger 220 microelectronic component 230 spacing Continuation member 240 first wafer 241 active surface 242 first fresh 塾 250 encapsulant 260 mold flow balance control 270 second wafer 271 active surface 272 second fresh 280 spacer 291 first bonding wire 292 second bonding wire 293 Three wire bonding SI spacing distance S2 separation distance
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