.1316687 九、發明說明： 【發明所屬之技術領域】 本發明係有關於晶片卡，特別係有關於一種晶片尺 寸晶片卡，特別可應用在高容量之微型保全數位卡 (Micro SD card)。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer card, and more particularly to a wafer size wafer card, particularly for use in a high-capacity micro SD card. [Prior Art]
晶片卡（chip card)在某一程度又可稱為ic卡或智 慧卡（smart card)，主要區別為記憶卡（mein〇ry card)與 鲁 微處理器卡（microprocessorcard)兩大類，兩種内部皆 封裝有記憶體晶片。晶片卡尺寸從約早期的信用卡的大 小往越來越小的發展’然而記憶體的容量要求卻越來 越大。例如一種記憶卡的規格係為保全數位卡（SD card) ’其尺寸為3 2mm X 24mm X 2.1 mm，内部封設有非 揮發性s己憶體晶片（non-volatile memory chip)，如快閃記情 體。在近一代的記憶卡的規格係為微型保全數位卡 • (micro SD card) ’ 其尺寸為 15mm X 11mm X 1mm，且記 憶體容量需求是在1GB以上，甚至於4 GB或更高。其 中’ SD係為Secure Digital之簡寫。 在早期的保全數位卡中，複數個記憶體晶片是先行封裝 成TSOP或BGA類型的記憶體封裝件（package)，再表面接 合至一電路板，以上下殼體夹扣該電路板，以組成一保全數 位卡。但是這種組合方式無法達到擴大記憶體容量與縮小晶 片卡尺寸的要求。 如第1圖所示’一種習知之晶片卡1〇〇包含一基板 5 • 1316687 11 ο、複數個第一層晶片1 20、複數個第二層晶月 一封膠體140以及一微處理器晶片151。由於 . 卡 100之接合面主要係由該基板 110之下表 成，必須為平坦狀，無法在下表面設置任何電子 該些第一層晶片120、該微處理器晶片151甚 元件152皆設置於該基板110之同一上表面。 二層晶片1 3 0則藉由間隔物1 7 0疊設於對應之 晶片120之上，複數個銲線1 61與1 62分別電 ® 該些第一層晶片120與該些第二層晶片130至 1 1 0，最後並以該封膠體 1 4 0密封該些第一 120、該些第二層晶片130、微處理器晶片151 元件 152。此一晶片卡 100之接合面面積約為 一層晶片120之主動面121面積之五倍，整個 大，不適用於微型晶片卡之應用。即使僅保留 的第一層晶片1 20與第二層晶片1 3 0，晶片卡 _ 接合面面積亦在第一層晶片120之主動面121 兩倍以上，並且其記憶體容量亦是被縮小。 【發明内容】 為了解決上述之問題，本發明之主要目的係 供一種晶片尺寸晶片卡，具有卡片為晶片尺寸 記憶體容量之功效。 本發明之次一目的係在於提供一種晶片尺 卡，能使多晶片水平堆疊，以在有限厚度下（約 避免晶片外露與金線外露之發生，並可將至少 丨 130、 該晶片 面所構 元件。 至被動 該些第 第一層 性連接 該基板 層晶片 與被動 單一第 尺寸過 單一組 100之 面積之 在於提 與具高 寸晶片 1.0mm) 一微電 6 ,1316687 子元件内嵌埋於黏晶層内。 本發明之再一目的係在於提供一種晶片尺寸晶片 卡’能減少晶片載體之内接指數量並使該些内接指密集 直線排列在一有限面積内。 本發明的目的及解決其技術問題是採用以下技術 方案來實現的。本發明揭示—種晶片尺寸晶片卡，主 要包含一具有複數個外接觸指之晶片載體、至少一設置於 該晶片載體上之微電子元件、一第一黏晶層、一第一晶片以 及封膠肚該第-黏晶層係形成於該晶片載體上並具有一 高於該微電子元件之厚度’以嵌埋該微電子元件。該第一晶 片係貼口又於該第一黏晶層i。該封膠體係形成於該晶片載體 上以密封該第一晶片。其中，該晶片卡係具有一外露該些外 接觸指之接合面，該微電子元件内藏於該第一晶片之下方， 以使該接合面之面積係介於該第一晶片之一主動面之i.O至 1.5 倍。 本發明揭示另一種晶片尺寸晶片卡，主要包含一具 有複數個外接觸指之晶片載體、一設置於該晶片載體 上之第一晶片、一疊設於該第一晶片上之第二晶片以 及一封膠體。該封膠體係形成於該晶片載體上，以密 封該第一晶片與該第二晶片。其中，該晶片卡係具有 一外露該些外接觸指之接合面，該接合面之面積係介 於該第一晶片之一主動面之1〇炱15倍，亦介於該第 二晶片之一主動面之1.0至1.5倍。 本發明的目的及解決其技術問題還可採用以下技 7 .1316687 術措施進一步實現。 前述的晶片尺寸晶片卡，其中該第一黏晶層係 . 含有複數個第一間隔球之黏膠，用以限定該第一 _ 層之厚度並使該第一晶片平行於該晶片載體。 前述的晶片尺寸晶片卡，其中該些第一間隔球 電絕緣性。 前述的晶片尺寸晶片卡，其中該微電子元件係 微控制器晶片。 ® 前述的晶片尺寸晶片卡，另包含有複數個銲線 係電性連接該微電子元件與該晶片載體並被該第 晶層所密封。 前述的晶片尺寸晶片卡，另包含有一間隔物， 形成於該微電子元件上，且該間隔物之厚度係大 述銲線之弧高。 前述的晶片尺寸晶片卡，其中該間隔物係為一 I 有複數個間隔球之内層黏晶層，該些間隔球之球 大於上述銲線之弧高。 前述的晶片尺寸晶片卡’其中該晶片載體係為 路基板，而該接合面係為該晶片載體之一下表面 前述的晶片尺寸晶片卡，其中該晶片載體之一 面係形成有複數個内接指。 前述的晶片尺寸晶片卡，另包含有複數個第 線，以電性連接該第一晶片之銲墊至該些内接指 前述的晶片尺寸晶片卡，其中該晶片卡係為記 為内 黏晶 係為 為一 ，其 一黏 其係 於上 内含 南係 一電 0 上表 一銲 0 憶卡 8 1316687 或微處理器卡。The chip card can be called an ic card or a smart card to some extent. The main difference is the mein〇ry card and the microprocessor card. Both are packaged with a memory chip. The size of the chip card has evolved from the size of the early credit card to smaller and smaller. However, the capacity requirements of the memory are getting bigger and bigger. For example, a memory card is a SD card that has a size of 3 2mm X 24mm X 2.1 mm and is internally sealed with a non-volatile memory chip, such as a flash memory. Love. In the recent generation of memory cards, the specification is a micro SD card. The size of the memory card is 15mm X 11mm X 1mm, and the memory capacity requirement is 1GB or more, or even 4 GB or higher. The 'SD' is a shorthand for Secure Digital. In the early security digital card, a plurality of memory chips were first packaged into a TSOP or BGA type memory package, and then surface-bonded to a circuit board, and the upper and lower cases were clipped to form a circuit board to constitute a memory package. A full digital card. However, this combination cannot meet the requirements of expanding the memory capacity and reducing the size of the wafer card. As shown in FIG. 1 'a conventional wafer card 1 〇〇 includes a substrate 5 • 1316687 11 ο , a plurality of first layer wafers 1 20 , a plurality of second layer wafers 140 , and a microprocessor chip 151. Since the bonding surface of the card 100 is mainly formed by the lower surface of the substrate 110, it must be flat, and no electrons can be disposed on the lower surface. The first layer wafer 120, the microprocessor chip 151 and the other components 152 are disposed on the bottom surface. The same upper surface of the substrate 110. The two-layer wafer 130 is stacked on the corresponding wafer 120 by spacers 170, and the plurality of bonding wires 1 61 and 1 62 are electrically charged to the first layer wafers 120 and the second layer wafers. 130 to 110, and finally sealing the first 120, the second layer wafer 130, and the microprocessor chip 151 element 152 with the encapsulant 140. The wafer card 100 has a joint area of about five times the area of the active surface 121 of the wafer 120, which is large and is not suitable for microchip cards. Even if only the first layer wafer 126 and the second layer wafer 130 are left, the wafer card _ bonding surface area is more than twice that of the active surface 121 of the first layer wafer 120, and the memory capacity thereof is also reduced. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a wafer size wafer card having the effect that the card is a wafer size memory capacity. A second object of the present invention is to provide a wafer ruler capable of horizontally stacking a plurality of wafers at a limited thickness (to avoid wafer exposure and gold wire exposure, and at least 丨130, the wafer surface structure) Component to the passive first layer of the substrate layer wafer and the passive single size over a single group 100 is raised with a high inch wafer 1.0mm) a micro-electric 6,1316687 sub-component embedded in Within the sticky layer. It is still another object of the present invention to provide a wafer size wafer card which reduces the number of fingers in the wafer carrier and allows the inscribed fingers to be densely aligned in a limited area. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a wafer size wafer card, which mainly comprises a wafer carrier having a plurality of external contact fingers, at least one microelectronic component disposed on the wafer carrier, a first die layer, a first wafer and a sealant. The first-mud layer is formed on the wafer carrier and has a thickness 'below the microelectronic element' to embed the microelectronic element. The first wafer is attached to the first die layer i. The encapsulation system is formed on the wafer carrier to seal the first wafer. Wherein the wafer card has a bonding surface exposing the external contact fingers, the microelectronic component being embedded under the first wafer such that an area of the bonding surface is interposed between one active surface of the first wafer iO to 1.5 times. The invention discloses another wafer size wafer card, which mainly comprises a wafer carrier having a plurality of external contact fingers, a first wafer disposed on the wafer carrier, a second wafer stacked on the first wafer, and a Sealing body. The encapsulation system is formed on the wafer carrier to seal the first wafer and the second wafer. Wherein the wafer card has a bonding surface exposing the external contact fingers, the bonding surface having an area of 1〇炱15 times of the active surface of the first wafer, and also being between the second wafer The active surface is 1.0 to 1.5 times. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. The aforementioned wafer size wafer card, wherein the first die layer comprises a plurality of first spacer ball adhesives for defining a thickness of the first layer and making the first wafer parallel to the wafer carrier. The aforementioned wafer size wafer card, wherein the first spacer balls are electrically insulating. The aforementioned wafer size wafer card, wherein the microelectronic component is a microcontroller chip. The aforementioned wafer size wafer card further includes a plurality of bonding wires electrically connecting the microelectronic component to the wafer carrier and being sealed by the first crystal layer. The aforementioned wafer size wafer card further includes a spacer formed on the microelectronic element, and the thickness of the spacer is an arc height of the bonding wire. In the above wafer size wafer card, the spacer is an inner layer of a plurality of spacer balls, and the balls of the spacer balls are larger than the arc height of the bonding wires. The wafer size wafer card of the foregoing is the substrate of the wafer, and the bonding surface is the wafer size wafer card of the lower surface of the wafer carrier, wherein the wafer carrier is formed with a plurality of internal fingers. The chip-size wafer card further includes a plurality of first lines electrically connected to the pads of the first wafer to the wafer-sized wafer cards of the internal contacts, wherein the wafer card is recorded as an internal die The system is one, and the other is attached to the upper part of the south line. The upper part of the table is a 0-return card 8 1316687 or a microprocessor card.
前述的晶片尺寸晶片卡’其中該晶片卡係為一微型 保全數位卡（Micro SD card)，其尺寸係在 15mm X 1 1 mm X 1 mm。 前述的晶片尺寸晶片卡’其中該接合面更不大於該 第一晶片之主動面之1.2倍面積，且該第一晶片之記 憶體容量係不小於256MB。 【實施方式】 在本發明之第一具體實施例中，揭示一種晶片尺寸 晶片卡，其晶片卡之外觀尺寸將接近晶片之尺寸，達 到真正的晶片卡微小化。如第2圖所示，一種晶片尺 寸晶片卡2 0 0主要包含一具有複數個外接觸指2 i 3之晶片 載體210、至少一設置於該晶片載體21〇上之微電子元件 220、一第一黏晶層231、一第一晶片230以及一封膠體250。 該晶片卡200可為記憶卡或微處理器卡，在本實施例 中’是以微型保全數位卡（Micro SD card)具體例舉之。 如第2圖所示，該晶片載體210係可為一電路基板， 例如小型印刷電路板或是電路薄膜。該晶片載體210係具有 上表面211與一下表面212。該些外接觸指213係形成於 該下表面212之一側邊；而該晶片載體210之上表面211係 形成有複數個内接指214，可透過控制器等微電子元件220 電性連接至該些外接觸指2 1 3。 在本實施例中，該微電子元件220係可為一微控制器 曰日片（micro controller chip).。或可包含有被動元件與 ‘1316687 邏輯元件等等。另可利用複數個第三銲線263、凸塊 或錫膏’使該微電子元件220電性連接至該晶片載體 210 ° 該第一黏晶層231係形成於該晶片載體210上並具有一 高於該微電子元件220之厚度，以嵌埋該微電子元件22〇。 在本實施例中’該第一黏晶層2 3 1更密封該些第三銲線 263。 該第一晶片230係貼設於該第一黏晶層231上，可藉由 鲁 該第一黏晶廣231黏接該第一晶片230之背面，該第一晶片 230之一主動面234上形成有複數個銲墊232。並可利用複 數個第一銲線261將該第一晶片230之銲墊232電性連接至 該晶片載體210之該些内接指214。在本實施例中，該第一 晶片230係為一非揮發性記憶體晶片，例如記憶體容量不 小於25 6MB之NAND型快閃記憶體晶片。 該封膠體250係形成於該晶片載體210之上表面2U，以 φ 密封該第一晶片230。該封膠體250之四周側面係為切割形 成之垂直側壁並切齊於該晶片載體210之邊緣，而為卡片型 態。故該晶片卡200之接合面係至少包含有該晶片載體2工〇 之下表面212 ’並外露出位在下表面212之該些外接觸指 213(如第3圖所示）。由於該微電子元件22〇係被該第—黏晶 層23 1所嵌埋密封，故該微電子元件22〇係内藏於該第一晶 片230之下方，以使該接合面之面積係介於該第一晶片23〇 之一主動面234之1.0至1.5倍。在本實施例中，該晶片 卡200係為一微型保全數位卡（Micr〇叩card)，其尺 10 .1316687 寸係在 15mmXllmmXlmni。玲 孩晶片卡200扣除如第 3圖所示其下方導滑缺口與扣接缺口該晶片卡2〇〇 之接合面（主要係為該晶片栽體21〇之下表面212)面積 約在150mm2。在本實施例中，4 T該第一晶片230之主動面 234之尺寸約在14.3mm χ 9 〇職，其面積約在 128.7mm2。該接合面之面積約為該第一晶片咖之主動面 234之丨.16倍。故該接合面更可控制在不大於該第一晶 片230之主動面234之1.2倍面積。因此，該晶片載 體210之上表面211中，該微電子元件22〇的設置面 積係重疊在該第一晶片2 3 〇之黏晶面積以内，整個晶 片卡200之接合面面積會接近第一晶片23〇之主動面 234面積，在有限的晶片卡2〇〇尺寸内封設大記憶體 各量的第一晶片23 〇，故提供一種晶片尺寸與高記憶 體谷量之微型晶片卡200，以符合晶圓切割效益。 較佳地，在該第一晶片230上可另疊設至少一第二 晶片240 ’以在有限的接合面内擴充記憶體容量。在 本實施例中’該第一晶片230與該第二晶片240係為同尺 寸同谷量之非揮發性記憶體晶片。該接合面（約為該晶 片载體210之下表面212)之面積亦介於該第二晶片 24〇之一主動面244之L〇至15倍。通常在第一晶片 230之主動面234上形成有一第二黏晶層241，其係黏 _^变.士歹 Λ-j^： μ第二晶片240之背面，該第二晶片24〇之主動面 44上係形成有複數個銲墊242。複數個第二銲線262係 丨生連接該第二晶片240之銲墊242與該晶片載體21〇之該 11 .1316687 些内接指214。如第4圖所示，在本實施例中，該些第一銲 線261之一端係連接至該些内接指214之—側，該些第二銲 線262之一端係連接至該些内接指214之另一側，藉此使得 訊號相通之該些内接指214為第一銲線261與第二銲線262 所共用連接，可以減少内接指214之數量。較佳地，由於晶 片尺寸之空間限制，該第一晶片230與該第二晶片24〇之邊 緣過於接近該晶片載體210之一邊緣（兩者邊緣的水平面間 隙約只有400μιη) ’使得該些内接指214為橫置擺設，即該 鲁 些内接^曰214之較長邊係與該晶片載趙21〇之鄰近邊緣為平 行，故該些内接各214之較短邊長度將不足以可供銲線的終 結接點（second bond)在打線接合時被拉斷。因此，在本實施 例中，如第4圖所示，該些第一銲線261之起始接點 261A(firStb〇nd，或可稱為結球端）應接合在對應内接指214 之一側，該些第二銲線262之起始接點262A應接合在對應 内接指214之另一側，且該些第一銲線261之起始接點261A φ 與該些第二銲線262之起始接點262A的排列方向是與該晶 片裁體210之鄰近邊緣為同向’以有效運用該晶片載體21〇 之上表面211在黏晶後的剩餘面積。此外，該微電子元件220 除了可嵌埋於s亥第一黏晶層231内，或可彼埋於該第二黏晶 層241内。 尤佳地，該第一黏晶層231係為内含有複數個第一 間隔球23 3之黏膠’用以限定該第一黏晶層23丨之厚 度並使該第一晶片230平行於該晶片載體2 i 〇，且能 黏接該第一晶片2 3 0。該些第一間隔球2 3 3係可為電 12 •1316687 絕緣丨生，以避免導接該些第三銲線263。此外，形成在 該第阳片230與該第二晶片240之間的第二黏晶層241亦 • 可内含有複數個第二間隔球243之黏膠，以使該第二晶片 2 4 0平朽於》士女α . 、〇第一曰日片230。因此，該第一晶片230與該 第一 μ片240在黏晶之後不會有歪斜現象，在受限的厚度 下該封膝體250之表面不會晶片外露與金線外露的問題。 因此該封膠體250之厚度係大於該第一晶片23〇、該第二 φ ββ片40該第一黏晶層23 1與該第二黏晶層241之厚度， 且°亥封膠體250與該晶片載體210之總厚度能控制在不超過 1.0mm的條件。 另’在本實施例中’該晶片卡2〇〇另包含有一間隔 ’其係形成於該微電子元件220上，且該間隔 物221之厚度係大於上述第三銲線263之弧高。該間 隔物221亦可為一内含有複數個第三間隔球222之内 層黏甜層’該些第三間隔球222之球直徑應小於上述 • 第一間隔球233之球直徑，以避免該第一晶片230壓 觸呈該些第三銲線263。 在本發明之第二具體實施例中，如第5圖所示，揭 不另一種晶片尺寸晶片卡3〇〇，主要包含一具有複數個 外接觸指313之晶片載體310、至少一設置於該晶片載體31〇 上之微電子元件320、一黏晶層331、一晶片330以及一封 膠體340。該晶片載體則係具有一上表面311與—下表面 312 ’該些外接觸指313係位於該下表面312,且複數個内接 ^ 314係形成於該上表面311。該微電子元件320係可為一 13 .1316687 微處理器晶片，可覆晶接合至該晶片載體3 10之上表面 3 11。該黏晶層33 1係形成於該晶片載體3 10之上表面3 !丄 並具有一高於該微電子元件320之厚度，以嵌埋該微電子元 件320，以使該微電子元件320重疊於該晶片330之黏晶區 内。較佳地’在被該黏晶層3 3 1所密封之黏晶區另可設置有 至少一被動元件321»而該些内接指314係位於該黏晶層331 覆蓋區域之外。The aforementioned wafer size wafer card' wherein the wafer card is a micro SD card having a size of 15 mm X 1 1 mm X 1 mm. In the foregoing wafer size wafer card, wherein the bonding surface is no more than 1.2 times the area of the active surface of the first wafer, and the memory capacity of the first wafer is not less than 256 MB. [Embodiment] In a first embodiment of the present invention, a wafer size wafer card is disclosed in which the apparent size of the wafer card is close to the size of the wafer to achieve a true wafer card miniaturization. As shown in FIG. 2, a wafer size wafer card 200 mainly includes a wafer carrier 210 having a plurality of external contact fingers 2 i 3 , at least one microelectronic component 220 disposed on the wafer carrier 21 , and a first A die layer 231, a first wafer 230, and a colloid 250. The chip card 200 can be a memory card or a microprocessor card, and is specifically exemplified in the present embodiment by a micro SD card. As shown in FIG. 2, the wafer carrier 210 can be a circuit substrate such as a small printed circuit board or a circuit film. The wafer carrier 210 has an upper surface 211 and a lower surface 212. The outer contact fingers 213 are formed on one side of the lower surface 212. The upper surface 211 of the wafer carrier 210 is formed with a plurality of internal fingers 214 electrically connected to the microelectronic component 220 such as a controller. These external contacts refer to 2 1 3 . In this embodiment, the microelectronic component 220 can be a microcontroller micro controller chip. Or it can contain passive components with '1316687 logic components and so on. The microelectronic component 220 can be electrically connected to the wafer carrier 210 by using a plurality of third bonding wires 263, bumps or solder pastes. The first bonding layer 231 is formed on the wafer carrier 210 and has a Above the thickness of the microelectronic element 220, the microelectronic element 22 is embedded. In the present embodiment, the first adhesive layer 2 3 1 further seals the third bonding wires 263. The first wafer 230 is attached to the first die layer 231, and the back surface of the first die 230 is adhered to the active surface 234 of the first die 230. A plurality of pads 232 are formed. The pads 232 of the first wafer 230 can be electrically connected to the inscribed fingers 214 of the wafer carrier 210 by a plurality of first bonding wires 261. In this embodiment, the first wafer 230 is a non-volatile memory chip, such as a NAND-type flash memory chip having a memory capacity of not less than 25 6 MB. The encapsulant 250 is formed on the upper surface 2U of the wafer carrier 210 to seal the first wafer 230 with φ. The sides of the encapsulant 250 are cut to form vertical sidewalls and are aligned with the edge of the wafer carrier 210 to form a card. Therefore, the bonding surface of the wafer card 200 includes at least the lower surface 212' of the wafer carrier 2 and the outer contact fingers 213 (shown in Fig. 3) exposed on the lower surface 212. The microelectronic device 22 is embedded in the first die 230, so that the area of the bonding surface is integrated. The active surface 234 of one of the first wafers 23 is 1.0 to 1.5 times. In this embodiment, the chip card 200 is a micro-credit card, and the ruler 10 .1316687 is at 15 mm X 11 mm Xlmni. The wafer card 200 is deducted as shown in Fig. 3, and the area of the lower sliding contact and the fastening notch of the wafer card 2 (mainly the surface 212 of the wafer carrier 21) is about 150 mm2. In this embodiment, the active surface 234 of the first wafer 230 is about 14.3 mm χ 9 ,, and its area is about 128.7 mm 2 . The area of the joint is about 16 times that of the active surface 234 of the first wafer. Therefore, the joint surface can be controlled to be no more than 1.2 times the area of the active surface 234 of the first wafer 230. Therefore, in the upper surface 211 of the wafer carrier 210, the disposed area of the microelectronic device 22 is overlapped within the die area of the first wafer 2, and the bonding surface area of the entire wafer card 200 is close to the first wafer. 23" active surface 234 area, the first wafer 23 大 of large memory is enclosed in a limited size of the wafer card, so a microchip card 200 with a wafer size and a high memory valley is provided. Meets wafer cutting benefits. Preferably, at least one second wafer 240' may be additionally stacked on the first wafer 230 to expand the memory capacity within a limited bonding surface. In the present embodiment, the first wafer 230 and the second wafer 240 are non-volatile memory wafers of the same size and the same amount. The area of the interface (about the lower surface 212 of the wafer carrier 210) is also between 15 and 15 times the active surface 244 of the second wafer 24 . Generally, a second adhesive layer 241 is formed on the active surface 234 of the first wafer 230, which is bonded to the back surface of the second wafer 240, and the second wafer 24 is actively activated. A plurality of pads 242 are formed on the face 44. A plurality of second bonding wires 262 are connected to the pads 242 of the second wafer 240 and the 11.1316687 internal fingers 214 of the wafer carrier 21. As shown in FIG. 4, in the embodiment, one end of the first bonding wires 261 is connected to the side of the inner connecting fingers 214, and one end of the second bonding wires 262 is connected to the inner ends. The other side of the finger 214 is such that the inscribed fingers 214 of the signal communication are connected by the first bonding wire 261 and the second bonding wire 262, and the number of the internal fingers 214 can be reduced. Preferably, due to the space limitation of the wafer size, the edges of the first wafer 230 and the second wafer 24 are too close to one edge of the wafer carrier 210 (the gap between the edges of the edges is only about 400 μm). The connecting finger 214 is a transverse arrangement, that is, the longer side of the inner connecting portion 214 is parallel to the adjacent edge of the wafer carrying surface 21, so the shorter side length of the inner connecting portions 214 will not be sufficient. The second bond that can be used for the wire bond is broken when the wire is bonded. Therefore, in the present embodiment, as shown in FIG. 4, the starting contact 261A (firStb〇nd, or may be referred to as the ball end) of the first bonding wires 261 should be bonded to one of the corresponding internal fingers 214. On the side, the starting contact 262A of the second bonding wires 262 should be joined to the other side of the corresponding internal finger 214, and the starting contacts 261A φ of the first bonding wires 261 and the second bonding wires The starting contact 262A of 262 is arranged in the same direction as the adjacent edge of the wafer blank 210 to effectively utilize the remaining area of the wafer carrier 21 above the surface 211 after the die bonding. In addition, the microelectronic component 220 may be embedded in the first die layer 231 or may be buried in the second die layer 241. More preferably, the first adhesive layer 231 is an adhesive having a plurality of first spacer balls 23 3 for limiting the thickness of the first adhesive layer 23 and making the first wafer 230 parallel to the The wafer carrier 2 i 〇 is capable of bonding the first wafer 203. The first spacer balls 2 3 3 may be electrically insulated 12 1316687 to avoid guiding the third bonding wires 263. In addition, the second adhesive layer 241 formed between the second positive electrode 230 and the second wafer 240 may also contain a plurality of adhesives of the second spacer ball 243 to make the second wafer 240. It is ruined by the "woman" α. Therefore, the first wafer 230 and the first microchip 240 are not skewed after being bonded, and the surface of the sealing body 250 does not have the problem of exposed wafers and exposed gold wires at a limited thickness. Therefore, the thickness of the encapsulant 250 is greater than the thickness of the first wafer 23〇, the second φββ sheet 40, the first viscous layer 23 1 and the second viscous layer 241, and The total thickness of the wafer carrier 210 can be controlled to a condition of not more than 1.0 mm. In the present embodiment, the wafer card 2 further includes a spacer formed on the microelectronic device 220, and the spacer 221 has a thickness greater than an arc height of the third bonding wire 263. The spacer 221 may also be an inner layer of a sweet layer containing a plurality of third spacer balls 222. The diameter of the balls of the third spacer balls 222 should be smaller than the diameter of the ball of the first spacer ball 233 to avoid the first A wafer 230 is pressed against the third bonding wires 263. In the second embodiment of the present invention, as shown in FIG. 5, another wafer size wafer card is disclosed, which mainly includes a wafer carrier 310 having a plurality of external contact fingers 313, at least one of which is disposed on the wafer carrier 310. A microelectronic component 320, a die layer 331, a wafer 330, and a gel 340 are disposed on the wafer carrier 31. The wafer carrier has an upper surface 311 and a lower surface 312'. The outer contact fingers 313 are located on the lower surface 312, and a plurality of inner contacts 314 are formed on the upper surface 311. The microelectronic component 320 can be a 13.1316687 microprocessor die that can be flip-chip bonded to the upper surface 31 of the wafer carrier 3 10 . The die layer 33 1 is formed on the upper surface 3 of the wafer carrier 3 10 and has a thickness higher than the thickness of the microelectronic component 320 to embed the microelectronic component 320 such that the microelectronic component 320 overlaps. In the die bond region of the wafer 330. Preferably, at least one passive component 321» is disposed in the die bond region sealed by the die bond layer 33, and the inner fingers 314 are located outside the coverage area of the die bond layer 331.
並且’該晶片330係貼設於該黏晶層33丨上，並以複數 個銲線350電性連接在該晶片330主動面333上之銲塾332 至該晶片載體310之内接指314。該封膠體34〇係形成於該 曰b片載體310上，以密封該晶片330與該黏晶層331。其中， 該晶片卡300係具有一外露該些外接觸指313之接合面，其 主要係由該晶片載體310之下矣而4生丄、 心r衣面312所構成。由於該微電 子元件320内藏於該晶片330之下士 ·、,冰外·!*人— 下方，以使該接合面之面積 月匕介於該晶片330之該主動面333之1〇至倍。 以上所述，僅是本發明沾& ^ & s月的較佳實施例而已，並非對 本發明作任何形式上的限制 ^ ^ ^ J |氏制’雖然本發明已以較佳實 施例揭露如上’然而並非用 开用以限定本發明，任何熟悉 本項技術者，在不脫離本發日日+ ♦赞明之技術範圍内，所作的 任何簡單修改、等效性變化盥 艾1匕興修飾，均仍屬於本發明 的技術範圍内。 【圖式簡單說明】And the wafer 330 is attached to the bonding layer 33, and is electrically connected to the bonding pad 332 on the active surface 333 of the wafer 330 to the internal finger 314 of the wafer carrier 310 by a plurality of bonding wires 350. The encapsulant 34 is formed on the 曰b sheet carrier 310 to seal the wafer 330 and the die layer 331. The wafer card 300 has a joint surface on which the external contact fingers 313 are exposed, and is mainly composed of the wafer carrier 310 and the core surface 312. Since the microelectronic component 320 is embedded in the wafer 330, the icy, and the outside of the wafer, so that the area of the bonding surface is between 1 and 2 times the active surface 333 of the wafer 330. . The above description is only a preferred embodiment of the present invention and does not impose any form of limitation on the present invention. Although the present invention has been disclosed in the preferred embodiments, As above, however, it is not intended to limit the invention, and any simple modifications and equivalent changes made by those skilled in the art without departing from the scope of the present invention will be modified. All remain within the technical scope of the present invention. [Simple description of the map]
1圖：習知一種多晶片封裝之晶片卡 2圖：依據本發明之第—實施例， 之截面示意圖 一種晶片尺寸 〇 晶 14 •1316687 片卡之截面示意圖。 第3.圖：依據本發明之第一實施例，該晶片尺寸晶片 卡之接合面示意圖。 第4圖.依據本發明之第一實施例，該晶片尺寸晶片 卡之晶片載體之内接指示意圖。 第5圖：依據本發明之第二實施例，另一種晶片尺寸 晶片卡之截面示意圖。 【主要元件符號說明】1 is a conventional wafer card of a multi-chip package. FIG. 2 is a cross-sectional view showing a wafer size crystallization of a wafer of a 13:1316687 chip according to a first embodiment of the present invention. Figure 3. Schematic diagram of the bonding surface of the wafer size wafer card in accordance with a first embodiment of the present invention. Fig. 4 is a schematic view showing the internal finger of the wafer carrier of the wafer size wafer card in accordance with the first embodiment of the present invention. Figure 5 is a cross-sectional view showing another wafer size wafer card in accordance with a second embodiment of the present invention. [Main component symbol description]
100晶片卡 161 銲 線 200 晶 片尺寸晶 210 晶 片載體 213 外接觸指 220 微 電子元件 230 第 一晶片 233 第 一間隔球 240 第 —晶片 243 第 —間隔球 261 第 一銲線 262 第 二銲線 263 第 三銲線100 wafer card 161 bonding wire 200 wafer size crystal 210 wafer carrier 213 outer contact finger 220 microelectronic component 230 first wafer 233 first spacer ball 240 first wafer 243 first spacer ball 261 first bonding wire 262 second bonding wire 263 Third wire
110基板 120第一層晶片 130第二層晶片140封膠體 1 5 1微處理器晶片 1 6 2銲線 片卡 211上表面 214内接指 221間隔物 2 3 1第—黏晶層 234主動面 241第二黏晶層 244主動面 261A起始接點 262A起始接點 121主動面 1 5 2被動元件 1 7 〇間隔物 212下表面 222第三間隔球 232銲墊 242銲墊 250封膠體 15 1316687 300 3 10 313 320 330 333 340 晶片尺寸晶片卡 晶片載體 3 11上表面 外接觸指 314内接指 微電子元件 321被動元件 晶片 331黏晶層 主動面 封膠體 350銲線110 substrate 120 first layer wafer 130 second layer wafer 140 encapsulant 1 5 1 microprocessor wafer 1 6 2 wire bond card 211 upper surface 214 inscribed fingers 221 spacers 2 3 1 first - sticky layer 234 active surface 241 second bonding layer 244 active surface 261A starting contact 262A starting contact 121 active surface 1 5 2 passive component 1 7 〇 spacer 212 lower surface 222 third spacer ball 232 pad 242 pad 250 sealing body 15 1316687 300 3 10 313 320 330 333 340 Wafer Size Wafer Card Wafer Carrier 3 11 Upper Surface External Contact Finger 314 Inscribed Finger Microelectronic Component 321 Passive Component Wafer 331 Bonded Layer Active Surface Sealant 350 Solder Wire