經濟部中次標隼局UKJE.消资合作社印製 4369 4 8 at B-7 _ 五、發明説明（I ) (一) 發明技術領域： 本發明係有關於一種多晶片半導體封裝結構及製法。 尤指一種可將兩個以上相同或不同功能之晶片堆疊於同一 包裝中，且其中之一晶片係以導線架之引腳作爲與外界連 結之介面而另有一晶片則係以錫球作爲與外界連結之介面 之多晶片半導體封裝結構及製法。 (二) 發明技術背景： 在現今半導骽製造的趨勢中，如何能在愈小的半導體 包裝中擠入愈多的邏輯電路而成本卻能相對降低，乃是全 球半導體業者所一致全力研究的課題，所以於此領域中的 研究、競爭也因此非常激烈》除了以不斷研發縮小晶片上 之電路設計的最小元件尺寸方式之外，另一種可以最低成 本直接達到單一半導體包裝之記憶容量倍增的方式，便是 在同一包裝中擠入兩片以上的晶片。 如圖一所示，爲習用之多晶片半導體封裝結構的一 例。其主要是藉由「引腳上著於晶片（Lead On Chip ;簡 稱LOC)」的技術將兩片晶片la、lb以熱熔性雙面膠帶 2a、2b分別結合於兩導線架3a、3b上，並以金線4a、4b (Gold Hre)分別焊接（Bonding)耦合晶片la、lb上之 電路與導線架3a、3b之相對應的引腳後，再把導線架3a上 的引腳架設連接於導線架3b之引腳6上，最後再加以灌注 封裝樹脂5 (Molding)成形爲一體的半導體封裝元件 (1C)。惟，此種單純以導線架之引腳6來作爲多個晶片 la、lb上之電路與外界聯通介面的最大缺點，便是引腳6 -2- 本紙張尺度適用中國國家揉準（CMS ) A4規格（2!0)<297公釐） (請先鬩讀背面之注意事項再填葙本頁) 訂 線| 436948 .½¾-部中央標隼局員工消費合作社印製 五、發明説明（> ) 數量也因此必須倍增、因而導致該半導體封裝元件的「長 度」將必須配合引脚數量的增加而增長許多。近來傳統單 晶片封裝元件（例如4MB DRAM 1C)的引腳數量已由過去 的二十隻脚、三十隻腳漸漸增加至目前所流行的四十二隻 腳甚至五十隻腳的1C，由於每一隻引腳均有其固定的寬 度，因此使得目前1C元件的長度也不斷加長、加大，若採 用如圖一所示之習用技術來進行多晶片封裝1C，則其引_ 的數量將甚至會達到八十或甚至一百隻腳以上，其1C勢必 會過長而顯得不盡實用。 如圖二所示，另一種習用之多晶片半導體封裝結構的 例子，係採用「錫球陣列接點（Ball Grid Array ;簡稱 BGA)」的技術將兩片晶片7a、7b以銀膠（常稱爲EPOXY) 加以相互結合後再黏貼於一基板8上，並以金線9a、9b (Gold Wire)分別焊接（Bonding)耦合晶片7a、7b上之 電路與基板8之相對應的焊墊後，經由基板8上之電路設計 或穿透基板8的導電栓設計，將晶片7a、7b上之電路透過 金線9a、9b而連接耦合於基板8底面的相對應之錫球1〇 上，成形爲一體的半導體封裝元件（1C) »惟，此種單純 以BGA技術之基板8上的錫球10來作爲多個晶片7a、7b上之 電路與外界聯通介面的最大缺點，便是該基板8的面積將 增大許多使得該半導體封裝元件的面積很大，並且於製程 上也有諸多不便而難以實施。由於現今BGA的技術均是採 用一基板8來支撐、固定晶片，再於基板8背（底）面處設 置錫球成爲訊號傳輸之接點。所以，基板的面積一般已經 {請先閱讀背面之注意事項再填寫本頁) 訂 -線I --- 本紙張尺度適用中國國家橾準（CNS ) A4現格（210x297公菜） 4 3 6 9 4 8 A7 經肩部中央標本局員工消f合作社印製 五、發明説明（J ) 比實際晶片的尺寸大了不少，再加上多晶片的堆叠將更直 接導致錫球數量的增加以及基板面積的擴大，在實用性上 i 將因此降低許多。此種單純以BGA技術來堆疊多晶片的另 一缺失，便是製程上的困難，例如圖二中所示的結構，其 上晶片7a與基板8之間所連接的金線9a幾乎是金線9b的兩 倍長度，過長的金線9a將非常難以焊接且更極易因外力或 過熱（因電阻值較大）而斷線；並且，於此種結構中晶片 7a的尺寸一定要比晶片7b更小而無法使用兩個相同尺寸或 規格的晶片進行堆疊，造成設計上的困擾；此外，過長且 密集的金線9a、9b於進行封裝樹脂的灌膠製程時，也常常 會被封裝樹脂所衝斷鬆脫導致斷路，所以在實務上並不甚 可行（產品良率過低）。 所以，前述之各種習用技術，實際上並無法完全滿足 如前述之縮小半導體元件尺寸及降低成本的未來趨勢與需 求，而仍留有一空間可供改進。 (三)發明目的： 本發明之主要目的，即在於提供一種多晶片半導體封 裝結構及製法，不僅結構簡單、製程容易、成本較低，且 1C元件的整體面積、長度均可較習用技術更爲縮小。 本發明之另一目的在於提供一種多晶片半導體封裝結 構及製法，藉由融合LOC技術及BGA技術來進行兩晶片的堆 疊於同一 1C元件中，不僅克服了前述習用技術的種種缺 失，且該兩晶片更可分別具有不同的功能、或亦可爲具有 相同功能之晶片》 ____4_____ 本紙浪尺度適用中國國家標牟（CNS ) Λ4規格（2丨0X297公釐） (請先閱讀背面之注項再填寫本頁) 訂 線 經濟部中央標隼局負工消费合作社印裝 五、發明説明（4 ) 爲了達成上述之目的，本發明所述之多晶片半導體封 裝結構的一較佳實施例中，包括有至少兩個晶片（即一第 一晶片及一第二晶片）、一具有複數個引腳之導線架、複 數個錫球以及封裝樹脂。其各個晶片均具有一作動面及一 非作動面，且於各個晶片的作動面上均設有複數個連接墊 以成爲晶片上之電路與外界連結之介面。第二晶片之作動 面上的複數個連接墊係藉由一技術手段分別耦合於對應之 引腳上，且第一晶片之非作動面係結合於導線架上。該複 數個錫球係直接設置於該第一晶片之作動面上相對應的複 數個連接墊上。該封裝樹脂則是用於包覆前述之晶片而成 爲一體之半導體封裝結構，且該複數個引腳及錫球係露出 於封裝樹脂外以成爲與外界連結之介面。由於本發明之多 晶片半導體封裝結構並沒有習用BGA基板的設置（兩晶片 係受導線架所支撐固定），因此1C元件的面積可大爲縮 小，也由於兩晶片係分別利用引腳與錫球來當作接點，因 此其引腳數置也不會太多、1C元件的長度可較短，且本發 明之整體結構簡單製程容易，成本也較爲低廉者。 爲使貴審査委員對於本發明之目的、特徵及功效， 能有更進一步之認識與瞭解，茲配合圖式詳細說明如后： (四)圖式之簡要說明： 圖一爲習用技術之多晶片半導體封裝結構之一例圓。 圚二爲習用技術之多晶片半導體封裝結構之另一例 圖。 (#先聞讀背面之注意事項再填ΚΤ本頁) 訂 線 本纸張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 436948 a7 五、發明説明（f ) 圖三係爲本發明之多晶片半導體封裝結構之一較佳實 施例圖。 圓四Α〜四F係爲圖三所示實施例結構之製程步驟流程 的一較佳實施例。 圖五係爲本發明之多晶片半導體封裝結構之另一較佳 實施例圖。 圖六A〜六F係爲圖五所示實施例結構之製程步驟流程 的一較佳實施例。 圖號說明： la、7a第一晶片 3a、3b導線架 5樹脂 8基板 lb、7b第二晶片 4a、4b、9a、9b金線 6引腳 10錫球 經濟部中央標皁局負Η消费合作钍印製 20、 40多晶片半導體封裝結構（兩較佳實施例） 21、 41第一晶片 22、42第二晶片 211、 221、411、421 作動面 212、 222、412、422非作動面 213、 223、413、423連接墊 214、 414內球 23、43雙面膠帶 24、44導線架 24卜441引腳 25銀膠 26、46樹脂 424焊料 27、47錫球 (五)發明之詳細說明 訂 線I (讀先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐} 4369 48 .¾¾•部中决標率局員工消费合作社印取 五、發明説明（t ) 本發明係有關於一種多晶片半導體封裝結構及製法， 主要是藉由同時融合LOC技術（引腳上著於晶片：Lead On Chip ;簡稱L0C)及BGA技術（錫球陣列接點：Ball Grid Array ;簡稱BGA)來進行兩晶片的堆疊於同一 1C元件中， 使其中一晶片是利用引腳來成爲晶片上之電路與外界連結 之介面，而另一晶片則是藉由錫球來作爲晶片上之電路與 外界連結之介面，且更省略了習用BGA技術所需的基板元 件。所以，不僅該兩晶片可分別具有不同的功能、或亦可 爲具有相同功能之晶片，且其整體的結構簡單、製程容 易、成本較低，並旦1C元件的整體面積、長度均可較習用 技術更爲縮小。 請參閱圖三，爲本發明之多晶片半導體封裝結構之一 較佳實施例圖。而圚四A〜四F則爲圖三所示實施例之製程 步驟流程的一較佳實施例》 於園三所示之較佳實施例中，該多晶片半導體封裝 (1C)結構20，包括有：複數個晶片、一導線架24、複數 個錫球27及封裝樹脂26。該複數個晶片於本實施例中係包 含有一第一晶片21及一第二晶片22，各個晶片21、22均具 有一作動面211、221 (Active Side)及一非作動面212、 222 (Inactive Side)，該作動面211、221 即爲晶片21、 22之電路設計所在的一側表面，並且，於各個晶片21、22 的作動面上211、221的預定位置處均設有複數個連接墊 213、223以成爲晶片21、22上之電路與外界連結之介面， (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 436948 :""部中央標卑局員Η消费合作社印絮 五、發明説明（7 ) 於本較佳實施例中該連接墊213、223即爲業界所俗稱的金 屬墊或網墊（A1 Pad)。 該導線架24 (Lead Frame)具有複數個引腳241 (Lead)，該第二晶片22之作動面221上的複數個連接墊 223係藉由一技術手段分別耦合於相對應之引腳241上，且 第一晶片21之非作動面212係結合於導線架24上。於本較 佳實施例中，用於耦合第二晶片22之連接墊233與相對應 之引腳241的該技術手段係爲焊線224 (Gold Wire Bonding)，旦該第一晶片21之非作動面212係藉由熱熔性 雙面膠帶23 (Dua卜Sided Adhesive Tape)貼合於導線架 24未與第二晶片22焊線耦合的一側面上，而第二晶片22之 非作動面222則是藉由銀膠25 (ΕΡ0Π)貼合於第一晶片21 之非作動面212上》當然，任何熟習半導體之人士在參閱 前述說明後，當可輕易思及，而可晅擇使用雙面膠帶來結 合第二晶片22與第一晶片2L· 該複數個錫球27 (Solder Ball)係分別設置於該第 一晶片21之作動面211上相對應的複數個連接墊213上，於 錫球27與連接墊213之間並預先植入有內球2H以成爲錫球 27結合於連接墊213上之介質。然後，再以封裝樹脂26進 行封裝（Molding)包覆前述之晶片21、22而成爲一體之 半導體封裝1C結構20，旦該複數個引腳241及錫球27係露 出於封裝樹脂26外以成爲與外界連結之介面。 藉由如圖三所示之結構，由於該第二晶片22是利用導 線架24之引腳241來成爲晶片22上之電路與外界連結之介 ___— —— —---- 本纸張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐} (請先閲讀背面之注意事項再填寫本S ) 訂 -線丨.！ 436948Printed by UKJE. Consumer Cooperatives, Ministry of Economic Affairs, Substandard Bureau 4369 4 8 at B-7 _ V. Description of Invention (I) (I) Technical Field of the Invention: The present invention relates to a multi-chip semiconductor package structure and manufacturing method. Especially one that can stack more than two chips with the same or different functions in the same package, and one of the chips uses the lead of the lead frame as the interface to the outside and the other chip uses the tin ball as the interface to the outside Multi-chip semiconductor package structure and manufacturing method of connected interface. (II) Technical background of the invention: In the current semiconductor manufacturing trend, how to squeeze more logic circuits into smaller semiconductor packages and reduce the cost can be relatively unanimously researched by the global semiconductor industry. Research, competition in this field is also very fierce. "In addition to continuous research and development to reduce the minimum component size of the circuit design on the chip, another way to directly reach the memory capacity of a single semiconductor package at the lowest cost , Is to squeeze more than two chips in the same package. As shown in Fig. 1, an example of a conventional multi-chip semiconductor package structure is shown. It mainly uses the technology of "Lead On Chip (LOC)" to combine the two chips la, lb on the two lead frames 3a, 3b with hot-melt double-sided tapes 2a, 2b, respectively. , And gold wires 4a, 4b (Gold Hre) are respectively used to bond (bonding) the corresponding pins on the coupling chips la, lb and the lead frames 3a, 3b, and then the pins on the lead frame 3a are erected and connected. On the lead 6 of the lead frame 3b, the packaging resin 5 (Molding) is poured into the semiconductor packaging element (1C). However, the biggest shortcoming of simply using pin 6 of the lead frame as the interface between the circuits on multiple chips la and lb and the outside world is pin 6 -2- This paper size is applicable to China National Standards (CMS) A4 specifications (2! 0) < 297 mm) (Please read the notes on the back before filling in this page) Thread line | 436948. ½-Printed by the Ministry of Standards and Standards Bureau Staff Consumer Cooperatives V. Invention Description ( >) Therefore, the number must be doubled, so that the "length" of the semiconductor package component will have to increase with the increase in the number of pins. Recently, the number of pins of traditional single-chip package components (such as 4MB DRAM 1C) has gradually increased from the past 20 pins and 30 pins to the currently popular 42-pin and even 50-pin 1C. Each pin has its fixed width, so that the current length of 1C components is constantly increasing and increasing. If the conventional technology shown in Figure 1 is used to package 1C in a multi-chip, the number of leads will be It will even reach eighty or even a hundred feet or more, and its 1C is bound to be too long and not practical. As shown in Figure 2, another example of a conventional multi-chip semiconductor package structure is the use of "Ball Grid Array (BGA)" technology to place two wafers 7a, 7b with silver glue (often called (EPOXY) are bonded to each other, and then adhered to a substrate 8, and the bonding pads of the circuits on the coupling wafers 7a, 7b and the substrate 8 are bonded with gold wires 9a, 9b (Gold Wire), respectively. Through the circuit design on the substrate 8 or the conductive plug design penetrating the substrate 8, the circuits on the wafers 7a, 7b are connected to the corresponding solder balls 10 coupled to the bottom surface of the substrate 8 through the gold wires 9a, 9b, and formed into Integrated semiconductor package components (1C) »However, the biggest disadvantage of this type of purely using the solder ball 10 on the substrate 8 of the BGA technology as the interface between the circuits on multiple wafers 7a and 7b and the outside world is the substrate 8. The area will increase a lot so that the area of the semiconductor package component is very large, and there are many inconveniences in the manufacturing process and it is difficult to implement. Since the current BGA technology uses a substrate 8 to support and fix the wafer, a solder ball is placed on the back (bottom) surface of the substrate 8 as a contact point for signal transmission. Therefore, the area of the substrate is generally {Please read the precautions on the back before filling in this page) Order-line I --- This paper size is applicable to China National Standards (CNS) A4 grid (210x297 common dishes) 4 3 6 9 4 8 A7 Printed by the staff of the Central Specimen Bureau of the Shoulder F. Cooperative cooperatives. 5. The invention description (J) is much larger than the actual wafer size. Coupled with the stacking of multiple wafers, it will directly lead to an increase in the number of solder balls and the substrate. As the area is enlarged, i will be greatly reduced in practicality. Another drawback of this method of simply stacking multiple wafers with BGA technology is the difficulty in the process. For example, the structure shown in FIG. 2 is such that the gold wires 9a connected between the wafer 7a and the substrate 8 are almost gold wires. The double length of 9b, the excessively long gold wire 9a will be very difficult to weld and more likely to be disconnected due to external forces or overheating (due to the large resistance value); and in this structure, the size of the chip 7a must be larger than that of the chip 7b is smaller and cannot be stacked using two wafers of the same size or specification, causing design problems; In addition, the long and dense gold wires 9a, 9b are often packaged during the encapsulation process of the packaging resin. The resin is broken due to loosening, so it is not practical in practice (the product yield is too low). Therefore, the aforementioned various conventional technologies cannot actually meet the future trends and requirements of reducing the size and cost of semiconductor elements as described above, while still leaving room for improvement. (3) Purpose of the invention: The main purpose of the present invention is to provide a multi-chip semiconductor package structure and manufacturing method. The structure is not only simple, the process is easy, and the cost is low, and the overall area and length of the 1C component can be more than conventional technology Zoom out. Another object of the present invention is to provide a multi-chip semiconductor package structure and manufacturing method. By combining LOC technology and BGA technology, two chips are stacked in the same 1C device, which not only overcomes the aforementioned shortcomings of conventional technologies, but also the two The chip can have different functions, or it can be a chip with the same function. ____4_____ This paper wave standard is applicable to China National Standards (CNS) Λ4 specifications (2 丨 0X297 mm) (Please read the notes on the back before filling out (This page) Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Subcontractor, Consumer Cooperatives, and V. Description of Invention (4) In order to achieve the above-mentioned object, a preferred embodiment of the multi-chip semiconductor package structure described in the present invention includes At least two chips (ie, a first chip and a second chip), a lead frame having a plurality of pins, a plurality of solder balls, and a packaging resin. Each of the chips has an active surface and a non-active surface, and a plurality of connection pads are provided on the active surface of each chip to become an interface between the circuit on the chip and the outside. The plurality of connection pads on the moving surface of the second chip are respectively coupled to the corresponding pins by a technical means, and the non-moving surface of the first chip is coupled to the lead frame. The plurality of solder balls are directly disposed on a plurality of connection pads corresponding to the operating surface of the first wafer. The encapsulating resin is used to cover the aforementioned wafers to form an integrated semiconductor encapsulation structure, and the plurality of pins and solder balls are exposed outside the encapsulating resin to become an interface for connection with the outside world. Because the multi-chip semiconductor package structure of the present invention does not have a conventional BGA substrate arrangement (two chips are supported and fixed by the lead frame), the area of the 1C component can be greatly reduced, and because the two chip systems use pins and solder balls, respectively As a contact, the number of pins is not too much, the length of the 1C component can be shorter, and the overall structure of the present invention is simple, the process is easy, and the cost is relatively low. In order for your reviewing committee to have a better understanding and understanding of the purpose, features and effects of the present invention, the detailed description with the drawings is as follows: (4) Brief description of the drawings: Figure 1 is a multi-chip of conventional technology An example of a semiconductor package structure is round. Figure 22 shows another example of a multi-chip semiconductor package structure using conventional technology. (# 先 读读 Cautions on the back, then fill in the KT page.) The size of the paper for the booklet is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 436948 a7 V. Description of the invention (f) Figure 3 is the invention A preferred embodiment of a multi-chip semiconductor package structure. Circles A through F are a preferred embodiment of the process flow of the structure of the embodiment shown in FIG. FIG. 5 is a diagram of another preferred embodiment of the multi-chip semiconductor package structure of the present invention. 6A to 6F are a preferred embodiment of the process flow of the structure of the embodiment shown in FIG. Description of drawing number: la, 7a first wafer 3a, 3b lead frame 5 resin 8 substrate lb, 7b second wafer 4a, 4b, 9a, 9b gold wire 6 pin 10 solder ball Central Ministry of Economic Affairs Ministry of Standards and Technology negative consumer cooperation钍 Printed 20 and 40-chip semiconductor package structures (two preferred embodiments) 21, 41 First chip 22, 42 Second chip 211, 221, 411, 421 Active surface 212, 222, 412, 422 Non-active surface 213 , 223, 413, 423 connection pads 214, 414 inner ball 23, 43 double-sided tape 24, 44 lead frame 24 441 lead 25 silver glue 26, 46 resin 424 solder 27, 47 solder ball (5) Detailed description of the invention Binding line I (read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) Α4 size (210X297 mm) 4369 48 .¾¾ • Printed by the Ministry of China ’s Bid Rate Cooperative Bureau V. Description of the invention (t) The present invention relates to a multi-chip semiconductor package structure and manufacturing method, mainly by integrating LOC technology (lead on chip: Lead On Chip; L0C for short) and BGA technology (tin ball) Array contact: Ball Grid Array (BGA for short) to stack two wafers on In the same 1C component, one of the chips uses pins to become the interface between the circuit on the chip and the outside world, and the other chip uses the solder ball as the interface between the circuit on the chip and the outside world, and is more omitted. The substrate components required for the conventional BGA technology are used. Therefore, not only the two wafers can have different functions, but also the wafers with the same function, and the overall structure is simple, the process is easy, and the cost is low. The overall area and length of the device can be reduced compared with conventional techniques. Please refer to FIG. 3, which is a diagram of a preferred embodiment of a multi-chip semiconductor package structure according to the present invention. A preferred embodiment of the process steps of the embodiment "In the preferred embodiment shown in the third embodiment, the multi-chip semiconductor package (1C) structure 20 includes: a plurality of wafers, a lead frame 24, a plurality of The solder ball 27 and the sealing resin 26. The plurality of wafers in this embodiment include a first wafer 21 and a second wafer 22, and each wafer 21, 22 has an active side 211, 221 (Active Side), and Inactive sides 212, 222 (Inactive Side), the active surfaces 211, 221 are the side surfaces where the circuit design of the wafers 21, 22 is located, and at predetermined positions on the active surfaces 211, 221 of each wafer 21, 22 A plurality of connection pads 213 and 223 are provided everywhere to become the interface between the circuits on the chips 21 and 22 and the outside world. (Please read the precautions on the back before filling this page.) The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 436948: " " Member of the Ministry of Standards and Standards Bureau ΗPrinted by Consumer Cooperatives V. Description of the invention (7) In the preferred embodiment, the connection pads 213 and 223 are commonly known as metals in the industry Pad or mesh pad (A1 Pad). The lead frame 24 (Lead Frame) has a plurality of pins 241 (Lead), and a plurality of connection pads 223 on the operating surface 221 of the second chip 22 are respectively coupled to the corresponding pins 241 by a technical means. The non-active surface 212 of the first chip 21 is bonded to the lead frame 24. In this preferred embodiment, the technical means for coupling the connection pad 233 of the second chip 22 and the corresponding pin 241 is Gold Wire Bonding. Once the first chip 21 is inactive, The surface 212 is adhered to the side surface of the lead frame 24 which is not coupled to the bonding wire of the second chip 22 by a hot-melt double-sided tape 23 (Duaded Adhesive Tape), and the non-active surface 222 of the second chip 22 is It is attached to the non-active surface 212 of the first chip 21 by silver glue 25 (EP0Π). Of course, anyone who is familiar with semiconductors can easily think about it after referring to the foregoing description, and can choose to use double-sided tape. To combine the second wafer 22 and the first wafer 2L. The plurality of solder balls 27 (Solder Balls) are respectively disposed on a plurality of connection pads 213 corresponding to the operating surface 211 of the first wafer 21, and are mounted on the solder balls 27. An inner ball 2H is pre-implanted between the connection pad 213 and the connection pad 213 to serve as a medium for the solder ball 27 to be bonded to the connection pad 213. Then, the sealing resin 26 is used for encapsulation (Molding) to cover the aforementioned wafers 21 and 22 to form an integrated semiconductor package 1C structure 20. Once the plurality of pins 241 and the solder balls 27 are exposed outside the encapsulation resin 26 to become Interface to the outside world. With the structure shown in FIG. 3, since the second chip 22 uses the lead 241 of the lead frame 24 to become the interface between the circuit on the chip 22 and the outside ___———————— This paper The scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) (Please read the precautions on the back before filling this S)
五、發明説明（ϊ ) ¾濟部中央榡隼局貝工消资合作社印¾. 面，而該第一晶片21則是藉由錫球27來作爲晶片21上之電 路與外界連結之介面，並且，由於第一與第二晶片21、22 均係定位於導線架24上而更可省略了習用BGA技術所需的 基板元件。所以，本發明之多晶片半導體封裝結構2〇可如 圖三所示般，不僅整體的體積較小、引腳數量適中使1C長 度不會過長、少了習用基板元件的設置使得1C的面積大爲 縮小、且更因結構與元件數董的簡化而使製造成本更爲低 廉。此外，由於該兩晶片21、22係分別藉由錫球27與引脚 241作爲兩晶片上之電路與外界連結之介面，所以，當第 一晶片21上之電路並未直接與第二晶片22上之電路耦合且 引腳241也未直接與錫球2?耦合時，該第一晶片21與第二 晶片22可爲具有不同功能之晶片，例如，第一晶片21可爲 一邏輯電路之晶片而第二晶片22係爲一記憶體電路之晶 片，因而可在同一 1C中同時包括有數種不同功能之晶片， 使1C之設計及使用彈性大爲增加。當然，任何熟習半導體 之人士在參閱前述說明後，當可輕易思及，而令該第一晶 片21與第二晶片22係爲具有相同功能之晶片，或是設計使 得第一晶片21與第二晶片22上的電路可直接或間接地相互 耦合者。 於以下所述之實施例中，相同於前述之元件將以相同 的編號及名稱命名，且不再重覆贅述其結構功能。 請參閱圖四A〜四F爲圖三所示實施例之多晶片半導體 封裝結構20之製法的一較佳製程步驟流程實施例，其包括 有下列步驟： ----------f------ΪΤ------予 (請先W讀背面之注意事項再填寫本頁) 本紙浪尺度適用中®园家標準（CMS ) A4規格（210X 297公釐） 經濟部中央榡准局負工消f合作社印聚 4369 48 五、發明説明（，） (a) 於一第一晶片21之非作動面212上藉由雙面膠帶 23結合一具有複數個引腳241之導線架24 « (b) 將一第二晶片22之非作動面222藉由銀膠25結合 於第一晶片21之非作動面212上》 (c) 進行焊線以將第二晶片22之作動面221上的連接 墊223藉由焊線224連接耦合於導線架24之引腳241上’使 第二晶片22上之電路可經由引腳241而與外界聯通。 (d) 於第一晶片21之作動面211上之適當位置的連接 墊213植入複數個內球214，並同時進行封裝樹脂26的灌注 封裝以包覆該第一、第二晶片21、22形成一體的半導體1C 元件，且該引腳241及內球214均至少有一部份係露出於封 裝樹脂26外。 (e) 植入複數個錫球27於該複數個內球214的位置 上，使第一晶片21上之電路可經由錫球27而與外界聯通。 ' (f)進行引腳241的彎腳成型加工使引脚241朝向具 齒球27之方向延伸一預定之角度、長度及形狀，必要時可 再進行多齒1C之間的切割分離製程，完成本發明之多晶片 半導體封裝結構2G的製造。 請參閱圚五，爲本發明之多晶片半導體封裝結構釗之 另一較佳實施例圖》而圖六A〜六F則爲圖五所示實施例之 製程步驟流程的一較佳實施例。 於圖五所示之較佳實施例中，該多晶片半導體封裝 (1C)結構40也同樣包括有：兩個晶片（第一晶片41及第 二晶片42)、一具有複數個引腳441的導線架44、複數個 ----- (請先閱讀背面之注意ί項再填寫本買) 訂 -線-! 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 經漭部中央標龙局貝工消费合作社印製 ! ' 4369 48 五、發明説明（（〇 ) 錫球47、及用來包覆晶片41、42成爲一體之1C結構的封裝 樹脂46 »該兩晶片41、42也同樣均具有一作動面41卜421 及一非作動面412、422，並且’於各個晶片41、42的作動 面上411、421也均設有複數個連接塾413、423。 該第一晶片41於圖五所示之較佳實施例中也是藉由雙 面膠帶43貼合於導線架44之一側面上’然而’任何熟習半 導體之人士在參閱前述說明後，當可輕易思及’而選擇令 該第一晶片41藉由銀膠貼合至導線架44上者。於導線架44 相對於第一晶片41的另一側面上結合有該第二晶片42，且 第二晶片42之作動面421上的連接墊423係藉由焊料424 (例如錫球）直接焊接於相對應之引腳441上’不僅因此 將第二晶片42結合固定於導線架44上，旦同時達到將第二 晶片42上之電路藉由引腳441與外界聯通的目的。至於第 一晶片41上之連接墊413則如同圖三之實施例一樣’是先 :後分別結合有內球414及錫球47，以使得第一晶片41上之 電路可藉由錫球47與外界聯通。 請參閱圖六A〜六F爲圖五所示實施例之多晶片半導體 封裝結構40之製法的一較佳製程步驟流程實施例，其包括 有下列步驟： (a) 於一第二晶片42之作動面421上的複數個連接塾 423處分別植入可導電性焊料424。 (b) 將第二晶片42之複數個焊料424以熱熔接（焊 接）的方式分別結合於一導線架44之複數個相對應的引腳 441上，使引腳441成爲第二晶片42上之電路與外界連結之 <請免閱讀背面之注意事項再填寫本頁) 丁 -'-β 線 本纸張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） 經濟部中央標年局貝工消f合作社印製 I ' 4 3 6 9 4 8 c _ 五、發明説明（丨I ) 介面，於導線架44相對於第二晶片42的另一側面上之適當 位置處並設有雙面膠帶43 ° (c) 將一第一晶片41之非作動面412結合於該導線架 44之雙面膠帶43上’使第一晶片41固定於導線架44上。 (d) 於第一晶片41之作動面411上之複數個連接墊 413處分別植入內球414，並進行封裝樹脂46的灌注封裝以 包覆該第一、第二晶片41、42 ’且該引腳441及內球414均 至少有一部份係露出於封裝樹脂46外。 (e) 植入複數個錫球47於該複數個內球414的位置 上，使錫球47成爲第一晶片41上之電路與外界連結之介 面。 (f) 進行引腳441的彎腳成型加工使引腳441朝向具 錫球47之方向延伸一預定之角度、長度及形狀，完成本發 明之多晶片半導體封裝結構40的製造。 ^ 綜上所述，本發明之一種多晶片半導體封裝結構及製 法，可有效改善習用以單純LOC或單純BGA技術來製造之習 用多晶片半導體1C封裝結構所具有之半導體元件的長度太 長、面積太大、整體結構複雜、製程困難、成本較高、實 用性較差等等之種種缺失。且本發明之多晶片半導體封裝 結構可選擇適用在同一 1C中同時包括有數種不同功能之晶 片（或也可是相同的晶片），使1C之設計及使用彈性大爲 增加，其整體結構非常簡單、體積面積與長度均較小、製 程容易、成本亦非常低廉，充份顯示出本發明之目的及功 效上均深富實施之進步性，極具產業之利用價值，且爲目 本紙張尺度適用中國囤家標準（CNS ) Λ4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本to:)V. Description of the invention (ϊ) ¾ Printed by the Central Government Bureau of the Ministry of Economic Affairs, Bei Gong Consumer Cooperative, and the first chip 21 uses the solder ball 27 as the interface between the circuit on the chip 21 and the outside world. In addition, since the first and second wafers 21 and 22 are both positioned on the lead frame 24, the substrate components required for the conventional BGA technology can be omitted. Therefore, the multi-chip semiconductor package structure 20 of the present invention can be as shown in Fig. 3. Not only the overall volume is small, the number of pins is moderate so that the length of the 1C will not be too long, and the setting of the conventional substrate components will reduce the area of the 1C. It is greatly reduced, and the manufacturing cost is lower due to the simplified structure and component count. In addition, since the two chips 21 and 22 are respectively used as the interface between the circuits on the two chips and the outside through the solder balls 27 and the pins 241, when the circuits on the first chip 21 are not directly connected to the second chip 22 When the above circuit is coupled and the pin 241 is not directly coupled to the solder ball 2 ?, the first chip 21 and the second chip 22 may be chips with different functions. For example, the first chip 21 may be a chip of a logic circuit The second chip 22 is a chip of a memory circuit, so it can simultaneously include several chips with different functions in the same 1C, which greatly increases the design and use flexibility of the 1C. Of course, anyone who is familiar with semiconductors can easily think about it after referring to the foregoing description, so that the first wafer 21 and the second wafer 22 are wafers with the same function, or the design is such that the first wafer 21 and the second wafer The circuits on the chip 22 may be directly or indirectly coupled to each other. In the embodiments described below, the same components as those described above will be named with the same numbers and names, and their structural functions will not be described repeatedly. Please refer to FIGS. 4A to 4F, which are one preferred process steps of the method for manufacturing the multi-chip semiconductor package structure 20 in the embodiment shown in FIG. 3, which includes the following steps: ---------- f ------ ΪΤ ------ Y (Please read the precautions on the reverse side before filling out this page) This paper is suitable for the standard of the gardener's standard (CMS) A4 (210X 297 mm) Economic The Ministry of Central and Taiwan Standards Bureau, Consumer Cooperatives, Cooperative Print 4369 48 5. Description of the invention (,) (a) A non-active surface 212 of a first chip 21 is combined with a double-sided tape 23 to have a plurality of pins 241 Lead frame 24 «(b) bonding the non-active surface 222 of a second wafer 22 to the non-active surface 212 of the first wafer 21 by silver glue 25" (c) bonding wires to bond the second wafer 22 The connection pad 223 on the operating surface 221 is connected to the pin 241 of the lead frame 24 through the bonding wire 224 so that the circuit on the second chip 22 can communicate with the outside via the pin 241. (d) A plurality of inner balls 214 are implanted in the connection pads 213 at appropriate positions on the operating surface 211 of the first chip 21, and the potting resin 26 is infused and encapsulated to cover the first and second chips 21, 22 An integrated semiconductor 1C device is formed, and at least a part of the pin 241 and the inner ball 214 is exposed outside the packaging resin 26. (e) The plurality of solder balls 27 are implanted at the positions of the plurality of inner balls 214, so that the circuit on the first wafer 21 can communicate with the outside world through the solder balls 27. '(f) Perform bending molding of the lead 241 so that the lead 241 extends a predetermined angle, length, and shape in the direction of the toothed ball 27. If necessary, a cutting and separating process between the multi-tooth 1C can be performed to complete Manufacturing of the multi-chip semiconductor package structure 2G of the present invention. Please refer to Figure 5 for another preferred embodiment of the multi-chip semiconductor package structure of the present invention "and Figures 6A to 6F are a preferred embodiment of the process flow of the embodiment shown in Figure 5. In the preferred embodiment shown in FIG. 5, the multi-chip semiconductor package (1C) structure 40 also includes two chips (a first chip 41 and a second chip 42), and a chip having a plurality of pins 441. Lead frame 44, multiple ----- (please read the note on the back first and then fill in this purchase) order-line-! This paper size applies to China National Standard (CNS) A4 specification (210 × 297 mm) Printed by the Central Biaolong Bureau Shellfisher Consumer Cooperative! '4369 48 V. Description of the invention ((〇) solder ball 47 and 1C structure packaging resin 46 used to cover the wafers 41 and 42 as a whole »The two wafers 41 Similarly, 42 and 42 also have an actuating surface 41, 421 and a non-acting surface 412, 422, and a plurality of connections 塾, 413, 423 are also provided on the actuating surfaces 411, 421 of each wafer 41, 42. A wafer 41 in the preferred embodiment shown in FIG. 5 is also attached to one side of the lead frame 44 by double-sided tape 43. However, anyone who is familiar with semiconductors can easily think about it after referring to the foregoing description. 'And choose to make the first chip 41 adhere to the lead frame 44 by silver glue. The second wafer 42 is bonded to the other side of the frame 44 opposite to the first wafer 41, and the connection pad 423 on the operating surface 421 of the second wafer 42 is directly soldered to the corresponding one by solder 424 (such as a solder ball). "On the pin 441," the second chip 42 is not only fixed on the lead frame 44, but also the purpose of connecting the circuit on the second chip 42 to the outside through the pin 441. As for the first chip 41, The connection pad 413 is the same as the embodiment of FIG. 3 'in which: the inner ball 414 and the solder ball 47 are respectively combined later, so that the circuit on the first chip 41 can communicate with the outside through the solder ball 47. Please refer to FIG. 6 A to 6F are a preferred process step embodiment of the method for manufacturing the multi-chip semiconductor package structure 40 in the embodiment shown in FIG. 5, which includes the following steps: (a) On the operating surface 421 of a second chip 42 Conductive solders 424 are respectively implanted at a plurality of connection points 423. (b) The plurality of solders 424 of the second chip 42 are respectively thermally welded (soldered) to a plurality of corresponding ones of a lead frame 44. Pin 441, so that pin 441 becomes the second chip 42 The circuit is connected to the outside world <Please read the precautions on the reverse side and fill out this page) D -'- β The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) The central standard of the Ministry of Economic Affairs Printed by the council of the year, the co-operative society I '4 3 6 9 4 8 c _ V. Description of the invention (丨 I) The interface is arranged at an appropriate position on the other side of the lead frame 44 relative to the second chip 42 With double-sided tape 43 ° (c) The non-active surface 412 of a first wafer 41 is bonded to the double-sided tape 43 of the lead frame 44 to fix the first wafer 41 to the lead frame 44. (d) Inner balls 414 are respectively implanted at a plurality of connection pads 413 on the operating surface 411 of the first chip 41, and the potting resin 46 is encapsulated to cover the first and second chips 41, 42 'and At least a part of the pin 441 and the inner ball 414 are exposed outside the packaging resin 46. (e) The plurality of solder balls 47 are implanted at the positions of the plurality of inner balls 414, so that the solder balls 47 become the interface between the circuit on the first chip 41 and the outside. (f) Perform bent-bent molding of the lead 441 so that the lead 441 extends a predetermined angle, length, and shape in the direction of the solder ball 47 to complete the manufacturing of the multi-chip semiconductor package structure 40 of the present invention. ^ In summary, a multi-chip semiconductor package structure and manufacturing method of the present invention can effectively improve the conventional multi-chip semiconductor 1C package structure that is conventionally manufactured using simple LOC or simple BGA technology. It is too big, the overall structure is complicated, the manufacturing process is difficult, the cost is high, the practicability is poor, and so on. In addition, the multi-chip semiconductor package structure of the present invention can be selected and applied to the same 1C and includes several different functions of the chip (or the same chip), which greatly increases the design and use flexibility of the 1C, and its overall structure is very simple, The volume area and length are small, the process is easy, and the cost is very low. It fully shows the progress and implementation of the present invention in terms of purpose and efficacy. It has great industrial value and is suitable for China as a standard paper size. Store Standard (CNS) Λ4 specification (210X297 mm) (Please read the precautions on the back before filling in this to :)
,1T l·' 436948 A7 :¾¾-部中央標本局員工消资合作社印製 五、發明説明（|> ) 前市面上前所未見之新發明，完全符合發明專利之要件， 爰依法提出申請β 唯以上所述者，僅爲本發明之較佳實施例而已，當不 能以之限定本發明所實施之範圍。即大凡依本發明申請專 利範圍所作之均等變化與修飾，皆應仍屬於本發明專利涵 蓋之範圍內，謹請貴審查委員明鑑，並祈惠准，是所至 禱。 (請先聞讀背面之注意事項再填寫本頁) .¾衣. --=1° 線 -y- 本紙張尺度適用中國國家標準（CNS ) A4現格（210 X 297公釐）, 1T l · '436948 A7: ¾¾- Printed by the Consumers' Cooperative of the Central Bureau of Specimen Bureau V. Invention Description (| >) A new invention not seen on the market before, which fully meets the requirements of an invention patent, and was proposed according to law The application β is only the above, which is only a preferred embodiment of the present invention, and it should not be used to limit the scope of the present invention. That is to say, all equal changes and modifications made in accordance with the scope of the patent application of the present invention should still fall within the scope of the patent of the present invention. I would like to ask your reviewing committee to make a clear reference and ask for your approval. (Please read the precautions on the back before filling this page). ¾ Clothing.-= 1 ° Line -y- This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm)