TW461058B - Stacked multi-chip package structure with integrated passive components - Google Patents

Stacked multi-chip package structure with integrated passive components Download PDF

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Publication number
TW461058B
TW461058B TW089121891A TW89121891A TW461058B TW 461058 B TW461058 B TW 461058B TW 089121891 A TW089121891 A TW 089121891A TW 89121891 A TW89121891 A TW 89121891A TW 461058 B TW461058 B TW 461058B
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TW
Taiwan
Prior art keywords
semiconductor wafer
chip
substrate
package structure
stacked multi
Prior art date
Application number
TW089121891A
Other languages
Chinese (zh)
Inventor
Shiau-Yu Luo
Tzung-Da He
Ji-Chiuan Wu
Original Assignee
Siliconware Precision Industries Co Ltd
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Priority to TW089121891A priority Critical patent/TW461058B/en
Application granted granted Critical
Publication of TW461058B publication Critical patent/TW461058B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

A stacked multi-chip package structure with integrated passive components is disclosed. The structure can be used for packaging at least two semiconductor chips and the related passive components can be integrated into the package structure without increasing lay-out area of the substrate to decrease the whole package size. The stacked multi-chip package structure is characterized in that the passive components are disposed in the space of the bottom chip in the multi-chip structure which is not occupied by the upper chip, instead of being integrated into the substrate. Therefore, the whole package size of the invention can get smaller than the prior art. In addition, the integrated passive components can electrically connect to the substrate by using wire-bonding technology, or can directly electrically bond to the semiconductor chips by using surface coupling technology.

Description

461058 A7 产______ B7 五、發明說明（1 ) [發明領域] (請先閱讀背面之注意事項再填寫本頁) 本發明係有關於一種半導體晶片封裝技術，特別是有 關於一種具有整合型被動元件（passive component)之堆養 式多晶片封裝結構’其可用以封裝二個或二個以上的半導 艘晶片’並同時將相關之被動元件整合於封裝結構中但 不會增加基板的佈局面積’以減小整體之封裝尺寸。 [發明背景] 多晶片封裝技術可用以同時將二個或二個以上之半導 體晶片一併封裝於同一個封裝單元之中，使得單—個多晶 片封裝單元即可提供較一般之單晶片封裝單元更大之操作 功能及記憶容量β半導體記憶體裝置，例如為快閃記德體 裝置’一般即採用多晶片封裝技術來將二個或二個以上之 記憶體晶片封裝於同一個封裝單元之令’藉以使得單一個 封裝單元即可提供數倍之記憶容量β 經濟部智慧財產局員工消费合作社印製 於某些半導艘應用中’例如為高頻半導體裝置中，常 有需要將被動元件’例如為電阻器、電感器、及電容器， 電性連接至所封裝之半導體晶片，藉以使得所封裝之半導 體晶片可具有特定之電流特性β 一般之習知技術係將此些 被動元件安置於基板上未被半導體晶片所佔據的多餘佈局 面積上》然而由於此種整合方式需要較大尺寸的基板來實 施’因此會使得整體之封裝尺寸較大。 相關之專利技術例如包括美國專利第5,633,785號 INTEGRATED CIRCUIT COMPONENT PACKAGE WITH INTEGRAL PASSIVE COMPONENT"。此專利技術採用一 本紙張尺度適用t國國家標準（CNS)A4規格（210x297公爱> 1 16069 ΛΓ Β7 經濟邾智慧財產局Mi工消費合作社印製 五、發明說明（2 ) 種特製之基板來安置半導體晶片；亦即此種基板係預先形 成有被動元件之電路結構’使得其上所安置之半導體晶片 邛可直接電性連接至此些被動元件。然而此種被動元件整 «方式卻有以下缺點，第一項缺點為其需要較大尺寸的基 板來整合此些被動元件，因此會使得整體之封裝尺寸顯著 地較大。第二項缺點為其將被動元件形成於基板中的整合 方式，將使得基板的整體結構及所需製程變得較為複雜， 因此會使得整體之纣裝製程具有較大的複雜度而不符合成 本效益。 [發明概述J a鑒於以上所述習知技術之缺點，本發明之主要目的便 是在於提供一種新穎之堆疊式多晶片封裝結構其可用以 ^時封裝半導體晶片和被動元件，但不必增加基板的佈局 面積’以減小整體之封裝尺寸9 本發明之另一目的在於提供一種新穎之堆疊式多晶片 封裝結構，其中所整合之被動元件可直接採用一般之零件 式破動元件，以使得整體之封裝製程更具有成本效益， 、根據以上所述之目的，本發明即提供了 一種具有整合 型被動元件之堆疊式多晶片封裝結構^ 廣義而言，本發明之堆#式多晶片封裝結構包含⑷ —一基板：（b)-第―丰導體晶片，其係安置於該基板上 第-丰導體晶片’其係安置於該第—半導體晶片上：該 第 4導體晶片之K -寸 及i d I至 -X.. (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線-------- 該第 .丰導體晶片之尺寸 被動t件其#安置取辕第.本導體晶M上 t461058 A7 Product ______ B7 V. Description of the Invention (1) [Field of Invention] (Please read the notes on the back before filling out this page) The present invention relates to a semiconductor chip packaging technology, especially to an integrated passive Passive component stack-type multi-chip packaging structure 'which can be used to package two or more semi-conductor wafers' and simultaneously integrate related passive components in the packaging structure without increasing the layout area of the substrate 'To reduce the overall package size. [Background of the Invention] Multi-chip packaging technology can be used to package two or more semiconductor wafers in the same packaging unit at the same time, so that a single multi-chip packaging unit can provide a more general single-chip packaging unit. Larger operating functions and memory capacity β semiconductor memory devices, such as flash memory devices 'Generally, multi-chip packaging technology is used to package two or more memory chips in the same packaging unit' In this way, a single package unit can provide several times the memory capacity. It is printed in some semi-conductor applications by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. For example, in high-frequency semiconductor devices, passive components are often required. For resistors, inductors, and capacitors, they are electrically connected to the packaged semiconductor chip, so that the packaged semiconductor chip can have specific current characteristics. Β Generally, the passive components are placed on the substrate. Occupied by the semiconductor chip's excess layout area. However, this integration method requires a larger size Substrate to implement 'thus making the overall size of the larger package. Related patented technologies include, for example, US Patent No. 5,633,785 INTEGRATED CIRCUIT COMPONENT PACKAGE WITH INTEGRAL PASSIVE COMPONENT ". This patented technology uses a paper size applicable to the national standard (CNS) A4 specification (210x297 Public Love > 1 16069 ΛΓ Β7 Printed by the Mi 邾 Consumer Cooperative of the Bureau of Economics, Intellectual Property and Property, etc.) 5. Description of the invention (2) Special substrates To place semiconductor wafers; that is, such substrates are pre-formed with a circuit structure of passive components' so that the semiconductor wafers placed thereon can be directly and electrically connected to these passive components. However, such passive components have the following methods: Disadvantage. The first disadvantage is that it requires a larger substrate to integrate these passive components, which will make the overall package size significantly larger. The second disadvantage is the integration of passive components in the substrate. It will make the overall structure of the substrate and the required process more complicated, so it will make the overall assembly process more complicated and not cost-effective. [Summary of the Invention In view of the disadvantages of the conventional technology described above, The main object of the present invention is to provide a novel stacked multi-chip package structure which can be used to package semiconductor wafers and Moving components, but it is not necessary to increase the layout area of the substrate 'to reduce the overall package size. 9 Another object of the present invention is to provide a novel stacked multi-chip packaging structure, in which the integrated passive components can directly adopt the general component type Breaking the components to make the overall packaging process more cost-effective. According to the above-mentioned purpose, the present invention provides a stacked multi-chip packaging structure with integrated passive components. ^ Broadly speaking, the stack of the present invention The # -type multi-chip package structure includes:-a substrate: (b)-the first-abundant conductor wafer, which is placed on the substrate-the first-abundant conductor wafer; which is placed on the first-semiconductor wafer: the fourth conductor Chip K-inch and id I to -X .. (Please read the precautions on the back before filling this page) ---- The size of the passive conductor chip is passive.

1606V 461058 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（3 ) 被該第二半導體晶片所佔據之空間上。 於上述之堆疊式多晶片封裝結構中，第一半導體晶片 及第二半導體晶片可藉由銲線技術或覆晶技術而電性連接 至基板；而被動元件則可藉由辉線技術（wire-bonding technology，WBT)而電性連接至基板、或是藉由表面藕接 技術（surface-mount technology, SMT)而直接電性銲結至第 一半導體晶片。 於上述之堆疊式多晶片封裝結構申，由於被動元件係 安置於第一半導體晶片上未被第二半導體晶片所佔據之多 餘空間上’而非安置於基板上，因此可使得整體之封裝尺 寸較習知技術更小。 [圖式簡述] 本發明之實質技術内容及其實施例已用圖解方式詳細 揭露繪製於本說明書所附之圖式之中。此些圖式之内容簡 述如下： 第1Α圖顯示本發明之堆壘式多晶片封裝結構之第一 實施例的立體示意圖； 第1Β圖顯示第1Α圖所示之堆疊式多晶片封裝結構的 剖面示意圖； 第2圖顧示本發明之堆疊式多晶片封裝結搆之第二實 施例的剖面示意圖： 第3圖顯示本發明之堆疊式多晶片封裝結搆之第三實 施例的剖面示意圖： 第4圖顯示本發明之堆疊式多晶片封裝結構之第四實 {請先閱讀背面之注意事項再填寫本頁) 裝 --—訂---1!-^ 本紙張尺度適用中國國家樓準（CNS〉A4規格（210 X 297公爱) 3 16069 Λ7 B7 五、發明說明（4 ) 施例的剖面示意圖； 經濟部智慧財產局員工消費合作社印絜 [圖式標號] 100 基板 100a 基板100之正面 100b 基板100之背面 110 第一半導體晶片 110a 第一半導體晶片 110 之電路面 110b 第一半導體晶片 no 之非電路面 120 第二半導體晶片 120a 第二半導體晶片 120 之電路面 120b 第二半導體晶片 120 之非電路面 130 被動元件 140 球栅陣列 151 第一黏膠層 152 第二黏膠層 153 第三黏膠層 161 第一銲線組 162 第二銲線組 163 第三銲線組 200 基板 200a 基板200之正面 200b 基板200之背面 210 第一丰導體晶片 :? 10a 第本導體晶Μ 2 .Η) 岑電路面 -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 461058 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（5 ) 210b 第一半導體晶片 2 10之非電路面 220 第二半導體晶片 220a 第二半導體晶片 220之電路面 220b 第二半導體晶片 220之非電路面 230 被動元件 240 球栅陣列 251 第一黏膝層 252 第二黏膠層 253 被動元件鲜墊 261 第一銲線組 262 第二銲線組 300 基板 300a 基板300之正面 300b 基板300之背面 310 第一半導體晶片 310a 第一半導體晶片 310之電路面 310b 第一半導體晶片 31 〇之非電路面 320 第二半導體晶片 320a 第二半導體晶片 320之電路面 320b 第二半導體晶片 320之非電路面 330 被動元件 340 球栅陣列 351 覆晶銲塊陣列 352 第一黏膠層 冬紙張尺度適用中國國家標準（CNS)A4規格（210 x 29/公t) 16069 lull - ---I---It*! —---0 {锖先間讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製. A7 B7 五、發明說明（6 ) 353 第二黏膠層 361 第一銲線組 362 第二銲線組 400 基板 400a 基板400之正面 400b 基板400之背面 410 第一半導體晶片 410a 第一半導體晶片 410之電路面 410b 第一半導體晶片 4 1 0之非電路面 420 第二半導體晶片 420a 第二半導體晶片 420之電路面 420b 第二半導體晶片 420之非電路面 430 被動元件 440 球柵陳列 451 第一黏膠層 452 覆晶銲塊陣列 453 第二黏膠層 461 第一銲線組 462 第二銲線組 ί發明實施例j 以T即配合所附圖式之第！ A至1 B圖-第2圖 第3 圖 '第4圖、和第5圖分別詳細揭露說明本發明之堆疊 式多晶片封裝結構之五個不同之實施例、 第一實施例/第I A至1 β圖）1606V 461058 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention (3) The space occupied by the second semiconductor chip. In the above-mentioned stacked multi-chip package structure, the first semiconductor wafer and the second semiconductor wafer can be electrically connected to the substrate by wire bonding technology or flip-chip technology; and passive components can be connected by wire-wire technology (wire- Bonding technology (WBT) is electrically connected to the substrate, or is directly electrically bonded to the first semiconductor chip by surface-mount technology (SMT). In the above-mentioned stacked multi-chip package structure, since the passive components are disposed on the first semiconductor wafer and not occupied by the second semiconductor wafer, rather than on the substrate, the overall package size can be reduced. The know-how is smaller. [Brief Description of the Drawings] The essential technical contents of the present invention and its embodiments have been disclosed in detail in the drawings in the drawings attached to this specification. The contents of these drawings are briefly described as follows: FIG. 1A shows a three-dimensional schematic view of the first embodiment of the stacked multi-chip packaging structure of the present invention; FIG. 1B shows a stacked multi-chip packaging structure shown in FIG. 1A. Sectional schematic diagram; FIG. 2 shows a sectional schematic diagram of a second embodiment of the stacked multi-chip package structure of the present invention: FIG. 3 shows a sectional schematic diagram of a third embodiment of the stacked multi-chip package structure of the present invention: The figure shows the fourth reality of the stacked multi-chip package structure of the present invention {Please read the precautions on the back before filling out this page) Assembling --- Order --- 1!-^ This paper size applies to China National Building Standard (CNS 〉 A4 specification (210 X 297 public love) 3 16069 Λ7 B7 V. Description of the invention (4) Sectional schematic diagram of the embodiment; printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [Symbol No.] 100 substrate 100a front side of substrate 100 100b Back surface 110 of substrate 100 First semiconductor wafer 110a Circuit surface 110b of first semiconductor wafer 110 Non-circuit surface 120 of first semiconductor wafer no Second semiconductor wafer 120a second half Circuit surface 120b of conductor wafer 120 Non-circuit surface of second semiconductor wafer 120 130 Passive element 140 Ball grid array 151 First adhesive layer 152 Second adhesive layer 153 Third adhesive layer 161 First bonding wire group 162 Second Bonding wire group 163 Third bonding wire group 200 Substrate 200a Front surface of substrate 200 200b Back surface of substrate 200 210 First abundance conductor wafer:? 10a First conductor crystal M 2 .Η) Cen circuit surface -------- ----- Installation -------- Order --------- line (please read the precautions on the back before filling this page) 461058 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Fifth, the description of the invention (5) 210b The non-circuit surface 220 of the first semiconductor wafer 2 10 The second semiconductor wafer 220a The circuit surface 220b of the second semiconductor wafer 220 The non-circuit surface 230 of the second semiconductor wafer 220 Passive element 240 Ball grid array 251 First adhesive layer 252 Second adhesive layer 253 Passive component pad 261 First bonding wire group 262 Second bonding wire group 300 Substrate 300a Front side of substrate 300 300b Back side of substrate 300 310 First semiconductor wafer 310a A circuit surface 310b of a semiconductor wafer 310, a non-circuit surface 320 of a first semiconductor wafer 31, a second semiconductor wafer 320a, a circuit surface 320b of a second semiconductor wafer 320, a non-circuit surface of a second semiconductor wafer 320, a passive element 340, a ball grid array 351, Chip-on-chip solder bump array 352 The first adhesive layer of winter paper is sized for China National Standard (CNS) A4 (210 x 29 / g t) 16069 lull---- I --- It *! ---- 0 {读 Read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. A7 B7 V. Invention Description (6) 353 Second adhesive layer 361 First bonding wire group 362 Second bonding wire Group 400 substrate 400a front surface 400b of substrate 400 back surface of substrate 400 410 first semiconductor wafer 410a first circuit surface 410b of first semiconductor wafer 410 non-circuit surface 420 of first semiconductor wafer 4 1 0 second semiconductor wafer 420a second semiconductor wafer 420 Circuit surface 420b Non-circuit surface 430 of the second semiconductor wafer 420 Passive component 440 Ball grid display 451 First adhesive layer 452 Flip chip array 453 Second The first adhesive layer 461 bonding wire 462 of the second set of bonding wires to set T j ί invention i.e. accompanying figures of the first embodiment! Figures A to 1 B-Figure 2 to Figure 3 and Figures 4 and 5 respectively detail five different embodiments of the stacked multi-chip package structure of the present invention, the first embodiment / IA to 1 β picture)

null ιι. Βι ΙΊ ί,,— ,r· ! r-ίη ίίί.'ί Μ·«ί·'·~ "·ι» ι··ιΐ' ·ιί αι ιι·· ui"1·····—「圓_"~師_^^· 画1· 卜1·—ηιπ—ι.-τ-ίτ ·ι·γ μ*γ^τ—ί γγγγιτ-· -mnr nr ι ι·ηι· 11 τιγ ι ~ι~ .......... ι-·ι •nv-nfi-m-irn-'ii |[ΤΓ ....丄一」-_、MTII1· 木啤ΚΙ.適用士阐國家螵舉（CNS) \4規格〔2Ui " 6 16069 ---- ------------------訂--------ί (請先閱讀背面之注意事項再填莴本頁) 經濟部智慧財產局員工消費合作社印製 461058 A7 ____B7___ 五、發明說明（7 ) 以下即配合所附囷式中之第1A至1B圈，詳細揭露說 明本發明之堆疊式多晶片封裝結構之第—實施例β 請參閱第1Α圖’本發明之堆疊式多晶片封裝結構包 含一基板100、一第一半導體晶片110、一第二半導體晶片 120、以及至少一被動元件13〇(註：此處之第1Α圏為簡化 之示意圖式’其僅顯示與本發明有關之元件；具體實施之 封裝結構的元件數目及佈局形態可能更為複雜）。 請同哼參閱第1Β圖和第1Α圖，基板100具有一正面 100a和一背面100b ;其中正面i〇〇a用以置晶（亦即用以安 置第一半導體晶片110和第二半導體晶片120)，而背面 100b則用以植置一球栅陣列（ball grid array)140。 苐一半導體晶片110具有一電路面lI〇a和一非電路面 110b(註：此處所謂之”電路面，，係指半導體晶片上形成積艘 電路元件和輪出入銲墊之正面；而"非電路面"則係指半導 體晶片上未形成積體電路元件和輸出入鲜墊之背面）,·其中 非電路面110b係藉由一第一黏膠層151，例如為一银膝 層’而黏貼至基板100的正面i 〇〇a上。此外，第一半導體 晶片110係藉由一第一銲線·组Ϊ61而電性連接至基板 100 «null ιι. Βι ΙΊ ί ,,-, r ·! r-ίη ίίί.'ί Μ · «ί · '~~ " · ι» ι ·· ιΐ' · ιί αι ι ·· ui " 1 ··· ·· — 「圆 _ " ~ 师 _ ^^ · Painting 1 · Bu 1 · —ηιπ—ι.-τ-ίτ · ι · γ μ * γ ^ τ—ί γγγγιτ- · -mnr nr ι ιηη · 11 τιγ ι ~ ι ~ .......... ι- · ι • nv-nfi-m-irn-'ii | [ΤΓ .... 丄 一 」-_, MTII1 · 木 beer ΚΙ .Applicable to National Standards (CNS) \ 4 specifications [2Ui " 6 16069 ---- ------------------ Order -------- ί (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 461058 A7 ____B7___ V. Description of the invention (7) The following is in accordance with the circles 1A to 1B in the attached formula, The detailed disclosure of the first embodiment of the stacked multi-chip package structure of the present invention is shown in FIG. 1A. The stacked multi-chip package structure of the present invention includes a substrate 100, a first semiconductor wafer 110, and a second semiconductor wafer. 120, and at least one passive element 13〇 (Note: The first 1A here is a simplified schematic diagram 'which shows only relevant to the present invention Element; number of elements and arrangement forms a package structure of particular embodiments may be more complicated). Please refer to FIG. 1B and FIG. 1A together. The substrate 100 has a front surface 100a and a back surface 100b. The front surface 100a is used for crystal placement (that is, the first semiconductor wafer 110 and the second semiconductor wafer 120 are disposed thereon). ), And the back 100b is used to plant a ball grid array 140. (1) A semiconductor wafer 110 has a circuit surface 110a and a non-circuit surface 110b (Note: the so-called "circuit surface" refers to the front side of the semiconductor wafer on which the building circuit components and wheel access pads are formed; and "Non-circuit surface" refers to the backside of the semiconductor wafer where integrated circuit components and I / O pads are not formed), where the non-circuit surface 110b is through a first adhesive layer 151, such as a silver knee layer 'And stuck to the front surface 〇〇a of the substrate 100. In addition, the first semiconductor wafer 110 is electrically connected to the substrate 100 through a first bonding wire · group 61 «

須注意的一點是，本發明之堆疊式多晶片封裝結構中 之第一半導體晶片120的尺寸須小於第一半導艘^片HQ 的尺寸’以使得第二半導體晶片120和被動元件13〇可同 時安置於第一半導體晶片110上。 ° 第二半導艘晶片120具有一電路面i2〇a和一非電路 I----------- - i I -----^ ----11^ ί請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 7 16069 Λ： Β7 五、發明說明（8 ) 120b ;其_非電路面120b係藉由一第二黏膠層in，例如 為一銀膠層’而黏貼至第一半導體晶片11〇的電路面u 〇a 上。此外’第二半導體晶片120係藉由一第二靜線組M2 而電性連接至基板100。 本發明之堆要式多晶片封裝結構的主要特點即在於將 被動元件130安置於第一半導體晶片11〇上未被第二半導 體晶片1 2 0所佔據之多餘空間上。於此實施例中，被動元 件1 30之安置方式例如係藉由一第三黏膠層丨53而黏貼至 第一半導體晶片110的電路面110a上，並採用銲線技術 (wire-bonding techno丨ogy，WBT)藉由一第三銲線組 163 而 電性連接至基板100。此第三銲線組163包括一對銲線， 用以分別將各個被動元件1 30之二端連接至基板1 00上的 對應銲墊（未顯示）。 接著後續之封裝膠體製程為習知技術，且非關本發明 ..之實質技術内容與範圍，因此以下將不對其作進一步詳細 之說明。 於上述之堆疊式多晶片封裝結構中，由於被動元件 130係被安置於第一半導體晶片U0上未被第二半導體晶 片120所佔據之多餘空間上1而非安置於基板100上，因 此可使得整體之封裝尺寸較習知技術更小。 第二實施例（笫2 Sp 以下即配合所附圖式中之.第2圖詳細揭露說明本發 明之堆疊式多晶片封裝結構之第二實施例， 如圖％承 第二實掩例之.堆疊式多晶片封裝結耩包含.| {琦先閱讀背面之注意事項再填寫本頁) 裝---- 訂---------線-- 經濟部智慧財產局異工消費合作，社印繁It should be noted that the size of the first semiconductor wafer 120 in the stacked multi-chip package structure of the present invention must be smaller than the size of the first semi-conductor wafer HQ 'so that the second semiconductor wafer 120 and the passive component 13 can be At the same time, it is placed on the first semiconductor wafer 110. ° The second semi-conductor wafer 120 has a circuit surface i2〇a and a non-circuit I ------------i I ----- ^ ---- 11 ^ ί Please read first Note on the back page, please fill in this page again) This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 7 16069 Λ: Β7 V. Description of the invention (8) 120b; its _non-circuit surface 120b is borrowed A second adhesive layer in, such as a silver adhesive layer, is adhered to the circuit surface u 0a of the first semiconductor wafer 11o. In addition, the second semiconductor wafer 120 is electrically connected to the substrate 100 through a second static line group M2. The main feature of the stack-type multi-chip packaging structure of the present invention is that the passive component 130 is disposed on the first semiconductor wafer 110 and in the excess space not occupied by the second semiconductor wafer 120. In this embodiment, the passive component 130 is disposed, for example, by a third adhesive layer 53 and pasted onto the circuit surface 110a of the first semiconductor wafer 110, and wire-bonding techno (ogy, WBT) is electrically connected to the substrate 100 through a third bonding wire group 163. The third bonding wire group 163 includes a pair of bonding wires for respectively connecting two ends of each passive component 130 to corresponding pads (not shown) on the substrate 100. The subsequent encapsulation system is a conventional technology and is not related to the essential technical content and scope of the present invention. Therefore, it will not be described in further detail below. In the above-mentioned stacked multi-chip package structure, since the passive component 130 is placed on the first semiconductor wafer U0 on the excess space 1 not occupied by the second semiconductor wafer 120 instead of being placed on the substrate 100, it can make The overall package size is smaller than the conventional technology. The second embodiment (笫 2 Sp is shown below in conjunction with the attached drawings. Figure 2 details the second embodiment of the stacked multi-chip package structure of the present invention, as shown in the second embodiment. Stacked Multi-chip Package Contains Included. | (Qi first read the notes on the back and then fill out this page) Packaging ---- Order --------- Line-Intellectual Property Bureau, Ministry of Economic Affairs She Yinfan

ka.K嗲過用Φ國阉萆樓莘（(：N：:：：；)w規格?9:.公嚀 I606V 經濟部智慧財產局員工消費合作社印製 461058 ^ A7 - —— --------- 五、發明說明（9 ) 一基板200、一第一半導體晶片21〇、一第二半導體晶片 220、以及至少一被動元件230。 基板200具有一正面200a和一背面200b ;其中正面 200a用以置晶（亦即用以安置第一半導體晶片21〇和第二 半導體晶片220)，而背面2〇〇b則用以植置一球柵陣列 240 - 第一半導體晶片210具有一電路面210a和一非電路面 21 〇b，其中非電路面21 Ob係藉由一第一黏膠層251，例如 為一銀膠層’而黏貼至基板2〇〇的正面2〇〇狂上。此外，第 一半導艘晶片210係藉由一第一銲線組261而電性連接至 基板200。 第二丰導體晶片220的尺寸小於第一半導體晶片210 的尺寸’且其具有一電路面22〇a和一非電路面220b ;其 中非電路面220b係藉由一第二黏膠層252,例如為一銀膠 層’而黏貼至第一半導體晶片210的電路面210a上。此外， 第二半導體晶片220係藉由一第二銲線組262而電性連接 至基板200。 本發明之堆要式多晶片封裝結構的主要特點即在於將 被動元件230安置於第一半導體晶片210上未被第二半導 體晶片220所佔據之多餘空間上。於此第二實施例中，其 與第一實施例不同之點僅在於此處之被動元件230係採用 表面藕接技術（surface-mount technology，SMT)而直接電性 銲結至第一半導體晶片210上對應的被動元件銲墊253 上，藉此而將被動元件230電性連接至第一半導體晶片 -----------1 i I ---I--^---------^ (請先閱讚背面之注意事項再填寫本頁> 本紙張尺度適用中國g家標準（CNS)A4規格（210 X 297公釐） 9 16069 A7 ___B7__ 五、發明說明（10 ) 210。 於上述之堆要式多晶片封裝結構中，由於被動元件 230係被安置於第一半導體晶片2]0上未被第二半導趙晶 片220所佔據之多餘空間，而非安置於基板200上，因此 可使得整體之封裝尺寸較習知技術更小。 第三實施例（第3圈） 以下即配合所附圖式中之第3圖’詳細揭露說明本發 明之堆疊式多晶片封裝結構之第三實施例。 如圖所示，第三實施例之堆疊式多晶片封裝結構包含 一基板300、一第一半導體晶片31〇、一第二半導體晶片 320、以及至少一被動元件3 30。 基板3 00具有一正面300a和一背面300b:其令正面 )00a用以置晶（亦即用以安置第一半導體晶片3 1 〇和第二 羊導體晶片320) ’而背面300b則用以植置一球栅陣列 340 = 第一半導體晶片310具有一電路面31〇a和一非電路面 3 1〇b :其中電路面310a係採用覆晶技術（fUp_chip technology卜藉由—覆晶銲塊陣列35]而電性銲結至基板 300的正面300a。 第二半導體晶片320的尺寸小於第—半導體晶片3 [〇 的尺寸且其具有—電路面32〇a和—非電路面320b ;其 中非電路面320b係藉由…第―黏穋層3 52,洌如為―銀膠 層而黏貼至第...〜半導體晶片Μ 0的非電路面.3 [ 0 b.丄，_此 外’第：半導體晶月320係藉由—第..銲線组3 W而電性 (請先satl背面之沒帝？事項再填寫本頁) —裝----ka.K 嗲 Using ΦGuo 阉 萆 lou 莘 ((: N ::::;) w specifications? 9: .Publication I606V Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 461058 ^ A7----- --- ------ V. Description of the invention (9) A substrate 200, a first semiconductor wafer 210, a second semiconductor wafer 220, and at least one passive element 230. The substrate 200 has a front surface 200a and a back surface 200b; The front surface 200a is used for placing crystals (that is, the first semiconductor wafer 21 and the second semiconductor wafer 220), and the back surface 200b is used for implanting a ball grid array 240-the first semiconductor wafer 210 has A circuit surface 210a and a non-circuit surface 21 OB, wherein the non-circuit surface 21 Ob is adhered to the front surface 200 of the substrate 200 through a first adhesive layer 251, such as a silver adhesive layer. In addition, the first semi-conductor wafer 210 is electrically connected to the substrate 200 through a first bonding wire group 261. The size of the second conductor wafer 220 is smaller than the size of the first semiconductor wafer 210 'and it has a The circuit surface 22a and a non-circuit surface 220b; wherein the non-circuit surface 220b is through a second adhesive layer 252, such as The silver adhesive layer is adhered to the circuit surface 210a of the first semiconductor wafer 210. In addition, the second semiconductor wafer 220 is electrically connected to the substrate 200 through a second bonding wire group 262. The stacking method of the present invention is various The main feature of the chip package structure is that the passive component 230 is disposed on the first semiconductor wafer 210 on the excess space not occupied by the second semiconductor wafer 220. In this second embodiment, it is different from the first embodiment The only point here is that the passive component 230 here uses surface-mount technology (SMT) to directly electrically bond to the corresponding passive component pad 253 on the first semiconductor wafer 210, thereby passively The device 230 is electrically connected to the first semiconductor wafer ----------- 1 i I --- I-^ --------- ^ (Please read the notes on the back of the praise first Fill out this page again> This paper size is applicable to China Standard (CNS) A4 (210 X 297 mm) 9 16069 A7 ___B7__ 5. Description of the invention (10) 210. In the above-mentioned multi-chip package structure Since the passive element 230 is placed on the first semiconductor wafer 2] 0 The extra space occupied by the semiconductor chip 220 is not placed on the substrate 200, so that the overall package size can be smaller than the conventional technology. Third Embodiment (Round 3) Fig. 3 'details the third embodiment of the stacked multi-chip packaging structure of the present invention. As shown in the figure, the stacked multi-chip packaging structure of the third embodiment includes a substrate 300 and a first semiconductor wafer 31. O, a second semiconductor wafer 320, and at least one passive element 3 30. The substrate 300 has a front surface 300a and a back surface 300b: the front surface 00a is used for placing crystals (that is, used to place the first semiconductor wafer 3 10 and the second sheep conductor wafer 320) 'and the back surface 300b is used for planting Set a ball grid array 340 = the first semiconductor wafer 310 has a circuit surface 31 〇a and a non-circuit surface 3 1 〇b: The circuit surface 310a is using flip-chip technology (fUp_chip technology)-flip-chip bonding pad array 35] and electrically bonded to the front side 300a of the substrate 300. The size of the second semiconductor wafer 320 is smaller than the size of the first semiconductor wafer 3 [0 and it has-circuit surface 32a and non-circuit surface 320b; The surface 320b is affixed to the non-circuit surface of the semiconductor wafer M 0 by the ―adhesive layer 3 52, such as a silver adhesive layer. 3 [0 b. The semiconductor crystal moon 320 is electrically connected to—the first: wire bonding group 3 W (please fill in this page first on the back of the satl) —installation ----

經濟部智慧財產局員工消費合作社EP.R 4 6 1 05 8 A7 B7 五、發明說明（) 連接至基板30(^ (請先閱讀背面之注意事項再填寫本頁> 本發明之堆疊式多晶片封裝結構的主要特點即在於將 被動元件330安置於第一半導體晶片31〇上未被第二半導 體晶片320所佔據之多餘空間上。於此第三實施例中被 動元件330係藉由一第二黏膠層353而黏貼至第一半導體 晶片310的非電路面310b上，並採用銲線技術藉由一第二 輝線組362而電性連接至基板3〇〇。 於上缚之堆疊式多晶片封裝結構中，由於被動元件 330係被安里於第一半導體晶片31〇上未被第二半導體晶 片320所佔據之多餘空間’而非安置於基板300上，因此 可使得整體之封裝尺寸較習知技術更小D 第四實施例（第4两、 以下即配合所附圊式令之第4圓’詳細揭露說明本發 明之堆疊式多晶片封裝結構之第四實施例β 如圖所示，第四實施例之堆疊式多晶片封裝結構包含 一基板400、一第一半導體晶片41〇、一第二半導體晶片 420、以及至少一被動元件430。 經濟部智慧財產局員工消費合作社印製 基板400異有一正面4〇〇a和一背面400b;其中正面 400a用以置晶（亦即用以安置第一半導體晶片41〇和第二 半導體晶片420)，而背面400b則用以植置一球柵陣列 440 ° 第一半導艘晶片410具有一電路面410a和一非電路面 41〇b ;其中非電路面410b係藉由一第一黏膠層451，例如 為一銀膠層，而黏貼至基板400的正面400a上。此外，第 本紙張尺度適用中國國家標準（CNS)A4蜆格（210 X 297公® ) 11 16069 A7 A7 經濟邾智慧財產局員工消費合作社vtpt ..---.__B7 ____ 五、發明說明（U ) 一半導體晶片410係藉由一第一銲線组461而電性連接至 基板400。 第二半導體晶片420的尺寸小於第一半導體晶片410 的尺寸，旦其具有一電路面4 2 0a和一非電路面420b :其 中電路面420a係採用覆晶技術，藉由一覆晶銲塊陣列452 而電性銲結至第一半導體晶片410的電路面410a。 本發明之堆疊式多晶片封裝結構的主要特點即在於將 被動元件430安置於第一半導體晶片410上未被第二半導 想晶片420所佔據之多餘空間上〇於此第四實施例中，被 動元件430係藉由一黏膠層453而黏貼至第一半導體晶片 410的電路面410a上，並採用銲線技術藉由一第二銲線組 462而電性連接至基板400。 於上述之堆疊式多晶片封裝結構令，由於被動元件 430係被安置於第一半導體晶片410上未被第二半導體晶 片420所佔據之多餘空間，而非安置於基板4〇〇上，因此 可使得整體之封裝尺寸較習知技術更小》 [结論] 綜而言之，本發明提供了 一種具有整合型被動元件之 堆疊式多晶片封裝結構，其特點在於將被動元件整合於多 晶片架構中之下層晶片上未被上層晶片所佔據之多餘空 間·而非整合於基板上，因此可使得整體之封裝尺寸較習 知技術更此外本發明之堆疊式多晶片封裝結構中所 整合之被動儿件可直接採用-般之零件式被動元件因此 可使得整體之封裝製程更具有成本致益 ---------------------訂_-------- <請先閱讀背面之浼意事項再填窵本頁) Ϊ6069 Α7 Β7 五、發明說明（u) 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之實質技術内容的範圍β本發明之實質技術内容 係廣義地定義於下述之申請專利範圍中。任何他人所完成 之技術實體或方法，若是與下述之申請專利範圍所定義者 為完全相同、或是為一種等效之變更，均將被視為涵蓋於 此專利II圍之中。 I I.. '裝 ----il— 訂 *--------^V ί琦先閱讀背面之注意事項再填窝本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中a S家標準（CNS)A4規格（210 X 297 13 16069Employees' Cooperatives EP.R 4 6 1 05 8 A7 B7 of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Connected to the substrate 30 (^ (Please read the precautions on the back before filling out this page) The main feature of the chip package structure is that the passive element 330 is disposed on the first semiconductor wafer 31 and is not occupied by the second semiconductor wafer 320. In this third embodiment, the passive element 330 is formed by a first The two adhesive layers 353 are adhered to the non-circuit surface 310b of the first semiconductor wafer 310, and are electrically connected to the substrate 300 through a second glow wire group 362 using a wire bonding technology. In the chip package structure, since the passive component 330 is disposed on the first semiconductor wafer 31o and not occupied by the second semiconductor wafer 320, instead of being disposed on the substrate 300, the overall package size can be made more conventional. Known technology is smaller D The fourth embodiment (the fourth two, the following is the fourth circle in accordance with the attached sequel to the detailed disclosure of the fourth embodiment of the stacked multi-chip package structure of the present invention β is shown in the figure, First The stacked multi-chip package structure of the embodiment includes a substrate 400, a first semiconductor wafer 4110, a second semiconductor wafer 420, and at least one passive element 430. The printed circuit board 400 of the consumer cooperative of the employee of the Intellectual Property Bureau of the Ministry of Economic Affairs Front 400a and a back 400b; the front 400a is used to place crystals (that is, the first semiconductor wafer 41 and the second semiconductor wafer 420), and the back 400b is used to plant a ball grid array 440 ° The first half of the guide wafer 410 has a circuit surface 410a and a non-circuit surface 410b; wherein the non-circuit surface 410b is adhered to the substrate 400 through a first adhesive layer 451, such as a silver adhesive layer. On the front side 400a. In addition, this paper size applies the Chinese National Standard (CNS) A4 grid (210 X 297 male ®) 11 16069 A7 A7 Economic and Intellectual Property Bureau Staff Consumer Cooperatives vtpt ..---.__ B7 ____ 5 Explanation of the invention (U) A semiconductor wafer 410 is electrically connected to the substrate 400 through a first bonding wire group 461. The size of the second semiconductor wafer 420 is smaller than that of the first semiconductor wafer 410, and once it has a circuit surface 4 2 0a and A non-circuit surface 420b: The circuit surface 420a is a flip-chip technology, and is electrically bonded to the circuit surface 410a of the first semiconductor wafer 410 through a flip-chip bonding pad array 452. The stacked multi-chip package structure of the present invention The main feature is that the passive component 430 is placed on the first semiconductor wafer 410 on the excess space not occupied by the second semiconductor wafer 420. In this fourth embodiment, the passive component 430 is made of an adhesive The layer 453 is adhered to the circuit surface 410a of the first semiconductor wafer 410, and is electrically connected to the substrate 400 through a second bonding wire group 462 using bonding wire technology. Based on the above-mentioned stacked multi-chip package structure, since the passive component 430 is disposed on the first semiconductor wafer 410 and not occupied by the second semiconductor wafer 420, it is not disposed on the substrate 400, so it can be used. Making the overall package size smaller than the conventional technology "[Conclusion] In summary, the present invention provides a stacked multi-chip packaging structure with integrated passive components, which is characterized by integrating passive components in a multi-chip architecture The extra space on the lower wafer that is not occupied by the upper wafer is not integrated on the substrate, so that the overall package size can be larger than the conventional technology. In addition, the passive components integrated in the stacked multi-chip packaging structure of the present invention Can directly use-general part-type passive components can therefore make the overall packaging process more cost-effective ------------ Order _----- --- < Please read the notice on the back before filling this page) Ϊ6069 Α7 Β7 V. Description of the Invention (u) The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Scope of substantial technical content Essence of the technical SUMMARY The present invention is broadly defined in the in the scope of the following patent. Any technical entity or method completed by another person, if it is exactly the same as defined in the scope of patent application described below, or an equivalent change, will be deemed to be covered by this patent II. I I .. '装 ---- il— order * -------- ^ V ί Qi first read the notes on the back before filling in this page) Printed on paper by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Standards are applicable in China Standards (CNS) A4 specifications (210 X 297 13 16069

Claims (1)

經濟部智慧財產局員工消費合作社fr):於 1606« AS B8 C8 DS 六、申請專利範圍 1. 一種堆疊式多晶片封裝結構，其包含： U)—基板： (b)—第一半導體晶片’其係安置於該基板上； (C)一第二半導體晶片’其係安置於該第一半導體 晶片上；該第二半導體晶片之尺寸小於該第一半導體晶 片之尺寸：以及 (d)至少一被動元件，其係安置於該第一半導體晶 片上未被該第二半導體晶片所佔據之空間上3 2. 如申請專利範圍第|項所述之堆疊式多晶片封裝結 構’其中該第一半導體晶之安置方式係藉由一黏膠層而 黏貼至該基板上，並藉由/銲線組而電性連接至該基 板。 3如申請專利範圍第丨項所述之堆疊式多晶片封裝結 構’其中該第一半導體晶片之安置方式係採用覆晶技 術’藉由一覆晶鲜塊陣列而電性#結至該基板a 4如申請專利範圍第丨項所述之堆疊式多晶片封裝結 構其中該第二半導體晶片之安置方式係藉由一黏膠層 而黏貼至該第一丰導體晶片上，並藉由一銲線組而電性 連接至該基板。 5如申請專利範圍第1項所述之堆疊式多晶片封裝結 搆，其中該第二半導體晶片之，安置方式係採用覆晶技 術，藉由一覆晶辉塊陣列而電性知結至該第一丰導體晶 片. 6如申請專利範園第丨項姊述之堆疊式多晶片封裝結 --- n_ ~—~πτ~ιιτ~·ι—wn ii τη—、τ·τ~ιτπ·-ΐίτι 鞾 蒂Λ t滴厗七阀闽家浮:® (OS'; 厂-爱） (請先閱讀背面之注意事項再填寫本頁) -裝--------訂---------線— A8B8C8D8 461058 六、申請專利範圍 構’其中該被動元件之安置方式係採用銲線技術，藉由 一銲線组而電性連接至該基板。 7.如申請專利範園第丨項所述之堆疊式多晶片封裝結 構’其中該被動元件之安置方式係採用表面藕接技術， 直接電性銲結至該第一半導體晶片β 8- —種堆疊式多晶片封裝結構，其包含： (a) —基板； (b) —第一半導體晶片，其係安置於該基板上； (c) 一第二半導體晶片，其係安置於該第一半導體 晶片上；該第二半導體晶片之尺寸小於該第一半導髏晶 片之尺寸；以及 (d) 至少一被動元件，其係安置於該第一半導體晶 片上未被該第二半導體晶片所佔據之空間上，且係採用 銲線技術藉由一銲線組而電性連接至該基板。 9. 如申請專利範圍第8項所述之堆疊式多晶片封裝結 構，其中該第一半導體晶之安置方式係藉由一黏膠層而 黏貼至該基板上，並藉由一銲線組而電性連接至該基 板。 10. 如申請專利範圍第8項所述之堆疊式多晶片封裝結 構’其中該第一半導體晶片之安置方式係採用覆晶技 術’藉由一復晶銲塊陣列而電性銲結至該基板。 11. 如申請專利範圍第8項所述之堆疊式多晶片封裝結 構’其中該第二半導體晶片之安置方式係藉由一黏膠層 而黏貼至該第一半導體晶片上，並藉由一銲線組而電性 - !i I J I I I I |\ · I I-----訂- - - - - ----^ / , ' (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財1局員Η消費合作社印製 本紙張尺度適用t國S家標準（CNS)A4規格（210 X 297公釐） 15 16069 經 濟 部 智 慧 財 產 局 消 費 合 ;· 社 丨6如申請專利範圍 搆其中該第二 而黏貼至該：第. 、申請專利範圍 連接至該基板。 12.如申請專利範圍第8項所述之堆番式多晶片封裝結 構，其中該第二半導體晶片之安置方式係採用覆晶技 術'藉由一覆晶銲塊陣列而電性鲜結至該第一半導體晶 片。 13_—種堆疊式多晶片封裝結構’其包含： (a) —基板； (b) —第一半導體晶片’其係安置於該基板上； (c) 一第二半導體晶片，其係安置於該第一半導體 晶片上：該第二半導體晶片之尺寸小於該第一半導體晶 片之尺寸：以及 (d)至少一被動元件，其係安置於該第一半導體晶 片上未被該第二半導體晶片所佔據之空間上，且係採用 表面藕接技術而電性銲結至該第一半導體晶片。 丨4.如申請專利範圍第13項所述之堆疊式多晶片封裝結 構’其中該第一半導艘晶之安置方式係藉由一黏膠層而 黏貼至該基板上，並藉由一銲線組而電性連接至該基 板’ 5如申請專利範圍第13項所述之堆疊式多晶片封裝結 構1其中該第—半導體晶片之安置方式係採用覆晶技 術’藉由一覆晶銲塊陣列而電性銲結至該基板 第丨3項,所述之堆疊式多晶片封裝結 丰導體晶片之安置方式係藉由..黏膠層 r導趙晶片上.並藉由…銲線組而電，卜 16069 461058 A8 B8 C8 D8六、申請專利範圍 連接至該基板。 17.如申請專利範圍第13項所述之堆疊式多晶片封裝結 構，其中該第二半導體晶片之安置方式係採用覆晶技 術，藉由一覆晶銲塊陣列而電性銲結至該第一半導體晶 片。 (請先閱讀背面之α意事項再填寫本頁) 裝-------訂------I線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 17 16069Employees 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs fr): In 1606 «AS B8 C8 DS VI. Application for patent scope 1. A stacked multi-chip package structure including: U)-substrate: (b)-first semiconductor wafer' It is placed on the substrate; (C) A second semiconductor wafer is placed on the first semiconductor wafer; the size of the second semiconductor wafer is smaller than the size of the first semiconductor wafer: and (d) at least one The passive component is placed on the first semiconductor wafer and not occupied by the second semiconductor wafer. 3 2. The stacked multi-chip package structure described in the scope of the patent application | item | where the first semiconductor The placement method of the crystal is to adhere to the substrate through an adhesive layer, and to electrically connect to the substrate through a bonding wire group. 3 The stacked multi-chip package structure described in item 丨 of the scope of the patent application 'wherein the first semiconductor wafer is placed using flip-chip technology' through an array of flip-chip fresh blocks and electrically #knot to the substrate a 4 The stacked multi-chip package structure described in item 丨 of the patent application scope, wherein the second semiconductor chip is disposed by an adhesive layer and pasted onto the first conductor chip, and by a bonding wire And is electrically connected to the substrate. 5. The stacked multi-chip package structure according to item 1 of the scope of the patent application, wherein the second semiconductor wafer is arranged using a flip-chip technology and is electrically connected to the first semiconductor chip through an array of flip-chip blocks. Yifeng Conductor Wafer. 6 As described in the patent application Fanyuan, the stacked multi-chip packaging junction described in the above-mentioned n- ~~~~ πτ ~ ιιτ ~ · ι-wn ii τη—, τ · τ ~ ιτπ · -ΐίτι鞾 蒂 Λ t 滴 厗 7 valve Fujian Jiafu: ® (OS '; factory-love) (Please read the precautions on the back before filling out this page) -Install -------- Order ----- ---- Wire — A8B8C8D8 461058 6. The scope of the patent application structure 'where the passive component is arranged using bonding wire technology and is electrically connected to the substrate through a bonding wire group. 7. The stacked multi-chip package structure according to item 丨 of the patent application park, wherein the passive component is arranged using surface bonding technology, and is directly electrically bonded to the first semiconductor wafer β 8-- A stacked multi-chip package structure including: (a) a substrate; (b) a first semiconductor wafer, which is disposed on the substrate; (c) a second semiconductor wafer, which is disposed on the first semiconductor On the wafer; the size of the second semiconductor wafer is smaller than the size of the first semiconductor wafer; and (d) at least one passive element that is disposed on the first semiconductor wafer and is not occupied by the second semiconductor wafer In space, it is electrically connected to the substrate through a bonding wire group using bonding wire technology. 9. The stacked multi-chip package structure according to item 8 of the scope of the patent application, wherein the first semiconductor crystal is disposed on the substrate by an adhesive layer, and by a bonding wire group. It is electrically connected to the substrate. 10. The stacked multi-chip package structure described in item 8 of the scope of the patent application, wherein the first semiconductor wafer is placed using a flip-chip technology, and is electrically bonded to the substrate through an array of polycrystalline bumps. . 11. The stacked multi-chip package structure described in item 8 of the scope of the patent application, wherein the second semiconductor wafer is placed on the first semiconductor wafer by an adhesive layer, and is soldered by a solder. Wire group and electrical-! I IJIIII | \ · I I ----- Order--------- ^ /, '(Please read the precautions on the back before filling this page) 1 Bureau member / Consumer cooperative prints the paper standard applicable to National Standards (CNS) A4 specifications (210 X 297 mm) 15 16069 Intellectual Property Bureau of the Ministry of Economic Affairs Consumption Cooperation; Second, stick to it: No. 1. The scope of patent application is connected to the substrate. 12. The stack-type multi-chip package structure as described in item 8 of the scope of the patent application, wherein the second semiconductor wafer is disposed using a flip-chip technology through an array of flip-chip solder bumps and electrically bonded to the chip. First semiconductor wafer. 13_—a stacked multi-chip package structure 'which includes: (a) a substrate; (b) a first semiconductor wafer' which is disposed on the substrate; (c) a second semiconductor wafer which is disposed on the On the first semiconductor wafer: the size of the second semiconductor wafer is smaller than the size of the first semiconductor wafer: and (d) at least one passive element, which is disposed on the first semiconductor wafer and is not occupied by the second semiconductor wafer In space, it is electrically bonded to the first semiconductor wafer by surface bonding technology.丨 4. The stacked multi-chip package structure described in item 13 of the scope of the patent application, wherein the first semi-conductor wafer is placed on the substrate by an adhesive layer, and by a solder Wire group to be electrically connected to the substrate '5 The stacked multi-chip package structure described in item 13 of the scope of patent application 1 where the first semiconductor wafer is placed using a flip-chip technology' through a flip-chip solder bump The array is electrically bonded to item 3 of the substrate. The stacking multi-chip package junction conductor chip is placed by means of an adhesive layer on the wafer and by a wire bond group. And electricity, BU 16069 461058 A8 B8 C8 D8 6. The scope of the patent application is connected to the substrate. 17. The stacked multi-chip package structure according to item 13 of the scope of the patent application, wherein the second semiconductor wafer is placed using a flip-chip technology and electrically bonded to the first chip through an array of flip-chip solder bumps. A semiconductor wafer. (Please read the α meanings on the back before filling this page.) ------------ Order ------ I-line Ministry of Economy Intellectual Property Bureau Employees Consumer Cooperatives printed this paper standard applicable to Chinese national standards (CNS ) A4 size (210 X 297 mm) 17 16069
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6921968B2 (en) 2003-05-02 2005-07-26 Advance Semiconductor Engineering, Inc. Stacked flip chip package
US7867818B2 (en) 2004-08-11 2011-01-11 Daewoong Suh Methods and apparatuses for providing stacked-die devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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