TW459315B - Stack-up chip packaging - Google Patents

Stack-up chip packaging Download PDF

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Publication number
TW459315B
TW459315B TW88105419A TW88105419A TW459315B TW 459315 B TW459315 B TW 459315B TW 88105419 A TW88105419 A TW 88105419A TW 88105419 A TW88105419 A TW 88105419A TW 459315 B TW459315 B TW 459315B
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TW
Taiwan
Prior art keywords
package
package substrate
substrate
patent application
item
Prior art date
Application number
TW88105419A
Other languages
Chinese (zh)
Inventor
Wen-Jiun Liou
Jian-Hung Lai
Jung-Jie Liou
Jeng-Ting Wu
Yi-Shiang Pan
Original Assignee
Walsin Advanced Electronics
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Priority to TW88105419A priority Critical patent/TW459315B/en
Priority to JP36328599A priority patent/JP2000299433A/en
Application granted granted Critical
Publication of TW459315B publication Critical patent/TW459315B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A kind of stack-up chip package can be used for the chip that is packaged completely. Each chip that is packaged completely is arranged in parallel with each other and is disposed in a stack-up manner. In addition, at the peripheral edge of package resin, solder ball or pin, and soldering point are used to electrically connect with each package substrate so as to form the stack-up chip package.

Description

經濟部中央標準局員工消費合作社印装 4593 15 A7 A7 4332txvf.d〇t/008 五、發明説明（I ) 本發明是有關於一種半導體封裝（Package)結構，且特 別是有關於一種堆疊式（Stack-Up)晶片封裝。 在半導體產業中，積體電路(Integrated Circuits, 1C)的 生產’主要分爲三個階段：矽晶片的製造、積體電路的製 作以及積體電路的封裝(Package)等。就積體電路的封裝而 言，此即是完成積體電路成品的最後步驟。封裝之目的在 於提供晶片（Die)與印刷電路板（Printed Circuit Board，PCB) 或其他適當元件之間電性連接的媒介及保護晶片。 在完成半導體製程後，晶片係由晶圓（Wafer)切割形 成。一般在晶片的周邊具有焊墊(Bonding Pad)，其作用爲 提供晶片檢測之測試點，以及提供晶片與其他元件間連接 之端點。爲了連接晶片和其他元件，因此必須使用導線 (Wire)或凸塊（Bump)作爲連接之媒介。 請參照第1圖，其所繪示的是以打線接合（Wire Bonding, WB)方式使單一晶片與外界進行電性連接。其中 係使用金線或鋁線等導線104以連接晶片100上之焊墊102 與外部元件。其次，請參照第2圖，其所繪示的是以捲帶 自動接合（Tape Automated Bonding, TAB)方式使單一晶片 與外界進行電性連接。其中是以凸塊（末顯示於圖中）作爲 晶片2〇0上的焊墊與捲帶晶片承載器之引腳202間的連接 媒介。然後，請參照第3圖，其所繪示的是以覆晶（Flip Chip， FC)方式使單一晶片與外界進行電性連接。在晶片300之 焊墊和電路基板的配線電極之間，係使用銲錫凸塊302進 行連接。 3 本紙浪尺皮逍用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注$項再填寫本頁) 訂 經濟部中央標準局貝工消費合作杜印装 459315 A7 433 2tw I'.dac/OOK 们 五、發明説明（飞，） 半導體晶片之封裝技術，早期是以插腳（Insertion Mount)方式，將晶片安裝於印刷電板進行封裝。近年來， 爲考量封裝基板之面積及因應電子產品輕、薄、短、小之 趨勢，已發展出多重晶片封裝（Multi-Chip Package, MCP) 技術。 對一般的半導體記憶體而言，如動態隨機存取記億體 (Dynamic Random Access Memory, DRAM) » 其晶片所使用 之封裝的方式，目前主要有小型J型外引腳封裝（Small Outline J-Lead, SOJ)，與小型外引腳封裝（Thin Small Outline Package, TSOP)兩種。 傳統之小型〗型外引腳封裝，係以打線接合之方式， 使用複數條導線電性連接基板表面之晶片與內引腳。再以 絕緣材料（如環氧樹脂Epoxy)包覆晶片、基板與內引腳進 行封裝，僅曝露出外引腳可與外界耦接。再利用表面黏著 技術（Surface Mounting Technology, SMT)，將封裝後之晶 片安裝於印刷電路板上，並使封裝之外引腳與印刷電路板 上之電路形成電性連接。由此可以製作一般所謂的單連線 5己憶體模組（Single In-Line Memory Module, SIMM)、雙連 線記憶體模組（Dual In-Line Memory Module, DIMM)或 Rambus 連線記憶體模組（Rambus In-Line Memory Module, RIMM)。然後將此晶片模組插入電腦等電器之電路基板的 插座（Socket)中，藉由模組基板中之金屬電極與電器基板 進行連接，完成模組之安裝。 此種習知之晶片模組，係先對晶片進行封裝，然後再 4 本紙張^^適用中關家^準（。叫八4«^(21〇\297公釐) (諳先閲讀背面之注意事項再填寫本頁) :士衣 訂 經濟部中央標準局員工消費合作社印製 d593 1 5 A7 4 3 3 21 w Γ. tf 〇c/00 8 g了 五、發明説明（、） 將封裝後的晶片安裝於印刷電路板上，才可使用，其製程 較爲繁瑣，且製造成本亦相對提高。此種晶片模組所使用 的封裝空間甚大’故不利於封裝密度的提昇，對日趨小型 化之電子產品而言’會有所限制。 因此，本發明提供--種堆疊式晶片封裝，應用於封裝 完成之晶片’以堆疊方式配置數個封裝完成之晶片，使其 彼此平行排列’再以焊接錫球（Solder Ball)或針腳（Pin)及 焊接點電性連接适些承載晶片之封裝基板（Substrate)，以 構成堆疊式晶片封裝。 根據本發明之上述及其他目的，提出一種堆疊式晶片 封裝，將數個封裝以彼此堆疊的方式形成。其中每一個封 裝均包括有晶片、封裝基板及封裝材料，晶片係配置於封 裝基板上，並由封裝材料所包覆。而各封裝基板之間係以 焊接錫球進行電性連接’或者是以針腳套接各封裝基板， 並利用焊接點電性連接針腳及封裝基板，達到電性連接各 封裝基板之目的’完成堆疊式晶片封裝。於堆疊式封裝整 體之外側封裝基板上，還具有由錫球所組成之球格陣列 (Bail Grid Array，BGA)，以提供堆疊式晶片封裝與其他電 路基板進行電性連接之媒介。以堆疊方式進行封裝，可提 高封裝密度。而封裝基板選用聚亞醯胺（P〇lyirnicie)軟板作 材料’則可縮減堆疊封裝之整體厚度，並降低封裝成品之 重量。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉較佳實施例，並配合所附圖式，作詳細 (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張λα適财關家榡準（CNS) Α4· (21()><297公董） 經濟部中央標準局負工消費合作社印製 4593 1 b A7Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4591 15 A7 A7 4332txvf.d〇t / 008 V. Description of the Invention (I) The present invention relates to a semiconductor package structure, and in particular to a stacked type ( Stack-Up) chip package. In the semiconductor industry, the production of integrated circuits (1C) is mainly divided into three stages: the manufacture of silicon wafers, the manufacture of integrated circuits, and the packaging of integrated circuits. As far as the packaging of integrated circuits is concerned, this is the final step to complete the finished integrated circuit. The purpose of packaging is to provide a medium for the electrical connection between the die and the printed circuit board (PCB) or other appropriate components and to protect the chip. After the semiconductor process is completed, the wafer is formed by wafer cutting. Generally, there are bonding pads on the periphery of the wafer, which are used to provide test points for wafer inspection and to provide endpoints for connections between the wafer and other components. In order to connect the chip and other components, wires or bumps must be used as the connection medium. Please refer to FIG. 1, which shows that a single chip is electrically connected to the outside by wire bonding (WB). Among them, a wire 104 such as a gold wire or an aluminum wire is used to connect the pad 102 on the chip 100 and an external component. Secondly, please refer to FIG. 2, which shows that a single chip is electrically connected to the outside by a Tape Automated Bonding (TAB) method. Among them, a bump (not shown in the figure) is used as a connection medium between the bonding pad on the wafer 200 and the pin 202 of the tape wafer carrier. Then, please refer to FIG. 3, which shows that a single chip is electrically connected to the outside by a flip chip (FC) method. The solder pads of the wafer 300 and the wiring electrodes of the circuit board are connected using solder bumps 302. 3 This paper uses Chinese National Standard (CNS) A4 specifications (210X297 mm) (please read the note on the back before filling out this page) Order the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Affairs Cooperation Du printed 459315 A7 433 2tw I'.dac / OOK 5. V. INTRODUCTION (Flying) The packaging technology of semiconductor wafers, in the early days, the chips were mounted on printed circuit boards for packaging by using the Insertion Mount method. In recent years, in order to consider the area of package substrates and respond to the trend of light, thin, short, and small electronic products, Multi-Chip Package (MCP) technology has been developed. For general semiconductor memory, such as Dynamic Random Access Memory (DRAM) »The packaging methods used for its chips are currently mainly small J-type outer pin packages (Small Outline J- Lead (SOJ), and Thin Small Outline Package (TSOP). The traditional small-size outer-lead package uses a wire bonding method to electrically connect the chip on the surface of the substrate and the inner leads using a plurality of wires. The chip, substrate and inner pins are then packaged with an insulating material (such as Epoxy), and only the outer pins can be exposed to be coupled to the outside. Surface mounting technology (SMT) is then used to mount the packaged wafer on the printed circuit board, and to make electrical connections between the pins outside the package and the circuits on the printed circuit board. This can be used to make the so-called Single In-Line Memory Module (SIMM), Dual In-Line Memory Module (DIMM), or Rambus connected memory. Module (Rambus In-Line Memory Module, RIMM). This chip module is then inserted into a socket of a circuit board of an electrical appliance such as a computer, and the metal electrode in the module substrate is connected to the electrical substrate to complete the module installation. This conventional chip module is to package the chip first, and then 4 papers ^^ applicable to Zhongguanjia ^ standard (. Called 8 4 «^ (21〇 \ 297 mm) (谙 Please read the note on the back first) Please fill in this page again for details): printed by d593 1 5 A7 4 3 3 21 w Γ. Tf 〇c / 00 8 g printed by the staff's consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. The chip is installed on a printed circuit board before it can be used. The manufacturing process is relatively tedious and the manufacturing cost is relatively high. The packaging space used by this chip module is very large, so it is not conducive to the improvement of packaging density, which is increasingly difficult to reduce For electronic products, there will be restrictions. Therefore, the present invention provides a stacked chip package, which is applied to a packaged wafer. 'Several packaged wafers are arranged in a stacked manner so that they are arranged in parallel with each other.' A solder ball or a pin and a solder joint are electrically connected to a package substrate suitable for carrying a chip to form a stacked chip package. According to the above and other objects of the present invention, a stacked chip package is proposed Several packages are formed on top of each other. Each package includes a chip, a package substrate, and a packaging material. The chip is disposed on the package substrate and is covered by the package material. The solder balls are electrically connected 'or the package substrates are socketed with pins, and the pins and the package substrate are electrically connected by using soldering points to achieve the purpose of electrically connecting the package substrates to complete the stacked chip package. In the stacked package The overall outer package substrate also has a Bail Grid Array (BGA) composed of solder balls to provide a medium for the electrical connection between the stacked chip package and other circuit substrates. Packages can be packaged in a stacked manner. Improve the packaging density. And the use of polyimide (Polyirnicie) soft board as the packaging substrate can reduce the overall thickness of the stacked package and reduce the weight of the packaged product. In order to allow the above and other objects, features, And advantages can be more obvious and easy to understand 'The following describes the preferred embodiment, and in conjunction with the attached drawings for details (please read the back Precautions to fill out this page) under this paper λα appropriate fiscal Kwan Su quasi (CNS) Α4 · (21 () > < 297 male directors) Ministry of Economic Affairs Bureau of Standards negative consumer cooperative work printed 4593 1 b A7

4 3 3 21 w ΐ'r d 〇 c/ 0{) S 五、發明説明（y ) 說明如下： 圖式之簡單說明： 第1圖繪示以打線接合方式使單一晶片與外界進行電 性連接； 第2圖繪示以帶狀自動接合方式使單一晶片與外界進 行電性連接； 第3圖繪示以覆晶方式使單一晶片與外界進行電性連 接； 第4A圖繪示依照本發明之第一實施例，一種堆疊式 晶片封裝之結構剖面示意圖； 第4B圖繪示依照本發明之第一實施例，另一種堆疊 式晶片封裝之結構剖面示意圖； 第5A圖繪示依照本發明之第一實施例，一種堆疊式 晶片封裝之封裝基板的下視圖； 第5B圖繪示依照本發明之第一實施例，另一種堆疊 式晶片封裝之封裝基板的下視圖； 第6A圖繪示依照本發明之第二實施例，一種堆疊式 晶片封裝之結構剖面示意圖； 第6B圖繪示依照本發明之第二實施例，另一種堆疊 式晶片封裝之結構剖面示意圖； 第6C圖繪示依照本發明之第二實施例，又一種堆疊 式晶片封裝之結構剖面示意圖； 第7A圖繪示依照本發明之第二實施例，一種堆疊式 晶片封裝之承載基板的上視圖； 6 (請先閱讀背面之注意事項再填寫本頁)4 3 3 21 w rd'rd 〇c / 0 {) S V. Description of the invention (y) The description is as follows: Brief description of the figure: Figure 1 shows a single chip electrically connected to the outside by wire bonding; FIG. 2 illustrates a single chip electrically connected to the outside by a strip-shaped automatic bonding method; FIG. 3 illustrates a single chip electrically connected to the outside by a flip-chip method; and FIG. 4A illustrates a first chip according to the present invention. An embodiment is a schematic cross-sectional view of a structure of a stacked chip package; FIG. 4B is a schematic cross-sectional view of a structure of a stacked chip package according to a first embodiment of the present invention; FIG. 5A is a first cross-sectional view of a structure of a stacked chip package according to the present invention; Embodiment, a bottom view of a package substrate of a stacked chip package; FIG. 5B illustrates a bottom view of a package substrate of another stacked chip package according to the first embodiment of the present invention; and FIG. 6A illustrates a package substrate according to the present invention The second embodiment is a schematic structural cross-sectional view of a stacked chip package; FIG. 6B is a schematic cross-sectional structural view of another stacked chip package according to a second embodiment of the present invention; FIG. 6C FIG. 7A is a schematic cross-sectional view showing a structure of a stacked chip package according to a second embodiment of the present invention; FIG. 7A is a top view of a carrier substrate of a stacked chip package according to the second embodiment of the present invention; (Read the notes on the back before filling out this page)

h1T 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 經濟部中央標率局員工消費合作社印裝 4593 1 5 Λ7 Α7 4 3 3 21 \ν Γ. d ο c / 〇 ϋ 8 五、發明説明（) 第7B圖繪示依照本發明之第二實施例，另一種堆疊 式晶片封裝之承載基板的上視圖； 圖式之標記說明： 100 ' 200、300、400、500 :晶片 102 :焊塾 104、405、505 :導線 202:引腳 3 02 :凸塊 402、502 :封裝樹脂 404、504 :第一封裝基板 406、506 :第二封裝基板 408 :焊墊 410 :焊接錫球 412、512 :球格陣列錫球 414 :晶片承載面 416、5 16 :錫球分佈面 508 :焊接點 510 :針腳 514 :封裝承載面 第一實施例 第4A圖與第4B圖分別繪示依照本發明之第一實施 例，不同的堆疊式晶片封裝之結構剖面示意圖。請參照第 4A圖與第4B圖，進行堆疊式晶片封裝時，首先提供分別 由晶片400、封裝樹脂402、第一封裝基板404及第二封 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐> (請先閱讀背面之注意事項再填寫本頁) 、1Τ Μ I. 經濟部中央標準局貝工消费合作社印裝 4593 1 5 4 …u'r.d。副 s ^ -_____ B7 _ 五、發明説明（c、） 裝基板4〇6所構成之晶片封裝。其中第一封裝基板4〇4例 如是球格陣列（BGA)封裝基板’其材質則包括陶瓷材料、 玻璃環氧基樹脂、雙順丁烯二酸醯亞胺（Bismaleimide_ Triazine，BT)樹脂、聚亞酸胺等，例如是陶瓷基板、以玻 璃環氧基樹脂爲材質之FR_4基板、以雙順丁烯二酸醯亞 胺樹脂爲材質之BT基板等；而第二封裝基板4〇6之材質 較佳的則是聚亞醯胺，這些封裝基板的上、下表面皆具有 電路圖案之導電層（未顯示於圖中）。 第一封裝基板4〇4中具有用以承載封裝晶片400之晶 片承載面414’和用以佈植球格陣列錫球412的錫球分佈 面416。此外在晶片承載面414之周緣還具有焊墊408， 用以和其他基板形成電性連接。而第二封裝基板4〇6之上、 下表面的周緣亦具有焊墊408 ’其功能亦是作爲與其他基 板進行電性連接之用。 如第4A圖及第4B圖所示’晶片400係分別貼附於 第一封裝基板4〇4之晶片承載面414以及第二封裝基板406 之表面，而晶片400與這些封裝基板之間的電性連接，例 如是以打線接合方式形成的導線405達到連接之目的，並 分別由封裝樹脂402所包覆構成晶片封裝’而每一個晶片 封裝中所封裝之晶片數目包括一個或一個以上。在第一封 裝基板4〇4與第二封裝基板406之間、以及各第二封裝基 板406之間，則佈植有焊接錫球410作爲中介物，用以連 接不同封裝基板之間的焊墊408,達到電性連接各晶片封 裝之目的。第4A圖中，於含球格陣列封裝基板404之晶 8 本紙張尺度適用中國國豕標準（CNS )八4規^ ( 210 X 297公羞） (請先閱讀背面之注意事項再填寫本頁) 訂 4 5 9 3 1 5 Α7 4332tuI doc/008 … 五、發明説明（/;) 片封裝上’僅堆疊單一個晶片封裝^然而在底部晶片封裝 上，亦可以堆疊方式疊覆數個晶片封裝，如第4B圖所示。 在堆疊式晶片封裝中，第一封裝基板404的錫球分佈 面416上，佈植有球格陣列錫球412，因而形成堆疊式球 格陣列（Stack-Up BGA)封裝，這些球格陣列錫球412係用 以作爲堆疊式晶片封裝整體與外部電路基板或其他元件之 間電性連接的媒介。 第5A圖與第5B圖分別繪示依照本發明之第一實施 例，不同的堆疊式晶片封裝之封裝基板的下視圖。如圖所 示，用以電性連接堆疊式晶片封裝內部各封裝基板之焊接 錫球410，係佈植於封裝基板406表面的焊墊(第4A及4B 圖中之408)上’位於包覆晶片400之封裝樹脂402的周圍 這些焊接錫球410係依據電性連接及接點數目之需求，而 呈不同型態之分佈，例如於封裝樹脂402外圍形成單層圏 狀分佈(如第5A圖），或多層圈狀分佈（如第5B圖）。然而 圖中所示之錫球分佈型態，係用以舉例說明本實施例，並 非用以限制本發明之範圍。 第二實施例 經濟部中央標準局員工消費合作社印装 (請先聞讀背面之注意事項再填寫本頁) 第6A圖至第6C圖分別繪示依照本發明之第二實施 例，不同的堆疊式晶片封裝之結構剖面示意圖。 請參照第6A圖，進行堆疊式晶片封裝時，首先提供 第一封裝基板504，例如是球格陣列封裝基板，其材質包 括陶瓷材料、玻璃環氧基樹脂、雙順丁烯二酸醯亞胺 (Bismaleimide-Triazine，BT)樹脂、聚亞釀胺等，例如是陶 9 本紙張尺度適用中國國家樣隼（CNS) Μ规格（2丨OX297公釐） 經濟部中央標準局貝工消費合作社印製 459315 , A7 4332n\ l'.d〇c/008 ------- B7 '— - ___ 五、發明説明（s) 瓷基板、以玻璃環氧基樹脂爲材質之FR-4基板、以雙順 丁烯二酸醯亞胺樹脂爲材質之BT基板等，較佳的材質是 陶瓷材料；以及由晶片500、封裝樹脂502及第二封裝基 板5〇6所構成之晶片封裝。其中第二封裝基板5〇6之材質 包括玻璃環氧基樹脂、雙順丁烯二酸醯亞胺樹脂、聚亞醯 胺等’而較佳的材質則是聚亞醯胺。而這些封裝基板的表 面具有電路圖案之導電層（未顯示於圖中）。 請參照第圖與第6C圖，與第—實施例之第4八及 4B圖類似’進行堆疊式晶片封裝時，提供分別由晶片5〇〇、 封裝樹脂502、第一封裝基板504及第二封裝基板5〇6所 構成之晶片封裝。其中第一封裝基板5〇4例如是球格陣列 封裝基板，其材質包括陶瓷材料、玻璃環氧基樹脂 '雙順 丁烯二酸醯亞胺（Bismaleimide-Triazine, BT)樹脂、聚亞酿 I女等，例如是陶瓷基板、以玻璃環氧基樹脂爲材皙之Fr_4 基板、以雙順丁烯二酸醯亞胺樹脂爲材質之BT基板等， 其較佳的材質是陶瓷材料；而第二封裝基板5〇6之材晳包 括玻璃環氧基樹脂、雙順丁烯二酸醯亞胺樹脂、聚亞醯胺 等’較佳的材質則是聚亞醯胺，這些封裝基板的表面具有 電路圖案之導電層（未顯示於圖中）。 如圖所示，第一封裝基板504中具有用以承載晶片或 晶片封裝和佈植針腳5 1 0之封裝承載面5 14，和用以佈植 球格陣列錫球5 1 2的錫球分佈面5 16。第6A圖中，晶片500 係貼附於第二封裝基板506之表面，而晶片5〇〇與第二封 裝基板5 0 6間之電性連接，例如是以打線接合方式形成的 10 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐] 叫 |_^--------^ 1 (請先閲讀背面之注意事項再填寫本頁)h1T This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm). It is printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 8 V. Description of the Invention (7) FIG. 7B shows a top view of a carrier substrate of another stacked chip package according to the second embodiment of the present invention; the description of the marks of the drawings: 100 '200, 300, 400, 500: Wafer 102: Solder pads 104, 405, 505: Wire 202: Pin 3 02: Bump 402, 502: Packaging resin 404, 504: First package substrate 406, 506: Second package substrate 408: Pad 410: Solder Solder balls 412, 512: Ball grid array solder balls 414: Wafer bearing surfaces 416, 5 16: Solder ball distribution surfaces 508: Solder joints 510: Pins 514: Package bearing surfaces The first embodiment is shown in Figures 4A and 4B. A schematic cross-sectional view showing the structure of different stacked chip packages according to the first embodiment of the present invention. Please refer to Figure 4A and Figure 4B. When stacking a chip package, first provide a chip 400, a packaging resin 402, a first package substrate 404, and a second package. 7 The paper size applies to China National Standard (CNS) A4 specifications (210X297mm > (Please read the notes on the back before filling out this page), 1Τ Μ I. Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4592 1 5 4… u'r.d. Vice s ^- _____ B7 _ 5. Description of the invention (c,) A wafer package composed of a mounting substrate 406. The first packaging substrate 404 is, for example, a ball grid array (BGA) packaging substrate. Its material includes ceramic materials and glass rings. Epoxy resin, bismaleimide triazine (BT) resin, polyimide, etc., for example, ceramic substrate, FR_4 substrate made of glass epoxy resin, bismaleimide Acid imidate resin is made of BT substrate, etc .; and the second package substrate 406 is better made of polyimide. The upper and lower surfaces of these package substrates have a conductive layer with a circuit pattern (not shown) (In the figure). First package substrate 40 It has a wafer supporting surface 414 'for carrying the packaged wafer 400 and a solder ball distribution surface 416 for mounting the ball grid array solder balls 412. In addition, there are solder pads 408 on the periphery of the wafer supporting surface 414 for other substrates. An electrical connection is formed. The peripheral edges of the upper and lower surfaces of the second package substrate 406 also have solder pads 408 ', which are also used for electrical connection with other substrates. As shown in Figures 4A and 4B It is shown that the wafer 400 is attached to the surface of the wafer supporting surface 414 of the first package substrate 404 and the surface of the second package substrate 406, and the electrical connection between the wafer 400 and these package substrates is, for example, wire bonding. The formed wires 405 achieve the purpose of connection, and are respectively covered with a packaging resin 402 to form a chip package. The number of chips packaged in each chip package includes one or more. In the first package substrate 404 and the second Between the package substrates 406 and between the second package substrates 406, solder balls 410 are planted as intermediaries to connect the bonding pads 408 between different package substrates to electrically connect the chip packages. Figure 4A, the crystal on the ball grid array package substrate 404 8 This paper size applies to China National Standard (CNS) Standard 8 4 ^ (210 X 297 public shame) (Please read the precautions on the back first Fill out this page again) Order 4 5 9 3 1 5 Α7 4332tuI doc / 008… 5. Description of the invention (/;) On the chip package 'only one single chip package is stacked ^ However, it can also be stacked on the bottom chip package. Several chip packages are shown in FIG. 4B. In a stacked chip package, a ball grid array solder ball 412 is planted on the solder ball distribution surface 416 of the first package substrate 404, thereby forming a stacked ball grid array ( Stack-Up BGA) packages. These ball grid array solder balls 412 are used as a medium for the electrical connection between the overall stack chip package and an external circuit substrate or other components. Figures 5A and 5B show the bottom views of the package substrates of different stacked chip packages according to the first embodiment of the present invention, respectively. As shown in the figure, the solder balls 410 for electrically connecting the package substrates inside the stacked chip package are placed on the bonding pads (408 in Figures 4A and 4B) on the surface of the package substrate 406 and are located on the cover. The solder balls 410 around the encapsulation resin 402 of the chip 400 are distributed in different types according to the requirements of electrical connection and the number of contacts. For example, a single-layer 圏 -shaped distribution is formed around the encapsulation resin 402 (as shown in FIG. 5A). ), Or multi-layered ring distribution (as shown in Figure 5B). However, the solder ball distribution pattern shown in the figure is used to illustrate this embodiment and is not intended to limit the scope of the present invention. The second embodiment is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). Figures 6A to 6C show different stacks according to the second embodiment of the present invention. Schematic cross-sectional view of a chip package. Please refer to FIG. 6A. When carrying out a stacked chip package, first provide a first package substrate 504, such as a ball grid array package substrate. The material includes ceramic material, glass epoxy resin, bismaleimide diimide (Bismaleimide-Triazine, BT) resin, polyurethane, etc. For example, the paper size 9 is applicable to the Chinese National Standard (CNS) M specification (2 丨 OX297 mm) Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy 459315, A7 4332n \ l'.d〇c / 008 ------- B7 '--___ V. Description of the invention (s) Porcelain substrate, FR-4 substrate made of glass epoxy resin, BT maleimide resin is a BT substrate made of a material such as BT substrate, and a preferable material is a ceramic material; and a chip package composed of a wafer 500, a packaging resin 502, and a second packaging substrate 506. Among them, the material of the second package substrate 506 includes glass epoxy resin, bismaleimide resin, polyimide, etc., and the preferred material is polyimide. The surface of these package substrates has a conductive layer with a circuit pattern (not shown in the figure). Please refer to FIG. 6 and FIG. 6C, which are similar to FIGS. 4A and 4B of the first embodiment. When performing a stacked wafer package, a wafer 500, a packaging resin 502, a first packaging substrate 504, and a second A chip package composed of a package substrate 506. The first package substrate 504 is, for example, a ball grid array package substrate, and the material includes ceramic material, glass epoxy resin 'bismaleimide-triazine (BT) resin, and polyurethane I Women, for example, are ceramic substrates, Fr_4 substrates made of glass epoxy resin, BT substrates made of bismaleimide resin, etc., and the preferred materials are ceramic materials; and The materials of the two packaging substrates 506 include glass epoxy resin, bismaleic acid imine resin, and polyimide. The preferred material is polyimide. The surface of these packaging substrates has The conductive layer of the circuit pattern (not shown). As shown in the figure, the first package substrate 504 has a package bearing surface 5 14 for carrying a wafer or a chip package and implanting pins 5 10, and a solder ball distribution for implanting a ball grid array solder ball 5 1 2 Face 5 16. In FIG. 6A, the chip 500 is attached to the surface of the second package substrate 506, and the electrical connection between the chip 500 and the second package substrate 506 is, for example, a 10-paper scale formed by wire bonding. Applicable to China National Standard (CNS) A4 specification (210X297mm) called | _ ^ -------- ^ 1 (Please read the precautions on the back before filling this page)

*1T A7 B7 4 5 9 3d1 5s 五、發明説明（7 ) 導線505進行連接，並由封裝樹脂5〇2所包覆形成晶片封 裝。而第6B及6C圖中，晶片5〇〇則是分別貼附於第一封 裝基板5〇4之封裝承載面以及第二封裝基板5〇6之表 面’與第6A圖相同，晶片500與這些封裝基板之間的電 性連接，例如是以打線接合方式形成的導線505完成連接， 並分別由封裝樹脂5〇2所包覆構成晶片封裝。而每一個晶 片封裝中所封裝之晶片數目包括一個或一個以上。配置於 封裝承載面514周緣之針腳510，係用以和第二封裝基板 5〇6套接，並以焊接點5〇8作爲媒介，於第二封裝基板506 與針腳510之間形成電性連接。第6Α圖中，係於球格陣 列封裝基板504上，堆疊數個晶片封裝。而第6Β及6C圖 中’則是於含球格陣列封裝基板5〇4之晶片封裝上，以堆 疊方式疊覆一個或數個晶片封裝。 與第一實施例相同，第一封裝基板5〇4的錫球分佈面 516上，具有球格陣列錫球512，用以作爲堆疊式晶片封 裝整體與其他元件間電性連接之媒介。 第7Α圖與第7Β圖分別繪示依照本發明之第二實施 例’不同的堆疊式晶片封裝之承載基板的上視圖。如圖所 示’用以套接堆疊式晶片封裝內部各封裝基板之針腳51〇， 係佈植於封裝基板504之封裝承載面的周緣，位於包覆晶 片500之封裝樹脂5〇2的周圍’迪由焊接點（第6Α至6C 圖中之508)連接針腳510及第二封裝基板，以達到電性連 接各封裝基板之目的。這些針腳510係依據電性連接及接 點數目之需求，而呈不同型態之分佈，例如於封裝樹脂5〇2* 1T A7 B7 4 5 9 3d1 5s 5. Description of the invention (7) The lead wire 505 is connected and covered with a sealing resin 502 to form a chip package. In FIGS. 6B and 6C, the wafer 500 is attached to the package bearing surface of the first package substrate 504 and the surface of the second package substrate 506, respectively. The same as in FIG. 6A, the wafer 500 and these The electrical connection between the package substrates is completed by, for example, wires 505 formed by wire bonding, and the chip packages are respectively covered with a packaging resin 502. The number of chips packaged in each chip package includes one or more. The pins 510 disposed on the periphery of the package bearing surface 514 are used to be socketed with the second package substrate 506, and the solder joint 508 is used as the medium to form an electrical connection between the second package substrate 506 and the pins 510. . In FIG. 6A, a plurality of chip packages are stacked on a ball grid array package substrate 504. In the 6B and 6C diagrams, ′ is on a wafer package containing a ball grid array package substrate 504, and one or several wafer packages are stacked in a stacked manner. Similar to the first embodiment, the solder ball distribution surface 516 of the first package substrate 504 has a ball grid array solder ball 512, which is used as a medium for the electrical connection between the stacked chip package as a whole and other components. FIG. 7A and FIG. 7B are top views of a carrier substrate of a different stacked chip package according to a second embodiment of the present invention, respectively. As shown in the figure, the pins 51 of the package substrates used to socket the stacked chip package are planted on the periphery of the package bearing surface of the package substrate 504 and located around the package resin 502 that covers the wafer 500. Di connects the pins 510 and the second package substrate with solder joints (508 in Figures 6A to 6C) to achieve the purpose of electrically connecting the package substrates. These pins 510 are distributed in different types according to the requirements of the electrical connection and the number of contacts, for example, in packaging resin 502

I I 本紙張尺度適用中國國家標準（CNS )八4*級（210X297公釐)' ' -- -----------' *------訂------^ I (請先聞讀背面之注意事項再填寫本頁) 經濟部中央橾準局負工消费合作社印製 /a on A7 B7 五、發明説明（，l ) 外圍形成單層圈狀分佈（如第7A圖），或多層圈狀分佈（如 第7B圖）。然而圖中所示之針腳分佈型態，係用以舉例說 明本實施例，並非用以限制本發明之範圍。 由上述本發明之較佳實施例可知，本發明可應用於已 封裝之晶片，將數個封裝以彼此疊覆的方式形成堆疊式晶 片封裝。其中使用表面覆有導線之軟板作爲封裝基板，由 於其厚度薄、重量輕，故可降低堆疊式晶片封裝之整體厚 度’並減輕封裝成品之重量。 本發明之特徵在於：各封裝基板之間使用焊接錫球進 行電性連接’或者是以針腳套接各封裝基板，並利用焊接 點電性連接針腳及封裝基板，達到電性連接各封裝基板之 目的’完成堆疊式晶片封裝。此外，於堆疊式封裝整體之 外側封裝基板上，還有錫球所組成之球格陣列，以提供堆 疊式晶片封裝與其他電路基板進行電性連接之媒介。 每一個封裝基板並不限於單一晶片的封裝，亦可進行 多個晶片的封裝；而將這些封裝彼此疊覆，則可進行三度 空間堆疊式晶片封裝。因此本發明可以提高封裝密度，符 合多重晶片模組封裝的趨勢，並提昇晶片模組之工作速 度’且可滿足電子產品微小化之需求。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍內’當可作各種之更動與潤飾’因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 本紙張认制中國國家 ----------衣------1 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局—工消費合作社印製II This paper size applies to China National Standard (CNS) Grade 8 * 4 (210X297mm) ''------------ '* ------ Order ------ ^ I (please read the notes on the back before filling out this page) Printed by the Central Consumers' Bureau of the Ministry of Economic Affairs / Consumer Cooperatives / a on A7 B7 V. Description of the invention (, l) A single-layer circle distribution is formed on the periphery (such as (Figure 7A), or multi-layered ring distribution (such as Figure 7B). However, the pin distribution pattern shown in the figure is used to illustrate the embodiment and is not intended to limit the scope of the present invention. According to the above-mentioned preferred embodiments of the present invention, it can be known that the present invention can be applied to a packaged wafer, and a plurality of packages are stacked to form a stacked wafer package. Among them, a flexible board with wires covered on its surface is used as the package substrate. Because of its thin thickness and light weight, the overall thickness of the stacked chip package can be reduced 'and the weight of the packaged product can be reduced. The present invention is characterized in that each package substrate is electrically connected using solder balls' or each package substrate is socketed with pins, and the pins and the package substrate are electrically connected by using soldering points to achieve the electrical connection of each package substrate Purpose 'to complete a stacked chip package. In addition, on the outer package substrate of the stacked package as a whole, there is a ball grid array composed of solder balls to provide a medium for the stacked chip package to be electrically connected to other circuit substrates. Each package substrate is not limited to a single chip package, and can also be packaged for multiple chips; and when these packages are stacked on top of each other, a three-dimensional stacking chip package can be performed. Therefore, the present invention can increase the packaging density, conform to the trend of multi-chip module packaging, and increase the working speed of the chip module ', and can meet the demand for miniaturization of electronic products. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention.' The scope of protection shall be determined by the scope of the attached patent application. This paper recognizes the country of China ---------- Clothing ------ 1 (Please read the notes on the back before filling this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs—Industrial and Consumer Cooperatives

Claims (1)

A8 B8 C8 D8 申請專利範圍 種堆疊式晶片封裝’至少包括： 經濟部中央揉隼局負工消费合作社印策 第一封裝基板’具有一晶片承載面； 第一封裝基板，與該第一封裝基板年行排列，並螂 曰曰片承載面位於該第一封裝基板之同側； 複數個晶片，分別配置於該晶片承載面及 基板之表面； _ 複數個封裝材料，分別配置於該晶片承載面及該第二 封裝基板之表面，並分別包覆該些晶片；以及 複數個焊接錫球，配置於該第一封裝基板與該第二封 裟基板之間，位於該晶片承載面之周緣，其中該第一封裝 基板與该第一封裝基板係以堆疊方式配置，並以該些焊接 錫球電性連接該第一封裝基板與該第二封裝基板。 2, 如申請專利範圍第1項所述之堆疊式晶片封裝，其 中該第二封裝基板之材質包括聚亞醯胺。 3. 如申請專利範圍第1項所述之堆疊式晶片封裝，其 中該第一封裝基板之材料係選自於由陶瓷材料、玻璃環氧 基樹脂、聚亞醯胺及雙順丁烯二酸醯亞胺所組成之族群中 的材料。 4·如申請專利範圍第丨項所述之堆疊式晶片封裝，其 中該第一封裝基板還具有一錫球分佈面。 5. 如申請專利範圍第4項所述之堆疊式晶片封裝，其 中還包括具有複數個錫球，配置於該錫球分佈面。 6. —種堆疊式晶片封裝，至少包括： 一第一封裝基板，具有一晶片承載面； 該 f請先閲讀背面之注^^項再填寫本頁} .裝. -锊_ 13 本紙張尺度逍用中國國家揉準（CNS ) A4規格（210x297公釐）A8 B8 C8 D8 Patent application scope Stacked chip packages 'at least include: The first package substrate' printed by the central government bureau of the Ministry of Economic Affairs and Consumer Cooperatives has a wafer bearing surface; a first package substrate, and the first package substrate It is arranged in rows, and the wafer bearing surface is located on the same side of the first package substrate; a plurality of wafers are respectively arranged on the wafer bearing surface and the surface of the substrate; _ a plurality of packaging materials are respectively arranged on the wafer bearing surface And the surface of the second package substrate, and respectively covering the wafers; and a plurality of solder balls disposed between the first package substrate and the second package substrate at a periphery of the wafer bearing surface, wherein The first package substrate and the first package substrate are configured in a stacked manner, and the first package substrate and the second package substrate are electrically connected by the solder balls. 2. The stacked chip package described in item 1 of the scope of patent application, wherein the material of the second package substrate includes polyimide. 3. The stacked chip package according to item 1 of the scope of patent application, wherein the material of the first package substrate is selected from the group consisting of ceramic materials, glass epoxy resins, polyimide, and bismaleic acid The material in the group consisting of fluorimine. 4. The stacked chip package according to item 丨 of the patent application scope, wherein the first package substrate further has a solder ball distribution surface. 5. The stacked chip package according to item 4 of the patent application scope, further comprising a plurality of solder balls arranged on the solder ball distribution surface. 6. — A stacked chip package, including at least: a first package substrate with a wafer bearing surface; please read the note ^^ on the back before filling in this page}. Packing.-锊 _ 13 This paper size Easy to use Chinese National Standard (CNS) A4 (210x297 mm) 申請專利範園 經濟部中央標率局貝工消费合作社印製 並跑!亥裝基板’與該第〜封裝基板平行排列’ 购位於該第—封裝基板之同側； 裝基板片’分_置於該晶片承糊及該些第二封 楼材料’㈣隨贿晶片承_及該些第 〜封^板之表面，並分別包覆該些晶片；以及 第壯丨断贿球’分_e置於該第-封裝基板與該些 基板之間，位於隨封裝材料之麗，其中該第 琴㈣5亥些第二封裝基板係以堆疊方式配置，並以 f k ϋ球難連賴第—雜難麵些第二封裝基 板。 _ 7·如申請_範圍帛6項所述之堆疊式晶片封裝，其 中該些第二封裝麵之材質包雜通胺。 —如申請專利範圍第6項所述之堆疊式晶片封裝’其 中該第一封裝基板之材料係選自於由陶瓷材料、玻璃環氧 基樹脂、聚亞醯胺及雙順丁烯二酸醯亞胺所組成之族群中 的材料。 9·如申請專利範圍第6項所述之堆疊式晶片封裝，其 中該第一封裝基板還具有一錫球分佈面。 10.如申請專利範圍第9項所述之堆疊式晶片封裝，其 中還包括具有複數個錫球，配置於該錫球分佈面。 11· —種堆疊式晶片封裝，至少包括： 複數個封裝，以堆疊方式配置平行排列；以及 複數個錫球，分別配置於該些封裝之間，位於該些封 Μ 本紙浪尺度適用中國國家標準（CNS ) Α4規格（210X 297公婕） ---------^------1Τ-------^ (請先閲讀背面之注意事項再填寫本筲) 經濟部中央標準局貝工消費合作社印製 ^59 3 1 5 A8 3 21\v Γ. doc/〇 〇 χ B8 C8 --- DS 六、申請專利範国 裝之周緣，用以電性連接該些封裝。 12.如申請專利範圍第Π項所述之堆疊式晶片封裝， 其中每一該些封裝中，還分別包括具有： 一封裝基板； —曰曰曰片’配置於該封裝基板上；以及 一封裝材料’配置於該封裝基板上，包覆該晶片。 Π如申請專利範圍第12項所述之堆疊式晶片封裝， 其中5亥封裝基板之材質包括聚亞醯胺。 14-一種堆疊式晶片封裝，至少包括： 一第—封裝基板，具有一封裝承載面； 一第〜封裝基板，與該第一封裝基板平行排列，並與 該封裝承載面位於該第一封裝基板之同側； 複數個晶片，分別配置於該封裝承載面及該第二封裝 基板之表面； 複數個封裝材料，分別配置於該封裝承載面及該第二 封裝基板之表面’並分別包覆該些晶片； 複數個針腳，配置於該封裝承載面之周緣，其中該第 一封裝基板與該第二封裝基板係以堆疊方式配置，並由該 些針腳與該第二封裝基板套接；以及 口 複數個焊接點，分別配置於該第二封裝基板與該些針 腳之間，用以電性連接該第二封裝基板、該些針腳與該第 一封裝基板。 I5‘如申請專利範圍第u項所述之堆疊式晶片封裝， 其中該第〜封裝基板之材料係選自於由陶瓷材料、玻璃環 15 ( CNS ) Α4ίΜ$- ( 210X297^ )___ ---------装------ΪΤ--------¾ t請先閲读背而之注意事項再填寫本育) 經濟部中央標準局貝工消費合作社印製 A8 B8 CS D8 申請專利範圍 氧基樹脂 中的材料 厶593 1 5 43-'2t^r.( 烯二酸醯亞胺所組成之族群 ^ =·如申請專利範圍第14項所述之堆疊式晶片封裝， :5 亥第二封裝基板之材料係選自於由玻璃環氧基樹脂' μ亞酿胺及雙順丁烯二酸醯亞胺所組成之族群中的材料。 ^ 如申請專利範圍第14項所述之堆疊式晶片封裝， /、中該第一封裝基板還具有一錫球分佈面。 ^ 3‘如申請專利範圍第Π項所述之堆疊式晶片封裝， 其中運包括具有複數個錫球，配置於該錫球分佈面。 19·〜種堆疊式晶片封裝，至少包括： 一第一封裝基板，具有一封裝承載面； 、複數個第二封裝基板，與該第一封裝基板平行排列’ 敢與該封裝承載面位於該第一封裝基板之同側； 複數個晶片’分別配置於該封裝承載面及該些第二封 裝基板之表面； —气=數個封裝材料，分別配置於該封裝承載面及該些第 一^裝基板之表面’並分別包覆該些晶片； 一土 =數個針腳，配置於該封裝承載面之周緣，其中該第 7*封裝基板與該些第二封裝基板係以堆疊方式配置，並由 該些針腳與該些第二封裝基板套接；以及 ,、複數個焊接點，分別配置於該些第二封裝基板與該些 針腳之間，用以電性連接該些第二封裝基板、該些針腳與 該第一封裝基板。 、 20.如申請專利範圍第I9項所述之堆疊式晶片封裝， (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 紡 A8 B8 CS D8 459315 4 3 3 21^ Γ, d in: /00 8 六、申請專利範圍 其中該第一封裝基板之材料係選自於由陶瓷材料、玻璃環 氧基樹脂、聚亞醯胺及雙順丁烯二酸醯亞胺所組成之族群 中的材料。 21. 如申請專利範圍第19項所述之堆疊式晶片封裝， 其中該第二封裝基板之材料係選自於由玻璃環氧基樹脂、 聚亞醯胺及雙順丁烯二酸醯亞胺所組成之族群中的材料。 22. 如申請專利範圍第I9項所述之堆疊式晶片封裝， 其中該第一封裝基板還具有一錫球分佈面。 23·如申請專利範圍第22項所述之堆疊式晶片封裝， 其中還包括具有複數個錫球，配置於該錫球分佈面。 24.—種堆疊式晶片封裝，至少包括： 一承載基板’具有一封裝承載面； 複數個封裝，以堆疊方式配置，與該承載基板平行排 列’並與該封裝承載面位於該承載基板之同側； 複數個針腳’配置於該封裝承載面之周緣，與該些封 裝套接；以及 複數個焊接點’配置於該些封裝與該些針腳之間，用 以電性連接該些封裝、該些針腳與該承載基板。 25_如申請專利範圍第24項所述之堆疊式晶片封裝， 其中該承載基板之材料係選自於由陶瓷材料、玻璃環氧基 樹脂、聚亞醯胺及雙順丁烯二酸醯亞胺所組成之族群中的 材料。 26.如申請專利範圍第24項所述之堆疊式晶片封裝， 其中每一該些封裝中，還分別包括具有： 本紙張尺度適用中國圃家標半（CNS > A4現格（210χ297公釐） (請先閏讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局貞工消費合作社印製 A B c D 4 593 1 5 4 3 3 21 \\ I\ d 〇 c / Ο Ο 8 六、申請專利範圍 一封裝基板； 一晶片，配置於該封裝基板上；以及 -一封裝材料，配置於該封裝基板上，包覆該晶片。 27. 如申請專利範圍第26項所述之堆疊式晶片封裝， 其中該封裝基板之材料係選自於由玻璃環氧基樹脂、聚亞 醯胺及雙順丁烯二酸醯亞胺所組成之族群中的材料。 28. 如申請專利範圍第24項所述之堆疊式晶片封裝， 其中該第承載基板還具有一錫球分佈面。 29. 如申請專利範圍第28項所述之堆疊式晶片封裝， 其中還包括具有複數個錫球，配置於該錫球分佈面。 ---------^------ΪΤ-------it (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標率局員工消費合作社印製 18 本紙張尺度適用中國國家標準（CNS ) A4说格（210><297公釐）Apply for a patent Fanyuan Ministry of Economic Affairs Central Standards Bureau Shellfish Consumer Cooperative Co., Ltd. printed and ran! Hai substrate is 'arranged in parallel with the ~ package substrate' purchased on the same side of the-package substrate; The wafer bearing paste and the second sealing materials are used to carry the bridging wafer bearing and the surfaces of the first to second sealing boards, and the wafers are respectively covered; It is placed between the first-package substrate and the substrates, and it is located with the packaging materials. Among them, the second package substrate and the second package substrate are arranged in a stacking manner, and the fk ball is difficult to be connected to the first-miscellaneous. Face some second package substrates. _7. The stacked chip package as described in the application_scope 申请 6, wherein the material of the second package surface is doped with amine. —The stacked chip package according to item 6 of the scope of the patent application, wherein the material of the first package substrate is selected from the group consisting of ceramic material, glass epoxy resin, polyimide, and bismaleic acid. Material in a group of imines. 9. The stacked chip package according to item 6 of the scope of patent application, wherein the first package substrate further has a solder ball distribution surface. 10. The stacked chip package according to item 9 of the patent application scope, further comprising a plurality of solder balls arranged on the solder ball distribution surface. 11. · A stacked chip package, including at least: a plurality of packages, arranged in a stack configuration in parallel; and a plurality of solder balls, respectively disposed between the packages, located between the packages. (CNS) Α4 Specification (210X 297 Gongjie) --------- ^ ------ 1Τ ------- ^ (Please read the notes on the back before filling in this card) Economy Printed by the Shell Standard Consumer Cooperative of the Ministry of Standards of the People's Republic of China ^ 59 3 1 5 A8 3 21 \ v Γ. Doc / 〇〇χ B8 C8 --- DS VI. The periphery of the patent application Fan Guozhuang, used to electrically connect these Package. 12. The stacked chip package according to item Π of the scope of patent application, wherein each of these packages further includes: a package substrate;-said chip is arranged on the package substrate; and a package The material 'is disposed on the package substrate and covers the wafer. Π The stacked chip package as described in item 12 of the scope of patent application, wherein the material of the 5H package substrate includes polyimide. 14- A stacked chip package comprising at least: a first-package substrate having a package bearing surface; a first-package substrate arranged in parallel with the first package substrate and located on the first package substrate with the package-bearing surface On the same side; a plurality of chips are respectively disposed on the surface of the package bearing surface and the second package substrate; a plurality of packaging materials are respectively disposed on the surface of the package bearing surface and the surface of the second package substrate 'and respectively cover the A plurality of pins; arranged at the periphery of the package bearing surface, wherein the first package substrate and the second package substrate are arranged in a stacking manner, and the pins are socketed with the second package substrate; and A plurality of solder joints are respectively disposed between the second package substrate and the pins, and are used to electrically connect the second package substrate, the pins and the first package substrate. I5 'The stacked chip package as described in item u of the scope of patent application, wherein the material of the ~~ package substrate is selected from ceramic materials, glass ring 15 (CNS) Α4ίΜ $-(210X297 ^) ___ --- ------ Equipment ------ ΪΤ -------- ¾ t Please read the precautions before filling in this education.) Printed by A8, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs B8 CS D8 Patent application materials in the oxy resin 5593 1 5 43-'2t ^ r. (The group consisting of sulfonium imine diimide ^ = · Stacked wafer as described in item 14 of the scope of patent application Package,: 5 The material of the second package substrate is a material selected from the group consisting of glass epoxy resin 'μmethylene amine and bismaleic acid imine. ^ If the scope of application for patent The stacked chip package according to item 14, wherein the first package substrate also has a solder ball distribution surface. ^ 3 'The stacked chip package according to item Π of the patent application scope, which includes a plurality of chip packages. A solder ball is disposed on the solder ball distribution surface. 19 · ~ stacked chip packages include at least: a first package substrate, Has a package bearing surface; a plurality of second package substrates arranged in parallel with the first package substrate; dare to be located on the same side of the first package substrate with the package bearing surface; a plurality of wafers are respectively arranged on the package bearing surface And the surfaces of the second packaging substrates;-gas = several packaging materials, respectively disposed on the packaging bearing surface and the surfaces of the first mounting substrates' and covering the wafers respectively; one soil = several pins , Arranged on the periphery of the package bearing surface, wherein the 7th * package substrate and the second package substrates are arranged in a stacking manner, and the pins are socketed with the second package substrates; and, The soldering points are respectively disposed between the second package substrates and the pins, and are used to electrically connect the second package substrates, the pins and the first package substrate. (Please read the precautions on the back before filling out this page)-Binding and ordering A8 B8 CS D8 459315 4 3 3 21 ^ Γ, d in: / 00 8 VI. Application scope Where the The material of a packaging substrate is a material selected from the group consisting of ceramic material, glass epoxy resin, polyimide, and bismaleimide. 21. If the scope of the patent application is the 19th item In the stacked chip package, the material of the second package substrate is a material selected from the group consisting of glass epoxy resin, polyimide, and bismaleimide. The stacked chip package according to item I9 of the patent application scope, wherein the first package substrate further has a solder ball distribution surface. 23. The stacked chip package according to item 22 of the patent application scope, further comprising a plurality of solder balls arranged on the solder ball distribution surface. 24. A stacked chip package, comprising at least: a carrier substrate 'having a package carrier surface; a plurality of packages arranged in a stacking manner and arranged in parallel with the carrier substrate' and located on the same substrate as the package carrier surface A plurality of pins are arranged on the periphery of the package bearing surface and are sleeved with the packages; and a plurality of solder joints are arranged between the packages and the pins for electrically connecting the packages, the These pins and the carrier substrate. 25_ The stacked chip package according to item 24 of the scope of patent application, wherein the material of the carrier substrate is selected from the group consisting of ceramic materials, glass epoxy resins, polyimide, and bismaleic acid. Material in the group of amines. 26. The stacked chip package as described in item 24 of the scope of patent application, each of these packages further includes: This paper size is applicable to the Chinese garden house standard (CNS > A4 present grid (210 x 297 mm) ) (Please read the notes on the reverse side before filling out this page) Order printed by the Zhengong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy AB c D 4 593 1 5 4 3 3 21 \\ I \ d 〇c / 〇 〇 8 6 The scope of the patent application is a package substrate; a wafer arranged on the package substrate; and-a packaging material arranged on the package substrate to cover the wafer. 27. The stacking type described in item 26 of the scope of patent application Chip package, wherein the material of the package substrate is a material selected from the group consisting of glass epoxy resin, polyimide and bismaleimide. 28. If the scope of application for a patent is 24 The stacked wafer package described in the above item, wherein the second carrier substrate further has a solder ball distribution surface. 29. The stacked wafer package described in item 28 of the scope of patent application, which further includes a plurality of solder balls arranged in the The solder ball distribution --------- ^ ------ ΪΤ ------- it (Please read the notes on the back before filling out this page) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 18 This paper size applies the Chinese National Standard (CNS) A4 standard (210 > < 297mm)
TW88105419A 1999-04-06 1999-04-06 Stack-up chip packaging TW459315B (en)

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TWI567904B (en) * 2013-03-06 2017-01-21 Win Semiconductors Corp A semiconductor wafer structure and a flip chip having a substrate through hole and a metal bump Stacked structure
TWI628724B (en) * 2016-01-15 2018-07-01 氣派科技股份有限公司 High-density integrated circuit package structure and integrated circuit

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KR100480908B1 (en) * 2001-12-28 2005-04-07 주식회사 하이닉스반도체 method for manufacturing stacked chip package
KR20080022452A (en) 2006-09-06 2008-03-11 삼성전자주식회사 Pop package and method of producing the same
JP5187735B2 (en) * 2008-01-29 2013-04-24 富士機械製造株式会社 BGA type semiconductor component mounting method and suction nozzle of component mounting machine
CN117457829A (en) * 2023-10-26 2024-01-26 深圳明阳电路科技股份有限公司 Embedded ceramic LED PCB chip and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI567904B (en) * 2013-03-06 2017-01-21 Win Semiconductors Corp A semiconductor wafer structure and a flip chip having a substrate through hole and a metal bump Stacked structure
TWI628724B (en) * 2016-01-15 2018-07-01 氣派科技股份有限公司 High-density integrated circuit package structure and integrated circuit

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