KR20030059459A - Chip stack package - Google Patents
Chip stack package Download PDFInfo
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- KR20030059459A KR20030059459A KR1020010088321A KR20010088321A KR20030059459A KR 20030059459 A KR20030059459 A KR 20030059459A KR 1020010088321 A KR1020010088321 A KR 1020010088321A KR 20010088321 A KR20010088321 A KR 20010088321A KR 20030059459 A KR20030059459 A KR 20030059459A
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- chip
- package
- flip chip
- printed circuit
- wiring board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로서, 보다 구체적으로는 두 개 이상의 집적회로 칩을 적층하여 하나의 패키지를 구성하는 칩 적층 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a chip stack package in which two or more integrated circuit chips are stacked to form one package.
반도체 산업에서 집적회로 칩에 대한 패키징(packaging) 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전하고 있다. 아울러, 전자 제품의 고성능화가 진행됨에 따라, 한정된 크기의 기판에 더 많은 수의 반도체 패키지를 실장하기 위한 노력들이 계속되고 있다. 이러한 노력의 일환으로 제안된 것이 하나의 패키지에 두 개 이상의 집적회로 칩을 내장하는 소위 멀티 칩 패키지(Multi Chip Package; MCP)이다.Packaging technology for integrated circuit chips in the semiconductor industry continues to evolve to meet the demand for miniaturization and mounting reliability. In addition, as the performance of electronic products increases, efforts are being made to mount a larger number of semiconductor packages on a limited size substrate. As part of this effort, what is proposed is a so-called Multi Chip Package (MCP), in which two or more integrated circuit chips are embedded in one package.
기존의 멀티 칩 패키지는 크기가 상대적으로 큰 집적회로 칩 위에 크기가 작은 집적회로 칩을 적층하는 구조가 일반적이며, 크기가 비슷한 두 칩의 경우에는 적층이 불가능하다. 또한, 웨이퍼 두께 문제 때문에 세 개 이상의 칩을 적층하기가 매우 힘들다.Conventional multi-chip packages generally have a structure in which a small integrated circuit chip is stacked on a relatively large integrated circuit chip, and stacking of two chips having similar sizes is impossible. In addition, stacking three or more chips is very difficult due to wafer thickness issues.
따라서, 본 발명은 상술한 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 크기가 비슷한 두 개 이상의 집적회로 칩을 적층하여 칩 적층 패키지를 구현하기 위한 것이다.Accordingly, the present invention has been made to solve the above-described problems of the prior art, an object of the present invention is to implement a chip stack package by stacking two or more integrated circuit chips of similar size.
도 1은 본 발명의 제1 실시예에 따른 칩 적층 패키지의 단면도이다.1 is a cross-sectional view of a chip stack package according to a first embodiment of the present invention.
도 2는 본 발명의 제2 실시예에 따른 칩 적층 패키지의 단면도이다.2 is a cross-sectional view of a chip stack package according to a second embodiment of the present invention.
도 3은 본 발명의 제3 실시예에 따른 칩 적층 패키지의 단면도이다.3 is a cross-sectional view of a chip stack package according to a third embodiment of the present invention.
도 4는 본 발명의 제4 실시예에 따른 칩 적층 패키지의 단면도이다.4 is a cross-sectional view of a chip stack package according to a fourth embodiment of the present invention.
도 5는 본 발명의 제5 실시예에 따른 칩 적층 패키지의 단면도이다.5 is a cross-sectional view of a chip stack package according to a fifth embodiment of the present invention.
도 6은 본 발명의 제6 실시예에 따른 칩 적층 패키지의 단면도이다.6 is a cross-sectional view of a chip stack package according to a sixth embodiment of the present invention.
도 7은 본 발명의 제7 실시예에 따른 칩 적층 패키지의 단면도이다.7 is a cross-sectional view of a chip stack package according to a seventh embodiment of the present invention.
도 8은 본 발명의 제8 실시예에 따른 칩 적층 패키지의 단면도이다.8 is a cross-sectional view of a chip stack package according to an eighth embodiment of the invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10, 20, 30, 40, 50, 60, 70, 80: 칩 적층 패키지(chip stack package)10, 20, 30, 40, 50, 60, 70, 80: chip stack package
11, 12, 21, 22, 32, 42, 61, 62, 72, 81, 82: 플립 칩 패키지(flip chip package)11, 12, 21, 22, 32, 42, 61, 62, 72, 81, 82: flip chip package
31, 41, 51, 52, 71: 베어 칩(bare chip)31, 41, 51, 52, 71: bare chip
13, 23, 63, 83: 테이프 배선 기판13, 23, 63, 83: tape wiring board
33, 43, 53, 73: 본딩 와이어(bonding wire)33, 43, 53, 73: bonding wire
14, 34, 44, 54, 64, 74, 84: 접착제(adhesive)14, 34, 44, 54, 64, 74, 84: adhesive
15, 25, 35, 45, 55, 65, 75, 85: 인쇄 회로 기판(printed circuit board)15, 25, 35, 45, 55, 65, 75, 85: printed circuit board
16, 26, 36, 46, 56, 66, 76, 86: 봉합제(encapsulant)16, 26, 36, 46, 56, 66, 76, 86: encapsulant
17, 27, 37, 47, 57, 67, 77, 87: 솔더 볼(solder ball)17, 27, 37, 47, 57, 67, 77, 87: solder balls
이러한 목적을 달성하기 위하여, 본 발명은 플립 칩 패키지, 베어 칩, 패드 재배열 칩 등과 테이프 배선 기판, 본딩 와이어 등을 적절히 활용하여 구현한 칩 적층 패키지를 제공한다.In order to achieve this object, the present invention provides a chip stack package implemented by using a flip chip package, a bare chip, a pad rearrangement chip, a tape wiring board, a bonding wire, and the like as appropriate.
본 발명에 따른 칩 적층 패키지는 하부면에 다수의 솔더 볼이 형성된 인쇄 회로 기판의 상부면에 크기가 비슷한 두 개 이상의 집적회로 칩이 적층되어 구성된다. 집적회로 칩으로서 플립 칩 패키지가 사용될 경우 테이프 배선 기판에 연결되거나 인쇄 회로 기판에 직접 연결되며, 베어 칩이나 패드 재배열 칩이 사용될 경우 본딩 와이어에 의하여 인쇄 회로 기판과 연결된다.The chip stack package according to the present invention is formed by stacking two or more integrated circuit chips of similar size on the top surface of a printed circuit board having a plurality of solder balls formed on the bottom surface thereof. When an integrated circuit chip is used, a flip chip package is connected to a tape wiring board or directly to a printed circuit board, and when a bare chip or a pad rearrangement chip is used, it is connected to a printed circuit board by a bonding wire.
또한, 본 발명에 따른 칩 적층 패키지는, 하부면에 다수의 솔더 볼이 형성된 인쇄 회로 기판의 상부면에 크기가 비슷한 두 개의 집적회로 칩을 적층하여 구성되며, 두 개의 집적회로 칩 중에서 하부 집적회로 칩은 플립 칩 패키지로 구성되어 크기가 비슷한 상부 집적회로 칩의 적층을 가능하게 한다.In addition, the chip stack package according to the present invention is configured by stacking two integrated circuit chips of similar size on the upper surface of a printed circuit board having a plurality of solder balls formed on the lower surface, the lower integrated circuit of the two integrated circuit chips The chip consists of a flip chip package to enable stacking of similarly sized upper integrated circuit chips.
이 경우, 상부 집적회로 칩은 플립 칩 패키지 또는 베어 칩으로 구성될 수 있다. 상부 집적회로 칩이 플립 칩 패키지로 구성되면, 상부 플립 칩 패키지와 하부 플립 칩 패키지 사이에 테이프 배선 기판이 개재되어 각각의 플립 칩 패키지 및 인쇄 회로 기판에 전기적으로 연결되거나, 상부 플립 칩 패키지와 하부 플립 칩 패키지 사이에 테이프 배선 기판이 개재되어 상부 플립 칩 패키지 및 인쇄 회로 기판에 전기적으로 연결되고, 하부 플립 칩 패키지가 직접 인쇄 회로 기판에 전기적으로 연결될 수 있다. 또한, 상부 집적회로 칩이 베어 칩으로 구성되면, 상부 베어 칩은 본딩 와이어에 의해 인쇄 회로 기판에 전기적으로 연결되며, 하부 플립 칩 패키지는 직접 인쇄 회로 기판에 전기적으로 연결될 수 있다.In this case, the upper integrated circuit chip may be configured as a flip chip package or a bare chip. When the upper integrated circuit chip is configured as a flip chip package, a tape wiring board is interposed between the upper flip chip package and the lower flip chip package to electrically connect the respective flip chip packages and the printed circuit board, or the upper flip chip package and the lower flip chip package. A tape wiring board may be interposed between the flip chip packages to electrically connect the upper flip chip package and the printed circuit board, and the lower flip chip package may be directly connected to the printed circuit board. In addition, when the upper integrated circuit chip is configured as a bare chip, the upper bare chip may be electrically connected to the printed circuit board by a bonding wire, and the lower flip chip package may be directly connected to the printed circuit board.
이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다. 첨부 도면에서 일부 구성요소는 도면의 명확한 이해를 돕기 위해 다소 과장되거나 개략적으로 도시되었음을 밝혀둔다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, it is to be noted that some of the components are somewhat exaggerated or schematically illustrated in order to facilitate a clear understanding of the drawings.
이하의 설명에서 사용되는 플립 칩 패키지(flip chip package)는 집적회로 칩의 본딩 패드(bonding pad)에 볼(ball) 또는 범프(bump)가 직접 형성되어 외부 접속 단자의 역할을 수행하는 단품 패키지 유형이며, 베어 칩(bare chip)은 볼이나 범프가 형성되지 않은 일반적인 집적회로 칩이다. 이는 본 발명이 속하는 기술분야에 잘 알려져 있으므로 자세한 설명을 생략한다.The flip chip package used in the following description is a single-piece package type in which a ball or bump is directly formed on a bonding pad of an integrated circuit chip to serve as an external connection terminal. A bare chip is a general integrated circuit chip in which balls or bumps are not formed. This is well known in the art to which the present invention pertains and will not be described in detail.
도 1은 본 발명의 제1 실시예에 따른 칩 적층 패키지의 단면도이다.1 is a cross-sectional view of a chip stack package according to a first embodiment of the present invention.
도 1을 참조하면, 제1 실시예에 따른 칩 적층 패키지(10)는 상부 플립 칩 패키지(11)와 하부 플립 칩 패키지(12)가 적층된 구조로 이루어지며, 상하부 플립 칩 패키지(11, 12) 사이에 테이프 배선 기판(13)이 개재된다. 테이프 배선 기판(13)의 상하부에는 각각 회로 패턴이 형성되어 있어서 상하부 플립 칩 패키지(11, 12)의 볼(또는 범프)과 물리적으로 접합되고 전기적으로 연결된다. 하부 플립 칩 패키지(12)의 뒷면은 인쇄 회로 기판(15)의 상부면에 접착제(14)로 고정되며, 테이프 배선 기판(13)은 인쇄 회로 기판(15)에 공지의 탭(TAB; Tape AutomatedBonding) 방식으로 연결된다. 인쇄 회로 기판(15)의 상부면에는 봉합제(16)가 형성되어 상하부 플립 칩 패키지(11, 12)와 테이프 배선 기판(13)을 보호하며, 하부면에는 칩 적층 패키지(10)의 외부 접속 단자가 되는 다수의 솔더 볼(17)이 규칙적으로 형성된다.Referring to FIG. 1, the chip stack package 10 according to the first embodiment has a structure in which an upper flip chip package 11 and a lower flip chip package 12 are stacked, and upper and lower flip chip packages 11 and 12 are stacked. ), The tape wiring board 13 is interposed. Circuit patterns are formed on the upper and lower portions of the tape wiring board 13 to be physically bonded and electrically connected to the balls (or bumps) of the upper and lower flip chip packages 11 and 12. The back side of the lower flip chip package 12 is fixed to the top surface of the printed circuit board 15 with an adhesive 14, and the tape wiring board 13 is a tape tab (TAB; Tape AutomatedBonding) known to the printed circuit board 15. ) Is connected in a way. An encapsulant 16 is formed on an upper surface of the printed circuit board 15 to protect the upper and lower flip chip packages 11 and 12 and the tape wiring board 13, and an external connection of the chip stack package 10 to the lower surface. A plurality of solder balls 17 serving as terminals are formed regularly.
본 발명의 칩 적층 패키지에 있어서, 하부 플립 칩 패키지는 제1 실시예와 달리 직접 인쇄 회로 기판에 전기적으로 연결할 수 있다. 도 2에 도시된 제2 실시예가 그 예이다.In the chip stack package of the present invention, the lower flip chip package may be electrically connected directly to the printed circuit board unlike the first embodiment. The second embodiment shown in FIG. 2 is an example.
도 2를 참조하면, 제2 실시예에 따른 칩 적층 패키지(20)는 상부 플립 칩 패키지(21)와 하부 플립 칩 패키지(22)가 적층된 구조로 이루어지며, 상하부 플립 칩 패키지(21, 22) 사이에 테이프 배선 기판(23)이 개재된다. 테이프 배선 기판(23)의 상부에는 회로 패턴이 형성되어 있어서 상부 플립 칩 패키지(21)의 볼(또는 범프)과 물리적으로 접합되고 전기적으로 연결된다. 하부 플립 칩 패키지(22)는 테이프 배선 기판(23)에 연결되지 않고 직접 인쇄 회로 기판(25)의 상부면에 전기적으로 연결된다. 이는 소위 플립 칩 본딩(flip chip bonding)으로 알려져 있다. 테이프 배선 기판(23)은 인쇄 회로 기판(25)에 공지의 탭(TAB) 방식으로 연결되고, 인쇄 회로 기판(25)의 상부면에 봉합제(26)가 형성되어 상하부 플립 칩 패키지(21, 22)와 테이프 배선 기판(23)을 보호하며, 하부면에 칩 적층 패키지(20)의 외부 접속 단자가 되는 다수의 솔더 볼(27)이 규칙적으로 형성된다.2, the chip stack package 20 according to the second embodiment has a structure in which an upper flip chip package 21 and a lower flip chip package 22 are stacked, and upper and lower flip chip packages 21 and 22. ), The tape wiring board 23 is interposed. A circuit pattern is formed on the tape wiring board 23 to be physically bonded and electrically connected to the balls (or bumps) of the upper flip chip package 21. The lower flip chip package 22 is electrically connected to the upper surface of the printed circuit board 25 directly rather than to the tape wiring board 23. This is known as flip chip bonding. The tape wiring board 23 is connected to the printed circuit board 25 in a known tab (TAB) manner, and an encapsulant 26 is formed on an upper surface of the printed circuit board 25 to form upper and lower flip chip packages 21, 22 and the tape wiring board 23 are protected, and a plurality of solder balls 27 serving as external connection terminals of the chip stack package 20 are regularly formed on the lower surface.
본 발명의 칩 적층 패키지에 있어서, 전술한 두 실시예에서의 상부 플립 칩 패키지는 베어 칩으로 대체할 수 있다. 도 3에 도시된 제3 실시예가 그 예이다.In the chip stack package of the present invention, the upper flip chip package in the above two embodiments may be replaced with a bare chip. The third embodiment shown in FIG. 3 is an example.
도 3을 참조하면, 제3 실시예에 따른 칩 적층 패키지(30)는 상부 베어 칩(31)과 하부 플립 칩 패키지(32)가 적층된 구조로 이루어지며, 상부 베어 칩(31)과 하부 플립 칩 패키지(32)는 뒷면을 맞대고 접착제(34)로 접합된다. 하부 플립 칩 패키지(32)는 제2 실시예와 마찬가지로 직접 인쇄 회로 기판(35)의 상부면에 전기적으로 연결되는 반면, 상부 베어 칩(31)은 본딩 와이어(33)에 의하여 인쇄 회로 기판(35)의 상부면에 전기적으로 연결된다. 전술한 실시예들과 마찬가지로, 인쇄 회로 기판(35)의 상부면에는 봉합제(36)가 형성되어 베어 칩(31)과 플립 칩 패키지(32)와 본딩 와이어(33)를 보호하며, 하부면에는 칩 적층 패키지(30)의 외부 접속 단자가 되는 다수의 솔더 볼(37)이 규칙적으로 형성된다.Referring to FIG. 3, the chip stack package 30 according to the third embodiment has a structure in which an upper bare chip 31 and a lower flip chip package 32 are stacked, and the upper bare chip 31 and the lower flip. The chip package 32 is bonded to the back with the adhesive 34. The lower flip chip package 32 is electrically connected to the upper surface of the direct printed circuit board 35 as in the second embodiment, while the upper bare chip 31 is connected to the printed circuit board 35 by the bonding wire 33. Is electrically connected to the top surface of the As in the above-described embodiments, an encapsulant 36 is formed on an upper surface of the printed circuit board 35 to protect the bare chip 31, the flip chip package 32, and the bonding wire 33. A plurality of solder balls 37 serving as external connection terminals of the chip stack package 30 are regularly formed.
본 발명의 칩 적층 패키지는, 전술한 실시예들과 달리, 세 개 이상의 집적회로 칩을 적층하여 구성할 수 있다. 이하 설명되는 실시예들이 그 예이다.Unlike the above-described embodiments, the chip stack package of the present invention may be configured by stacking three or more integrated circuit chips. The embodiments described below are examples.
도 4를 참조하면, 본 발명의 제4 실시예에 따른 칩 적층 패키지(40)는 상부 베어 칩(41)과 두 개가 나란히 배치된 하부 플립 칩 패키지(42)들이 적층된 구조로 이루어진다. 상부 베어 칩(41)과 하부 플립 칩 패키지(42)들은 뒷면을 맞대고 접착제(44)로 접합된다. 하부 플립 칩 패키지(42)들은 인쇄 회로 기판(45)의 상부면에 전기적으로 연결되고, 상부 베어 칩(41)은 본딩 와이어(43)에 의하여 인쇄 회로 기판(45)의 상부면에 전기적으로 연결된다. 인쇄 회로 기판(45)의 상부면에는 봉합제(46)가 형성되어 베어 칩(41)과 플립 칩 패키지(42)와 본딩 와이어(43)를 보호하며, 하부면에는 칩 적층 패키지(40)의 외부 접속 단자가 되는 다수의 솔더 볼(47)이 규칙적으로 형성된다.Referring to FIG. 4, the chip stack package 40 according to the fourth embodiment of the present invention has a structure in which the upper flip chip 41 and the lower flip chip packages 42 are disposed in parallel with each other. The upper bare chip 41 and the lower flip chip packages 42 are bonded back to each other with adhesive 44. The lower flip chip packages 42 are electrically connected to the upper surface of the printed circuit board 45, and the upper bare chip 41 is electrically connected to the upper surface of the printed circuit board 45 by the bonding wire 43. do. An encapsulant 46 is formed on an upper surface of the printed circuit board 45 to protect the bare chip 41, the flip chip package 42, and the bonding wire 43, and the lower surface of the chip stack package 40. A plurality of solder balls 47 serving as external connection terminals are formed regularly.
세 개 이상의 집적회로 칩을 적층할 때, 제4 실시예의 하부 플립 칩 패키지는 패드 재배열 칩으로 대체할 수 있다. 도 5에 도시된 제5 실시예가 그 예이다.When stacking three or more integrated circuit chips, the bottom flip chip package of the fourth embodiment can be replaced with a pad rearrangement chip. The fifth embodiment shown in FIG. 5 is an example.
도 5를 참조하면, 본 발명의 제5 실시예에 따른 칩 적층 패키지(50)는 상부 베어 칩(51)과 두 개가 나란히 배치된 하부의 패드 재배열 칩(52)들이 적층된 구조로 이루어진다. 패드 재배열 칩(52)은 통상적으로 칩 상부면 중앙이나 양쪽 가장자리에 형성되는 본딩 패드가 한쪽 가장자리로 재배치(redistribution)된 집적회로 칩을 말한다. 상부 베어 칩(51)과 하부 재배열 칩(52)들은 각각 상부를 향하며, 각각의 뒷면은 접착제(54)에 의하여 하부 재배열 칩(52)의 상부면 또는 인쇄 회로 기판(55)의 상부면에 접합된다. 각각의 칩(51, 52)들은 본딩 와이어(53)에 의하여 인쇄 회로 기판(55)의 상부면에 전기적으로 연결되고, 봉합제(56)에 의하여 보호된다. 인쇄 회로 기판(55)의 하부면에는 칩 적층 패키지(50)의 외부 접속 단자가 되는 다수의 솔더 볼(57)이 규칙적으로 형성된다.Referring to FIG. 5, the chip stack package 50 according to the fifth embodiment of the present invention has a structure in which upper pads 51 and lower pad rearrangement chips 52 arranged in parallel with each other are stacked. The pad rearrangement chip 52 generally refers to an integrated circuit chip in which bonding pads formed at the center or both edges of the chip top surface are redistributed to one edge. The upper bare chip 51 and the lower rearrangement chips 52 face upwards, respectively, and each back side is by an adhesive 54 the upper side of the lower rearrangement chip 52 or the upper side of the printed circuit board 55. Is bonded to. Each chip 51, 52 is electrically connected to the top surface of the printed circuit board 55 by a bonding wire 53 and protected by an encapsulant 56. On the lower surface of the printed circuit board 55, a plurality of solder balls 57 serving as external connection terminals of the chip stack package 50 are regularly formed.
한편, 칩 적층 패키지를 구성하는 집적회로 칩을 모두 플립 칩 패키지로 사용할 수도 있다. 도 6에 도시된 제6 실시예가 그 예이다.Meanwhile, all integrated circuit chips constituting the chip stack package may be used as flip chip packages. The sixth embodiment shown in FIG. 6 is an example.
도 6을 참조하면, 본 발명의 제6 실시예에 따른 칩 적층 패키지(60)는 상부 플립 칩 패키지(61)와 두 개가 나란히 배치된 하부 플립 칩 패키지(62)들이 적층된 구조로 이루어진다. 상하부 플립 칩 패키지(61, 62)들은 뒷면을 맞대고 접착제(64)로 접합된다. 상부 플립 칩 패키지(61)은 테이프 배선 기판(63)과 전기적으로 연결되며, 하부 플립 칩 패키지(62)들은 직접 인쇄 회로 기판(65)의 상부면에 전기적으로 연결된다. 테이프 배선 기판(63)은 인쇄 회로 기판(55)에 공지의 탭(TAB) 방식으로 연결되고, 인쇄 회로 기판(65)의 상부면에 봉합제(66)가 형성되어 상하부 플립 칩 패키지(61, 62)와 테이프 배선 기판(63)을 보호하며, 하부면에 칩 적층 패키지(60)의 외부 접속 단자가 되는 다수의 솔더 볼(67)이 규칙적으로 형성된다.Referring to FIG. 6, the chip stack package 60 according to the sixth embodiment of the present invention has a structure in which the upper flip chip package 61 and the lower flip chip package 62 in parallel with each other are stacked. The upper and lower flip chip packages 61 and 62 are bonded to each other with adhesive 64. The upper flip chip package 61 is electrically connected to the tape wiring board 63, and the lower flip chip packages 62 are directly connected to the upper surface of the printed circuit board 65. The tape wiring board 63 is connected to the printed circuit board 55 in a known tab (TAB) manner, and an encapsulant 66 is formed on an upper surface of the printed circuit board 65 to form upper and lower flip chip packages 61. 62 and the tape wiring board 63 are protected, and a plurality of solder balls 67 are formed on the lower surface of the chip stack package 60 to be external connection terminals.
그 밖에, 네 개 이상의 집적회로 칩들을 사용하여 본 발명의 칩 적층 패키지를 구성할 수도 있다. 도 7에 도시된 제7 실시예의 경우 네 개의 집적회로 칩을, 도 8에 도시된 제8 실시예의 경우 여섯 개의 집적회로 칩을 사용하는 예이다.In addition, the chip stack package of the present invention may be configured using four or more integrated circuit chips. In the seventh embodiment shown in FIG. 7, four integrated circuit chips are used. In the eighth embodiment shown in FIG. 8, six integrated circuit chips are used.
도 7을 참조하면, 본 발명의 제7 실시예에 따른 칩 적층 패키지(70)는 인쇄 회로 기판(75)의 상부면에 플립 칩 본딩된 두 개의 하부 플립 칩 패키지(72)와, 그 위에 접착제(74)에 의하여 접합되고 본딩 와이어(73)에 의하여 인쇄 회로 기판(75)에 연결된 두 개의 상부 베어 칩(71)의 적층 구조로 이루어진다. 봉합제(76)와 솔더 볼(77)은 전술한 예들과 동일하다.Referring to FIG. 7, the chip stack package 70 according to the seventh embodiment of the present invention includes two lower flip chip packages 72 flip chip bonded to an upper surface of a printed circuit board 75, and an adhesive thereon. It consists of a laminated structure of two upper bare chips 71 bonded by 74 and connected to a printed circuit board 75 by a bonding wire 73. Encapsulant 76 and solder ball 77 are the same as the examples described above.
도 8을 참조하면, 본 발명의 제8 실시예에 따른 칩 적층 패키지(80)는 인쇄 회로 기판(85)의 상부면에 두 개의 플립 칩 패키지(82)가 플립 칩 본딩되고, 그 위에 두 개의 플립 칩 패키지(82)가 접착제(84)에 의하여 접합되며, 테이프 배선 기판(83)을 개재하여 다시 두 개의 플립 칩 패키지(81)가 연결되는 적층 구조로 이루어진다. 테이프 배선 기판(83)은 인쇄 회로 기판(85)에 연결되며, 봉합제(86)와 솔더 볼(87)은 전술한 예들과 동일하다.Referring to FIG. 8, in the chip stack package 80 according to the eighth embodiment of the present invention, two flip chip packages 82 are flip-chip bonded to an upper surface of a printed circuit board 85, and two chip stack packages 80 are flip chip bonded thereon. The flip chip package 82 is bonded by an adhesive 84, and is formed in a laminated structure in which two flip chip packages 81 are connected again via a tape wiring board 83. The tape wiring board 83 is connected to the printed circuit board 85, and the encapsulant 86 and the solder ball 87 are the same as the examples described above.
이상 설명한 바와 같이, 본 발명은 플립 칩 패키지, 베어 칩, 패드 재배열 칩 등과 테이프 배선 기판, 본딩 와이어 등을 적절히 활용함으로써 크기가 비슷한집적회로 칩을 적층한 칩 적층 패키지를 구현할 수 있다. 또한, 플립 칩 패키지를 사용하는 경우 전기적 특성이 향상되며, 기존의 볼 그리드 어레이(ball grid array; BGA) 패키지 생산 시설을 활용할 수 있다.As described above, the present invention can implement a chip stack package in which integrated circuit chips having similar sizes are stacked by appropriately utilizing a flip chip package, a bare chip, a pad rearrangement chip, a tape wiring board, and a bonding wire. In addition, when the flip chip package is used, the electrical characteristics are improved, and an existing ball grid array (BGA) package production facility may be utilized.
본 명세서와 도면에는 본 발명의 바람직한 실시예에 대하여 개시하였으며, 비록 특정 용어들이 사용되었으나, 이는 단지 본 발명의 기술 내용을 쉽게 설명하고 발명의 이해를 돕기 위한 일반적인 의미에서 사용된 것이지, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예 외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명한 것이다.In the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms have been used, these are merely used in a general sense to easily explain the technical contents of the present invention and to help the understanding of the present invention. It is not intended to limit the scope. It is apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.
Claims (6)
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| KR1020010088321A KR100808582B1 (en) | 2001-12-29 | 2001-12-29 | Chip stack package |
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| KR1020010088321A KR100808582B1 (en) | 2001-12-29 | 2001-12-29 | Chip stack package |
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|---|---|---|---|
| KR1020010088321A KR100808582B1 (en) | 2001-12-29 | 2001-12-29 | Chip stack package |
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| KR (1) | KR100808582B1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100651125B1 (en) * | 2005-03-21 | 2006-12-01 | 삼성전자주식회사 | Double molded multi chip package and manufacturing method thereof |
| KR100912427B1 (en) * | 2006-10-23 | 2009-08-14 | 삼성전자주식회사 | Stacked chip package and method for forming thereof |
| WO2019040203A1 (en) * | 2017-08-24 | 2019-02-28 | Micron Technology, Inc. | Hybrid additive structure stackable memory die using wire bond |
| CN110444527A (en) * | 2019-07-23 | 2019-11-12 | 中国科学技术大学 | A kind of chip-packaging structure, device and method |
| US10593568B2 (en) | 2017-08-24 | 2020-03-17 | Micron Technology, Inc. | Thrumold post package with reverse build up hybrid additive structure |
| US11037910B2 (en) | 2017-08-24 | 2021-06-15 | Micron Technology, Inc. | Semiconductor device having laterally offset stacked semiconductor dies |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102605617B1 (en) | 2016-11-10 | 2023-11-23 | 삼성전자주식회사 | Stacked semiconductor package |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100533847B1 (en) * | 1999-08-09 | 2005-12-07 | 삼성전자주식회사 | Stacked flip chip package using carrier tape |
| KR100401019B1 (en) * | 1999-12-30 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | semiconductor package and its manufacturing method |
| KR100610917B1 (en) * | 2000-06-12 | 2006-08-09 | 앰코 테크놀로지 코리아 주식회사 | Wire bonding structure between semiconductor chip and substrate, and semiconductor package using it, and manufacturing method of the same |
-
2001
- 2001-12-29 KR KR1020010088321A patent/KR100808582B1/en not_active IP Right Cessation
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100651125B1 (en) * | 2005-03-21 | 2006-12-01 | 삼성전자주식회사 | Double molded multi chip package and manufacturing method thereof |
| KR100912427B1 (en) * | 2006-10-23 | 2009-08-14 | 삼성전자주식회사 | Stacked chip package and method for forming thereof |
| US7638365B2 (en) | 2006-10-23 | 2009-12-29 | Samsung Electronics Co., Ltd. | Stacked chip package and method for forming the same |
| WO2019040203A1 (en) * | 2017-08-24 | 2019-02-28 | Micron Technology, Inc. | Hybrid additive structure stackable memory die using wire bond |
| US10593568B2 (en) | 2017-08-24 | 2020-03-17 | Micron Technology, Inc. | Thrumold post package with reverse build up hybrid additive structure |
| CN111033732A (en) * | 2017-08-24 | 2020-04-17 | 美光科技公司 | Stackable memory die using hybrid addition structure of wire bonds |
| US11037910B2 (en) | 2017-08-24 | 2021-06-15 | Micron Technology, Inc. | Semiconductor device having laterally offset stacked semiconductor dies |
| US11929349B2 (en) | 2017-08-24 | 2024-03-12 | Micron Technology, Inc. | Semiconductor device having laterally offset stacked semiconductor dies |
| CN110444527A (en) * | 2019-07-23 | 2019-11-12 | 中国科学技术大学 | A kind of chip-packaging structure, device and method |
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| Publication number | Publication date |
|---|---|
| KR100808582B1 (en) | 2008-02-29 |
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