KR20010063032A - Stack-up package frame - Google Patents

Abstract

PURPOSE: A stack-up package frame is provided to improve a degree of integration of a package by providing a stack-up package. CONSTITUTION: A stack-up package frame(430a) includes the first package substrate(404). A chip holding surface(414) is formed on the first package substrate(404). The second package substrate(406) is laminated on the first package substrate(404). One or more chips(400) are located at the chip holding surface(414) and the second package substrate(406). The first package substrate(404) has a solder holding surface(416). The stack-up package frame(430a) has a plurality of ball-grid array solder balls(412) connected with the solder holding surface(416). The chip holding surface(414) and the second package substrate(406) include a plurality of ball pads(408). The ball pads(408) are located at the substrates(404,406).

Description

Stack-Up Package Frames {STACK-UP PACKAGE FRAME}

The present invention relates to a semiconductor package frame, and more particularly to a stack-up package frame.

Fabrication of integrated circuit (IC) products includes (1) preparing semiconductor wafers; (2) forming circuit elements such as a metal-oxide-semiconductor transistor and a multi-level interconnector on the wafer; And (3) packaging the manufactured chips as the final step of forming the IC products. By packaging the chips, damage to the wafer can be prevented. The package serves as an intermediary for the electrical connection between the chips of the wafer and a printed circuit board (PCB) or other devices.

In manufacturing IC products, the wafer is divided into a plurality of chips. The chips are each wrapped in a bonding pad. The bonding pad is used as a test point in wafer testing. In addition, the bonding pad is connected to a terminal for electrically connecting the chip with the chip.

At this time, there must be a plurality of wires or bumps connecting the chip and the medium for electrically connecting the chip.

As shown in FIG. 1, the chip 100 is electrically connected to external chips by wire bonding (“WP”). In particular, the chip is electrically connected to the outside by using the gold line 104 or the aluminum line to connect the bonding pads of the chip 100 and the external circuits.

As shown in FIG. 2, the chip 200 is electrically connected to external chips by tape automated bonding (“TAB”). 2, bumps (not shown in the figure) are provided as a medium for connecting between the bonding chip pad and the leads 202 of the tape wafer carrier.

As shown in FIG. 3, the chip 300 is electrically connected to the external chips by a flip chip (“FC”) method. A plurality of solder bumps 302 are used as a medium for connecting between the bonding pads of the chip 300 and the adaptive electrodes of the circuit board.

In the prior art, chips are mounted on a PCB for a package. In recent years, multi-chip package ("MCP") technology has been developed to reduce the overall size of the packaged products to be as small as possible.

In a typical semiconductor device such as dynamic random access memory (DRAM), the chips are usually packaged by small outline J-lead (SOJ) technology or thin small outline package (TSOP).

In the SOJ technique, chips on a substrate are electrically connected to an inline lead by a plurality of conductive lines. Some insulation materials, such as epode resins, may be used to cover the chip, substrate, and inline leads to make a package. Outline leads are exposed and electrically connected to external devices. The package chips are mounted on a PCB by surface mounting technology ("SMT"). In the SMT, the outline lead of the package and the circuit of the PCB are electrically connected to each other.

Chip modules, such as single inline memory modules ("SIMMs"), dual inline memory modules ("DIMMs"), or rambus inline memory modules ("RIMMs"), It can be manufactured using the techniques mentioned above. The chip module is inserted into a socket of a circuit board. The circuit board is mounted in an electronic device such as a computer. The inserted chip module is installed by connecting the metal electrode of the chip module and the substrate of the electronic device.

The manufacture of the chip module includes a first packaging step for the chip and mounting the chip on the PCB. The process is complex and expensive. In addition, since the chip module is large, it is difficult to increase the package density. As a result, many microelectronic product developments have limitations.

An object of the present invention to solve the above-mentioned problems is to provide a stack-up package frame for improving the package density.

1 shows a chip electrically connected to external circuits by wire bonding;

2 shows a chip electrically connected to external circuits by tape automated bonding (" TAB ");

3 shows a chip electrically connected to external circuits by a flip chip ("FC") method;

4A is a cross-sectional view schematically showing one stack-up package frame according to the first embodiment of the present invention;

4B is a cross-sectional view schematically showing another stack-up package frame according to the first embodiment of the present invention;

5A is a plan view showing one stack-up BGA package frame according to the first embodiment of the present invention;

5B is a plan view showing another stack-up BGA package frame according to the first embodiment of the present invention;

6A is a schematic cross-sectional view of one stack-up package frame according to a second embodiment of the present invention;

6B is a cross-sectional view schematically showing another stack-up package frame according to the second embodiment of the present invention;

6C is a cross-sectional view of another stack-up package frame according to the second embodiment of the present invention;

7A is a plan view showing one stack-up BGA package frame according to the second embodiment of the present invention; And

7B is a plan view showing another stack-up BGA package frame according to the second embodiment of the present invention.

The stack-up package frame includes a first package substrate having chips that act as chip supporters to hold surfaces on the substrate. At least one second package substrate is laminated on the first package substrate in parallel. A plurality of chips is located on the chip and the second package substrate holding the substrate. A plurality of package materials, such as a first package resin and a second package resin, are respectively located on the chip holding the substrate and on the second package substrate for converting the chips. A plurality of conductors such as solder balls or pins are positioned between the first package substrate and the second package substrate to surround the chip holding the substrate. At this time, the first package substrate is electrically connected to the second package substrate by the conductor such as solder balls or pins so as to be connected between the chips on the other film of the first and the second package substrate. In general, the conductors that are not in contact with package materials belonging to the underlayer of the substrates verify that a mechanical supporting object holds the second package substrate.

The first package substrate is a ceramic material, an epoxy-glass fabric composite resin, a bismaleimidetriazine resin, a polyimide, and their It is formed with either mixture. The second package substrate is usually formed of the polyimide resin.

Using the stack-up package frames according to the invention, many packages can be stacked on each other in a three dimensional arrangement. Thus, the stack-up package frame is a multi-chip module that increases the package density and the operating time of the chip module. In addition, the thickness and weight of the stack-up package frames are reduced by using a package substrate formed of a light material such as polyimide.

It is obvious that both the foregoing general description and the following detailed description are merely exemplary, and are not intended to limit the invention, including the claims.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)

4A and 4B are cross-sectional views schematically showing two different stack-up package frames according to the first embodiment of the present invention.

As shown in FIG. 4A, the stack-up package frame 430a includes a first package substrate 404. The first package substrate 404 has a chip holding surface 414 formed thereon that acts as a chip supporter. The second package substrate 406 is stacked in parallel on the first package substrate 404. At least one chip 400 is positioned on the chip holding surface 414 and the second package substrate 406. The chips 400 are each of the first package substrate 404 and the second package substrate ( 406) and electrically connected (by wiring, TAB or bump). A plurality of package materials, such as a first package resin 402 and a second package resin 402a, are respectively disposed on the chip holding surface 414 and the second package substrate 406 to cover the chips 400. Located. A plurality of conductive objects 410, such as solder balls 410, are positioned on the chip holding surface 414 between the first package substrate 404 and the second package substrate 406 to provide the first package. Surround the resin 402. The conductive objects 410 serve as a supporting structure for holding the second package substrate 406, and the second package substrate 406 according to a desired connection scheme for the first package substrate 404. Electrical connection. Because of the conductive objects 410, the second package substrate 406 is usually not in contact with the first package resin 402.

The first package substrate 404 is, for example, a ceramic material, epoxy-glass tissue synthetic resin (FR-4, FR-5), bismaleimidetriazine resin (BT), polyimide, and these It is formed of any one of the mixtures. On the other hand, the second package substrate 406 is preferably formed of the polyimide. The substrates 404 and 406 have electrical circuit patterns (not shown in the figure) located on their upper and lower surfaces, respectively.

The first package substrate 404 further includes the solder holding surface 416. The stack-up frame 430a further includes a plurality of solder balls, such as ball-grid array solder balls 412 connected to the solder holding surface 416. The ball-grid array solder balls 412 are a medium for electrically connecting the stack-up package frame 430a and other circuit boards.

The chip holding surface 414 and the second package substrate 406 further include a plurality of bull pads 408. Several ball pads 408 are located on the substrates 404, 406, usually at the brim of the substrates 404, 406. Several of the ball pads 408 are also located on the top and bottom surfaces of the second package 406 for electrically connecting subsequent second package substrates 406, as will be discussed in detail later.

The following summarizes the general features of FIG. 4A. The first package substrate 404, the first package resin 402 adjacent to the first package substrate 404, and the chips 400 covered by the first package resin 402 are first together. It acts as a package 407. The chips 400 covered by the second package substrate 406, the second package resin 402a adjacent to the second package substrate 406, and the second package resin 406 are second together. It acts as a package 409a. The packages 407 and 409a each include at least one chip 400.

The stack-up package frame 430a further includes a plurality of solder balls 410. In order to electrically connect the first package 470 and the second package 409a, the solder balls 410 are ball pads of the first package substrate 404 and the second package substrate 406. 408 is located between.

The stack-up package frame 430a including the ball-grid array solder balls 412 acts as a stack-up ball-grid array (BGA) package frame. The ball-grid array solder balls 412 connected to the solder ball holding surface 416 of the first package substrate 404 connect the stack-up package frame 430a and external circuit boards (not shown). It acts as a medium for making electrical connections.

The structure of FIG. 4A can be applied to further have a stack-up structure. As shown in FIG. 4B, one or more packages 409b that are substantially identical to the second package 409a are sequentially positioned on the second package 409a in the same manner as the second package 409a. . The stack-up package frame 430a and the packages 409b located on the second package 409a together serve as another stack-up package frame 430b. The ball pads 408 are formed on both surfaces of each of the second package substrate 406 in the stack-up structure so as to be connected between the other films of the second package substrate 406.

5A and 5B are plan views illustrating a stack-up package frame according to a first embodiment of the present invention. As shown in FIG. 5A, depending on the result of the electrical connection and the desired number of connecting terminals, the solder balls 410 located on the ball pads 408 shown in FIGS. 4A and 4B It is arranged in a substantially square ring surrounding the first package resin 402. As shown in FIG. 5B, the solder balls 410 may also be disposed within a plurality of square rings having substantially the same center. It is apparent that the scope of the first embodiment is not limited to the above forms, and various modifications and similar forms may be included.

(Second embodiment)

6A through 6C are cross-sectional views schematically showing three different stack-up package frames according to a second embodiment of the present invention.

As shown in FIG. 6A, the stack-up package frame 530a includes a first package substrate 504 having a pin holding surface 514. The first package substrate 506 is stacked in parallel on the first package substrate 504. A plurality of chips 500 is positioned on the pin holding surface 514 and the second package substrate 506. The chips 400 are each electrically connected to the first package substrate 504 and the second package substrate 506 (by wiring, TAB or bump). A plurality of package materials, such as a first package resin 502 and a second package resin 502a, are positioned on the pin holding surface 514 and the second package substrate 506 to cover the chips 500. do. A plurality of pins 510 are positioned between the first package substrate 504 and the second package substrate 506 to surround the pin holding surface 514. In this case, the first package substrate 504 is vertically coupled to the second package substrate 506 by the pins 510. The pins 510 together act as a supporting frame to hold the second package substrate 506 through a plurality of solder joints 508. The solder joints 508 solder the pins 510 and the second package substrate 506 and are located on the surface of the second package substrate 506. The joint force of the solder is used to hold the second package substrate 506.

The first package substrate 504 is optionally a BGA package substrate, usually a ceramic material, epoxy-glass tissue resins (FR-4, FR-5), bismaleimidetriazine resin (BT), and their It is formed with either mixture. The second package substrate 506 is usually formed of any one of epoxy-glass tissue synthetic resins (FR-4, FR-5), bismaleidetriazine resin (BT), polyimide, and mixtures thereof. Preferably, the second package substrate 506 is formed of polyimide. The first package substrate 504 and the second package substrate 506 each have an electrical circuit pattern (not shown) located on the top and bottom surfaces of the package substrate.

The first package substrate 504 further includes a solder ball holding substrate 516. The stack-up package frame 530a further includes a plurality of solder balls, such as ball-grid array solder balls 512 connected to the solder ball holding substrate 516. The ball-grid array solder balls 512 are a medium for electrically connecting the stack-up package frame 530a and other circuit boards.

The pin holding surface 514 and the second package substrate 506 further include a plurality of solder joints 508. Some of the solder joints 508 are positioned to surround the chip holding substrate 514 for electrically connecting the first package substrate 504 and the second package substrate 506. The remaining solder joints 508 are positioned on the second package substrate 506 for electrically connecting the first package substrate 504 and any other package substrate sequentially formed thereon.

The first package substrate 504, the first package resin 502 adjacent to the first package substrate 504, and the chips 500 covered by the first package resin 502 are together together in a first package. Acts as 507. The second package substrate 506, the second package resin 503a adjacent to the second package substrate 506, and the chips 500 covered by the second package resin 506 are together together in a second package. Act as 509a. The first package 507 and the second package 509a each include at least one chip 500.

The stack-up frame 530a further includes a plurality of pins 510. In order to electrically connect the first package 507 and the second package 509, the pins 510 may be connected to the solder joints of the first package substrate 508 and the second package substrate 506. 508 acts as a link between them.

The stack-up package frame 530a including the ball-grid array solder balls 512 serves as a stack-up ball-grid array (BGA) package frame. The ball-grid array solder balls 512 connected to the solder ball holding surface 516 of the first package substrate 504 may include the stack-up package frame 530a and external circuit boards (not shown). Acts as a medium for electrically connecting

As shown in FIG. 6B, one or more packages 509b that are substantially the same as the second package 509a are sequentially placed on the second package 509a, the same as the second package 509a. . The stack-up package frame 530a and the packages 509b sequentially placed thereon act together as another stack-up package frame 530b.

6C shows another stack-up package frame 530c with two packages 509c. The stack-up package frame 530c includes the package 509c in which all packages are substantially the same as the second package 509a shown in FIGS. 6A and 6B. The stack-up package frame 530c includes a substrate 504c having the pin holding surface 514c at the top and the solder ball holding surface 516 at the bottom. A plurality of GBA solder balls 512 are connected to the solder ball holding surface 516c. The substrate 504c differs from other package substrates in that it does not have adjacent chips. The substrate 504c under the packages 509c is connected in series with the packages by the pins 510c.

7A and 7B are plan views illustrating a stack-up BGA package frame according to a second embodiment of the present invention. Referring to FIG. 7A, depending on the result of the electrical connection and the desired number of connection terminals, the pins 510 located on the solder joints 508 shown in FIGS. 6A and 6B may be formed of the first package resin. Arranged in a substantially square ring surrounding 502. Alternatively, as shown in FIG. 7B, the pins 510 may be arranged in a plurality of substantially square square rings. It is obvious that the scope of the first embodiment is not limited to the arrangement. On the other hand, arrangements similar to the various variations may be used.

A feature of the present invention resides in that the solder balls are positioned between the first package substrate and the second package substrate to surround the chip holding surface. In this case, the first package substrate is electrically connected to the second package substrate by the solder balls. Alternatively, the solder balls may be composed of a plurality of pins. In using the pins, solder joints are positioned between the second package substrate and the pins such that the second package substrate, the pins, and the first package substrate are electrically connected to each other. The stack-up package frame according to the present invention further includes a plurality of solder balls, such as a ball-grid array solder ball, connected to the solder ball holding surface. The solder balls act as a medium for electrically connecting the stack-up package frame and other circuit boards.

According to the present invention as described above, the thickness and weight of the stack-up frames can be reduced by using a package substrate formed of a light material such as polyimide. The package substrates then have electrical circuit patterns located on the top and bottom surfaces, respectively.

In addition, many packages are stacked in a three-dimensional array using the stack-up package according to the present invention. Thus, the stack-up package frame is a multi-chip module package, which can increase the package density and operation speed of the chip module and develop various microelectronic products.

Claims (19)

The stack-up package frame is A first package substrate having a chip holding surface thereon; At least one second package substrate stacked on the first substrate package substrate; A plurality of chips located on the chip holding surface and the second package substrate including at least one chip; A plurality of package materials located on the chip holding surface and the second package substrate to cover the chips; And If the at least one second package substrate includes multiple substrates or is positioned to surround the package materials on the chip holding surface, includes a plurality of conductive objects positioned on substrates between the second package substrates, The second package substrate is parallel to the first package substrate, The chips are electrically connected to the first package substrate and the second package substrate, respectively. And the first package substrate is electrically connected to the second package substrate by the conductive objects, which also act as a holding structure. The stack-up package frame of claim 1, wherein the second package substrate is formed of polyimide. The method of claim 1, wherein the first package substrate is a ceramic material, an epoxy-glass fabric composite resin, a bismaleimidetriazine resin, or a polyimide. A stack-up package frame, characterized in that formed from any one of them. The stack-up package frame of claim 1, wherein the first package substrate further comprises a solder ball holding surface facing the chip holding surface. 5. The stack-up package frame of claim 4, wherein the frame further comprises a plurality of solder balls connected to the solder ball holding surface. The stack-up package frame of claim 1, wherein the conductive materials are comprised of solder balls. The stack-up package frame is A plurality of conductive objects; And And all two adjacent package films comprise a plurality of package films separated by the conductive objects, wherein the package films are electrically connected to each other by the conductive objects. The method of claim 7, wherein the packages are each, A package substrate; At least one chip located on the package substrate; And The stack-up package frame further comprises a package material located on the package substrate to cover the chip. 10. The stack-up package frame of claim 8, wherein the package substrate is formed of polyimide. 8. The stack-up package frame of claim 7, wherein the conductive objects are composed of solder balls. The stack-up package frame is A first package substrate having a pin holding surface thereon; At least one package substrate stacked on the first package substrate each including at least one chip; A plurality of package materials located on the pin holding surface and the second package substrate to cover the chips; A plurality of conductive pins positioned on the chip holding surface to surround the package materials; And A plurality of the solder joints positioned on the second package substrate and the conductive pins to electrically connect the chips on the second package substrate and the first package substrates to each other via solder joints on the conductive pins; , The chips are electrically connected to the first package substrate and the second package substrate, respectively. The first package substrate is coupled in series with the second package substrate by the pins, And the solder joints also provide a bonding force of the solder for holding the second package substrate. The stack-up package frame of claim 11, wherein the first package substrate is formed of any one of a ceramic material, an epoxy-glass tissue resin, a bismaleimide triazine resin, and a combination thereof. The stack-up package frame of claim 11, wherein the second package substrate is formed of any one of an epoxy-glass tissue resin, bismaleimidetriazine resin, polyimide, and a combination thereof. 12. The stack-up package frame of claim 11, wherein the first package substrate further comprises a solder ball holding surface facing the chip holding surface, wherein the plurality of solder balls are located on the solder ball holding surface. . The stack-up package frame is A support substrate having a pin holding surface thereon; A plurality of package films deposited on the support substrate; A plurality of conductive pins positioned to surround the pin holding surface; And A plurality of said solder joints located on said package films and said conductive pins for electrically connecting said package films and solder joints through said pins, The package films are parallel to the support substrate, The package films are coupled in series with each other by the conductive pins, And the plurality of solder joints also provide solder bonding force for holding the package films on the conductive pins. The stack-up package frame of claim 15, wherein the support substrate is formed of any one selected from a ceramic material, an epoxy-glass tissue synthetic resin, a bismaleimide triazine resin, and a synthetic resin thereof. The method of claim 15, wherein the package films are each, A package substrate; At least one chip located on the package substrate; And And a package material located on the package substrate to cover the chips, wherein the chips are electrically connected to the package substrate. 18. The stack-up package frame according to claim 17, wherein the package substrate is formed of any one selected from epoxy-glass tissue resin, bismaleimidetriazine resin, polyimide, and mixtures thereof. 16. The stack-up package frame of claim 15, wherein the support substrate further comprises a solder ball holding surface facing the chip holding surface, wherein the plurality of solder balls are located on the solder ball holding surface.