CN117673039A - FPGA three-dimensional core particle packaging structure - Google Patents
FPGA three-dimensional core particle packaging structure Download PDFInfo
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- CN117673039A CN117673039A CN202311639166.3A CN202311639166A CN117673039A CN 117673039 A CN117673039 A CN 117673039A CN 202311639166 A CN202311639166 A CN 202311639166A CN 117673039 A CN117673039 A CN 117673039A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 169
- 239000007771 core particle Substances 0.000 title abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 96
- 230000008054 signal transmission Effects 0.000 claims abstract description 10
- 210000001503 joint Anatomy 0.000 claims description 10
- 238000003032 molecular docking Methods 0.000 description 15
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to the technical field of chip packaging, in particular to an FPGA three-dimensional core particle packaging structure. The invention provides an FPGA three-dimensional core particle packaging structure, which comprises: the FPGA packaging modules are stacked, and each FPGA packaging module is provided with an FPGA chip and a micro-bump structure for interconnection; the topological layout of the elements and the micro-bump structures in each FPGA packaging module is the same; at least part of the micro-bump structures in the FPGA packaging modules of the adjacent layers are overlapped in layout, and the FPGA chips in the adjacent FPGA packaging modules are interconnected through the micro-bump structures at the overlapped positions; the connecting substrate is used for arranging the stacked FPGA packaging modules and realizing the external signal transmission of each FPGA packaging module. The invention provides an FPGA three-dimensional core particle packaging structure, which can increase the capacity of an FPGA core particle in a unit area and improve the performance of the FPGA core particle.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to an FPGA three-dimensional core particle packaging structure.
Background
The capacity of FPGA die is limited by the number of CLBs (configure Logic block, configurable logic blocks), which in turn are limited by the power consumption/area/pin/package process. Future high performance applications require FPGAs with high capacity to enable more data processing. However, in the existing FPGA packaging structure, the unit area is limited by the number of CLBs, and the capacity cannot be broken through, so that the performance cannot be improved.
Therefore, a solution is needed to enable the FPGA core to accommodate a larger number of CLBs per unit area, thereby achieving capacity breakthrough and performance improvement.
Disclosure of Invention
In order to solve the problems, the invention provides an FPGA three-dimensional core particle packaging structure, which aims to solve the problems that the capacity of the FPGA core particle is limited by the number of CLBs, the capacity is difficult to break through, and the performance is difficult to improve.
The invention provides an FPGA three-dimensional core particle packaging structure, which comprises: the FPGA packaging modules are stacked, and each FPGA packaging module is provided with an FPGA chip and a micro-bump structure for interconnection; the topological layout of the elements and the micro-bump structures in each FPGA packaging module is the same; at least part of the micro-bump structures in the FPGA packaging modules of the adjacent layers are overlapped in layout, and the FPGA chips in the adjacent FPGA packaging modules are interconnected through the micro-bump structures at the overlapped positions; the connection substrate is used for arranging the stacked FPGA packaging modules and realizing signal transmission of the FPGA packaging modules to the outside.
Optionally, the stacking manner of the FPGA packaging module is: the FPGA packaging modules are completely overlapped, and projection patterns of the FPGA packaging modules in different layers on the connecting substrate are completely overlapped.
Optionally, the stacking manner of the FPGA packaging module is: the FPGA packaging modules of the adjacent layers are partially staggered and partially overlapped after horizontally rotating for 180 degrees; and the FPGA packaging modules of the adjacent layers are interconnected through the micro-bump structure at the overlapping position.
Optionally, the connection substrate includes a main substrate and a raised substrate; the heightened substrate is overlapped at a part of the main substrate; the FPGA packaging module which is not directly connected with the main substrate is provided with a non-overlapping area; and the heightened substrate is at least partially corresponding to a non-overlapping region in the FPGA packaging module which is not directly connected with the main substrate, and is electrically connected with the FPGA packaging module at a corresponding position.
Optionally, a distance between the main substrate and the directly connected FPGA packaging module is a first distance; the distance between the heightened substrate and the FPGA packaging module which is not directly connected is a second distance; the first distance and the second distance are the same.
Optionally, the raised substrate is provided with an I/O interface, and the I/O interface is electrically connected to the non-overlapping region.
Optionally, the FPGA packaging module includes a packaging substrate, where the packaging substrate has an overlapping area, and is configured to set the micro bump structure of the overlapping interconnection; the packaging substrate right opposite position under the micro-bump structure in the overlapping region is provided with a front connection opening facing the micro-bump structure and a back connection opening facing away from the surface of one side of the micro-bump structure; the front connection opening is electrically connected with the corresponding back connection opening; the front connection opening is connected with the micro-bump structure, and the back connection opening is suitable for being connected with the micro-bump structure at a corresponding position in the lower FPGA packaging module.
Optionally, the connection substrate is provided with a connection circuit and a docking interface, and the docking interface is used for being connected with the stacked FPGA packaging modules, so as to realize external signal transmission of each FPGA packaging module through the connection circuit; the FPGA packaging module comprises a first FPGA packaging module and a second FPGA packaging module; the second FPGA packaging module is stacked and arranged above the first FPGA packaging module, and in the first FPGA packaging module, a back connection opening positioned in the overlapping area is electrically connected with a butt joint interface at a corresponding position on the connection substrate.
Optionally, the connection substrate is provided with a substrate micro-bump structure, and the substrate micro-bump structure is arranged corresponding to the docking interfaces, is connected with the docking interfaces in a one-to-one correspondence manner, and is suitable for being electrically connected with the back connection opening in the upper FPGA packaging module.
Optionally, the FPGA packaging module includes an Xbar interconnection switch, and the Xbar interconnection switches in the FPGA packaging modules of adjacent layers are connected through the microbump structures in the overlapping areas.
The FPGA three-dimensional core particle packaging structure comprises a plurality of FPGA packaging modules which are stacked, wherein FPGA chips in the FPGA packaging modules of adjacent layers are interconnected through a micro-bump structure at an overlapping position. Therefore, interconnection among stacked FPGA chips is realized, three-dimensional stacking packaging of the FPGA chips can be realized, the number of CLBs in the FPGA core particles in unit area is increased, the capacity of the FPGA core particles in unit area is increased, and the performance of the FPGA core particles is improved. Compared with the mode of packaging before stacking, and different FPGA chips are stacked and packaged through wire bonding and TSV through holes, the method has fewer process steps, and the wire bonding mode is easy to cause the problems of wire breakage, partial welding and the like, so that the yield is lower; the micro bump structure is more stable and the yield is higher. Compared with the wire bonding mode and when the transmission is problematic, the wire bonding-TSV process product is more in wire winding and difficult to test, and the micro-bump array connection mode can more conveniently judge which layer of chips are problematic.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic structural diagram of an FPGA three-dimensional core package structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a first FPGA package module and a second FPGA package module in the FPGA three-dimensional core package structure of FIG. 1;
FIG. 3 is a schematic structural diagram of an FPGA three-dimensional core package structure according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a first FPGA package module and a second FPGA package module in the FPGA three-dimensional core package structure of FIG. 1;
fig. 5 is a schematic diagram of connection relationship between an Xbar interconnection switch in a first FPGA package module and an Xbar interconnection switch in a second FPGA package module in the FPGA three-dimensional core package structure according to an embodiment of the present invention.
Detailed Description
In order to solve the problems that the capacity of FPGA core particles is limited by the quantity of CLBs, the capacity is difficult to break through, and the performance is difficult to improve. The invention provides an FPGA three-dimensional core particle packaging structure.
The invention provides an FPGA three-dimensional core particle packaging structure, which comprises: the FPGA packaging modules are stacked, and each FPGA packaging module is provided with an FPGA chip and a micro-bump structure for interconnection; the topological layout of the elements and the micro-bump structures in each FPGA packaging module is the same; at least part of the micro-bump structures in the FPGA packaging modules of the adjacent layers are overlapped in layout, and the FPGA chips in the adjacent FPGA packaging modules are interconnected through the micro-bump structures at the overlapped positions; the connection substrate is used for arranging the stacked FPGA packaging modules and realizing signal transmission of the FPGA packaging modules to the outside.
The FPGA three-dimensional core particle packaging structure provided by the invention can effectively improve the number of CLBs in the FPGA core particles in unit area, thereby increasing the capacity of the FPGA and improving the performance of the FPGA. .
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Examples
Referring to fig. 1-5, the present invention provides an FPGA three-dimensional core package structure, comprising:
the FPGA packaging modules are stacked, and each FPGA packaging module is provided with an FPGA chip and a micro-bump structure for interconnection; the topological layout of the elements and the micro-bump structures in each FPGA packaging module is the same.
At least part of the micro-bump structures in the FPGA packaging modules of the adjacent layers are overlapped in layout, and the FPGA chips in the adjacent FPGA packaging modules are interconnected through the micro-bump structures at the overlapped positions; the connection substrate is used for arranging the stacked FPGA packaging modules and realizing signal transmission of the FPGA packaging modules to the outside. An FPGA package module can be considered a CLB.
The FPGA three-dimensional core particle packaging structure provided by the embodiment comprises a plurality of FPGA packaging modules which are stacked, wherein FPGA chips in the FPGA packaging modules of adjacent layers are interconnected through a micro-bump structure at an overlapping position. Therefore, interconnection among stacked FPGA chips is realized, three-dimensional stacking packaging of the FPGA chips can be realized, the number of CLBs in the FPGA core particles in unit area is increased, the capacity of the FPGA core particles in unit area is increased, and the performance of the FPGA core particles is improved. Compared with the mode of packaging before stacking, different FPGA chips are stacked and packaged through wire bonding and TSV through holes, the method has fewer process steps, and the wire bonding mode is easy to cause the problems of wire breakage, partial welding and the like, so that the yield is lower; the micro bump structure is more stable and the yield is higher. Compared with the wire bonding mode and when the transmission is problematic, the wire bonding-TSV process product is more in wire winding and difficult to test, and the micro-bump array connection mode can more conveniently judge which layer of chips are problematic.
Specifically, referring to fig. 1-2 or fig. 3-4, the FPGA package module includes a package substrate (e.g. 211, 221 in fig. 1), and the micro bump structure (e.g. 213, 223 in fig. 1) is connected to the FPGA chip through a connection circuit (not shown) in the package substrate. The package substrate has an overlap region for providing the microbump structures (black blocks in fig. 1 and circles in fig. 2) of the overlapping interconnects. The package substrate under the micro-bump structure in the overlapping region has front connection openings (e.g., 2111, 2211 in fig. 1) facing the micro-bump structure and back connection openings (e.g., 2112, 2212 in fig. 1) on a side surface facing away from the micro-bump structure; the front connection opening is electrically connected with the corresponding back connection opening; the front connection opening is connected with the micro-bump structure, and the back connection opening is suitable for being connected with the micro-bump structure at a corresponding position in the lower FPGA packaging module.
Further, the connection substrate 100 is provided with a connection circuit and a docking interface (not shown in the figure), and the docking interface is used for being connected with the stacked FPGA packaging modules, so as to realize external signal transmission of each FPGA packaging module through the connection circuit.
The electrical connection between the front-side connection opening and the corresponding back-side connection opening can be through-connected by means of, for example, a TSV via, or can be non-through-connected by means of traces inside the package substrate.
Further, the connection substrate is provided with a substrate micro-bump structure, the substrate micro-bump structure is arranged corresponding to the butt joint interfaces, is connected with the butt joint interfaces in a one-to-one correspondence manner, and is suitable for being electrically connected with the back connection opening in the upper FPGA packaging module.
Referring to fig. 1-2 or fig. 3-4, the FPGA packaging module includes a first FPGA packaging module 210 and a second FPGA packaging module 220. The second FPGA packaging module 220 is stacked above the first FPGA packaging module 210, and in the first FPGA packaging module 210, the back connection opening 2112 located in the overlapping area is electrically connected to the docking interface at the corresponding position on the connection substrate. In the embodiments of fig. 1-2 or fig. 3-4, the stacked FPGA packaging modules include only a first FPGA packaging module 210 and a second FPGA packaging module 220. In other embodiments, more FPGA package modules so stacked may also be included.
Further, the connection substrate is provided with a substrate micro-bump structure, the substrate micro-bump structure is arranged corresponding to the butt joint interfaces, is connected with the butt joint interfaces in a one-to-one correspondence manner, and is suitable for being electrically connected with the back connection opening in the upper FPGA packaging module.
In various embodiments, the stacking manner of the FPGA package module may have a variety of options.
For example, referring to fig. 1 and 2, in some embodiments, the FPGA package module is stacked in the following manner: the FPGA packaging modules are completely overlapped, and projection patterns of the FPGA packaging modules in different layers on the connecting substrate are completely overlapped. That is, the first FPGA packaging module 210 and the second FPGA packaging module 220 are completely overlapped, and the projection patterns of the first FPGA packaging module 210 and the second FPGA packaging module 220 on the connection substrate 100 are completely overlapped. A in fig. 2 is merely for showing the direction of the package module, and is not used for indicating specific technical features.
In this manner, the first FPGA packaging module 210 includes a first packaging substrate 211, on which a first FPGA chip 212 is disposed, and a first microbump structure 213 arranged in an array for interconnection. Meanwhile, a front connection opening 2111 facing the first micro-bump structure 213 and a back connection opening 2112 facing away from the surface of one side of the first micro-bump structure 213 are formed in the opposite position of the first package substrate 211 below the first micro-bump structure 213 on the first package substrate 211; the second FPGA packaging module 220 includes a second packaging substrate 221, on which a second FPGA chip 222 and a second microbump structure 223 for interconnection are disposed on the second packaging substrate 221. Meanwhile, the second package substrate 221 under the second micro-bump structure 223 on the second package substrate 221 has a front connection opening 2211 facing the second micro-bump structure 223 and a back connection opening 2212 on a side surface facing away from the second micro-bump structure 223; the front side connection openings 2111, 2211 are electrically connected with the corresponding back side connection openings 2112, 2212; the front connection openings 2111, 2211 connect the corresponding micro bump structures 213, 223; the backside connection openings 2212 on the second package substrate 221 are adapted to connect with the first micro bump structures 213 at corresponding positions in the underlying first FPGA package module.
The connection substrate 100 is provided with a substrate micro-bump structure (the structure form is the same as the first micro-bump structure 213 and the second micro-bump structure 223), and the substrate micro-bump structure is arranged corresponding to the docking interfaces, is connected with the docking interfaces in a one-to-one correspondence manner, and is suitable for electrically connecting with the upper back connection opening of the FPGA packaging module, i.e., the first FPGA packaging module 210.
Instead of the above-described stacking method, a stacking method that does not completely overlap may also be selected.
For example, referring to fig. 3 and 4, in some other embodiments, the FPGA package module is stacked in the following manner: the FPGA packaging modules of the adjacent layers are partially staggered and partially overlapped after horizontally rotating for 180 degrees; and the FPGA packaging modules of the adjacent layers are interconnected through the micro-bump structure at the overlapping position. Referring to fig. 4, the first FPGA packaging module 210 and the second FPGA packaging module 220 are partially misaligned and partially overlapped after being horizontally rotated by 180 °. A in fig. 4 is merely for showing the direction of the package module, and is not used for indicating specific technical features.
Further, referring to fig. 4, in this stacked manner, the connection substrate 100 includes a main substrate 110 and a lift substrate 120. The raised substrate 120 is stacked on a portion of the main substrate 110. The FPGA packaging module not directly connected to the main substrate, that is, the second FPGA packaging module 220 has a non-overlapping region. The raised substrate 120 is at least partially corresponding to the non-overlapping region in the FPGA packaging module that is not directly connected to the main substrate, that is, the second FPGA packaging module 220, and is electrically connected to the FPGA packaging module, that is, the second FPGA packaging module 220, at a corresponding position.
In this stacking manner, on one hand, interconnection of the first FPGA chip 212 and the second FPGA chip 222 in the first FPGA packaging module 210 and the second FPGA packaging module 220 of the adjacent layers is realized by using the overlapping region, stacking connection of multiple chips is realized in a unit area, and external signal connection is realized by connecting the main substrate 110 together. Meanwhile, the second FPGA packaging module 220 may be symmetrically rotated 180 ° to leave a considerable part of the non-overlapped micro bumps, or an area for interconnection, that is, a non-overlapped area, which is not shielded by the first FPGA packaging module 210 below, so as to connect with the connection substrate, to implement more interface connection and more signal transmission. Not only the capacity of the chip is increased, but also the transmission line of the signal is increased, so that the improvement of the capacity and the performance can be ensured. In addition, by increasing the distance between the connection substrate and the package module, the structure stability and the signal transmission stability are also ensured.
In the connection mode, a docking interface may be disposed on the main substrate 110, and a substrate micro bump structure may be disposed on the main substrate, and connected to the docking interface in a one-to-one correspondence manner, and connected to a back connection opening on the back of the first package substrate 211 of the first FPGA package module 210. The heightening substrate 120 is also provided with a docking interface, and the heightening substrate 120 is also provided with a micro-bump structure, which is connected with the docking structure in one-to-one correspondence, and is connected with a back connection opening of the back surface of the second package substrate 221 of the second FPGA package module 220. Alternatively, the connection may be made by other means such as copper pillars or solder balls.
The raised substrate 120 is provided with an I/O interface that is electrically connected to the non-overlapping region. In the present embodiment, for example, a docking interface of the build-up substrate 120 is set as an I/O interface. That is, since the overlap region has already achieved external connection of the second FPGA packaging module 220, the non-overlap region becomes a spare interconnection region, which can be utilized to achieve more docking transmission lines, for example, provided as a DDR I/O connection interface.
Further, the distance between the main substrate 110 and the directly connected FPGA packaging module is a first distance; the distance between the heightened substrate 120 and the FPGA packaging module which is not directly connected is a second distance; the first distance and the second distance are the same.
In the embodiment of fig. 3 and fig. 4, a first distance is between the main substrate 110 and the first FPGA packaging module 210 that is directly connected to the first FPGA packaging module; the distance between the raised substrate 120 and the second FPGA packaging module 220 that is not directly connected is a second distance; the first distance and the second distance are the same. Therefore, the distances between different FPGA packaging modules and the connecting substrate are the same, and the overall structural specification is uniform everywhere, so that the overall stability of the structure is higher.
In addition, the FPGA packaging module comprises Xbar interconnection switches, and the Xbar interconnection switches in the FPGA packaging modules of adjacent layers are connected through the micro-bump structures in the overlapping areas. For example, as shown in FIG. 5, the first FPGA package module 210 of the adjacent layer includes a first Xbar interconnect switch array 214 and the second FPGA package module 220 includes a second Xbar interconnect switch array 224; the first Xbar interconnect switch array 214 and the second Xbar interconnect switch array 224 also implement interconnection through the micro bumps in the overlapping area, so that the connection of the lines, such as the I/O connection, can be more flexibly shared, and more data processing can be implemented. The Xbar interconnection switch arrays of the upper layer and the lower layer are communicated in such a way that the connection line of the Xbar can be expanded from two dimensions to three dimensions, and can be connected to any node in the layers up and down through FPGA programming, so that the connection is more flexible compared with the wire bonding-TSV mode that the connection can only be connected to fixed nodes.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (10)
1. An FPGA three-dimensional core package structure, comprising:
the FPGA packaging modules are stacked, and each FPGA packaging module is provided with an FPGA chip and a micro-bump structure for interconnection; the topological layout of the elements and the micro-bump structures in each FPGA packaging module is the same;
at least part of the micro-bump structures in the FPGA packaging modules of the adjacent layers are overlapped in layout, and the FPGA chips in the adjacent FPGA packaging modules are interconnected through the micro-bump structures at the overlapped positions;
the connection substrate is used for arranging the stacked FPGA packaging modules and realizing signal transmission of the FPGA packaging modules to the outside.
2. The FPGA three-dimensional core packaging structure of claim 1 wherein,
the stacking mode of the FPGA packaging module is as follows: the FPGA packaging modules are completely overlapped, and projection patterns of the FPGA packaging modules in different layers on the connecting substrate are completely overlapped.
3. The FPGA three-dimensional core packaging structure of claim 1 wherein,
the stacking mode of the FPGA packaging module is as follows: the FPGA packaging modules of the adjacent layers are partially staggered and partially overlapped after horizontally rotating for 180 degrees; and the FPGA packaging modules of the adjacent layers are interconnected through the micro-bump structure at the overlapping position.
4. The FPGA three-dimensional core package structure of claim 3, wherein,
the connecting substrate comprises a main substrate and a heightening substrate; the heightened substrate is overlapped at a part of the main substrate; the FPGA packaging module which is not directly connected with the main substrate is provided with a non-overlapping area; and the heightened substrate is at least partially corresponding to a non-overlapping region in the FPGA packaging module which is not directly connected with the main substrate, and is electrically connected with the FPGA packaging module at a corresponding position.
5. The FPGA three-dimensional core package structure of claim 4, wherein,
the distance between the main substrate and the FPGA packaging module which is directly connected is a first distance; the distance between the heightened substrate and the FPGA packaging module which is not directly connected is a second distance; the first distance and the second distance are the same.
6. The FPGA three-dimensional core package structure of claim 4, wherein,
the raised substrate is provided with an I/O interface adapted to be electrically connected to the non-overlapping region.
7. The FPGA three-dimensional core packaging structure of any of claims 1-6 wherein,
the FPGA packaging module comprises a packaging substrate, wherein the packaging substrate is provided with an overlapping area and is used for arranging the micro-bump structure which is overlapped and interconnected; the packaging substrate right opposite position under the micro-bump structure in the overlapping region is provided with a front connection opening facing the micro-bump structure and a back connection opening facing away from the surface of one side of the micro-bump structure; the front connection opening is electrically connected with the corresponding back connection opening; the front connection opening is connected with the micro-bump structure, and the back connection opening is suitable for being connected with the micro-bump structure at a corresponding position in the lower FPGA packaging module.
8. The FPGA three-dimensional core packaging structure of claim 7 wherein,
the connection substrate is provided with a connection circuit and a butt joint interface, and the butt joint interface is used for being connected with the stacked FPGA packaging modules so as to realize the external signal transmission of each FPGA packaging module through the connection circuit;
the FPGA packaging module comprises a first FPGA packaging module and a second FPGA packaging module; the second FPGA packaging module is stacked and arranged above the first FPGA packaging module, and in the first FPGA packaging module, a back connection opening positioned in the overlapping area is electrically connected with a butt joint interface at a corresponding position on the connection substrate.
9. The FPGA three-dimensional core packaging structure of claim 8 wherein,
the connecting substrate is provided with a substrate micro-bump structure, the substrate micro-bump structure is arranged corresponding to the butt joint interfaces, is connected with the butt joint interfaces in a one-to-one correspondence manner, and is suitable for being electrically connected with the back connection opening in the upper FPGA packaging module.
10. The FPGA three-dimensional core packaging structure of any of claims 1-9 wherein,
the FPGA packaging module comprises Xbar interconnection switches, and the Xbar interconnection switches in the FPGA packaging modules of adjacent layers are connected through the micro-bump structures in the overlapping areas.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311639166.3A CN117673039B (en) | 2023-12-01 | 2023-12-01 | FPGA three-dimensional core particle packaging structure |
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| KR20010063032A (en) * | 1999-12-21 | 2001-07-09 | 유-행 치아오 | Stack-up package frame |
| US7098542B1 (en) * | 2003-11-07 | 2006-08-29 | Xilinx, Inc. | Multi-chip configuration to connect flip-chips to flip-chips |
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| CN114496960A (en) * | 2022-02-07 | 2022-05-13 | 西安微电子技术研究所 | Integrated packaging structure based on TSV silicon through connection substrate stacking and manufacturing method |
| CN115377076A (en) * | 2022-08-31 | 2022-11-22 | 西安微电子技术研究所 | Wiring structure and method of DDR3 storage micro-module |
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| KR20010063032A (en) * | 1999-12-21 | 2001-07-09 | 유-행 치아오 | Stack-up package frame |
| US7098542B1 (en) * | 2003-11-07 | 2006-08-29 | Xilinx, Inc. | Multi-chip configuration to connect flip-chips to flip-chips |
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