KR20000052093A - Multi-chip chip scale package - Google Patents

Abstract

PURPOSE: A multi-chip chip scale package is provided which has reduced thickness and surface area, to improve the operation of a chip by shortening the signal transmission path. CONSTITUTION: A film carrier is used in a multi-chip chip scale package. Two same chips(50,52) having different sizes can be placed on a film carrier(58). The above chips are arranged face to face in a side of each film carrier by using the flip chip technology. In addition, bumps(64,66) are formed on each chip and are connected with the film carrier electrically. An insulation material(68) is filled between the chips and one side of each chip is revealed. Moreover, a conductive wire(56) of the film carrier is connected to the chip directly without passing through other carrier.

Description

Multi-chip chip scale package {MULTI-CHIP CHIP SCALE PACKAGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor packing structure, and more particularly to a multi-chip chip scale package (CSP).

As semiconductor manufacturing process technologies are further developed, appropriate technologies must be further developed to meet the requirements of semiconductor devices. The semiconductor device manufacturing process typically includes the following three steps. In a first step, as an epitaxy technique, it is used to form a semiconductor substrate. In the second step, a semiconductor device such as a metal-oxide semiconductor (MOS), a multilevel interconnection, or the like is formed on a semiconductor substrate. In the third step, there is a packing process. BACKGROUND OF THE INVENTION In the recent semiconductor device manufacturing process, the manufacture of devices or electronic products in thin, light and small dimensions has become mainstream. In other words, semiconductor devices are becoming highly integrated. In terms of packages, many technologies such as chip scale packages, multi-chip modules (MCMs), etc. have been developed to achieve high integration. Advances in semiconductor manufacturing process technology with a line width of 0.18 micrometers have attracted great interest and intense research, which has further reduced package volume. Therefore, the technique of arranging one or more chips in one package becomes very important. In a multi-chip package, microchips chips, memory chips including dynamic random access memory (DRAM) and flash memory and logic circuit chips are used to reduce semiconductor manufacturing process costs and package volume. Can be packaged in a package. Furthermore, the signal transmission path has been shortened to enhance efficiency. Multi-chip integrated circuit packing techniques can also be applied to multi-chip systems having various functions and operating frequencies as listed below.

1. A system that includes memory chips, microprocessors, resistors, capacitors, and inductors.

2. A system comprising a memory chip (DRAM), a logic circuit chip and a memory chip (Flash memory).

3. A system that includes analog chips, logic chips, memory chips (including DRAM, SRAM, flash memory), resistors, capacitors, and inductors.

A conventional multi-chip module is shown in FIG. Multi-level printed circuit boards (PCBs, hereinafter referred to as PCBs) are typically applied as substrates for carriers of multi-chip modules. One or more chips 12 are attached by an insulating glue 14 on the substrate 10. Bonding pads on the chip 12 are electrically connected to terminals on the substrate 10 by conductive wires 16. In addition to wire bonding, the connection between the chip 12 and the substrate 10 may result in bump formation by flip chip or controlled collapse chip connection (C4) technology. It is also possible. Resin 18 is used to seal the chip 12 and electrical connection between the entire package and the PCB is achieved by a ball grid array (BGA). The BGA uses a solder ball 20 to connect the terminal to the PCB. The conventional multi-chip module described above requires a large surface because the chips are not packaged on the same surface side. Therefore, a problem arises in that the package volume increases and the signal transmission path between the chips becomes long. In addition, although the package volume can be reduced using flip chip technology to connect the chip and carrier, a known good die (KGD) method should be used for the test. This leads to problems of yield reduction and high cost.

US Patent no. 5,331, 235 discloses face to face multi-chip packages to further reduce package volume. The multi-chip package is shown in FIG. 2, the multi-chip package includes chips 30 and 32 facing each other by a tape automatic bonding (TAB) method. Two chips 30, 32 have bumps 34, 36, respectively, for inner leading bonding (ILB), which bumps 34, 36 are electrically connected to the film carrier 38. . The chips 30 and 32 are connected to a lead frame 40 for outer leading bonding (OLB). Solder balls 42 are formed between the chips 30 and 32. Then, the chips 30, 32, the film carrier 38 and the lead frame 40 are molded by resin 44. The multi-chip package described above uses tape autobonding technology. Electrical connections between the chips and the PCB are made by lead frame or other carrier installation. Thus, the signal transmission path becomes long. In addition, the use of package molding material (resin) increases thickness and surface area. This reduces applicability and reduces efficiency in heat dissipation. Furthermore, this kind of package cannot achieve mass production.

The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a multi-chip chip scale package with reduced thickness and surface area. According to the present invention, the package surface area is almost equal to or slightly larger than the largest chip among the packages to be packaged.

According to the multi-chip chip scale package according to the present invention, the signal transmission path is shortened to improve chip operation.

According to the multi-chip chip scale package according to the present invention, heat dissipation is increased. The heat dissipation occurs through a printed circuit on a metal plate or PCB. Or by other heat dissipation devices.

In addition, according to the present invention, inspection of the chip package is performed during the packaging process without the KGD method.

1 is a cross-sectional view schematically showing a conventional multi-chip module package;

2 is a cross-sectional view showing a conventional face-to-face multi-chip module package;

3 is a cross-sectional view showing a multi-chip chip scale package according to a preferred embodiment of the present invention;

4A-4D show film carriers of a multi-chip chip scale package according to a preferred embodiment of the present invention;

5 is a cross-sectional view showing a film carrier having location holes of a multi-chip chip scale package according to a preferred embodiment of the present invention; And

6A and 6B are cross-sectional views illustrating a multi-chip chip scale package applied to a printed circuit board according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

50, 52: chip 54: insulating film

56 conductive wire 58 film carrier

64, 66: bump 68: insulating material

80: reading hole 82: pre-floating ring

84: corner support ring 86: position hole

100: printed wiring circuit board 102: substrate

104, 106: printed wiring circuit

(Configuration)

Multi-chip chip scale packages for achieving the above objects and effects use a film carrier to carry two chips having different sizes. Using flip chip technology, the two chips are placed on both sides of the film carrier so that they face each other. Each of the chips has a bump connected to the film carrier. An insulating material is filled between the chips while the other side of each of the chips is exposed. As a result, the thickness of the package decreases and heat dissipation increases. In addition, a conductive wire is formed on the film carrier to directly connect with an external signal. Thus the signaling path is shortened due to the added carrier.

In arranging a multi-chip chip scale package on a PCB, the chip has a side and can be directly connected to a printed wiring circuit or metal plate on the PCB to provide effective heat dissipation. Additional heat dissipation hatches may also be mounted on the surface of other chips in the distal end of the PCB, further improving the heat dissipation effect.

In addition, at least one location hole may be formed on the insulating film and filled with an insulating material so that the chip may be more stably connected to the film carrier. Thus, improved packing quality and enhanced reliability can be achieved.

The foregoing general description and the following detailed description are exemplary and explanatory only and do not limit the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3 to 6. The package process typically includes the following steps.

1) Carrier selection: Chip type should be selected according to special requirements, eg lead frame, film carrier or PCB. Film carriers are commonly used in tape auto bonding techniques;

2) Electrical connection between chip and carrier: At present, technologies such as wire bonding, film automatic bonding and film chip or controlled collapsing chip connection (C4) have been developed and widely used; And

3) Package and device sealing: The chip and carrier are covered or shielded by resin, ceramic or other packing material to protect the connections between the device and the chip and carrier on the chip.

3 is a cross-sectional view showing a multi-chip chip scale package according to the present invention. According to the present invention, two chips 50 and 52 having different sizes are packaged in one package, and the package size is almost the same as the larger of the chips 50 and 52. For example, one chip 50 is formed as shown in FIG. 3 to have a larger surface area than the other chip 52. The chips 50 and 52 include DRAM, read only memory (ROM), logic or analog circuitry, and other components. In the case of a carrier, the film carrier 58 is selected in the embodiment of the present invention. As shown in the figure, the film carrier 58 includes an insulating film 54 and a conductive wire 56 formed on the insulating film 54. Since the conductive wire 56 of the film carrier 58 has a thinner and narrower dimension than the conductive wire used for other types of carriers, such a package can be applied to high frequency devices.

Flip chip (or C4) technology is used to form an electrical connection between the chips 50, 52 and the film carrier 58. By the flip chip technique, the thickness of the package is reduced and the signal transmission path is reduced. The chips 50, 52 each comprise several elements on their surfaces 60,62. Bonding pads (not shown) may be formed on the surfaces 60 and 62 of the chips 50 and 52, and bumps 64 and 66 may be formed in the bonding pads, respectively. The chips 50, 52 are placed face to face (60-to-face 62) on opposite sides of the film carrier 58. The chips 50 and 52 are electrically connected to each other through the bumps 64 and 66. Preferably, a chip 52 having a relatively small size is placed on the side of the carrier film 56 where the insulating film 54 is located. As a result, the package may be thinner. In addition, the bump 66 of the chip 52 is preferably connected to the inner end of the conductive wire 56 surrounded by the insulating film 54 shown in cross section. On the other hand, the bump 64 of the chip 50 is preferably connected to the conductive wire 56 at a position corresponding to the insulating film 54, the conductive wire connected to the bump 66 ( To the opposite side of the side corresponding to 56). This method prevents misalignment between the bumps 64 and 66 and the conductive wire 56 caused by deformation or dislocation due to junction stress.

In package and device sealing, an insulating material 68, such as epoxy, is filled between the chips 50,52. The insulating material 68 is filled between the chips 50, 52 to protect only the elements on the surfaces 60, 62 of the chips 50, 52. On the other hand, the other sides 70, 72 of the chips 50, 52 are exposed, which reduces the package dimensions and provides a heat dissipation pass.

Since the conductive wire 56 of the film carrier 58 was used for signal transmission to the outside without using an additional carrier, the signal transmission path is reduced. As shown in the figure, the conductive wire 56 is bent to form a curved or specially required shape. Since the formation process of the conductive wire 56 and the subsequent surface mount technique between the conductive wire 56 and the PCB are conventional techniques, the description thereof is omitted.

4A-4D are plan views showing various examples of film carriers. The film carrier 58 is described in detail here. Referring to FIG. 4A, a film carrier 58 includes the insulating film 54 and the conductive wire 56, eg, copper wire, and the conductive wire 56 is on the insulating film 54. Are arranged. Typically, the conductive wire 56 is in a flexible (bentable) state in a strip shape before being packaged. In automatic production, the insulating film 54 has leading holes 80 at both ends for ease of movement of the film carrier 58. 4A shows a long lead cantilever wire. Only the outer end of the conductive wire 56 is in contact with the insulating film 54.

Referring to FIG. 4B, the film carrier 58 has a free-floating ring 82 inside the insulating film 54 and is connected to the inner end of the conductive wire 56. . Thus, the inner end of the conductive wire 56 may be positioned along the pre-floating ring 82. 4C shows a film carrier 58 having a corner supported ring 84 inside the insulating film 54. The corner support ring 84 has a corner for connection with the insulating film 54. Due to the corner support ring 84, the conductive wire 56 is firmly laid on the insulating film 54. The pre-floating ring 82 of FIG. 4B and the corner support ring 84 of FIG. 4C are both formed of an insulating material, and are preferably formed of a material constituting the insulating film. In addition, the rings 82 and 84 may both be taped to the conductive wire 56 or may be formed together with the insulating film 54.

In order to improve the fixing (fixing) of the insulating material 68 filled between the chips 50, 52 shown in FIG. 3, an improved film carrier 58 is disclosed in the present invention as shown in FIG. 4D. . The film carrier 58 includes a corner support ring 84 similar to that shown in FIG. 4C. A corner of the corner support ring 84 is formed with a locating hole 86 having a cross shape, a round shape, a square shape or another geometric shape. Although the insulating material 68 is filled between the chips 50 and 52 within the range as shown by the dashed-line frame 88 in FIG. 5, the location hole 86 is formed by the insulating material. It is filled with (68). As a result, the fixing of the insulating material 68 is improved, and the fixing effect between the chips 50 and 52 and the film carrier 58 is increased.

6A and 6B schematically illustrate a multi-chip chip scale package applied to a printed circuit board (PCB). PCB 100 typically includes a substrate 102, printed circuits 104, 106. The substrate is, for example, a multi-level printed wiring circuit board formed by lamination. The material constituting the printed wiring circuit includes, for example, a copper foil. In addition, the PCB 100 is in electrical contact with the conductive wire 56 of the film carrier 58 directly. The signal transmission path is thus shorter than in the prior art, which forms the connection between the conductive wires of the film carrier and the PCB by surface mount technology. In the present invention, the insulating material 68 is filled between the surfaces 60 and 62 of the chips 50 and 52 while the other surfaces 70 and 72 are exposed. While the packing of the chips 50, 52 is placed on the PCB 100, as shown in FIGS. 6A and 6B, the surface 72 of the chip 52 is directly connected to the printed wiring circuit. do. The surface 72 of the chip 52 is in contact with the PCB 100, increasing the heat dissipation path. For example, the surface area of the printed wiring circuit 106 may be extended through a ground wire connected on the printed wiring circuit board 100. As a result, the heat dissipation effect is improved. In addition, a heat dissipation device 108, such as a heat sink or heat spreader, is mounted on the surface 70 of the chip 50 at the distal location of the PCB. A heat dissipation pass of the chip 50 can be provided. In FIG. 6B the package is rolled over while being placed on the PCB 100.

Using the film carrier described above, chip package inspection is performed during the package process without the use of conventional KGD methods. Thus, the process cost is reduced.

In summary, the present invention includes at least the following effects.

1) The application of multi-chip chip scale packages reduces the package thickness and surface area. The size of the package is only a little larger than the size of the larger chips that are packaged.

2) The conductive wire of the film carrier is directly connected to the chip for signal transmission, which reduces the signal transmission path between the chip and the PCB and improves the chip's operating performance.

3) The present invention improves heat dissipation ability by applying a bared-chip package. Heat is dissipated through a printed circuit on a PCB, metal plate, or additionally formed heat dissipation device.

4) Package inspection is performed directly on the chip while being packaged without the conventional KGD process.

5) The formation of the position holes improves the fixation of the filled insulating material between the chip and the film carrier so that the chip is placed more firmly in the film carrier.

It will be apparent to those skilled in the art that other embodiments of the invention may be derived from the description and the embodiments disclosed herein. The detailed description and examples of the present invention are merely exemplary, and the true scope and spirit of the present invention are pointed out by the claims claimed below.

According to the multi-chip chip scale package of the present invention, the thickness and surface area of the package can be reduced, and the conductive wire of the film carrier is directly connected to the chip for signal transmission, thereby reducing the signal transmission path between the chip and the PCB The chip's operating performance is improved, and the heat-dissipation capability is improved by applying a bare-chip package, and package inspection is performed directly on the chip while being packaged without the conventional KGD process, Forming improves the fixation of the filled insulating material between the chip and the film carrier, which has the effect of placing the chip more firmly on the film carrier.

Claims (19)

With film carrier, The film carrier comprises an insulating film and a plurality of conductive wires arranged on the insulating film; A first chip having a first bump connected to said film carrier, formed on a first side having said insulating film of said film carrier; A second chip having a second bump connected to the film carrier, formed on a second side of the film carrier opposite the first side; And And an insulating material filled between the first chip and the second chip on the first side and the second side of the film carrier. The method of claim 1, And the first chip is smaller in size than the second chip. The method of claim 1, And the film carrier further comprises at least one location hole filled by the insulating material. The method of claim 1, And a pre-floating ring surrounded by the insulating film to strengthen the support of the conductive wire. The method of claim 1, And the film carrier further comprises a corner support ring surrounded by the insulation film and connected to the insulation film. The method of claim 5, And the corner support ring has a plurality of corners connected to the insulating film. The method of claim 6, Wherein each corner has at least one location hole. The method of claim 1, Wherein said first chip and said second chip each have one exposed side and the other side shielded by said insulating material. In a printed wiring board having a package arranged, The printed wiring circuit board, A substrate; And A plurality of printed wiring circuits on the substrate; The package, A film carrier, said film carrier comprising an insulating film; And a plurality of conductive wires arranged on the insulating film; A first chip having a first bump connected to said film carrier, formed on a first side having said insulating film of said film carrier; A second chip having a second bump connected to the film carrier, formed on a second side of the film carrier opposite the first side; One of the first chip and the second chip is connected on the substrate; And And an insulating material filled between the first chip and the second chip on the first side and the second side of the film carrier. The method of claim 9, One of the first chip and the second chip has a rear surface connected to at least one of the printed wiring circuits on the substrate, and the other chip has an exposed back surface Printed wiring circuit board with packages arranged. The method of claim 9, A printed wiring circuit board with a package arranged thereon, wherein a heat dissipation device is mounted on the exposed back surface. The method of claim 11, And the heat dissipation device comprises a heat spreader. The method of claim 11, And the heat dissipation device comprises a heat sink. The method of claim 9, And the insulating film includes at least one location hole filled by the insulating material. The method of claim 9, And the substrate comprises a multi-level printed wiring circuit board. The method of claim 9, And the film carrier further comprises a pre-floating ring surrounded by the insulating film to reinforce the support of the conductive wire. The method of claim 9, And the film carrier further comprises a corner support ring surrounded by the insulating film and connected to the insulating film. The method of claim 17, Wherein said corner support ring has a plurality of corners connected to said insulating film. Chip scale package. The method of claim 18, Wherein each corner has at least a location hole.