KR100639203B1 - Method for stacking a semiconductor device with plastic package and a semiconductor device with bga package - Google Patents

Method for stacking a semiconductor device with plastic package and a semiconductor device with bga package Download PDF

Info

Publication number
KR100639203B1
KR100639203B1 KR1020020039236A KR20020039236A KR100639203B1 KR 100639203 B1 KR100639203 B1 KR 100639203B1 KR 1020020039236 A KR1020020039236 A KR 1020020039236A KR 20020039236 A KR20020039236 A KR 20020039236A KR 100639203 B1 KR100639203 B1 KR 100639203B1
Authority
KR
South Korea
Prior art keywords
semiconductor device
package
bga package
plastic package
solder balls
Prior art date
Application number
KR1020020039236A
Other languages
Korean (ko)
Other versions
KR20040004979A (en
Inventor
황찬기
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020020039236A priority Critical patent/KR100639203B1/en
Publication of KR20040004979A publication Critical patent/KR20040004979A/en
Application granted granted Critical
Publication of KR100639203B1 publication Critical patent/KR100639203B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

본 발명은 플라스틱 패키지를 갖는 제1 반도체 장치와 BGA 패키지를 갖는 제2 반도체 장치를 적층하는 방법을 개시한다. 개시된 본 발명은, 다수개의 외부 리드를 구비한 플라스틱 패키지를 갖는 제1 반도체 장치와 다수개의 솔더 볼을 구비한 BGA 패키지를 갖는 제2 반도체 장치를 적층하는 방법에 있어서, 상기 플라스틱 패키지의 외부 리드들의 리드 숄더(lead shoulder)부 각각에, 대응되는 상기 BGA 패키지의 솔더 볼 각각을 접착시키는 단계; 및 상기 솔더 볼에 대해 리플로우를 수행하는 단계;를 포함하는 것을 일 특징으로 한다. 이와 같은 본 발명의 구성에 의하면, 플라스틱 패키지와 BGA 패키지를 갖는 반도체 장치를 용이하게 다층 적층할 수 있다. 또한 패키지의 구조 및 제조 공정이 단순하여 품질 및 생산성이 우수하다.The present invention discloses a method of laminating a first semiconductor device having a plastic package and a second semiconductor device having a BGA package. Disclosed is a method of stacking a first semiconductor device having a plastic package having a plurality of external leads and a second semiconductor device having a BGA package having a plurality of solder balls. Bonding each of the solder balls of the corresponding BGA package to each of the lead shoulder portions; And performing a reflow on the solder balls. According to such a structure of this invention, the semiconductor device which has a plastic package and a BGA package can be easily laminated | multilayer laminated | stacked. In addition, the package structure and manufacturing process is simple, it is excellent in quality and productivity.

플라스틱 패키지, BGA 패키지, 반도체 칩, 저층, 솔더 볼Plastic Package, BGA Package, Semiconductor Chip, Low Layer, Solder Ball

Description

플라스틱 패키지를 갖는 반도체 장치와 비지에이 패키지를 갖는 반도체 장치를 적층하는 방법{METHOD FOR STACKING A SEMICONDUCTOR DEVICE WITH PLASTIC PACKAGE AND A SEMICONDUCTOR DEVICE WITH BGA PACKAGE}A method of laminating a semiconductor device having a plastic package and a semiconductor device having a BG package {METHOD FOR STACKING A SEMICONDUCTOR DEVICE WITH PLASTIC PACKAGE AND A SEMICONDUCTOR DEVICE WITH BGA PACKAGE}

도 1은 종래의 볼 그리드 어레이 패키지의 제조 방법을 설명하는 도면.BRIEF DESCRIPTION OF THE DRAWINGS The figure explaining the manufacturing method of the conventional ball grid array package.

도 2는 종래의 플라스틱 패키지의 제조 방법을 설명하는 도면.2 is a view for explaining a manufacturing method of a conventional plastic package.

도 3은 본 발명의 제1 실시예에 의한 반도체 장치의 적층 방법을 설명하는 도면.3 is a view for explaining a lamination method for a semiconductor device according to the first embodiment of the present invention.

도 4는 본 발명의 제2 실시예에 의한 반도체 장치의 적층 방법을 설명하는 도면.4 is a diagram for explaining a lamination method for a semiconductor device according to a second embodiment of the present invention.

도 5는 본 발명의 제3 실시예에 의한 반도체 장치의 적층 방법을 설명하는 도면.Fig. 5 is a diagram for explaining a lamination method for a semiconductor device according to the third embodiment of the present invention.

도 6은 본 발명의 제4 실시예에 의한 반도체 장치의 적층 방법을 설명하는 도면.Fig. 6 is a diagram for explaining a lamination method for a semiconductor device according to the fourth embodiment of the present invention.

본 발명은 반도체 장치의 적층 방법에 관한 것으로서, 특히 플라스틱 패키지 를 갖는 반도체 장치와 비지에이 패키지를 갖는 반도체 장치를 적층하는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of laminating semiconductor devices, and more particularly, to a method of laminating a semiconductor device having a plastic package and a semiconductor device having a visual package.

전자제품의 소형화, 경량화, 고기능화, 대용량화 등의 추세에 따라 여러 유형의 반도체 장치 패키지가 개발되었는데, 이 중 대표적인 것이 플라스틱(plastic) 패키지와 볼 그리드 어레이(ball grid array : 이하, "BGA"라고 함) 패키지이다. Various types of semiconductor device packages have been developed according to the trend of miniaturization, light weight, high functionality, and large capacity of electronic products. Among them, plastic packages and ball grid arrays (hereinafter referred to as "BGA") ) Package.

먼저 도 1은 종래의 볼 그리드 어레이(ball grid array : 이하, "BGA"라고 함) 패키지의 제조 방법을 설명하는 도면이다. 먼저 도 1a에 도시되어 있는 바와 같이 인쇄 회로 기판(102) 위에 에폭시와 같은 접착제(104)를 도포하여 반도체 칩(106)을 부착시킨다. 본 명세서에서 "부착"은 용접, 접착제 등에 의해 물리적으로 연결되어 있는 경우를 가리키고, "접착"은 단순히 붙어있는 경우를 가리키는 용어로 구별되어 사용된다. 다음에는 도 1b에 도시되어 있는 바와 같이 인쇄 회로 기판(102)과 반도체 칩(106)의 전기적 연결을 위하여 금(gold) 등으로 된 와이어(108)를 본딩한다. 다음에는 도 1c에 도시되어 있는 바와 같이 반도체 칩(106)을 외부의 충격으로부터 보호하기 위하여 에폭시 몰딩 화합물(epoxy molding compound)(110)을 사용하여 몰딩(molding)을 실시한다. 다음에는 도 1d에 도시되어 있는 바와 같이 인쇄 회로 기판(102)의 아랫면(112)에 형성되어 있는 볼 랜드(116)에 플럭스(flux)를 사용하여 솔더 볼(118)을 부착시킨다. 도 1e는 솔더 볼(118)이 부착된 인쇄 회로 기판(102)의 저면도이다. First, FIG. 1 is a view for explaining a method of manufacturing a conventional ball grid array package (hereinafter, referred to as "BGA"). First, as illustrated in FIG. 1A, an adhesive 104 such as epoxy is applied onto a printed circuit board 102 to attach the semiconductor chip 106. In the present specification, "attachment" refers to a case where the connection is physically connected by welding, adhesive, or the like, and "adhesion" is used by being distinguished by a term indicating simply the case where it is attached. Next, as shown in FIG. 1B, a wire 108 made of gold or the like is bonded for electrical connection between the printed circuit board 102 and the semiconductor chip 106. Next, as illustrated in FIG. 1C, molding is performed using an epoxy molding compound 110 to protect the semiconductor chip 106 from external impact. Next, as shown in FIG. 1D, the solder balls 118 are attached to the ball lands 116 formed on the bottom surface 112 of the printed circuit board 102 using flux. 1E is a bottom view of a printed circuit board 102 with solder balls 118 attached.

도 2는 종래의 플라스틱 패키지의 제조 방법을 설명하는 도면이다. 먼저 도 2a에 도시되어 있는 바와 같이 리드프레임(202a)에 에폭시(204)를 사용하여 반도체 칩(206)을 부착시킨다. 다음에는 도 2b에 도시되어 있는 바와 같이 외부 회로와의 연결을 위한 리드프레임(202b, 202c)과 반도체 칩(206)과의 전기적 연결을 위하여 금(gold) 등으로 이루어진 와이어(208)를 본딩한다. 다음에는 도 2c에 도시되어 있는 바와 같이 에폭시 몰딩 화합물(210)을 사용하여 리드프레임(202b, 202c)의 일부만이 노출되도록 하여 몰딩하므로써 반도체 칩(206)을 외부의 충격으로부터 보호한다. 다음에는 리드프레임(202b, 202c)의 댐버(dambar)(도시되지 않음)를 제거하는 절단(trim) 공정을 통해 각각의 리드(lead)를 전기적으로 분리해 주고, 도 2d에 도시되어 있는 바와 같이 제형(form) 공정을 통해 리드(212)의 형상을 만들어 준다. 2 is a view for explaining a manufacturing method of a conventional plastic package. First, as illustrated in FIG. 2A, the semiconductor chip 206 is attached to the lead frame 202a using an epoxy 204. Next, as shown in FIG. 2B, a wire 208 made of gold or the like is bonded to electrically connect the lead frames 202b and 202c and the semiconductor chip 206 to the external circuit. . Next, as shown in FIG. 2C, only part of the lead frames 202b and 202c are exposed by using the epoxy molding compound 210 to protect the semiconductor chip 206 from external shock. Next, the leads are electrically separated through a trim process of removing the dambars (not shown) of the leadframes 202b and 202c, as shown in FIG. 2D. The shape of the lead 212 through a form (form) process.

한편 요즘에는 제한된 영역을 갖는 마더 보드(mother board)에 반도체 장치를 더욱 고밀도로 실장하거나, 반도체 장치의 성능을 최소한의 경비로 업그레이드하기 위한 노력으로 패키지된 반도체 장치를 적층하는 방법에 대한 연구가 활발히 진행되고 있다. 이러한 추세에 따라 가장 대표적인 반도체 장치의 패키지인 플라스틱 패키지, BGA 패키지를 갖는 반도체 장치를 여러 조합에 대해 효율적으로 적층하는 방법이 필요하게 되었다. On the other hand, nowadays, researches on the method of stacking the packaged semiconductor device in an effort to mount the semiconductor device more densely on a mother board having a limited area or to upgrade the performance of the semiconductor device at a minimum cost are actively conducted. It's going on. According to this trend, there is a need for a method of efficiently stacking a semiconductor device having a plastic package and a BGA package, which are the packages of the most representative semiconductor devices, in various combinations.

본 발명은 이와 같은 필요에 따라 도출된 것으로서, 플라스틱 패키지의 반도체 장치와 BGA 패키지의 반도체 장치를 필요한 만큼 용이하게 적층하는 방법을 제공함에 그 목적이 있다. The present invention has been made according to such a need, and an object thereof is to provide a method of easily stacking semiconductor devices in a plastic package and semiconductor devices in a BGA package as necessary.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 다수개의 외부 리드를 구비한 플라스틱 패키지를 갖는 제1 반도체 장치와 다수개의 솔더 볼을 구비한 BGA 패키지를 갖는 제2 반도체 장치를 적층하는 방법에 있어서, 상기 플라스틱 패키지의 외부 리드들의 리드 숄더(lead shoulder)부 각각에, 대응되는 상기 BGA 패키지의 솔더 볼 각각을 접착시키는 단계; 및 상기 솔더 볼에 대해 리플로우를 수행하는 단계;를 포함하는 반도체 장치의 적층 방법을 제공한다. In order to achieve the above object, the present invention provides a method for laminating a first semiconductor device having a plastic package having a plurality of external leads and a second semiconductor device having a BGA package having a plurality of solder balls. Bonding each of the solder balls of the corresponding BGA package to each of the lead shoulder portions of the outer leads of the plastic package; And performing a reflow on the solder balls.

바람직하게는, 상기 솔더 볼 접착 단계 이전에 상기 플라스틱 패키지의 리드 숄더부에 솔더 페이스트(solder paste)를 도팅하는 단계가 더 포함된다. 또한 상기 제2 반도체 장치에서 솔더 볼은 상기 제2 반도체 장치를 구성하는 인쇄 회로 기판의 에지(edge)에 부착된다. Preferably, prior to the solder ball bonding step further comprises the step of doping a solder paste (solder paste) in the lead shoulder portion of the plastic package. In the second semiconductor device, a solder ball is attached to an edge of a printed circuit board constituting the second semiconductor device.

또한, 본 발명은, 다수개의 외부 리드를 구비한 플라스틱 패키지를 갖는 제1 반도체 장치와 다수개의 솔더 볼을 구비한 BGA 패키지를 갖는 제2 반도체 장치를 적층하는 방법에 있어서, 상기 플라스틱 패키지의 외부 리드들의 리드 숄더(lead shoulder)부 각각에, 대응되는 상기 BGA 패키지의 솔더 볼 각각을 접착시키는 단계; 상기 솔더 볼에 대해 열압착을 수행하는 단계;를 포함하는 반도체 장치의 적층 방법을 제공한다.In addition, the present invention is a method of laminating a first semiconductor device having a plastic package having a plurality of external leads and a second semiconductor device having a BGA package having a plurality of solder balls, the external lead of the plastic package Bonding each of the solder balls of the corresponding BGA package to each of the lead shoulder portions of the field; And performing thermocompression bonding on the solder balls.

바람직하게는, 상기 솔더 볼 접착 단계 이전에 상기 리드 숄더부에 LOC 테이프를 접착시키는 단계가 더 포함된다. Preferably, the step of adhering the LOC tape to the lead shoulder portion prior to the solder ball bonding step is further included.

게다가, 본 발명은, 플라스틱 패키지를 갖는 제1 반도체 장치와, 양면에 볼 랜드(ball land)가 형성되어 있는 인쇄 회로 기판을 이용하여 형성된 BGA 패키지를 갖는 제2 반도체 장치를 적층하는 방법에 있어서, 상기 BGA 패키지의 인쇄 회로 기판에서 윗면의 볼 랜드에 솔더 볼을 부착시키는 단계; 상기 BGA 패키지 윗면의 솔더 볼에 상기 플라스틱 패키지의 외부 리드를 접착하는 단계; 및 상기 솔더 볼에 대해 리플로우를 수행하는 단계;를 포함하는 반도체 장치의 적층 방법을 제공한다.Furthermore, the present invention relates to a method of laminating a first semiconductor device having a plastic package and a second semiconductor device having a BGA package formed by using a printed circuit board having ball lands formed on both surfaces thereof. Attaching a solder ball to a ball land on an upper surface of the printed circuit board of the BGA package; Bonding an outer lead of the plastic package to a solder ball on an upper surface of the BGA package; And performing a reflow on the solder balls.

삭제delete

삭제delete

삭제delete

이와 같은 본 발명의 구성에 의하면, 플라스틱 패키지와 BGA 패키지를 갖는 반도체 장치들을 다양한 조합으로 적층할 수 있다. 또한, 패키지의 구조 및 제조 공정이 단순하여 품질 및 생산성을 향상시킬 수 있다. According to the configuration of the present invention as described above, semiconductor devices having a plastic package and a BGA package can be stacked in various combinations. In addition, the structure and manufacturing process of the package can be simplified to improve quality and productivity.

(실시예)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. 여기서, 설명의 일관성을 위하여 도면에서 동일한 참조부호는 동일 또는 유사한 구성요소를 나타내는 것으로 한다.(Example)
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to denote the same or similar elements for the sake of consistency of description.

도 3은 본 발명의 제1 실시예에 의한 반도체 장치의 적층 방법을 설명하는 도면으로서, 플라스틱 패키지를 갖는 반도체 장치 위에 BGA 패키지를 갖는 반도체 장치를 적층하는 경우이다. FIG. 3 is a view for explaining a stacking method of a semiconductor device according to a first embodiment of the present invention, in which a semiconductor device having a BGA package is stacked on a semiconductor device having a plastic package.

먼저 도 3a와 도 3b에 도시되어 있는 바와 같이 플라스틱 패키지를 갖는 반도체 장치(301)에서 패키지로부터 돌출되어 있는 외부 리드의 리드 숄더(lead shoulder)부(304)에 전기적 특성이 우수한 솔더 페이스트(solder paste)(306)를 도팅한다. 솔더 페이스트는 미세한 크기를 갖는 마이크로 솔더 볼과 플럭스(flux)로 이루어져 있다. 다음에는 도 3c에 도시되어 있는 바와 같이 반도체 장치(302)는 BGA 패키지를 가지고 있으며, 반도체 장치(302)를 구성하는 인쇄 회로 기판(308)의 아랫면의 볼 랜드(ball land)(310)에 부착되어 있는 솔더 볼(312)을 솔더 페이스트(306)에 접착시키고, 솔더 볼(312)에 대해 리플로우를 수행한다. 리드 숄더부(304)에 솔더 페이스트(306)를 도팅하고 솔더 볼(312)을 리플로우(reflow)하는 대신에 리드 온 칩(lead on chip : 이하, "LOC"라고 함) 테이프를 부착한 후에 솔더 볼(312)에 대해 열압착을 수행하여도 된다. 한편 반도체 장치(301)의 리드 숄더부(304)에 반도체 장치(302)의 솔더 볼(312)을 부착시키기 위해서는 솔더 볼(312)이 반도체 장치(302)의 에지에 형성되어 있어야 한다. First, in the semiconductor device 301 having a plastic package, as shown in FIGS. 3A and 3B, a solder paste having excellent electrical characteristics on the lead shoulder portion 304 of the external lead protruding from the package is shown. Do 306). Solder paste consists of micro solder balls and flux with fine size. Next, as shown in FIG. 3C, the semiconductor device 302 has a BGA package, and is attached to a ball land 310 on the bottom surface of the printed circuit board 308 constituting the semiconductor device 302. The solder ball 312 is adhered to the solder paste 306 and reflowed to the solder ball 312. Instead of dotting the solder paste 306 to the lead shoulder portion 304 and reflowing the solder balls 312, a lead on chip (hereinafter referred to as "LOC") tape is attached. The thermal bonding may be performed on the solder balls 312. Meanwhile, in order to attach the solder balls 312 of the semiconductor device 302 to the lead shoulder portion 304 of the semiconductor device 301, the solder balls 312 must be formed at the edge of the semiconductor device 302.

도 4는 본 발명의 제2 실시예에 의한 반도체 장치의 적층 방법을 설명하는 도면으로서, BGA 패키지를 갖는 반도체 장치(401) 위에 플라스틱 패키지를 갖는 반도체 장치(402)를 적층하는 경우이다. FIG. 4 is a view for explaining a stacking method of a semiconductor device according to a second embodiment of the present invention, in which a semiconductor device 402 having a plastic package is stacked on a semiconductor device 401 having a BGA package.

도 4에 도시되어 있는 바와 같이 반도체 장치(401)를 구성하는 인쇄 회로 기판(404)은 양면에 볼 랜드(406, 408)가 형성되어 있다. 인쇄 회로 기판(404)의 윗면에 형성되어 있는 볼 랜드(406)는 반도체 장치(402)와의 적층을 위하여 사용되고, 아랫면에 형성되어 있는 볼 랜드(408)는 마더 모듈(도시되어 있지 않음)에 실장하기 위하여 사용된다. 솔더 볼(410)은 도 4에 도시되어 있는 바와 같이 인쇄 회로 기판(404)의 윗면 볼 랜드(406)와 반도체 장치(402)의 리드(414) 사이에 부착되어 인쇄 회로 기판(404)과 리드(414)를 전기적으로 연결한다. 솔더 볼(412)은 인쇄 회로 기판(404)의 아랫면 볼 랜드(408)에 부착되어 적층된 반도체 장치(400)를 마더 보드(도시되어 있지 않음)에 실장한다. As shown in FIG. 4, ball lands 406 and 408 are formed on both surfaces of the printed circuit board 404 constituting the semiconductor device 401. The ball land 406 formed on the upper surface of the printed circuit board 404 is used for stacking with the semiconductor device 402, and the ball land 408 formed on the lower surface is mounted on a mother module (not shown). To be used. Solder balls 410 are attached between the top ball land 406 of the printed circuit board 404 and the leads 414 of the semiconductor device 402, as shown in FIG. 4, to the printed circuit board 404 and the leads. 414 is electrically connected. The solder balls 412 are attached to the bottom ball lands 408 of the printed circuit board 404 to mount the stacked semiconductor devices 400 on a motherboard (not shown).

도 5는 본 발명의 제3 실시예에 의한 반도체 장치의 적층 방법을 설명하는 도면으로서 플라스틱 패키지를 갖는 반도체 장치(501) 위에 BGA 패키지를 갖는 반도체 장치(502)를 적층하고, 다시 반도체 장치(502) 위에 BGA 패키지를 갖는 반도체 장치(503)를 적층하는 경우이다. 도 5에 도시되어 있는 바와 같이 반도체 장치(502)의 인쇄 회로 기판(505)은 양면에 솔더 볼(510, 512)을 부착하기 위한 볼 랜드(507, 508)가 형성되어 있으며, 반도체 장치(503)의 인쇄 회로 기판(506)은 아랫면에만 솔더 볼을 부착하기 위한 볼 랜드(509)가 형성되어 있다. 솔더 볼(510, 512)을 부착시키는 방법은 도 3을 참조하여 이미 설명한 바와 같다. FIG. 5 is a view for explaining a stacking method of a semiconductor device according to a third embodiment of the present invention. The semiconductor device 502 having a BGA package is stacked on the semiconductor device 501 having a plastic package, and the semiconductor device 502 is again stacked. Is a case where a semiconductor device 503 having a BGA package is stacked on the substrate). As shown in FIG. 5, the printed circuit board 505 of the semiconductor device 502 includes ball lands 507 and 508 for attaching solder balls 510 and 512 to both surfaces thereof, and the semiconductor device 503. Of the printed circuit board 506 is formed with a ball land 509 for attaching solder balls only to the bottom surface thereof. The method of attaching the solder balls 510 and 512 is as described above with reference to FIG. 3.

도 6은 본 발명의 제4 실시예에 의한 반도체 장치의 적층 방법을 설명하는 도면으로서 플라스틱 패키지를 갖는 반도체 장치(601) 위에 BGA 패키지를 갖는 반도체 장치(602)를 적층하고, 반도체 장치(602) 위에 BGA 패키지를 갖는 반도체 장치(603)를 적층하고, 다시 반도체 장치(603) 위에 BGA 패키지를 갖는 반도체 장치(604)를 적층한 경우이다. FIG. 6 is a view for explaining a stacking method of a semiconductor device according to a fourth embodiment of the present invention. The semiconductor device 602 having a BGA package is stacked on the semiconductor device 601 having a plastic package, and the semiconductor device 602 is stacked. This is the case where the semiconductor device 603 having the BGA package is stacked on top, and the semiconductor device 604 having the BGA package is stacked on the semiconductor device 603 again.

인쇄 회로 기판(608)은 양면에 솔더 볼을 부착하기 위한 볼 랜드(614, 616)를 구비하고, 인쇄 회로 기판(610) 역시 양면에 볼 랜드(618, 620)를 구비하고 있다. 그러나 인쇄 회로 기판(612)은 반도체 칩이 장착되는 윗면에만 볼 랜드(622)가 구비되어도 된다. 반도체 장치(603) 위에 반도체 장치(604)를 적층할 때는 인쇄 회로 기판(610, 612)의 윗면이 서로 마주보도록 하여 각자의 윗면에 부착된 솔더 볼(628, 630)을 접착시킨 후, 솔더 볼(628, 630)에 대해 리플로우 또는 열압착을 수행하여 솔더 볼(628, 630)을 서로 부착시킨다. The printed circuit board 608 includes ball lands 614 and 616 for attaching solder balls to both sides, and the printed circuit board 610 also includes ball lands 618 and 620 on both sides. However, the printed circuit board 612 may be provided with the ball land 622 only on the upper surface on which the semiconductor chip is mounted. When the semiconductor device 604 is stacked on the semiconductor device 603, the upper surfaces of the printed circuit boards 610 and 612 face each other to bond the solder balls 628 and 630 attached to the upper surfaces thereof, and then the solder balls. Reflow or thermocompression is performed on 628 and 630 to attach solder balls 628 and 630 to each other.

여기서 설명된 실시예들은 본 발명을 당업자가 용이하게 이해하고 실시할 수 있도록 하기 위한 것일 뿐이며, 본 발명의 범위를 한정하려는 것은 아니다. 따라서 당업자들은 본 발명의 범위 안에서 다양한 변형이나 변경이 가능함을 주목하여야 한다. 본 발명의 범위는 원칙적으로 후술하는 특허청구범위에 의하여 정하여진다.The embodiments described herein are merely intended to enable those skilled in the art to easily understand and practice the present invention, and are not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications or changes are possible within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.

이와 같은 본 발명의 구성에 의하면 플라스틱 패키지, BGA 패키지를 갖는 반도체 장치의 여러 조합을 용이하게 다층 적층할 수 있다. 또한 패키지의 구조 및 제조 공정이 단순하여 품질 및 생산성이 우수하다.According to the configuration of the present invention as described above, various combinations of a semiconductor package having a plastic package and a BGA package can be easily laminated in multiple layers. In addition, the package structure and manufacturing process is simple, it is excellent in quality and productivity.

Claims (9)

다수개의 외부 리드를 구비한 플라스틱 패키지를 갖는 제1 반도체 장치와 다수개의 솔더 볼을 구비한 BGA 패키지를 갖는 제2 반도체 장치를 적층하는 방법에 있어서,A method of laminating a first semiconductor device having a plastic package with a plurality of external leads and a second semiconductor device having a BGA package with a plurality of solder balls, the method comprising: 상기 플라스틱 패키지의 외부 리드들의 리드 숄더(lead shoulder)부 각각에, 대응되는 상기 BGA 패키지의 솔더 볼 각각을 접착시키는 단계; 및 Bonding each solder ball of the corresponding BGA package to each of the lead shoulder portions of the outer leads of the plastic package; And 상기 솔더 볼에 대해 리플로우를 수행하는 단계;Performing a reflow on the solder balls; 를 포함하는 것을 특징으로 하는 반도체 장치의 적층 방법.Laminating method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 솔더 볼 접착 단계 이전에 상기 플라스틱 패키지의 리드 숄더부에 솔더 페이스트(solder paste)를 도팅하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 적층 방법.And soldering solder paste to a lead shoulder portion of the plastic package prior to the solder ball bonding step. 제 1 항에 있어서,The method of claim 1, 상기 제2 반도체 장치에서 솔더 볼은 상기 제2 반도체 장치를 구성하는 인쇄 회로 기판의 에지(edge)에 부착되어 있는 것을 특징으로 하는 반도체 장치의 적층 방법.In the second semiconductor device, a solder ball is attached to an edge of a printed circuit board constituting the second semiconductor device. 다수개의 외부 리드를 구비한 플라스틱 패키지를 갖는 제1 반도체 장치와 다수개의 솔더 볼을 구비한 BGA 패키지를 갖는 제2 반도체 장치를 적층하는 방법에 있어서,A method of laminating a first semiconductor device having a plastic package with a plurality of external leads and a second semiconductor device having a BGA package with a plurality of solder balls, the method comprising: 상기 플라스틱 패키지의 외부 리드들의 리드 숄더(lead shoulder)부 각각에, 대응되는 상기 BGA 패키지의 솔더 볼 각각을 접착시키는 단계; Bonding each solder ball of the corresponding BGA package to each of the lead shoulder portions of the outer leads of the plastic package; 상기 솔더 볼에 대해 열압착을 수행하는 단계;Performing thermocompression on the solder balls; 를 포함하는 것을 특징으로 하는 반도체 장치의 적층 방법.Laminating method of a semiconductor device comprising a. 제 4 항에 있어서,The method of claim 4, wherein 상기 솔더 볼 접착 단계 이전에 상기 리드 숄더부에 LOC 테이프를 접착시키는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 적층 방법.Adhering a LOC tape to the lead shoulder portion prior to the solder ball bonding step. 플라스틱 패키지를 갖는 제1 반도체 장치와, 양면에 볼 랜드(ball land)가 형성되어 있는 인쇄 회로 기판을 이용하여 형성된 BGA 패키지를 갖는 제2 반도체 장치를 적층하는 방법에 있어서,1. A method of laminating a first semiconductor device having a plastic package and a second semiconductor device having a BGA package formed by using a printed circuit board having ball lands formed on both surfaces thereof. 상기 BGA 패키지의 인쇄 회로 기판에서 윗면의 볼 랜드에 솔더 볼을 부착시키는 단계; Attaching a solder ball to a ball land on an upper surface of the printed circuit board of the BGA package; 상기 BGA 패키지 윗면의 솔더 볼에 상기 플라스틱 패키지의 외부 리드를 접착하는 단계; 및 Bonding an outer lead of the plastic package to a solder ball on an upper surface of the BGA package; And 상기 솔더 볼에 대해 리플로우를 수행하는 단계;Performing a reflow on the solder balls; 를 포함하는 것을 특징으로 하는 반도체 장치의 적층 방법.Laminating method of a semiconductor device comprising a. 삭제delete 삭제delete 삭제delete
KR1020020039236A 2002-07-08 2002-07-08 Method for stacking a semiconductor device with plastic package and a semiconductor device with bga package KR100639203B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020020039236A KR100639203B1 (en) 2002-07-08 2002-07-08 Method for stacking a semiconductor device with plastic package and a semiconductor device with bga package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020020039236A KR100639203B1 (en) 2002-07-08 2002-07-08 Method for stacking a semiconductor device with plastic package and a semiconductor device with bga package

Publications (2)

Publication Number Publication Date
KR20040004979A KR20040004979A (en) 2004-01-16
KR100639203B1 true KR100639203B1 (en) 2006-10-30

Family

ID=37315358

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020039236A KR100639203B1 (en) 2002-07-08 2002-07-08 Method for stacking a semiconductor device with plastic package and a semiconductor device with bga package

Country Status (1)

Country Link
KR (1) KR100639203B1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613541A (en) * 1992-03-02 1994-01-21 Motorola Inc Three-dimensional multichip semiconductor device which can be laminated and manufacture thereof
JPH08125118A (en) * 1994-10-21 1996-05-17 Hitachi Ltd Semiconductor integrated circuit
KR20010046110A (en) * 1999-11-10 2001-06-05 밍-퉁 센 Semiconductor chip module
KR20010063032A (en) * 1999-12-21 2001-07-09 유-행 치아오 Stack-up package frame
KR20010099298A (en) * 2001-09-20 2001-11-09 신이술 Mehod of stacking a semiconductor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613541A (en) * 1992-03-02 1994-01-21 Motorola Inc Three-dimensional multichip semiconductor device which can be laminated and manufacture thereof
JPH08125118A (en) * 1994-10-21 1996-05-17 Hitachi Ltd Semiconductor integrated circuit
KR20010046110A (en) * 1999-11-10 2001-06-05 밍-퉁 센 Semiconductor chip module
KR20010063032A (en) * 1999-12-21 2001-07-09 유-행 치아오 Stack-up package frame
KR20010099298A (en) * 2001-09-20 2001-11-09 신이술 Mehod of stacking a semiconductor

Also Published As

Publication number Publication date
KR20040004979A (en) 2004-01-16

Similar Documents

Publication Publication Date Title
US6093969A (en) Face-to-face (FTF) stacked assembly of substrate-on-bare-chip (SOBC) modules
JP3063032B2 (en) Ball grid array type semiconductor package and method of manufacturing the same
US7679178B2 (en) Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof
KR100608608B1 (en) Semiconductor chip package having bonding pad structure of mixing type and manufacturing method thereof
KR100716871B1 (en) Carrier frame for semiconductor package and semiconductor package using it and its manufacturing method
US7119425B2 (en) Stacked multi-chip semiconductor package improving connection reliability of stacked chips
JP5227501B2 (en) Stack die package and method of manufacturing the same
US5894107A (en) Chip-size package (CSP) using a multi-layer laminated lead frame
JP2005045251A (en) Stacked-semiconductor-chip bga package and method for manufacturing the same
KR100265566B1 (en) Ship stack package
US6574858B1 (en) Method of manufacturing a chip package
KR20020061812A (en) Ball grid array type multi chip package and stack package
US7573131B2 (en) Die-up integrated circuit package with grounded stiffener
US6855573B2 (en) Integrated circuit package and manufacturing method therefor with unique interconnector
US5559305A (en) Semiconductor package having adjacently arranged semiconductor chips
US5889333A (en) Semiconductor device and method for manufacturing such
JP2003086760A (en) Semiconductor device and manufacturing method therefor
JP2006190834A (en) Semiconductor package and flexible circuit board
US7154171B1 (en) Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
KR100639203B1 (en) Method for stacking a semiconductor device with plastic package and a semiconductor device with bga package
KR100443516B1 (en) Stack package and manufacturing method thereof
JP2007221133A (en) Integrated circuit package
KR100650049B1 (en) Assembly-stacked package using multichip module
KR20020028473A (en) Stack package
KR100612761B1 (en) Chip scale stack chip package

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
J201 Request for trial against refusal decision
AMND Amendment
B701 Decision to grant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100920

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee