KR20030055835A - Package stacking structure - Google Patents

Package stacking structure Download PDF

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Publication number
KR20030055835A
KR20030055835A KR1020010085927A KR20010085927A KR20030055835A KR 20030055835 A KR20030055835 A KR 20030055835A KR 1020010085927 A KR1020010085927 A KR 1020010085927A KR 20010085927 A KR20010085927 A KR 20010085927A KR 20030055835 A KR20030055835 A KR 20030055835A
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South Korea
Prior art keywords
package
substrate
stacked
semiconductor chips
lead
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KR1020010085927A
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Korean (ko)
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이규진
김진호
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삼성전자주식회사
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Priority to KR1020010085927A priority Critical patent/KR20030055835A/en
Publication of KR20030055835A publication Critical patent/KR20030055835A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE: A package stacking structure is provided to stack two to six semiconductor chips on a substrate by stacking a lead type package on a semiconductor package mounted on the substrate. CONSTITUTION: A package stacking structure includes a substrate(30), the first package(40), a connective substrate(60), and the second package(50). The first package has an external connection terminal mounted on one side of the substrate. The connective substrate is formed on the substrate of the outside of the first package. The second package includes a lead mounted on an upper portion of the connective substrate. The connective substrate includes a body(62), a contact pad(63), and a connection pad(65). The contact pad is electrically connected to the first package. The connection pad is electrically connected to the contact pad.

Description

패키지 적층 구조{Package stacking structure}Package stacking structure

본 발명은 한 개 내지 세 개 정도의 반도체 칩이 적층된 반도체 패키지가 기판 적층된 패키지 적층 구조에 관한 것이다.The present invention relates to a package stack structure in which a semiconductor package in which one or three semiconductor chips are stacked is stacked on a substrate.

전자기기의 경박단소화 추세에 따라 반도체 칩을 탑재하는 패키징 기술도 고속, 고기능, 고밀도 실장이 요구되고 있다. 이러한 요구에 따라 최근 반도체 칩을 최소한의 공간상에 패키징하는 멀티 칩 패키지(Multi Chip Package; MCP)나 칩 스케일 패키지(Chip Scale Package; CSP)가 주류를 이루고 있다.In accordance with the trend toward lighter and shorter electronic devices, packaging technology for mounting semiconductor chips is also required for high speed, high performance, and high density mounting. In response to these demands, a multi chip package (MCP) or a chip scale package (CSP) for packaging a semiconductor chip in a minimal space has become mainstream in recent years.

예컨대, 도 1에 도시된 바와 같이, 두 개의 반도체 칩(12)을 리드 프레임(14)의 다이 패드(16)에 적층하여 적층 칩 패키지(10)를 구현할 수 있다. 이때, 상대적으로 상부에 위치하는 반도체 칩은 상대적으로 하부에 위치하는 반도체 칩보다는 크기가 작아야 한다.For example, as illustrated in FIG. 1, two semiconductor chips 12 may be stacked on the die pad 16 of the lead frame 14 to implement the stacked chip package 10. In this case, the semiconductor chip positioned relatively on the upper side should be smaller than the semiconductor chip positioned relatively on the lower side.

그리고 최근에 와서는 두 개의 반도체 칩을 적층하는 것을 넘어 3 내지 6개 정도의 반도체 칩을 적층하는 경우도 있다. 예컨대, 도 2에 도시된 바와 같이, 네 개의 반도체 칩(22)을 기판(24)에 적층하여 멀티 칩 패키지(20)를 구현할 수 있다.본 실시예에서는 기판(24)의 상부에 적층된 두 개의 반도체 칩은 크기가 동일하며, 크기가 동일한 두 개의 반도체 칩 위에 적층되는 반도체 칩 두 개는 위로 올라갈수록 크기가 작은 반도체 칩이 적층되어 있다.In recent years, three to six semiconductor chips may be stacked beyond two semiconductor chips. For example, as illustrated in FIG. 2, four semiconductor chips 22 may be stacked on a substrate 24 to implement a multi-chip package 20. In this embodiment, the two stacked chips are stacked on top of the substrate 24. The two semiconductor chips have the same size, and the two semiconductor chips stacked on the two semiconductor chips having the same size are stacked with smaller semiconductor chips as they go up.

그러나 이와 같이 4개 이상의 반도체 칩들(22)이 적층된 멀티 칩 패키지(20)의 경우, 반도체 칩들(22)이 적층되는 기판(24)의 라우팅(routing)에 문제가 발생될 수 있다. 또한 적층되는 반도체 칩들(22)의 크기의 차이로 인한 적층상의 문제 예컨대, 본딩 와이어(28)의 길이가 길어져 본딩 와이어(28) 사이의 전기적 쇼트 문제, 통상적인 와이어 본딩 방식과 더불어 역 와이어 본딩 방식을 동시에 사용해야 하는 문제, 반도체 칩(22)을 적층할 때 사용되는 접착제가 반도체 칩922)의 활성면에 형성된 전극 패드 영역을 오염시키는 문제 등이 발생될 수 있다.However, in the multi-chip package 20 in which four or more semiconductor chips 22 are stacked in this manner, a problem may occur in the routing of the substrate 24 on which the semiconductor chips 22 are stacked. In addition, the stacking problem due to the difference in the size of the semiconductor chips 22 to be stacked, for example, the length of the bonding wire 28 is long, the electrical short between the bonding wires 28, in addition to the conventional wire bonding method in addition to the reverse wire bonding method May be used at the same time, or the adhesive used when the semiconductor chip 22 is stacked may contaminate the electrode pad region formed on the active surface of the semiconductor chip 922.

그리고 적층되는 반도체 칩(22)의 수가 증가할수록 멀티 칩 패키지(20)의 수율이 떨어지는 문제점을 안고 있다. 즉, 테스트 공정 진행시 적층된 반도체 칩(22) 중에서 적어도 하나의 반도체 칩(22)이 불량을 경우 멀티 칩 패키지(20)는 불량으로 처리된다.As the number of stacked semiconductor chips 22 increases, the yield of the multi-chip package 20 falls. That is, when at least one semiconductor chip 22 of the stacked semiconductor chips 22 is defective during the test process, the multi-chip package 20 is treated as defective.

또한, 제조된 멀티 칩 패키지(20)에 대한 테스트 공정 시간이 적층된 반도체 칩(22) 수에 비례하여 증가하기 때문에, 생산성이 떨어지는 문제점을 안고 있다.In addition, since the test process time for the manufactured multi-chip package 20 increases in proportion to the number of stacked semiconductor chips 22, there is a problem in that productivity is lowered.

따라서, 본 발명의 목적은 4개 이상의 반도체 칩을 하나의 패키징화에 따른 문제점을 극복할 수 있는 패키지 적층 구조를 제공하는 데 있다.Accordingly, an object of the present invention is to provide a package stack structure that can overcome the problems caused by packaging four or more semiconductor chips.

도 1은 종래기술에 따른 두 개의 반도체 칩이 적층된 리드 프레임을 이용한 적층 칩 패키지를 보여주는 단면도이다.1 is a cross-sectional view illustrating a laminated chip package using a lead frame in which two semiconductor chips according to the prior art are stacked.

도 2는 종래기술에 따른 다수개의 반도체 칩이 적층된 볼 그리드 어레이 타입의 적층 칩 패키지를 보여주는 단면도이다.2 is a cross-sectional view illustrating a stacked chip package of a ball grid array type in which a plurality of semiconductor chips according to the related art are stacked.

도 3은 본 발명의 제 1 실시예에 따른 볼 그리드 어레이 패키지 위에 리드 프레임 타임의 패키지가 연결 기판을 매개로 기판에 적층된 구조를 보여주는 도면이다.FIG. 3 is a view illustrating a structure in which a lead frame time package is stacked on a substrate via a connecting substrate on the ball grid array package according to the first embodiment of the present invention.

도 4는 본 발명의 제 2 실시예에 따른 두 개의 리드 프레임 타입의 패키지가 연결 기판을 매개로 기판에 적층된 구조를 보여주는 도면이다.4 is a view illustrating a structure in which two lead frame type packages according to a second embodiment of the present invention are stacked on a substrate via a connecting substrate.

도 5는 본 발명의 제 3 실시예에 따른 랜드 그리드 어레이 타입의 패키지 위에 리드 프레임 타임의 패키지가 연결 기판을 매개로 기판에 적층된 구조를 보여주는 도면이다.FIG. 5 is a view illustrating a structure in which a lead frame time package is stacked on a substrate via a connecting substrate on a land grid array type package according to a third embodiment of the present invention.

* 도면의 주요 부분에 대한 설명 *Description of the main parts of the drawing

30, 130, 230 : 기판30, 130, 230: substrate

40 : BGA 패키지40: BGA Package

50, 140, 150, 250 : 리드 타입의 패키지50, 140, 150, 250: lead type package

60, 160, 260 : 연결 기판60, 160, 260: connecting board

62 : 기판 몸체62: substrate body

64 : 배선 패턴64: wiring pattern

240 : LGA 패키지240: LGA Package

상기 목적을 달성하기 위하여, 본 발명은 1개 내지 3개의 반도체 칩이 적층된 반도체 패키지를 기판에 적층하여 4개 이상의 반도체 칩이 적층된 멀티 패키지를 기판에 실장한 것과 같은 패키지 적층 구조를 제공한다.In order to achieve the above object, the present invention provides a package stacking structure in which a semiconductor package in which one to three semiconductor chips are stacked is stacked on a substrate to mount a multi-package in which four or more semiconductor chips are stacked on a substrate. .

본 발명의 바람직한 실시 양태에 있어서, 1개 내지 3개의 반도체 칩이 적층된 패키지를 기판에 적층한 패키지 적층 구조로, 기판과; 상기 기판의 일면에 실장되는 외부접속단자가 형성된 제 1 패키지와; 상기 제 1 패키지 외측의 상기 기판에 형성된 연결 기판과; 리드가 상기 연결 기판의 상부에 실장되며 하부면이 상기 제 1 패키지의 상부면에 근접하게 설치되는 제 2 패키지;를 포함하며,In a preferred embodiment of the present invention, there is provided a package stacking structure in which a package in which one to three semiconductor chips are stacked is stacked on a substrate, the substrate; A first package having an external connection terminal mounted on one surface of the substrate; A connection substrate formed on the substrate outside the first package; And a second package having a lead mounted on an upper portion of the connection substrate and having a lower surface proximate to an upper surface of the first package.

상기 연결 기판은, 기판 몸체와; 상기 기판 몸체의 양면에 형성된 배선 패턴으로, 상기 기판 몸체의 하부면에 형성되어 상기 기판에 접속되어 상기 기판과 제 1 패키지와 전기적으로 연결되는 접속 패드와, 상기 기판 몸체의 상부면에 형성되며 상기 제 2 패키지의 리드가 접속되며, 상기 접속 패드와 전기적으로 연결된 연결 패드를 포함하는 것을 특징으로 하는 패키지 적층 구조를 제공한다.The connecting substrate includes a substrate body; A wiring pattern formed on both sides of the substrate body, the connection pad being formed on a lower surface of the substrate body and connected to the substrate and electrically connected to the substrate and the first package, and formed on an upper surface of the substrate body; The lead of the second package is connected, and provides a package stack structure comprising a connection pad electrically connected to the connection pad.

본 발명에 따른 제 1 패키지는 볼 그리드 어레이(BGA) 타입, 리드 타입 또는 랜드 그리드 어레이(LGA) 타입의 패키지가 사용될 수 있다.The first package according to the present invention may be a ball grid array (BGA) type, lead type or land grid array (LGA) type package.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 3은 본 발명의 제 1 실시예에 따른 볼 그리드 어레이(Ball Grid Array; BGA) 패키지(40) 위에 리드 타입의 패키지(50)가 기판(30)에 적층된 구조를 보여주는 도면이다. 도 3을 참조하면, 본 발명의 제 1 실시예에 따른 패키지 적층 구조는 기판(30) 위에 BGA 패키지(40)가 실장되고, BGA 패키지(40) 위에 리드 타입의 패키지(50)가 적층되고, 리드 타입의 패키진(50)은 연결 기판(60)을 매개로 기판(30)과 전기적으로 연결된 구조를 갖는다. 이때, BGA 패키지의 솔더 볼(42)이 기판의 기판 패드(32a)에 융착되어 실장된다. 그리고, BGA 패키지(40) 및 리드 타입의 패키지(50)는 1개 내지 3개의 반도체 칩이 적층된 멀티 칩 패키지이다.3 is a view showing a structure in which a lead type package 50 is stacked on a substrate 30 on a ball grid array (BGA) package 40 according to a first embodiment of the present invention. Referring to FIG. 3, in the package stacking structure according to the first embodiment of the present invention, a BGA package 40 is mounted on a substrate 30, and a lead type package 50 is stacked on the BGA package 40. The lead-type package 50 has a structure electrically connected to the substrate 30 via the connection substrate 60. At this time, the solder ball 42 of the BGA package is fused and mounted on the substrate pad 32a of the substrate. The BGA package 40 and the lead type package 50 are multi-chip packages in which one to three semiconductor chips are stacked.

따라서, 본 발명의 제 1 실시예에서는 1개 내지 3개의 반도체 칩이 적층된 패키지(40, 50)를 적층함으로써, 2개 내지 6개의 반도체 칩을 기판(60)에 적층할 수 있다. 즉, 본 발명에 따른 패키지 적층 구조는 1개의 반도체 칩이 실장된 패키지들을 적층하는 것에 비해서 두께를 얇게 가져갈 수 있고, 여러개의 반도체 칩이 실장된 멀티 칩 패키지에서 적층되는 반도체 칩이 증가할수록 발생될 수 있는 불량율의 증가를 줄일 수 있다.Therefore, in the first embodiment of the present invention, two to six semiconductor chips can be stacked on the substrate 60 by stacking packages 40 and 50 in which one to three semiconductor chips are stacked. That is, the package stacking structure according to the present invention may have a thinner thickness than that of stacking packages in which one semiconductor chip is mounted, and may be generated as the number of semiconductor chips stacked in a multi-chip package in which several semiconductor chips are mounted increases. It is possible to reduce the increase of the defective rate.

특히, 연결 기판(60)은 리드 타입의 패키지(50)가 BGA 패키지(40) 위에 적층될 때, 리드 타입의 패키지의 리드(52)와 기판의 기판 패드(32b)를 연결하는 전기적 연결 수단이다. 즉, 연결 기판(60)을 사용함으로써, 리드 타입의 패키지(50)를 제조할 때 리드(52)를 길게 형성할 필요가 없이 통상적인 타입의 패키지로 제조하면 된다. 연결 기판(60)은 기판 몸체(62)와 기판 몸체(62)에 형성된 배선 패턴(64)을 포함한다. 배선 패턴(64)은 기판 몸체(62)의 하부면에 형성되어 기판의 기판 패드(32b)와 각기 접합되는 접속 패드(63)와, 기판 몸체(62)의 상부면에 형성되며 리드 타입의 패키지의 리드(52)와 각기 접합되는 연결 패드(65)를 포함하며, 접속 패드(63)와 연결 패드(65)는 기판 몸체(62)를 관통하여 형성된 비아(67)를 통하여 전기적으로 연결된다. 그리고 연결 기판(60)은 BGA 패키지(40)와 리드 타입의 패키지(50)가 기판(30)에 적층된 상태에서, 리드(52)의 말단과 기판(30)의 상부면 사이의 높이보다는 두껍게 형성하는 것이 바람직하다.In particular, the connecting substrate 60 is an electrical connecting means for connecting the lead 52 of the lead type package and the substrate pad 32b of the substrate when the lead type package 50 is stacked on the BGA package 40. . That is, by using the connection board 60, when manufacturing the lead type package 50, it is not necessary to form the lead 52 long, and it is good to manufacture it by the package of a normal type. The connection substrate 60 includes a substrate body 62 and a wiring pattern 64 formed on the substrate body 62. The wiring pattern 64 is formed on the lower surface of the substrate body 62 to be connected to the substrate pad 32b of the substrate, respectively, and the connection pad 63 is formed on the upper surface of the substrate body 62. The connecting pads 65 are connected to the leads 52, respectively, and the connecting pads 63 and the connecting pads 65 are electrically connected through the vias 67 formed through the substrate body 62. The connecting substrate 60 is thicker than the height between the end of the lead 52 and the upper surface of the substrate 30 in a state in which the BGA package 40 and the lead type package 50 are stacked on the substrate 30. It is preferable to form.

한편, 본 발명에 따른 연결 기판(60)은 기판 몸체(62)의 양면에 배선 패턴(64)이 형성된 2층의 배선 기판으로 구현하지만, 기판 몸체의 내부에 적어도 한 층 이상의 내부 배선 패턴이 형성된 다층의 배선 기판으로 구현할 수 있다. 물론, 기판 몸체의 양면에 형성된 배선 패턴과 내부 배선 패턴은 비아를 통하여 전기적으로 연결된다.On the other hand, the connection board 60 according to the present invention is implemented as a two-layer wiring board having wiring patterns 64 formed on both sides of the substrate body 62, but at least one internal wiring pattern is formed inside the substrate body. It can be implemented with a multilayer wiring board. Of course, the wiring patterns and the internal wiring patterns formed on both sides of the substrate body are electrically connected through the vias.

본 발명의 제 1 실시예에서는 연결 기판(60)을 매개로 BGA 패키지(40) 위에 리드 타입의 패키지(50)가 적층된 구조로 구현하였지만, BGA 패키지(40) 대신에 도 4에 도시된 바와 같이, 리드 타입의 패키지(140)를 사용할 수도 있다. 이때, 기판(130) 바로 위에 실장되는 리드 타입의 패키지(140; 이하, 제 1 패키지)는 제 1 패키지(140) 위에 적층되는 리드 타입의 패키지(150; 이하, 제 2 패키지라 한다)의 리드(152)가 접합되는 연결 기판(160) 사이의 기판 영역에 실장될 수 있는 크기를 갖는다. 물론, 제 1 및 제 2 패키지(140, 150)는 1 내지 3개의 반도체 칩이 적층된 멀티 칩 패키지이다.In the first exemplary embodiment of the present invention, the lead type package 50 is stacked on the BGA package 40 via the connection board 60, but as shown in FIG. 4 instead of the BGA package 40. Similarly, a lead type package 140 may be used. In this case, the lead-type package 140 (hereinafter, referred to as a first package) mounted directly on the substrate 130 may be a lead of the lead-type package 150 (hereinafter referred to as a second package) stacked on the first package 140. 152 has a size that can be mounted in a substrate region between connecting substrates 160 to which it is bonded. Of course, the first and second packages 140 and 150 are multi-chip packages in which one to three semiconductor chips are stacked.

또는 도 5에 도시된 바와 같이, 제 3 실시예에 따른 패키지 적층 구조는 제 1 실시예에 따른 BGA 패키지 대신에 랜드 그리드 어레이(Land Grid Array; LGA) 패키지(240)가 기판(230)에 실장된 구조를 갖는다. 물론, LGA 패키지(230)는 리드 타입의 패키지(250)의 리드(252)가 접합되는 연결 기판(260) 사이의 기판 영역에실장될 수 있는 크기를 갖는다.Alternatively, as shown in FIG. 5, in the package stacking structure according to the third embodiment, a land grid array (LGA) package 240 is mounted on the substrate 230 instead of the BGA package according to the first embodiment. Has a structure. Of course, the LGA package 230 has a size that can be mounted in the substrate region between the connection substrate 260 to which the leads 252 of the lead type package 250 are bonded.

한편, 본 명세서와 도면에 개시된 본 발명의 실시예들은 이해를 돕기 위해 특정 예를 제시한 것에 지나지 않으며, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예들 이외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명한 것이다.On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention may be implemented.

따라서, 본 발명의 구조를 따르면 소정 유형의 1개 내지 3개의 반도체 칩이 적층된 반도체 패키지를 기판에 실장한 다음, 그 반도체 패키지 위에 1개 내지 3개의 반도체 칩이 적층된 리드 타입의 패키지를 적층하여 리드 타입의 패키지의 리드와 기판 사이에 연결 기판을 매개시켜 전기적으로 연결함으로써, 2개 내지 6개의 반도체 칩을 기판 상에 적층할 수 있다.Therefore, according to the structure of the present invention, a semiconductor package in which one to three semiconductor chips of a predetermined type are stacked is mounted on a substrate, and then a lead type package in which one to three semiconductor chips are stacked is stacked on the semiconductor package. Therefore, two to six semiconductor chips may be stacked on the substrate by electrically connecting the lead between the lead of the package of the lead type package and the substrate.

그리고, 1개 내지 3개의 반도체 칩이 적층된 반도체 패키지를 기판 적층함으로써, 하나의 패키지에 적층되는 반도체 칩이 늘어남으로써 발생될 수 있는 불량율을 줄일 수 있다.In addition, by stacking a semiconductor package in which one to three semiconductor chips are stacked on a substrate, a defective rate that may be generated by increasing the number of semiconductor chips stacked in one package may be reduced.

Claims (4)

1개 내지 3개의 반도체 칩이 적층된 패키지를 기판에 적층한 패키지 적층 구조로,A package stack structure in which a package in which one to three semiconductor chips are stacked is stacked on a substrate. 기판과;A substrate; 상기 기판의 일면에 실장되는 외부접속단자가 형성된 제 1 패키지와;A first package having an external connection terminal mounted on one surface of the substrate; 상기 제 1 패키지 외측의 상기 기판에 형성된 연결 기판과;A connection substrate formed on the substrate outside the first package; 리드가 상기 연결 기판의 상부에 실장되며 하부면이 상기 제 1 패키지의 상부면에 근접하게 설치되는 제 2 패키지;를 포함하며,And a second package having a lead mounted on an upper portion of the connection substrate and having a lower surface proximate to an upper surface of the first package. 상기 연결 기판은,The connecting substrate, 기판 몸체와;A substrate body; 상기 기판 몸체의 양면에 형성된 배선 패턴으로, 상기 기판 몸체의 하부면에 형성되어 상기 기판에 접속되어 상기 기판과 제 1 패키지와 전기적으로 연결되는 접속 패드와, 상기 기판 몸체의 상부면에 형성되며 상기 제 2 패키지의 리드가 접속되며, 상기 접속 패드와 전기적으로 연결된 연결 패드를 포함하는 것을 특징으로 하는 패키지 적층 구조.A wiring pattern formed on both sides of the substrate body, the connection pad being formed on a lower surface of the substrate body and connected to the substrate and electrically connected to the substrate and the first package, and formed on an upper surface of the substrate body; And a connection pad to which the leads of the second package are connected and electrically connected to the connection pads. 제 1항에 있어서, 상기 제 1 패키지는 볼 그리드 어레이(BGA) 타입, 리드 타입 또는 랜드 그리드 어레이(LGA) 타입의 패키지인 것을 특징으로 하는 패키지 적층 구조.2. The package stack structure of claim 1, wherein the first package is a ball grid array (BGA) type, lead type or land grid array (LGA) type package. 제 1항에 있어서, 상기 접속 패드와 연결 패드는 상기 기판 몸체를 관통하여 형성된 비아를 통하여 전기적으로 연결된 것을 특징으로 하는 패키지 적층 구조.The package stack structure of claim 1, wherein the connection pads and the connection pads are electrically connected through vias formed through the substrate body. 제 3항에 있어서, 상기 배선 패턴은 상기 기판 몸체 안에 형성된 적어도 한 층 이상의 내부 배선 패턴을 더 포함하며, 상기 접속 패드, 내부 배선 패턴 및 연결 패드는 비아를 통하여 전기적으로 연결된 것을 특징으로 하는 패키지 적층 구조.The package stack of claim 3, wherein the wiring pattern further comprises at least one internal wiring pattern formed in the substrate body, wherein the connection pad, the internal wiring pattern, and the connection pad are electrically connected through vias. rescue.
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Publication number Priority date Publication date Assignee Title
KR20030057186A (en) * 2001-12-28 2003-07-04 동부전자 주식회사 semiconductor package and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030057186A (en) * 2001-12-28 2003-07-04 동부전자 주식회사 semiconductor package and its manufacturing method

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