TW200834844A - Multi-chip face-to-face stack package - Google Patents

Abstract

A multi-chip face-to face stack package mainly comprises a substrate, a first chip, a second chip, a plurality of first bumps, a plurality of second bumps and a plurality of external terminals disposed on the substrate. The substrate has a plurality of first bump holes and a plurality of second bump holes. The active surface of the first chip is attached to a first surface of the substrate. The first bumps are located in the first bump holes respectively to electrically connect the first chip with the substrate. The active surface of the second chip is attached to a second surface of the substrate. The second bumps are located in the second bump holes respectively to electrically connect the second chip with the substrate. Accordingly, the substrate is interposed between the face-to-face chips, and the bumps are embedded in the substrate so that the package has short electrical transmission and thinner package profile.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a multi-chip package construction, and more particularly to a multi-wafer face-to-face stacked package construction. [Prior Art]

As electronic technology continues to evolve, more functional and more user-friendly products are being introduced, and in terms of electronic products, they are also designed to be light, thin, short, and small. As miniaturization and increased operational speed requirements increase, multiple wafers are integrated into a single package structure to achieve more than twice the capacity or more functionality, such as in previous multi-wafer stacked package configurations. A plurality of wafers are stacked and encapsulated in a package material. As shown in FIG. 1 , the conventional multi-wafer stacked package structure 1 is a back-to-back stacked type, and mainly includes a substrate, a first wafer 120, a second wafer 130, and a plurality of bonding wires 141. , 142 and a plurality of external terminals 150. The substrate 11 has a first surface lu, a second surface 112 and a slot 1 i 3 . The active surface 121 of the first wafer i 2 is disposed on the first surface m, and the plurality of pads 122 of the first wafer 12 are corresponding to the slots 113. The bonding wires 141 pass through the slots 113 and electrically connect the pads 122 to the back surface 123 of the substrate wafer 120, that is, the first crystal. The main 132' of the second wafer 130 can be formed by the bonding wires 142. The second wafer 13 〇 #面1 3 1 has a plurality of pads electrically connected to the pads 1 3 2 to the back 1 3 3 is disposed on the first 120 and the sixth 200834844

The two wafers 130 are stacked in a back-to-back manner. The external terminals i5 are disposed on the second surface 112 of the substrate 11 for external connection. The multi-wafer stack package structure 100 further includes a glue 16 形成 formed on the first surface 1U of the substrate 110 and the slot 113 to seal the first wafer 120, the second wafer 130 and the solder Line 142. The encapsulant 160 may be further formed on the second surface of the substrate 11 , 12 - a knife to seal the bonding wires 141 . However, the volume of the multi-wafer stacked package structure increases as the number of stacked wafers increases, so that the number of wafer stacks is limited to increase memory capacity and/or expansion functionality. [Summary of the Invention]

The main object of the present invention is to provide a multi-wafer face-to-face stacked package structure, whereby the stack of multi-chips has the effect of reducing the package size and shortening the electrical connection path to improve performance. The purpose of this month and the resolution of its technical problems are achieved by the following technical solutions. According to the present invention, a multi-wafer® opposite stacked package structure mainly includes a substrate, a first bump, a plurality of first first wafers, a second wafer, a plurality of bumps, and a plurality of external terminals. The substrate has a first surface 'the second surface' and a plurality of first bump receiving holes and a plurality of the second bump receiving holes. The active surface of the first wafer is disposed on the first surface of the substrate, and the first wafer has a plurality of first electrodes aligned with the first bump receiving holes. The first bumps are disposed on the first surface of the first bump receiving hole of the substrate and electrically connected to the second wafer. The active surface is disposed on the second surface of the substrate of the 7 200834844 And the second wafer has a plurality of second electrodes aligned with the second bump receiving holes. The second bumps are disposed in the second bump receiving holes and electrically connect the second electrodes to the substrate. The external terminals are disposed on the substrate. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing multi-wafer face-to-face stacked package structure, the first bumps may be disposed in the first bump receiving holes by the second surface of the substrate, and the second bumps are formed by the substrate The first surface is disposed in the second bump receiving holes. In the foregoing multi-wafer face-to-face stacked package structure, the second wafer can cover the first bump receiving holes such that the first bumps are located between the first wafer and the second wafer. In the aforementioned multi-wafer face-to-face stacked package configuration, the first wafer system may have a size smaller than the second wafer to not cover the second bump receiving holes. In the aforementioned multi-wafer face-to-face stacked package configuration, the second bumps may be located on both sides of the first wafer. In the aforementioned multi-wafer face-to-face stacked package structure, the external terminals may be disposed on the second surface of the substrate. In the aforementioned multi-wafer face-to-face stacked package configuration, the substrate has a wiring layer 'which may be formed on the first surface. In the foregoing multi-wafer face-to-face stacked package structure, a glue may be further included on the first surface of the substrate to seal the first wafer and the second bumps. In the aforementioned multi-wafer face-to-face stacked package configuration, the encapsulant may be formed on one of the second surfaces of the substrate to seal the second wafer. In the aforementioned multi-wafer face-to-face stacked package structure, the external terminals may be disposed on the first surface of the substrate. In the aforementioned multi-wafer face-to-face stacked package configuration, the substrate may have a wiring layer formed on the second surface. In the foregoing multi-wafer face-to-face stacked package configuration, a further colloid may be included which is formed on the second surface of the substrate to seal the first wafer. In the aforementioned multi-wafer face-to-face stacked package structure, the encapsulation body may be formed on one of the first surfaces of the substrate to seal the first wafer and the second bumps. In the foregoing multi-wafer face-to-face stacked package structure, at least one third wafer may be further disposed on the second wafer and electrically connected to the substrate. In the foregoing multi-wafer face-to-face stacked package structure, at least one fourth wafer may be further disposed on the first wafer and electrically connected to the substrate. In the multi-wafer face-to-face stacked package configuration described above, the substrate may be a flexible circuit substrate. In the multi-wafer face-to-face stacked package construction described above, the first wafer and the second wafer system may be high frequency memory wafers. 9 200834844 The electrode systems in the foregoing multi-wafer face-to-face stacked package structure may be soldered. The second electrode systems may be bumps. In the foregoing multi-wafer face-to-face stacked package structure, the electrode system may be The bumps, the second electrodes may be fresh 塾 [Embodiment] According to the first embodiment of the present invention, the multi-wafer face-to-face stacked package structure is not determined. Figure 2 shows the polycrystal

A cross-sectional view of the surface-to-surface stacking structure of the sun and the moon. Figure 3 is a top plan view of a substrate in a multi-packaged package structure. Referring to FIG. 2 , the multi-chip wafer face-to-face stack 200 mainly includes a substrate 21 , a first wafer 22 〇 ' : a sheet 230 , a plurality of first bumps 241 , a plurality of second bumps ... and a plurality An external terminal is 25〇. As shown in the figure, the plate 210 has a first surface bauxite from the first surface 212, a plurality of first bump receiving holes 213, and a plurality of holes. 2 1 4. The first bump receiving holes 213 盥 盥 ... 弟 弟 一 凸 凸 凸 凸 214 214 214 214 214 214

The first surface 211 is budded with the first to first surfaces 212. Preferably, the substrate 2 1 can be a flexible circuit board, which is advantageous for thinning and lightening of the package. The second chip 220 has an active surface 221 and a plurality of active surfaces 2 2 . 1 on the Chu Le an electrode 222. The first electrodes 222 can be solder bumps. The first wafer active surface 221 is disposed on the first surface 211 of the substrate 210 and the first electrodes 222 are aligned on the first bumps. 10 200834844 Hole 2 13. As shown in FIG. 2 , the first bumps 24 i are disposed in the first protruding accommodating holes 213 and electrically connected to the first electrodes 222 to the circuit layer 215 of the substrate 210 . The conventional wire bonding step can be omitted, which has the convenience of simplifying the process and shortening the effect of the electrical conduction path. In this embodiment, the second bumps 203 occlude the first bump accommodating holes 213 ′ such that the first bumps 241 are located between the first wafer 220 and the second wafer 230 . . The first bumps 241 are disposed in the first bump receiving holes 213 by the second surface 212 of the substrate 210. The second wafer 230 has an active surface 231 and a plurality of second electrodes 232 on the active surface 231. The second electrodes 232 can be bumps. In this embodiment, the first wafer 220 and the second wafer 230 may be high frequency memory chips, such as DDR3 DRAM, having a frequency greater than 1 GHz. The active surface 231 of the second wafer 230 is disposed on the second surface 212 of the substrate 210, and the second electrodes 23 2 are aligned on the second bumps. The hole 2 14 is accommodated. As shown in FIGS. 2 and 3, the first wafer 220 may have a size smaller than that of the second wafer 230 so as not to cover the second bump receiving holes 2 14 . The second bumps 242 are disposed in the second bump receiving holes 214 and electrically connect the second electrodes 232 to the substrate 2 10 , so that the conventional wire bonding electrical connection can be omitted. The effect of the electrical connection path. The second bumps 242 are disposed in the second bump receiving holes 214 by the first surface 211 of the substrate 210. The second bumps 242 can be located on both sides of the first wafer 22〇200834844. The external terminals 250 are disposed on the substrate 210 for external bonding to an external printed circuit board. In this embodiment, the external terminals 25 can be disposed on the second surface 212 of the substrate 21〇. In this embodiment, the external terminals 25 may include solder balls, solder paste, metal ball metal plugs or ACF conductive paste. In addition, the substrate 2 i has a circuit layer 215 which can be formed on the first surface 211 so that the core layer of the substrate 210 is a exposed surface to save a solder mask layer. The positioning of the external terminal 250 is increased, so that the package size can be reduced and the manufacturing cost can be reduced. Therefore, in the present invention, the two wafers 22 and 23 are stacked face to face between the substrates 210, and the bumps 241 and 242 for electrically connecting are partially embedded in the bump receiving holes 213 and 214 of the substrate 210. Get the new multi-chip stack package architecture of the new king. The active faces of the wafers 2 2 and 230 will be in close contact with the substrate and electrically connected to the circuit layer 215 of the substrate 210 by the bumps 241 , so that the multi-chip face-to-face stacked package structure 200 has a thinner Thickness, lighter weight and shorter electric conduction path. Furthermore, the distance between the electrical conduction paths is shortened, and the transmission speed is increased & the inductance effect is low, which effectively improves the reliability and sin of the product, so it can be especially applied to DDR3 or Ramb〇us high frequency recording hidden body. Stacked package of cymbals. In addition, the structural design of the present invention can be used in conjunction with existing packaging processes and wire bonding equipment. More specifically, the multi-wafer face-to-face stacked package structure 200 may further include a glue 260' formed on the first 12 200834844 surface 211 of the substrate 2 to seal the first wafer 22 and the first Two bumps 242. The encapsulant 260 can be formed on one of the second surfaces 212 of the substrate 210 to seal the second wafer 230 without impeding the arrangement of the external terminals 250. In accordance with a second embodiment of the present invention, FIG. 4 illustrates a cross-sectional view of another multi-wafer face-to-face stacked package configuration. Please refer to FIG. 4' The multi-wafer face-to-face stacked package structure 300 mainly includes one

The substrate 310, a first wafer 32, a second wafer 33, a plurality of first bumps 341, a plurality of second bumps 342, and a plurality of external terminals 350. The substrate 31 has a first surface 311, a second surface 312, a plurality of first bump receiving holes 313 and a plurality of second bump valleys 3 1 4 . In this embodiment, the substrate 310 is a flexible circuit substrate ‘and may have a circuit layer 315 formed on the second surface 312. The active surface 321 of the first wafer 320 is disposed on the first surface 31 of the substrate 310, and the first wafer 320 has a plurality of first alignments in the first bump receiving holes 313. Electrode 3 22 . In the embodiment, the first electrodes 322 may be solder pads or bumps. The first bumps 34 are disposed in the first bump receiving holes 313 and electrically connected to the first electrodes 322 to the substrate 310. For example, the lead ends of the circuit layer 315 on the first bump receiving holes 3 1 3 can be soldered by wire bonding pins to be bonded to the first bumps 3 4 j. The active surface 3 3 1 of the second wafer 310 is disposed on the second surface 3 1 2 of the substrate 3 10 , and the second wafer 310 has a plurality of 13 200834844 aligned in the first The second bump accommodates the second electrode 332 of the hole 314. In this embodiment, the second electrodes 332 can be solder pads. The second bumps 3 42 are disposed in the second bump receiving holes 3丨4 and electrically connected to the second electrodes 3 3 2 to the substrate 3丨〇. For example, the ball end formed by the wire bonding needle can be used as the second bumps 342, which are soldered to the second electrodes 332, and the circuit layer 315 is bonded to the second bump receiving holes 3 14 Metal part. Further, the external terminals 35 are disposed on the substrate 3A for external bonding. In this embodiment, the external terminals 35 can be disposed on the first surface 311 of the substrate 310. Referring to FIG. 4 again, the multi-wafer face-to-face stacked package structure 3 can further include a glue 3 60' formed on the second surface 312 of the substrate 31 to seal the second wafer 330. The encapsulant 36 can be formed on one of the first surfaces 311 of the substrate 3 10 to seal the first wafer 32 and the second bumps 342. Therefore, the dual-wafer is stacked face-to-face and interposed between the substrates, so that the active surface of the wafer is in close contact with the upper surface of the substrate, and the bumps of the electrical connection are partially embedded in the substrate, so that the electrical shortening can be achieved. Connect the path and reduce the volume of the package construction. In accordance with a third embodiment of the present invention, FIG. 5 illustrates a cross-sectional view of another multi-wafer face-to-face stacked package configuration. Referring to FIG. 5, the multi-wafer face-to-face stacked package structure 400 is substantially the same as the second embodiment but can stack more wafers, and mainly includes a substrate 410, a first wafer 42A, and a second wafer 43. a plurality of first protrusions 14 200834844 blocks 441, a plurality of second bumps 442, and a plurality of external connections. The substrate 410 has a first surface 411, a second plurality of first bump receiving holes 413 and a plurality a second protrusion 414, the first wafer 420 is disposed on the substrate 410 such that the active surface of the first wafer 420 is in close contact with the y and the first wafer 420 has a plurality of alignments therein. The block houses the first electrode 422 of the hole 413. The first bumps are disposed in the first bump receiving holes 413 and electrically connected to the electrodes 422 to the substrate 410. The second wafer 430 is disposed on the 412' of the substrate 410 such that the active surface of the second wafer 43 0 is in close contact with the second wafer 430 and the second wafer 430 has a plurality of alignments in the block receiving hole 414. Second electrode 432. The second bumps are disposed in the second bump receiving holes 4 1 4 and electrically connected to the electrodes 432 to the substrate 410. The external terminals 450 are substrates 4 10 for external connection. In the present embodiment, please refer to FIG. 5 again. The opposite stacked package structure 400 may further include at least one 470 to expand the memory capacity. The third wafers 47 are on the second wafer 430. Each of the third wafers 47 is electrically connected to the active pads of the third wafer 47 by a plurality of bonding wires 472 electrically connected to the pads 471. In this embodiment, the third surface of the third wafer 47A is opposite to the first surface of the black surface 450, and the first surface of the block receiving hole is opposite to the first surface I plate. 4 1 0, the second protrusions 442 are disposed on the multi-chip surface, the third wafer system can be stacked with a plurality of edges, and the substrate is provided with a 15 200834844 spacer 480 to provide the The three wafers 47 are spaced apart from each other in the jade stack and can avoid the solder wires 472 located at the upper third wafer. The multi-wafer face-to-face stacked package structure 400 may further include a colloid 460 ′ which seals the first wafer 420 , the 442th portion, the second wafer 430 , the third wafers 47 〇 and the 472° φ according to the present invention. In a fourth embodiment, FIG. 6 is a cross-sectional view showing a multi-wafer face-to-face stacked package structure having the same basic structure as the first embodiment, and more wafers can be stacked. As shown in FIG. 6, the multi-chip face-to-face stacked package structure 5 includes a substrate 510, a first wafer 5 2 〇, a plurality of first bumps, a second wafer 530, and a plurality of second bumps 542. And a plurality of terminals 55 〇. The substrate 51 has a first surface 511, a surface 5 1 2, a plurality of first bump receiving holes 5 1 3 and a plurality of ® block receiving holes 5 1 4 . The first wafer 520 is disposed on the first 511 of the substrate 5 i , and the first wafer 520 has a plurality of first electrodes 522 aligned in a bump receiving hole 513 . The first protrusions are disposed in the first bump receiving holes 513 and electrically connected to the first electrode 522 to the substrate 510. The second wafer 530 is disposed on the fifth portion of the substrate 5 i ,, and the second wafer 530 has a plurality of second electrodes aligned in the two bump receiving holes 51 5 3 2. The 470 presses of the second bumps have a two bumps and some solder wires. The other structure is referred to as a main package L 541, and an external second second convex surface. The first blocks 54 1 are connected to the surfaces. The second blocks 5 42 16 200834844 are disposed in the second bump receiving holes 514 and electrically connected to the second electrodes 532 to the substrate 51 . The external terminals 55 are disposed on the substrate 510 for external bonding. The multi-wafer face-to-face stacked package structure 5 further includes a third wafer 570 disposed on the second wafer 53 and electrically connected to the third wafer 57 by a plurality of bonding wires 572. Pad 571 to the substrate 5 10 . Moreover, the invention is not limited to the number of stacked wafers. • As shown in Fig. 6, the multi-wafer face-to-face stacked package structure 500 may further include at least a fourth wafer 58A to expand the memory capacity. The fourth wafers 580 may be stacked on the first wafer 52A. Each of the fourth wafers 580 has a plurality of pads 5 8 i formed on the edge of the fourth wafer 580 , and the pads 582 are electrically connected to the substrate 5 by a plurality of bonding wires 582 . 1 0. In this embodiment, a spacer 105 is disposed between the fourth wafers 580 for attaching to the fourth wafer 580, and the fourth wafer 58 located above is prevented from being pressed. The wire bonds 582 are touched. The multi-wafer face-to-face stacked package structure 500 may further include a glue 560 that seals the first wafer 520, the second bumps 542, the second wafer 530, and the third wafers 57. The fourth wafers and the bonding wires 572, 582. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. A person skilled in the art can make some modifications or modifications to equivalent embodiments using the above-disclosed technical contents without departing from the technical scope of the present invention, but without departing from the technical solution of the present invention, The present invention is not limited to any simple modifications, equivalent changes and modifications of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional multi-wafer stacked package structure. Fig. 2 is a schematic view showing the wearing of a multi-chip face-to-face stacked package structure in accordance with a first embodiment of the present invention. Figure 3 is a top plan view of a substrate in a multi-wafer face-to-face stacked package configuration in accordance with a first embodiment of the present invention. Figure 4 is a schematic illustration of a wear side of a multi-wafer face-to-face stacked package construction in accordance with an embodiment of the present invention. Figure 5: Another multi-wafer in accordance with a third embodiment of the present invention

A schematic cross-sectional view of a face-to-face stacked package structure. Figure 6 is a perspective view of another multi-wafer face-to-face stacked package construction in accordance with a fourth embodiment of the present invention. [Main component symbol description] 100 multi-chip stacked package structure 110 substrate 111 first 113 slot 120 first 曰 y B 曰 121 active 123 back 130 second wafer 131 active surface 112 second surface surface 122 pad surface 132 welding Pad 18

200834844 133 back 141 bonding wire 142 bonding wire 150 external terminal 160 sealing body 200 multi-chip face-to-face stacked package structure 210 substrate 211 first surface 213 first bump accommodating hole 214 second bump accommodating hole 220 first wafer 221 active Face 230 second wafer 231 active surface 241 first bump 242 second bump 250 external terminal 260 sealant 212 215 222 232 second surface circuit layer first electrode second electrode

300 multi-chip face-to-face stacked package structure 310 substrate 311 first surface 313 first bump receiving hole 314 second bump receiving hole 320 first wafer 321 active surface 330 second wafer 331 active surface 341 first bump 342 Two bumps 350 external terminals 360 encapsulant 400 multi-wafer face-to-face stacked package structure 410 substrate 411 first surface 312 315 322 332 412 second surface circuit layer first electrode second electrode second surface 413 first bump receiving hole 414 Second bump receiving hole 420 first wafer 422 first electrode 19 200834844 430 second wafer 441 first bump 450 external terminal 470 third wafer 432 second electrode 442 second bump 460 sealant 471 pad 472 soldering Line 480 spacer 500 multi-wafer face-to-face stacked package configuration 512 second surface 510 substrate 511 first surface

513 first bump receiving hole 514 second bump receiving hole 520 first wafer 522 first electrode 530 second wafer 541 first bump 550 external terminal 532 second electrode 542 second bump 560 sealant 570 Three wafers 571 pads 580 fourth wafers 581 pads 572 bonding wires 582 bonding wires

590 spacer 20

Claims (1)

200834844 X. Patent Application Scope 1. β1, a multi-wafer face-to-face stacked package structure, comprising: a substrate having a first surface, a second surface, a plurality of first bump receiving holes and a plurality of second a bump receiving hole; a first wafer having an active surface disposed on the first surface of the substrate, and the first wafer has a plurality of first electrodes aligned on the first bump receiving holes a plurality of first bumps disposed in the first bump receiving holes and electrically connecting the first electrodes to the substrate; a second wafer having an active surface disposed on the substrate The second surface, and the second wafer has a plurality of second electrodes aligned on the second bump receiving holes; and a plurality of second bumps disposed on the second bumps And electrically connecting the second electrodes to the substrate; and a plurality of external terminals disposed on the substrate. ® 2 as claimed in the scope of patents! The multi-wafer face-to-face stacking structure of the present invention, wherein the first bumps are disposed in the first bump receiving holes by the second surface of the substrate, and the second bumps are The first surface of the substrate is disposed in the second bump receiving holes. 3. The multi-wafer face-to-face stacked package structure of the second aspect of the invention, wherein the second wafer system covers the first bump receiving holes, so that the first bumps are located at the first Between the wafer and the second wafer. 4. The multi-wafer face-to-face stacked package structure of claim </ RTI> wherein the first wafer has a size less than the second wafer of 21 200834844 inches to cover the second bump receiving holes. . The multi-wafer face-to-face stack package structure of claim 4, wherein the second bumps are located on both sides of the first wafer. The multi-wafer face-to-face stacked package structure described in the first paragraph of the patent application of the present invention, wherein the external terminals are disposed on the second surface of the substrate. The multi-wafer face-to-face stacking seal described in claim 1 or 6 of the patent scope 4, wherein the substrate has a wiring layer formed on the first surface. 8 &gt; The multi-wafer face-to-face stacked package described in claim 6 of the patent scope, further comprising a colloid formed on the first surface of the substrate, the first wafer and the first wafer are sealed Second bump. 9. The multi-wafer face-to-face stacked package structure of claim 8, wherein the encapsulation system is formed on one of the second surfaces of the substrate to seal the second wafer. The multi-chip face-to-face stacked package described in claim 1, wherein the external terminals are disposed on the first surface of the substrate. The multi-wafer face-to-face stacking structure described in claim 1 or claim 11, wherein the substrate has a wiring layer formed on the surface of the second surface. The multi-wafer face-to-face stacked package described in claim 10 of the patent application, further comprising a colloid formed on the substrate to seal the second wafer. The multi-wafer face-to-face stacking package according to the 12th item of the Shenqing patent scope, wherein the encapsulation system is further formed on a portion of the first surface 22 of the substrate 22 200834844 to seal the first wafer and the second Bump. 14. The multi-wafer face-to-face stacked package structure of claim 1 further comprising at least one third wafer disposed on the second wafer and electrically connected to the substrate. 15. The multi-wafer face-to-face stacked package structure of claim 1 or claim 14, further comprising at least one fourth wafer disposed on the first wafer and electrically connected to the substrate. 16. The multi-wafer face-to-face stacked package structure of claim 1, wherein the substrate is a flexible circuit substrate. 17. The multi-wafer face-to-face stacked package structure of claim 1, wherein the first wafer and the second wafer are high frequency memory wafers. 18. The multi-wafer face-to-face stacked package structure of claim 1, wherein the first electrodes are pads and the second electrodes are bumps. 19. The multi-wafer face-to-face stacking structure of claim 1, wherein the first electrodes are bumps, and the second electrodes are &lt; ί 23