TW200834844A - Multi-chip face-to-face stack package - Google Patents

Multi-chip face-to-face stack package Download PDF

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Publication number
TW200834844A
TW200834844A TW96105664A TW96105664A TW200834844A TW 200834844 A TW200834844 A TW 200834844A TW 96105664 A TW96105664 A TW 96105664A TW 96105664 A TW96105664 A TW 96105664A TW 200834844 A TW200834844 A TW 200834844A
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Taiwan
Prior art keywords
wafer
face
substrate
bumps
stacked package
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TW96105664A
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Chinese (zh)
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TWI351089B (en
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Hsiang-Ming Huang
An-Hong Liu
Yeong-Jyh Lin
Yi-Chang Lee
Shu-Ching Ho
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Chipmos Technologies Inc
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Publication of TW200834844A publication Critical patent/TW200834844A/en
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Publication of TWI351089B publication Critical patent/TWI351089B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

A multi-chip face-to face stack package mainly comprises a substrate, a first chip, a second chip, a plurality of first bumps, a plurality of second bumps and a plurality of external terminals disposed on the substrate. The substrate has a plurality of first bump holes and a plurality of second bump holes. The active surface of the first chip is attached to a first surface of the substrate. The first bumps are located in the first bump holes respectively to electrically connect the first chip with the substrate. The active surface of the second chip is attached to a second surface of the substrate. The second bumps are located in the second bump holes respectively to electrically connect the second chip with the substrate. Accordingly, the substrate is interposed between the face-to-face chips, and the bumps are embedded in the substrate so that the package has short electrical transmission and thinner package profile.

Description

200834844 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種多晶片封裝構造,特別係有關 於一種多晶片面對面堆疊封裝構造。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a multi-chip package construction, and more particularly to a multi-wafer face-to-face stacked package construction. [Prior Art]

由於電子科技不斷地演進,功能性更複雜、更人性 化的產品推陳出新,就電子產品外觀而言,也朝向輕、 薄、短、小的趨勢設計。隨著微小化以及高運作速度需 求的增加,多個晶片會整合在一封裝構造内,以達到兩 倍以上之容量或更多功能之需求,例如在以往的多晶片 堆疊封裝構造中,其係將多個晶片堆疊並封膠在一封裝 材料内。 晴參閱第1圖所示,習知多晶片堆疊封裝構造1 〇 〇 係為背對背堆疊型態,主要包含一基板丨丨〇、一第一晶 片12 0、一第二晶片130、複數個銲線141、142以及複 數個外接端子150。該基板11〇係具有一第一表面lu、 一第二表面1 1 2以及一槽孔1 i 3。該第一晶片i 2〇係之 主動面121係設置於該第一表面m,且該第一晶片12〇 之複數個銲墊122係對應該槽孔113。該些銲線141係 通過該槽孔113並電性連接該些銲墊122至該基板 晶片120之背面123,也就是說該第_晶 1 1 〇。該第二晶片1 3 0之主 132 ’可藉由該些銲線142 基板110。該第二晶片13〇 #面1 3 1係具有複數個銲墊 電性連接該些銲墊1 3 2至該 之背面1 3 3係設置於該第一 120與該第 6 200834844As electronic technology continues to evolve, more functional and more user-friendly products are being introduced, and in terms of electronic products, they are also designed to be light, thin, short, and small. As miniaturization and increased operational speed requirements increase, multiple wafers are integrated into a single package structure to achieve more than twice the capacity or more functionality, such as in previous multi-wafer stacked package configurations. A plurality of wafers are stacked and encapsulated in a package material. As shown in FIG. 1 , the conventional multi-wafer stacked package structure 1 is a back-to-back stacked type, and mainly includes a substrate, a first wafer 120, a second wafer 130, and a plurality of bonding wires 141. , 142 and a plurality of external terminals 150. The substrate 11 has a first surface lu, a second surface 112 and a slot 1 i 3 . The active surface 121 of the first wafer i 2 is disposed on the first surface m, and the plurality of pads 122 of the first wafer 12 are corresponding to the slots 113. The bonding wires 141 pass through the slots 113 and electrically connect the pads 122 to the back surface 123 of the substrate wafer 120, that is, the first crystal. The main 132' of the second wafer 130 can be formed by the bonding wires 142. The second wafer 13 〇 #面1 3 1 has a plurality of pads electrically connected to the pads 1 3 2 to the back 1 3 3 is disposed on the first 120 and the sixth 200834844

二晶片130係以背對背方式堆疊。該些外接端子i5〇係 設置於該基板11〇之第二表面112,以供對外連接。該 多晶片堆疊封裝構造100另包含一封膠體16〇,其係形 成於該基板110之第一表面1U與該槽孔113,以密封 該第一晶片120、該第二晶片130與該些銲線142。該 封膠體160可另形成於該基板11〇之第二表面、12之— 邻刀以岔封該些銲線141。然而,該多晶片堆疊封裝構 造之體積會隨著所堆疊之晶片增加而增加,故使得晶片 堆疊的數量受限制而無法增加記憶體容量及/或擴充功 能。 【發明内容】The two wafers 130 are stacked in a back-to-back manner. The external terminals i5 are disposed on the second surface 112 of the substrate 11 for external connection. The multi-wafer stack package structure 100 further includes a glue 16 形成 formed on the first surface 1U of the substrate 110 and the slot 113 to seal the first wafer 120, the second wafer 130 and the solder Line 142. The encapsulant 160 may be further formed on the second surface of the substrate 11 , 12 - a knife to seal the bonding wires 141 . However, the volume of the multi-wafer stacked package structure increases as the number of stacked wafers increases, so that the number of wafer stacks is limited to increase memory capacity and/or expansion functionality. [Summary of the Invention]

本發明之主要目的係在於提供一種多晶片面對面堆 疊封裝構造,藉以使多晶片之堆疊具有縮小封裝尺寸並 縮短電性連接路徑以增進效能之功效。 本心月的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明,-種多晶片®對面堆疊封裝 構造主要包含一基板、 個第一凸塊、複數個第 一第一晶片、一第二晶片、複數 二凸塊以及複數個外接端子。該 基板係具有-第一表面'—第二表面'複數個第一凸塊 容置孔與複數個第=凸塊容置孔。該第—晶片之主動面 係設置於該基板之該第一表面,ϋ且該第-晶片係具有 複數個對準在該些第一 凸塊容置孔之第一電極。該些第 一凸塊係設置於該些 些第一電極至該基板 第一凸塊容置孔内並電性連接該 該第二晶片之主動面係設置於該 7 200834844 基板之該第二表面,並且該第二晶片係具有複數個對準 在該些第二凸塊容置孔之第二電極。該些第二凸塊係設 置於該些第二凸塊容置孔内並電性連接該些第二電極 至該基板。該些外接端子係設置於該基板。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的多晶片面對面堆疊封裝構造中,該些第一 凸塊係可由該基板之第二表面設置於該些第一凸塊容 置孔内,且該些第二凸塊係由該基板之第一表面設置於 該些第二凸塊容置孔内。 在前述的多晶片面對面堆疊封裝構造中,該第二晶 片係可遮蓋該些第一凸塊容置孔,以使該些第一凸塊位 於該第一晶片與該第二晶片之間。 在前述的多晶片面對面堆疊封裝構造中,該第一晶 片係可具有小於該第二晶片之尺寸,以不遮蓋該些第二 凸塊容置孔。 在前述的多晶片面對面堆疊封裝構造中,該些第二 凸塊係可位於該第一晶片之兩側。 在前述的多晶片面對面堆疊封裝構造中,該些外接 端子係可設置於該基板之第二表面。 在前述的多晶片面對面堆疊封裝構造中,該基板係 具有一線路層’其係可形成於該第一表面。 在前述的多晶片面對面堆疊封裝構造中,可另包含 有一封膠體,其係形成於該基板之第一表面,以密封該 8 200834844 第一晶片與該些第二凸塊。 在前述的多晶片面對面堆疊封裝構造中,該封膠體 係可更形成於該基板之第二表面之一部位,以密封該第 二晶片。 在前述的多晶片面對面堆疊封裝構造中,該些外接 端子係可設置於該基板之第一表面。 在前述的多晶片面對面堆疊封裝構造中,該基板係 可具有一線路層,其係形成於該第二表面。 在前述的多晶片面對面堆疊封裝構造中,可另包含 有一封膠體,其係形成於該基板之第二表面,以密封該 第一晶片。 在前述的多晶片面對面堆疊封裝構造中,該封膠體 係可更形成於該基板之第一表面之一部位,以密封該第 一晶片與該些第二凸塊。 在前述的多晶片面對面堆疊封裝構造中,可另包含 有至少一第三晶片,其係設置於該第二晶片上並電性連 接至該基板。 在前述的多晶片面對面堆疊封裝構造中,可另包含 有至少一第四晶片,其係設置於該第一晶片上並電性連 接至該基板。 在刖述的多晶片面對面堆疊封裝構造中,該基板係 可為一可撓性電路基板。 在則述的多晶片面對面堆疊封裝構造中’該第一晶 片與該第二晶片係可為高頻記憶體晶片。 9 200834844 該些第 該些第 在前述的多晶片面對面堆疊封裳構造中 電極係可為銲整’該些第二電極係可為凸塊 在前述的多晶片面對面堆疊封裝構造中 電極係可為凸塊,該些第二電極係可為鮮塾 【實施方式】 依據本發明之第一具體實施例,揭干接々 判不一種多晶片面 對面堆疊封裝構造。第2圖係為該多晶The main object of the present invention is to provide a multi-wafer face-to-face stacked package structure, whereby the stack of multi-chips has the effect of reducing the package size and shortening the electrical connection path to improve performance. The purpose of this month and the resolution of its technical problems are achieved by the following technical solutions. According to the present invention, a multi-wafer® opposite stacked package structure mainly includes a substrate, a first bump, a plurality of first first wafers, a second wafer, a plurality of bumps, and a plurality of external terminals. The substrate has a first surface 'the second surface' and a plurality of first bump receiving holes and a plurality of the second bump receiving holes. The active surface of the first wafer is disposed on the first surface of the substrate, and the first wafer has a plurality of first electrodes aligned with the first bump receiving holes. The first bumps are disposed on the first surface of the first bump receiving hole of the substrate and electrically connected to the second wafer. The active surface is disposed on the second surface of the substrate of the 7 200834844 And the second wafer has a plurality of second electrodes aligned with the second bump receiving holes. The second bumps are disposed in the second bump receiving holes and electrically connect the second electrodes to the substrate. The external terminals are disposed on the substrate. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing multi-wafer face-to-face stacked package structure, the first bumps may be disposed in the first bump receiving holes by the second surface of the substrate, and the second bumps are formed by the substrate The first surface is disposed in the second bump receiving holes. In the foregoing multi-wafer face-to-face stacked package structure, the second wafer can cover the first bump receiving holes such that the first bumps are located between the first wafer and the second wafer. In the aforementioned multi-wafer face-to-face stacked package configuration, the first wafer system may have a size smaller than the second wafer to not cover the second bump receiving holes. In the aforementioned multi-wafer face-to-face stacked package configuration, the second bumps may be located on both sides of the first wafer. In the aforementioned multi-wafer face-to-face stacked package structure, the external terminals may be disposed on the second surface of the substrate. In the aforementioned multi-wafer face-to-face stacked package configuration, the substrate has a wiring layer 'which may be formed on the first surface. In the foregoing multi-wafer face-to-face stacked package structure, a glue may be further included on the first surface of the substrate to seal the first wafer and the second bumps. In the aforementioned multi-wafer face-to-face stacked package configuration, the encapsulant may be formed on one of the second surfaces of the substrate to seal the second wafer. In the aforementioned multi-wafer face-to-face stacked package structure, the external terminals may be disposed on the first surface of the substrate. In the aforementioned multi-wafer face-to-face stacked package configuration, the substrate may have a wiring layer formed on the second surface. In the foregoing multi-wafer face-to-face stacked package configuration, a further colloid may be included which is formed on the second surface of the substrate to seal the first wafer. In the aforementioned multi-wafer face-to-face stacked package structure, the encapsulation body may be formed on one of the first surfaces of the substrate to seal the first wafer and the second bumps. In the foregoing multi-wafer face-to-face stacked package structure, at least one third wafer may be further disposed on the second wafer and electrically connected to the substrate. In the foregoing multi-wafer face-to-face stacked package structure, at least one fourth wafer may be further disposed on the first wafer and electrically connected to the substrate. In the multi-wafer face-to-face stacked package configuration described above, the substrate may be a flexible circuit substrate. In the multi-wafer face-to-face stacked package construction described above, the first wafer and the second wafer system may be high frequency memory wafers. 9 200834844 The electrode systems in the foregoing multi-wafer face-to-face stacked package structure may be soldered. The second electrode systems may be bumps. In the foregoing multi-wafer face-to-face stacked package structure, the electrode system may be The bumps, the second electrodes may be fresh 塾 [Embodiment] According to the first embodiment of the present invention, the multi-wafer face-to-face stacked package structure is not determined. Figure 2 shows the polycrystal

日日月面對面堆聶封 裝構造之截面示意圖。第3圖係為該多 且 日日乃曲對面堆疊 封裝構造中一基板之頂面示意圖。 請參閱第2圖所示,言亥多晶片面對面堆叠 200主要包含一基板21〇、一第一晶片22〇 ' : 片230、複數個第一凸塊241、複數個第二凸塊…以 及複數個外接端子25〇。請參閱第…圖所示,該其 板210係具有一第一表 乂土 从 第一表面212、複數 個第一凸塊容置孔213血複數 •、後数個弟一凸塊容置孔2 1 4。 該些第一凸塊容置孔213盥第一六 …弟一凸塊谷置孔214係可貫A cross-sectional view of the surface-to-surface stacking structure of the sun and the moon. Figure 3 is a top plan view of a substrate in a multi-packaged package structure. Referring to FIG. 2 , the multi-chip wafer face-to-face stack 200 mainly includes a substrate 21 , a first wafer 22 〇 ' : a sheet 230 , a plurality of first bumps 241 , a plurality of second bumps ... and a plurality An external terminal is 25〇. As shown in the figure, the plate 210 has a first surface bauxite from the first surface 212, a plurality of first bump receiving holes 213, and a plurality of holes. 2 1 4. The first bump receiving holes 213 盥 盥 ... 弟 弟 一 凸 凸 凸 凸 214 214 214 214 214 214

芽該第一表面211與兮筮—主I 〜第一表面212。較佳地,該基板 2 1 〇係可為一可撓性番 電路基板,有利於封裝薄化、輕量 化0 I第 曰曰片220係具有一主動面221以及複數個在 該主動面2 2 1上之楚 乐一電極222。該些第一電極222係 可為銲塾。利用总y 片勘著材料之黏接,使得該第一晶片 ^主動面221係設置於該基板210之該第一表面 211並且該些第一電極222係對準在該些第一凸塊容 10 200834844 置孔2 13。請參閱第2圖所示,該些第一凸塊24 i係設 置於該些第一凸瑰容置孔213内並電性連接該些第一 電極222至該基板210之線路層215,故可省略以往的 打線電性連接步驟,具有製程簡化的方便性及縮短電性 傳導路徑之功效。在本實施例中,該第二晶片2 3 0係可 遮蓋該些第一凸塊容置孔213 ’以使該些第一凸塊241 位於該第一晶片220與該第二晶片230之間。其中,該 些第一凸塊241係可由該基板210之第二表面212設置 於該些第一凸塊容置孔213内。 該第二晶片230係具有一主動面231以及複數個在 該主動面231上之第二電極232。該些第二電極232係 可為凸塊。在本實施例中,該第一晶片220與該第二晶 片230係可為高頻記憶體晶片,如DDR3 DRAM,其頻 率係大於1 GHz。利用一晶片黏著材料之黏接,使得該 第二晶片230之該主動面231係設置於該基板210之該 第二表面212,並且該些第二電極23 2對準在該些第二 凸塊容置孔2 14。請參閱第2及3圖所示,該第一晶片 220係可具有小於該第二晶片230之尺寸,以不遮蓋該 些第二凸塊容置孔2 1 4。該些第二凸塊242係設置於該 些第二凸塊容置孔214内並電性連接該些第二電極232 至該基板2 1 0,因此可省略以往的打線電性連接,具有 縮短電性連接路徑之功效。其中,該些第二凸塊242係 由該基板210之第一表面211設置於該些第二凸塊容置 孔214内。該些第二凸塊242係可位於該第一晶片22〇 η 200834844 之兩側。 该些外接端子2 5 0係設置於該基板2 1 0,以供對外 接合至一外部印刷電路板。在本實施例中,該些外接端 子25〇係可設置於該基板21〇之第二表面212。在本實 施例中,該些外接端子25〇係可包含銲球、錫膏、金屬 球金屬栓或ACF導電膠。此外,較佳地,該基板2 i 〇 係具有一線路層215,其係可形成於該第一表面211, 以使該基板2 1 0之核心層為顯露面,以節省一防銲層並 增加外接端子250之定位性,故可縮小封裝體積及降低 製造成本。 因此,本發明係利用兩晶片22〇與23〇面對面堆疊 在基板210之間,並且用以電性連接之凸塊241與242 局部嵌埋於基板210之凸塊容置孔213與214内,得到 種王新首創的多晶片堆疊封裝架構。該些晶片2 2 〇與 230之主動面將緊貼於基板之丨❹並以凸塊241與電 性連接至該基板210之該線路層215,使該多晶片面對 面堆疊封裝構造200具有較薄厚度、更輕量化與更短的 電座傳導路徑。再者,電性傳導路徑之距離縮短,更可 使傳輸速度提高&電感效應%低,有效提高產品之信賴 度及可罪度,故可特別運用於DDR3或Ramb〇us高頻記 隱體曰曰片之堆疊封裝。此外,本發明之結構設計係可同 時沿用既有之封裝製程與打線設備。 更具體而S ’該多晶片面對面堆疊封裝構造200可 另包含有一封膠體260 ’其係形成於該基板2〗〇之第一 12 200834844 表面211,以密封該第一晶片22〇與該些第二凸塊242。 該封膠體260係可更形成於該基板210之第二表面212 之一部位,以密封該第二晶片23 0,但不妨礙該些外接 端子250的設置。 依據本發明之第二具體實施例,第4圖揭示另一種 多晶片面對面堆疊封裝構造之截面示意圖。請參閱第4 圖所示’該多晶片面對面堆疊封裝構造3 00主要包含一The first surface 211 is budded with the first to first surfaces 212. Preferably, the substrate 2 1 can be a flexible circuit board, which is advantageous for thinning and lightening of the package. The second chip 220 has an active surface 221 and a plurality of active surfaces 2 2 . 1 on the Chu Le an electrode 222. The first electrodes 222 can be solder bumps. The first wafer active surface 221 is disposed on the first surface 211 of the substrate 210 and the first electrodes 222 are aligned on the first bumps. 10 200834844 Hole 2 13. As shown in FIG. 2 , the first bumps 24 i are disposed in the first protruding accommodating holes 213 and electrically connected to the first electrodes 222 to the circuit layer 215 of the substrate 210 . The conventional wire bonding step can be omitted, which has the convenience of simplifying the process and shortening the effect of the electrical conduction path. In this embodiment, the second bumps 203 occlude the first bump accommodating holes 213 ′ such that the first bumps 241 are located between the first wafer 220 and the second wafer 230 . . The first bumps 241 are disposed in the first bump receiving holes 213 by the second surface 212 of the substrate 210. The second wafer 230 has an active surface 231 and a plurality of second electrodes 232 on the active surface 231. The second electrodes 232 can be bumps. In this embodiment, the first wafer 220 and the second wafer 230 may be high frequency memory chips, such as DDR3 DRAM, having a frequency greater than 1 GHz. The active surface 231 of the second wafer 230 is disposed on the second surface 212 of the substrate 210, and the second electrodes 23 2 are aligned on the second bumps. The hole 2 14 is accommodated. As shown in FIGS. 2 and 3, the first wafer 220 may have a size smaller than that of the second wafer 230 so as not to cover the second bump receiving holes 2 14 . The second bumps 242 are disposed in the second bump receiving holes 214 and electrically connect the second electrodes 232 to the substrate 2 10 , so that the conventional wire bonding electrical connection can be omitted. The effect of the electrical connection path. The second bumps 242 are disposed in the second bump receiving holes 214 by the first surface 211 of the substrate 210. The second bumps 242 can be located on both sides of the first wafer 22〇200834844. The external terminals 250 are disposed on the substrate 210 for external bonding to an external printed circuit board. In this embodiment, the external terminals 25 can be disposed on the second surface 212 of the substrate 21〇. In this embodiment, the external terminals 25 may include solder balls, solder paste, metal ball metal plugs or ACF conductive paste. In addition, the substrate 2 i has a circuit layer 215 which can be formed on the first surface 211 so that the core layer of the substrate 210 is a exposed surface to save a solder mask layer. The positioning of the external terminal 250 is increased, so that the package size can be reduced and the manufacturing cost can be reduced. Therefore, in the present invention, the two wafers 22 and 23 are stacked face to face between the substrates 210, and the bumps 241 and 242 for electrically connecting are partially embedded in the bump receiving holes 213 and 214 of the substrate 210. Get the new multi-chip stack package architecture of the new king. The active faces of the wafers 2 2 and 230 will be in close contact with the substrate and electrically connected to the circuit layer 215 of the substrate 210 by the bumps 241 , so that the multi-chip face-to-face stacked package structure 200 has a thinner Thickness, lighter weight and shorter electric conduction path. Furthermore, the distance between the electrical conduction paths is shortened, and the transmission speed is increased & the inductance effect is low, which effectively improves the reliability and sin of the product, so it can be especially applied to DDR3 or Ramb〇us high frequency recording hidden body. Stacked package of cymbals. In addition, the structural design of the present invention can be used in conjunction with existing packaging processes and wire bonding equipment. More specifically, the multi-wafer face-to-face stacked package structure 200 may further include a glue 260' formed on the first 12 200834844 surface 211 of the substrate 2 to seal the first wafer 22 and the first Two bumps 242. The encapsulant 260 can be formed on one of the second surfaces 212 of the substrate 210 to seal the second wafer 230 without impeding the arrangement of the external terminals 250. In accordance with a second embodiment of the present invention, FIG. 4 illustrates a cross-sectional view of another multi-wafer face-to-face stacked package configuration. Please refer to FIG. 4' The multi-wafer face-to-face stacked package structure 300 mainly includes one

基板310、一第一晶片32〇、一第二晶片33〇、複數個 第一凸塊3 4 1、複數個第二凸塊3 42以及複數個外接端 子350。該基板31〇係具有一第一表面311、一第二表 面312、複數個第一凸塊容置孔313與複數個第二凸塊 谷置孔3 1 4。在本實施例中,該基板3 1 0係為一可撓性 電路基板’可更具有一線路層3 1 5,其係形成於該第二 表面3 12。 該第一晶片320之主動面321係設置於該基板310 之該第一表面3 1 1,並且該第一晶片320係具有複數個 對準在該些第一凸塊容置孔313之第一電極3 22。在本 實施例中’該些第一電極322係可為銲墊,亦可為凸 塊。該些第一凸塊34〗係設置於該些第一凸塊容置孔 313内並電性連接該些第一電極322至該基板310。例 如可以利用打線銲針壓焊該線路層315在該些第一凸 塊容置孔3 1 3上之引線端,以接合至該些第一凸塊3 4 j。 該第二晶片3 3 0之主動面3 3 1係設置於該基板3 1 0 之該第二表面3 1 2,並且該第二晶片3 3 0係具有複數個 13 200834844 對準在該些第二凸塊容置孔314之第二電極332。在本 實施例中,該些第二電極332係可為銲墊。該些第二凸 塊3 42係設置於該些第二凸塊容置孔3丨4内並電性連接 該些第二電極3 3 2至該基板3丨〇。例如可以利用打線銲 針形成之結球端作為該些第二凸塊342,其係焊接在該 些第二電極332,並接合該線路層315在該些第二凸塊 容置孔3 1 4之金屬部分。 此外’該些外接端子3 5 〇係設置於該基板3丨〇,以 供對外接合。在本實施例中,該些外接端子3 5 〇係可設 置於該基板310之第一表面311。請再參閱第4圖所示, 該多晶片面對面堆疊封裝構造3 〇〇可另包含有一封膠 體3 60’其係形成於該基板31〇之第二表面312,以密 封該第二晶片330。該封膠體36〇係可更形成於該基板 3 10之第一表面311之一部位,以密封該第一晶片32〇 與該些第二凸塊342。 因此’利用雙晶片面對面堆疊且介設於基板之間, 以使晶片之主動面緊貼於該基板之上下表面,並且電性 連接之凸塊係局部嵌埋基板内,如此可達到縮短電性連 接路徑以及縮小封裝構造之體積。 依據本發明之第三具體實施例,第5圖揭示另一種 多晶片面對面堆疊封裝構造之截面示意圖。請參閱第5 圖所示’該多晶片面對面堆疊封裝構造400大致與第二 具體實施例相同但可堆疊更多晶片,主要包含一基板 410、一第一晶片42〇、一第二晶片43〇、複數個第一凸 14 200834844 塊441、複數個第二凸塊442以及複數個外接〗 該基板410係具有一第一表面411、一第二表 複數個第一凸塊容置孔413與複數個第二凸 414 〇 該第一晶片420係設置於該基板410之該 41卜以使該第一晶片420之主動面緊貼於該y 並且該第一晶片420係具有複數個對準在該 塊容置孔413之第一電極422。該些第一凸塊 置於該些第一凸塊容置孔413内並電性連接 電極422至該基板410。 該第二晶片430設置於該基板410之該 412’以使該第二晶片43 0之主動面緊貼於該^ 並且該第二晶片430係具有複數個對準在該 塊容置孔414之第二電極432。該些第二凸塊 置於該些第二凸塊容置孔4 1 4内並電性連接 電極432至該基板410。該些外接端子450係 基板4 1 0,以供對外連接。 在本實施例中’請再參閱第5圖所示,該 對面堆疊封裝構造400可另包含有至少一 470,以擴充記憶體容量。該些第三晶片47〇 於該第二晶片430上。每一第三晶片47〇係具 銲墊471,其係形成該第三晶片47〇之主動面 藉由複數個銲線472電性連接該些銲墊471 。在本實施例中,該些第三晶片47〇之間 黑子450 〇 面 412、 塊容置孔 第一表面 Η反 4 1 0, 些第一凸 441係設 該些第一 第二表面 I 板 4 1 0, 些第二凸 442係設 該些第二 設置於該 多晶片面 第三晶片 係可堆疊 有複數個 邊緣,並 至該基板 係設有一 15 200834844 間隔片480,以提供該些第三晶片47〇在玉向堆 打線間隔’並且可避免位於在較上方之第三晶片 觸至相對下方之該些銲線472。 該多晶片面對面堆疊封襞構造400可另包含 膠體460 ’其係密封該第一晶片420、該些第 442、該第二晶片430、該些第三晶片47〇與該 472 ° φ 依據本發明之第四具體實施例,第6圖揭示 多晶片面對面堆疊封裝構造之截面示意圖,其基 係與第一具體實施例相同,更可堆疊更多晶片。 第6圖所示,該多晶片面對面堆疊封裝構造5 〇 〇 含一基板5 1 0、一第一晶片5 2 〇、複數個第一凸场 一第二晶片530、複數個第二凸塊542以及複數 端子55〇。該基板51〇係具有一第一表面511、 表面5 1 2、複數個第一凸塊容置孔5 1 3與複數個 ® 塊容置孔5 1 4。 該第一晶片520係設置於該基板5 i 〇之該第 511,並且該第一晶片520係具有複數個對準在 一凸塊容置孔513之第一電極522。該些第一凸 係設置於該些第一凸塊容置孔513内並電性連 第一電極522至該基板510。 該第二晶片5 3 0係設置於該基板5 i 〇之該第 5 1 2,並且該第二晶片5 3 0係具有複數個對準在 二凸塊容置孔5 1 4之第二電極5 3 2。該些第二凸 疊時之 470壓 有一封 二凸塊 些銲線 另一種 本架構 請參閱 主要包 L 541、 個外接 一第二 第二凸 一表面 該些第 塊54 1 接該些 一表面 該些第 塊5 42 16 200834844 係設置於該些第二凸塊容置孔514内並電性連接該些 第二電極532至該基板51〇。該些外接端子55〇係設置 於該基板5 1 0,以供對外接合。 該多晶片面對面堆疊封裝構造5〇〇可另包含有一第 三晶片570,其係設置於該第二晶片53〇上並藉由複數 個銲線572電性連接該第三晶片57〇之複數個銲墊571 至該基板5 1 0。此外,本發明不局限晶片所堆疊之數量。 • 請在參閱第6圖所示,該多晶片面對面堆疊封裝構造 500可另包含有至少一第四晶片58〇,以擴充記憶體容 量。該些第四晶片580可堆疊於該第一晶片52〇上。每 一第四晶片5 80係具有複數個銲墊5 8 i,其係形成該第 四晶片580之邊緣,並藉由複數個銲線582電性連接該 些銲墊5 8 1至該基板5 1 0。在本實施例中,該些第四晶 片5 8 0之間係設有一間隔片5 9 0,以供貼設其於之第四 晶片580,並且可避免位於上方之該第四晶片58〇壓觸 籲 至該些銲線582。 其中該多晶片面對面堆疊封裝構造5 0 0可另包含有 一封膠體560,其係密封該第一晶片520、該些第二凸 塊542、該第二晶片530、該些第三晶片57〇、該些第 四晶片與該些銲線572、582。 以上所述,僅是本發明的較佳實施例而已,並非對 本發明作任何形式上的限制,雖然本發明已以較佳實施 例揭露如上,然而並非用以限定本發明,任何熟悉本專 業的技術人員,在不脫離本發明技術方案範圍内,當可 17 200834844 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例,但凡是未脫離本發明技術方案的内 容,依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾,均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖:習知多晶片堆疊封裝構造之截面示意圖。 第2圖··依據本發明之第—具體實施例,一種多晶片面 對面堆疊封裝構造之戴面示意圖。 第3圖:依據本發明之第-具體實施例,該多晶片面對 面堆疊封裝構造中一基板之頂面示意圖。 第4圖:依據本發明之第:具體實施例,另-種多晶片 面對面堆疊封裝構造之戴面示意圖。 第5圖:依據本發明之第三具體實施例,另一種多晶片The substrate 310, a first wafer 32, a second wafer 33, a plurality of first bumps 341, a plurality of second bumps 342, and a plurality of external terminals 350. The substrate 31 has a first surface 311, a second surface 312, a plurality of first bump receiving holes 313 and a plurality of second bump valleys 3 1 4 . In this embodiment, the substrate 310 is a flexible circuit substrate ‘and may have a circuit layer 315 formed on the second surface 312. The active surface 321 of the first wafer 320 is disposed on the first surface 31 of the substrate 310, and the first wafer 320 has a plurality of first alignments in the first bump receiving holes 313. Electrode 3 22 . In the embodiment, the first electrodes 322 may be solder pads or bumps. The first bumps 34 are disposed in the first bump receiving holes 313 and electrically connected to the first electrodes 322 to the substrate 310. For example, the lead ends of the circuit layer 315 on the first bump receiving holes 3 1 3 can be soldered by wire bonding pins to be bonded to the first bumps 3 4 j. The active surface 3 3 1 of the second wafer 310 is disposed on the second surface 3 1 2 of the substrate 3 10 , and the second wafer 310 has a plurality of 13 200834844 aligned in the first The second bump accommodates the second electrode 332 of the hole 314. In this embodiment, the second electrodes 332 can be solder pads. The second bumps 3 42 are disposed in the second bump receiving holes 3丨4 and electrically connected to the second electrodes 3 3 2 to the substrate 3丨〇. For example, the ball end formed by the wire bonding needle can be used as the second bumps 342, which are soldered to the second electrodes 332, and the circuit layer 315 is bonded to the second bump receiving holes 3 14 Metal part. Further, the external terminals 35 are disposed on the substrate 3A for external bonding. In this embodiment, the external terminals 35 can be disposed on the first surface 311 of the substrate 310. Referring to FIG. 4 again, the multi-wafer face-to-face stacked package structure 3 can further include a glue 3 60' formed on the second surface 312 of the substrate 31 to seal the second wafer 330. The encapsulant 36 can be formed on one of the first surfaces 311 of the substrate 3 10 to seal the first wafer 32 and the second bumps 342. Therefore, the dual-wafer is stacked face-to-face and interposed between the substrates, so that the active surface of the wafer is in close contact with the upper surface of the substrate, and the bumps of the electrical connection are partially embedded in the substrate, so that the electrical shortening can be achieved. Connect the path and reduce the volume of the package construction. In accordance with a third embodiment of the present invention, FIG. 5 illustrates a cross-sectional view of another multi-wafer face-to-face stacked package configuration. Referring to FIG. 5, the multi-wafer face-to-face stacked package structure 400 is substantially the same as the second embodiment but can stack more wafers, and mainly includes a substrate 410, a first wafer 42A, and a second wafer 43. a plurality of first protrusions 14 200834844 blocks 441, a plurality of second bumps 442, and a plurality of external connections. The substrate 410 has a first surface 411, a second plurality of first bump receiving holes 413 and a plurality a second protrusion 414, the first wafer 420 is disposed on the substrate 410 such that the active surface of the first wafer 420 is in close contact with the y and the first wafer 420 has a plurality of alignments therein. The block houses the first electrode 422 of the hole 413. The first bumps are disposed in the first bump receiving holes 413 and electrically connected to the electrodes 422 to the substrate 410. The second wafer 430 is disposed on the 412' of the substrate 410 such that the active surface of the second wafer 43 0 is in close contact with the second wafer 430 and the second wafer 430 has a plurality of alignments in the block receiving hole 414. Second electrode 432. The second bumps are disposed in the second bump receiving holes 4 1 4 and electrically connected to the electrodes 432 to the substrate 410. The external terminals 450 are substrates 4 10 for external connection. In the present embodiment, please refer to FIG. 5 again. The opposite stacked package structure 400 may further include at least one 470 to expand the memory capacity. The third wafers 47 are on the second wafer 430. Each of the third wafers 47 is electrically connected to the active pads of the third wafer 47 by a plurality of bonding wires 472 electrically connected to the pads 471. In this embodiment, the third surface of the third wafer 47A is opposite to the first surface of the black surface 450, and the first surface of the block receiving hole is opposite to the first surface I plate. 4 1 0, the second protrusions 442 are disposed on the multi-chip surface, the third wafer system can be stacked with a plurality of edges, and the substrate is provided with a 15 200834844 spacer 480 to provide the The three wafers 47 are spaced apart from each other in the jade stack and can avoid the solder wires 472 located at the upper third wafer. The multi-wafer face-to-face stacked package structure 400 may further include a colloid 460 ′ which seals the first wafer 420 , the 442th portion, the second wafer 430 , the third wafers 47 〇 and the 472° φ according to the present invention. In a fourth embodiment, FIG. 6 is a cross-sectional view showing a multi-wafer face-to-face stacked package structure having the same basic structure as the first embodiment, and more wafers can be stacked. As shown in FIG. 6, the multi-chip face-to-face stacked package structure 5 includes a substrate 510, a first wafer 5 2 〇, a plurality of first bumps, a second wafer 530, and a plurality of second bumps 542. And a plurality of terminals 55 〇. The substrate 51 has a first surface 511, a surface 5 1 2, a plurality of first bump receiving holes 5 1 3 and a plurality of ® block receiving holes 5 1 4 . The first wafer 520 is disposed on the first 511 of the substrate 5 i , and the first wafer 520 has a plurality of first electrodes 522 aligned in a bump receiving hole 513 . The first protrusions are disposed in the first bump receiving holes 513 and electrically connected to the first electrode 522 to the substrate 510. The second wafer 530 is disposed on the fifth portion of the substrate 5 i ,, and the second wafer 530 has a plurality of second electrodes aligned in the two bump receiving holes 51 5 3 2. The 470 presses of the second bumps have a two bumps and some solder wires. The other structure is referred to as a main package L 541, and an external second second convex surface. The first blocks 54 1 are connected to the surfaces. The second blocks 5 42 16 200834844 are disposed in the second bump receiving holes 514 and electrically connected to the second electrodes 532 to the substrate 51 . The external terminals 55 are disposed on the substrate 510 for external bonding. The multi-wafer face-to-face stacked package structure 5 further includes a third wafer 570 disposed on the second wafer 53 and electrically connected to the third wafer 57 by a plurality of bonding wires 572. Pad 571 to the substrate 5 10 . Moreover, the invention is not limited to the number of stacked wafers. • As shown in Fig. 6, the multi-wafer face-to-face stacked package structure 500 may further include at least a fourth wafer 58A to expand the memory capacity. The fourth wafers 580 may be stacked on the first wafer 52A. Each of the fourth wafers 580 has a plurality of pads 5 8 i formed on the edge of the fourth wafer 580 , and the pads 582 are electrically connected to the substrate 5 by a plurality of bonding wires 582 . 1 0. In this embodiment, a spacer 105 is disposed between the fourth wafers 580 for attaching to the fourth wafer 580, and the fourth wafer 58 located above is prevented from being pressed. The wire bonds 582 are touched. The multi-wafer face-to-face stacked package structure 500 may further include a glue 560 that seals the first wafer 520, the second bumps 542, the second wafer 530, and the third wafers 57. The fourth wafers and the bonding wires 572, 582. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. A person skilled in the art can make some modifications or modifications to equivalent embodiments using the above-disclosed technical contents without departing from the technical scope of the present invention, but without departing from the technical solution of the present invention, The present invention is not limited to any simple modifications, equivalent changes and modifications of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional multi-wafer stacked package structure. Fig. 2 is a schematic view showing the wearing of a multi-chip face-to-face stacked package structure in accordance with a first embodiment of the present invention. Figure 3 is a top plan view of a substrate in a multi-wafer face-to-face stacked package configuration in accordance with a first embodiment of the present invention. Figure 4 is a schematic illustration of a wear side of a multi-wafer face-to-face stacked package construction in accordance with an embodiment of the present invention. Figure 5: Another multi-wafer in accordance with a third embodiment of the present invention

面對面堆疊封裝構造之截面示意圖。 第6圖:依據本發明之第四具體實施例,另一種多晶片 面對面堆疊封裝構造之戴面示意圖。 【主要元件符號說明】 100多晶片堆疊封裝構造 110 基板 111 第 一 113 槽孔 120 第一 曰 y B曰乃 121 主 動 123 背面 130 第二 晶片 131 主 動 表面 112第二表面 面 122銲墊 面 132銲墊 18A schematic cross-sectional view of a face-to-face stacked package structure. Figure 6 is a perspective view of another multi-wafer face-to-face stacked package construction in accordance with a fourth embodiment of the present invention. [Main component symbol description] 100 multi-chip stacked package structure 110 substrate 111 first 113 slot 120 first 曰 y B 曰 121 active 123 back 130 second wafer 131 active surface 112 second surface surface 122 pad surface 132 welding Pad 18

200834844 133背面 141銲線 142銲線 150外接端子 160封膠體 200多晶片面對面堆疊封裝構造 210基板 211第一表面 213第一凸塊容置孔 214第二凸塊容置孔 220第一晶片 221主動面 230第二晶片 231主動面 241第一凸塊 242第二凸塊 250外接端子 260封膠體 212 215 222 232 第二表面 線路層 第一電極 第二電極200834844 133 back 141 bonding wire 142 bonding wire 150 external terminal 160 sealing body 200 multi-chip face-to-face stacked package structure 210 substrate 211 first surface 213 first bump accommodating hole 214 second bump accommodating hole 220 first wafer 221 active Face 230 second wafer 231 active surface 241 first bump 242 second bump 250 external terminal 260 sealant 212 215 222 232 second surface circuit layer first electrode second electrode

300多晶片面對面堆疊封裝構造 310基板 311第一表面 313第一凸塊容置孔 314第二凸塊容置孔 320第一晶片 321主動面 330第二晶片 331主動面 341第一凸塊 342第二凸塊 350外接端子 360封膠體 400多晶片面對面堆疊封裝構造 410基板 411第一表面 312 315 322 332 412 第二表面 線路層 第一電極 第二電極 第二表面 413第一凸塊容置孔 414第二凸塊容置孔 420第一晶片 422第一電極 19 200834844 430第二晶片 441第一凸塊 450外接端子 470第三晶片 432第二電極 442第二凸塊 460封膠體 471銲墊 472銲線 480間隔片 500多晶片面對面堆疊封裝構造 512第二表面 510基板 511第一表面300 multi-chip face-to-face stacked package structure 310 substrate 311 first surface 313 first bump receiving hole 314 second bump receiving hole 320 first wafer 321 active surface 330 second wafer 331 active surface 341 first bump 342 Two bumps 350 external terminals 360 encapsulant 400 multi-wafer face-to-face stacked package structure 410 substrate 411 first surface 312 315 322 332 412 second surface circuit layer first electrode second electrode second surface 413 first bump receiving hole 414 Second bump receiving hole 420 first wafer 422 first electrode 19 200834844 430 second wafer 441 first bump 450 external terminal 470 third wafer 432 second electrode 442 second bump 460 sealant 471 pad 472 soldering Line 480 spacer 500 multi-wafer face-to-face stacked package configuration 512 second surface 510 substrate 511 first surface

513第一凸塊容置孔 514第二凸塊容置孔 520第一晶片 522第一電極 530第二晶片 541第一凸塊 550外接端子 532第二電極 542第二凸塊 560封膠體 570第三晶片 571銲墊 580第四晶片 581銲墊 572銲線 582銲線513 first bump receiving hole 514 second bump receiving hole 520 first wafer 522 first electrode 530 second wafer 541 first bump 550 external terminal 532 second electrode 542 second bump 560 sealant 570 Three wafers 571 pads 580 fourth wafers 581 pads 572 bonding wires 582 bonding wires

590間隔片 20590 spacer 20

Claims (1)

200834844 十、申請專利範圍·β 1、一種多晶片面對面堆疊封裝構造,包含: 一基板,其係具有一第一表面、一第二表面、複數個第 一凸塊容置孔與複數個第二凸塊容置孔; 一第一晶片,其主動面係設置於該基板之該第一表面, 並且該第一晶片係具有複數個對準在該些第一凸塊容置 孔之第一電極; • 複數個第一凸塊,其係設置於該些第一凸塊容置孔内並 電性連接該些第一電極至該基板; 一第二晶片,其主動面係設置於該基板之該第二表面, 並且該第二晶片係具有複數個對準在該些第二凸塊容置 孔之第二電極; 複數個第二凸塊,其係設置於該些第二凸塊容置孔内並 電性連接該些第二電極至該基板;以及 複數個外接端子,其係設置於該基板。 ® 2如申请專利範圍第!項所述之多晶片面對面堆疊封裝構 這,其中該些第一凸塊係由該基板之第二表面設置於該 些第一凸塊容置孔内,且該些第二凸塊係由該基板之第 一表面設置於該些第二凸塊容置孔内。 3、如申凊專利範圍第丨項所述之多晶片面對面堆疊封裝構 k ’其中該第二晶片係遮蓋該些第一凸塊容置孔,以使 該些第一凸塊位於該第一晶片與該第二晶片之間。 4如申明專利範圍第〗或3項所述之多晶片面對面堆疊封 裝構造’其中該第一晶片係具有小於該第二晶片之尺 21 200834844 寸,以不遮蓋該些第二凸塊容置孔。 、如申請專利範圍第4項所述之多晶片面對面堆#封裝構 造,其中該些第二凸塊位於該第一晶片之兩侧。 申月專利範圍第1項所述之多晶片面對面堆疊封裝構 k ’其中該些外接端子係設置於該基板之第二表面。 申叫專利範圍第1或6項所述之多晶片面對面堆疊封200834844 X. Patent Application Scope 1. β1, a multi-wafer face-to-face stacked package structure, comprising: a substrate having a first surface, a second surface, a plurality of first bump receiving holes and a plurality of second a bump receiving hole; a first wafer having an active surface disposed on the first surface of the substrate, and the first wafer has a plurality of first electrodes aligned on the first bump receiving holes a plurality of first bumps disposed in the first bump receiving holes and electrically connecting the first electrodes to the substrate; a second wafer having an active surface disposed on the substrate The second surface, and the second wafer has a plurality of second electrodes aligned on the second bump receiving holes; and a plurality of second bumps disposed on the second bumps And electrically connecting the second electrodes to the substrate; and a plurality of external terminals disposed on the substrate. ® 2 as claimed in the scope of patents! The multi-wafer face-to-face stacking structure of the present invention, wherein the first bumps are disposed in the first bump receiving holes by the second surface of the substrate, and the second bumps are The first surface of the substrate is disposed in the second bump receiving holes. 3. The multi-wafer face-to-face stacked package structure of the second aspect of the invention, wherein the second wafer system covers the first bump receiving holes, so that the first bumps are located at the first Between the wafer and the second wafer. 4. The multi-wafer face-to-face stacked package structure of claim </ RTI> wherein the first wafer has a size less than the second wafer of 21 200834844 inches to cover the second bump receiving holes. . The multi-wafer face-to-face stack package structure of claim 4, wherein the second bumps are located on both sides of the first wafer. The multi-wafer face-to-face stacked package structure described in the first paragraph of the patent application of the present invention, wherein the external terminals are disposed on the second surface of the substrate. The multi-wafer face-to-face stacking seal described in claim 1 or 6 of the patent scope 構4,其中該基板係具有一線路層,其係形成於該第 表面。 8 &gt; 由丄 ^請專利範圍第6項所述之多晶片面對面堆疊封裝構 =,另包含有一封膠體,其係形成於該基板之第一表面, 乂费封該第一晶片與該些第二凸塊。 9、如由 ^ 明專利範圍第8項所述之多晶片面對面堆疊封裝構 造,其中該封膠體係更形成於該基板之第二表面之一部 1 D饭’以密封該第二晶片。 ϋ申請專利範圍第1項所述之多晶片面對面堆疊封裝 u冓乂,其中該些外接端子係設置於該基板之第一表面。 秦如申凊專利範圍第1或11項所述之多晶片面對面堆疊 势構這,其中該基板係具有一線路層,其係形成於誃 卓二表面。 、μ 申請專利範圍第10項所述之多晶片面對面堆疊封裝 冓义,另包含有一封膠體,其係形成於該基板之 而 ^ 一衣 句’以密封該第二晶片。 如申晴專利範圍第12項所述之多晶片面對面堆疊封裝 籌込,其中該封膠體係更形成於該基板之第一表面之一 22 200834844 部位,以密封該第一晶片與該些第二凸塊。 14、 如申請專利範圍第1項所述之多晶片面對面堆疊封裝 構造’另包含有至少一第三晶片,其係設置於該第二晶 片上並電性連接至該基板。 15、 如申請專利範圍第1或14項所述之多晶片面對面堆疊 封裝構造,另包含有至少一第四晶片,其係設置於該第 一晶片上並電性連接至該基板。 16、 如申请專利範圍第1項所述之多晶片面對面堆疊封裝 構造’其中該基板係為一可撓性電路基板。 17、 如申請專利範圍第1項所述之多晶片面對面堆疊封裝 構造,其中該第一晶片與該第二晶片係為高頻記憶體晶 片。 18、 如申請專利範圍第1項所述之多晶片面對面堆疊封裝 構造,其中該些第一電極係為銲墊,該些第二電極係為 凸塊。 19、 妒申知專利範圍第1項所述之多晶片面對面堆聂封穿 構造,其中該些第一電極係為凸塊,該些第二電極係&amp; 銲蛰。 ί 234, wherein the substrate has a wiring layer formed on the first surface. 8 &gt; The multi-wafer face-to-face stacked package described in claim 6 of the patent scope, further comprising a colloid formed on the first surface of the substrate, the first wafer and the first wafer are sealed Second bump. 9. The multi-wafer face-to-face stacked package structure of claim 8, wherein the encapsulation system is formed on one of the second surfaces of the substrate to seal the second wafer. The multi-chip face-to-face stacked package described in claim 1, wherein the external terminals are disposed on the first surface of the substrate. The multi-wafer face-to-face stacking structure described in claim 1 or claim 11, wherein the substrate has a wiring layer formed on the surface of the second surface. The multi-wafer face-to-face stacked package described in claim 10 of the patent application, further comprising a colloid formed on the substrate to seal the second wafer. The multi-wafer face-to-face stacking package according to the 12th item of the Shenqing patent scope, wherein the encapsulation system is further formed on a portion of the first surface 22 of the substrate 22 200834844 to seal the first wafer and the second Bump. 14. The multi-wafer face-to-face stacked package structure of claim 1 further comprising at least one third wafer disposed on the second wafer and electrically connected to the substrate. 15. The multi-wafer face-to-face stacked package structure of claim 1 or claim 14, further comprising at least one fourth wafer disposed on the first wafer and electrically connected to the substrate. 16. The multi-wafer face-to-face stacked package structure of claim 1, wherein the substrate is a flexible circuit substrate. 17. The multi-wafer face-to-face stacked package structure of claim 1, wherein the first wafer and the second wafer are high frequency memory wafers. 18. The multi-wafer face-to-face stacked package structure of claim 1, wherein the first electrodes are pads and the second electrodes are bumps. 19. The multi-wafer face-to-face stacking structure of claim 1, wherein the first electrodes are bumps, and the second electrodes are &lt; ί 23
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US10991674B2 (en) 2018-03-29 2021-04-27 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic assembly and electronic system with impedance matched interconnect structures

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US10431549B2 (en) 2018-01-10 2019-10-01 Powertech Technology Inc. Semiconductor package and manufacturing method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10991674B2 (en) 2018-03-29 2021-04-27 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic assembly and electronic system with impedance matched interconnect structures

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