201236119 六、發明說明： 【發明所屬之技術領域】 • 本發明是有關於一種半導體封裝結構，且特別是有關 於一種具有載板與導電線路之封裝結構。 【先前技術】 隨著半導體技術的發展，封裝體整合愈來愈多的功 能，使得封裝體之元件數量與内部構造更加複雜。為了縮 小封裝結構之體積，以朝向微型化之目標，有必要將各封 Φ 裝體堆疊在一起，進而形成堆疊式封裝結構。 請同時參照第1A圖與第1B圖，第1A圖係繪示習知 技術中封裝結構的剖視示意圖，第1B圖係繪示習知技術中 封裝結構的俯視示意圖。封裝結構10包含一第一基板2卜 一第一晶片41、數個銲球61、一第一封膠71、一第二基 板22、一第二晶片42、數個銲線62、一第二封膠72以及 數個金屬球81。 第一基板21具有數個第一接墊31與數個第二接墊 32。第一晶片41位於第一基板21上，並具有數個第一銲 φ 墊51，此些第一銲墊51經由此些銲球61電性連接此些第 一接墊31。第一封膠71覆蓋第一晶片41、此些銲球61與 此些第一接墊31。 第二基板22位於第一封膠71之上方，並具有數個第 三接墊33與數個第四接墊34。第二晶片42位於第二基板 22上，並具有數個第二銲墊52，此些第二銲墊52經由此 些銲線62電性連接此些第三接墊33。第二封膠72覆蓋第 二晶片42、此些銲線62與此些第三接墊33。此些金屬球 . 81位於第一基板21與第二基板22之間，並電性連接此些 第二接墊32與此些第四接墊34。 201236119 在上述之習知技術中，當第一晶片41之厚度增加時， 為保持第一基板21與第二基板22間之電性連接，金屬球 81之高度Η需配合增加。由於金屬球81係為一球體，當 高度Η增加時，金屬球81之寬度W亦隨之增加。在第一 基板21與第二基板22之面積相同下，金屬球81之寬度W 限制了金屬球81所能設置的數量，使得第二晶片42與第 一基板21之間導電路徑的數量受限。再者，金屬球81的 高度Η有限，通常僅能設置一個第一晶片41，且第一晶片 41之厚度很小。 再者，因封裝結構10無散熱功能，常導致第一晶片 Ρ 41與第二晶片42之熱能往封裝結構10外散發的速度緩 慢，容易影響第一晶片41與第二晶片42之正常運作。同 時，封裝結構10亦無電磁屏蔽功能，以致無法屏蔽第一晶 片41與第二晶片42不受電磁波之干擾。 因此，目前亟需一種具有新穎性與進步性之封裝結 構，以解決上述之問題。 【發明内容】 φ 鑒於先前技術之問題，本發明之目的係提供一種具載 板之封裝結構。利用載板與導電線路電性連接晶片與基 板，俾能設置較多或較厚的晶片，同時藉由金屬層加強各 晶片之散熱效能，並屏蔽電磁波之干擾。 為達上述之目的，根據本發明之一態樣，具載板之封 裝結構包含一基板、一第一晶片、一第一載板、至少一第 二載板、數個導電線路以及一第二晶片。第一晶片位於基 板上，並電性連接基板。第一載板位於第一晶片之上方， 並具有數個導通孔，此些導通孔貫穿第一載板。第二載板 位於第一晶片之外側，並設置於基板上。此些導電線路自 201236119 第一載板延伸至第二載板，並電性連接此些導通孔與基 板。第二晶片位於第一載板上，並電性連接此些導通孔。 依據本發明一實施例，上述之第一載板更具有數個導 電材料、相對之一第一面與一第二面。第一面面向第一晶 片，第二晶片位於第二面上，此些導通孔貫穿第一面與第 二面，此些導電材料分別位於此些導通孔内，並電性連接 第二晶片與此些導電線路。 依據本發明一實施例，上述之封裝結構更包含數個銲 球，基板具有數個接墊，第二載板接觸此些接墊，第二晶 片具有數個銲墊，此些銲球位於此些銲墊與此些導通孔之 • 間，此些導電線路各自彎折成倒L形之形狀，並依序自此 些導通孔、第一載板、第二載板延伸至此些接墊。 依據本發明一實施例，上述之封裝結構更包含一第一 金屬層，第一金屬層覆蓋於第一載板上並具有數個開口， 開口顯露出導通孔，第二晶片電性隔絕第一金屬層。 依據本發明一實施例，上述之封裝結構更包含一第二 金屬層，第二載板具有相對之一第三面與一第四面，第三 面面向第一晶片，第二金屬層覆蓋於第四面上。上述之第 一金屬層與第二金屬層係用以對第一晶片及第二晶片作熱 •能之散發或電磁波之屏蔽。 依據本發明一實施例，上述之封裝結構更包含一第一 封膠與一第二封膠。第一封膠覆蓋基板與第一晶片，第二 封膠覆蓋第一載板與第二晶片。第一載板位於第一封膠之 上方，第二載板位於第一封膠之外側。 依據本發明一實施例，上述之封裝結構中，二個第二 載板位於第一載板之兩側，並與第一載板構成门字型之形 狀，此些導電線路沿著第一載板與第二載板各自彎折成倒 L型之形狀。 201236119 依據本發明一實施例，上述之封裝結構中，四個第二 載板位於第一載板之周圍，並與第一載板構成蓋子型之形 狀，此些導電線路沿著第一載板與第二載板各自彎折成倒 L型之形狀。 根據本發明之另一態樣，具載板之封裝結構包含一基 板、一第一晶片、一第一載板、至少一第二載板、數個導 電線路以及一第二晶片。第一晶片位於基板上，並電性連 接基板。第一載板位於第一晶片之上方。第二載板位於第 一晶片之外側，並設置於基板上。導電線路依序自第一載 板、第二載板延伸至基板。第二晶片位於第一載板上，並 • 具有數個銲墊，此些銲墊經由此些導電線路電性連接基板。 依據本發明一實施例，上述之封裝結構更包含數個銲 線，基板具有數個接墊，此些銲線電性連接此些銲墊與此 些導電線路，第二載板接觸此些接墊，此些導電線路各自 彎折成倒L形之形狀，並依序自第一載板、第二載板延伸 至此些接塾。 依據本發明一實施例，上述之封裝結構更包含一第一 金屬層，第一載板具有相對之一第一面與一第二面，第二 晶片位於第一面上，並面向第一晶片，第一金屬層覆蓋於 鲁第二面上。 依據本發明一實施例，上述之封裝結構更包含一第二 金屬層，第二載板具有相對之一第三面與一第四面，第三 面面向第一晶片，第二金屬層覆蓋於第四面上。上述之第 一金屬層與第二金屬層係用以對第一晶片及第二晶片作熱 能之散發或電磁波之屏蔽。 依據本發明一實施例，上述之封裝結構更包含一第一 封膠與一第二封膠。第一封膠覆蓋基板與第一晶片，第二 封膠接觸第一封膠，並覆蓋第一載板與第二晶片。第一載 201236119 板位於第二封膠之上方，第二載板位於第一封膠之外側。 依據本發明一實施例，上述之封裝結構中，二個第二 載板位於第一載板之兩側，並與第一載板構成门字型之形 狀，此些導電線路沿著第一载板與第二載板各自彎折成倒 L型之形狀。 依據本發明一實施例，上述之封裝結構中，四個第二 載板位於第一載板之周圍，並與第一載板構成蓋子型之形 狀，此些導電線路沿著第一載板與第二載板各自彎折成倒 L型之形狀。 根據本發明之又一態樣，具載板之封裝結構包含一基 板、一第一晶片、一第一載板、至少一第二載板、數個導 電線路以及一第二晶片。基板具有數個接墊。第一晶片位 於基板上，並電性連接基板。第一載板位於第一晶片之上 方。第二載板位於第一晶片之外側，並接觸此些接墊。導 電線路自第一載板延伸至第二載板，並電性連接接墊。第 二晶片位於第一載板上，並電性連接此些導電線路。 依據本發明一實施例，上述之封裝結構更包含數個銲 線，基板具有數個接墊，第二晶片具有數個銲墊，此些銲 線電性連接此些銲墊與此些導電線路，此些導電線路各自 彎折成倒L形之形狀。 依據本發明一實施例，上述之封裝結構更包含一第一 金屬層，第一載板具有相對之一第一面與一第二面，第一 面面向第一晶片，第一金屬層覆蓋於第一面上，第二晶片 位於第二面上。 依據本發明一實施例，上述之封裝結構更包含一第二 金屬層，第二載板具有相對之一第三面與一第四面，第三 面面向第一晶片，第二金屬層覆蓋於第三面上。上述之第 一金屬層與第二金屬層係用以對第一晶片及第二晶片作熱 201236119 能之散發或電磁波之屏蔽。 依據本發明一實施例，上述之封裝結構更包含一第一 封膠與一第二封膠，第一封膠覆蓋基板與第一晶片，第二 封膠覆蓋第一載板、第二晶片、第二載板與此些導電線路， 第一載板位於第一封膠之上方，第二載板位於第一封膠之 外側。 依據本發明一實施例，上述之封裝結構中，二個第二 載板位於第一載板之兩側，並與第一載板構成门字型之形 狀，此些導電線路沿著第一載板與第二載板各自彎折成倒 L型之形狀。 依據本發明一實施例，上述之封裝結構中，四個第二 載板位於第一載板之周圍，並與第一載板構成蓋子型之形 狀，此些導電線路沿著第一載板與第二載板各自彎折成倒 L型之形狀。 综上所述，本發明藉由載板與導電線路取代習知技術 之金屬球，用以電性連接晶片與基板。由於導電線路的寬 度較小，故可設置較多數量的導電線路於晶片與基板之 間。同時，導電線路能任意延展，在導電線路之高度增加 時，導電線路之寬度並不需隨之增加，因此可設置較多或 較厚的晶片。 【實施方式】 為了使本發明之敘述更加詳盡與完備，可參照所附之 圖式及以下所述各種較佳實施例，圖式中相同之號碼代表 相同或相似之元件。另一方面，眾所週知的元件與步驟並 未描述於實施例中，以避免造成本發明不必要的限制。 請參閱第2圖，係繪示本發明第一實施例中具載板之 封裝結構的剖視示意圖。封裝結構100包含一基板110、 201236119 至少一第一晶片121、一第一載板131、至少一第二載板 132、數個導電線路151以及一第二晶片122。 • 第一晶片121位於基板110上，並電性連接基板11〇。 第一載板131位於第一晶片121之上方，並具有數個導通 孔133 ’此些導通孔133貫穿第一載板131。第二載板132 位於第一晶片121之外側，並設置於基板11〇上。此些導 電線路151自第一載板131延伸至第二載板132，並電性 連接此些導通孔133與基板110。第二晶片122位於第一 載板131上，並電性連接此些導通孔133。 第一載板131更具有數個導電材料134、相對之一第 鲁一面141與一第二面142。第一載板131之第一面141面 向第一晶片121，第二晶片122位於第一載板131之第二 面142上，此些導通孔133貫穿第一載板131之第一面141 與第二面142,此些導電材料134分別位於此些導通孔133 内，並電性連接第二晶片122與此些導電線路151。 封裝結構100更包含數個銲球181或數個銲線182， 基板110具有數個第一接墊111，第一晶片121具有數個第 一銲墊171，此些第一銲墊171可經由此些銲球181或銲 線182電性連接此些第一接墊U1。 • 封裝結構1〇〇更包含數個銲球183，基板110更具有 數個第二接墊112，第二载板132接觸此些第二接墊ι12。 第二晶片122具有數個第二銲墊172，此些銲球183位於 此些第二銲墊172與此些導通孔133之間，用以電性連接 第二晶片122與此些導通孔133。 上述之導電線路151各自彎折成倒L形之形狀，並依 序自此些導通孔133、第一載板131之第一面14卜第二載 板132之第三面143延伸至基板11〇之第二接墊112，用以 . 電性連接此些導通孔133與基板11(^實作上，未彎折前 201236119 的導電線路151除直線外，亦可為斜線、彎曲線、規則型 線路、不規則型線路或任意形狀的線路。 封裝結構100更包含一第一金屬層161，第一金屬層 161覆蓋於第一載板131之第二面142上，並具有數個開 口 163，此些開口 163顯露出此些導通孔133，第二晶片 122電性隔絕第一金屬層ι61。 封裝結構100更包含一第二金屬層162，第二載板132 具有相對之一第三面143與一第四面144，第三面143面 向第一晶片121，第二金屬層162覆蓋於第二載板132之 第四面144上。201236119 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a semiconductor package structure, and more particularly to a package structure having a carrier and a conductive line. [Prior Art] With the development of semiconductor technology, more and more functions of package integration have made the component number and internal structure of the package more complicated. In order to reduce the size of the package structure, in order to achieve the goal of miniaturization, it is necessary to stack the Φ packages together to form a stacked package structure. Referring to FIG. 1A and FIG. 1B simultaneously, FIG. 1A is a cross-sectional view showing a package structure in the prior art, and FIG. 1B is a top plan view showing a package structure in the prior art. The package structure 10 includes a first substrate 2, a first wafer 41, a plurality of solder balls 61, a first sealant 71, a second substrate 22, a second wafer 42, a plurality of bonding wires 62, and a second Sealant 72 and a plurality of metal balls 81. The first substrate 21 has a plurality of first pads 31 and a plurality of second pads 32. The first wafer 41 is located on the first substrate 21 and has a plurality of first solder pads 51. The first pads 51 are electrically connected to the first pads 31 via the solder balls 61. The first adhesive 71 covers the first wafer 41, the solder balls 61 and the first pads 31. The second substrate 22 is located above the first sealant 71 and has a plurality of third pads 33 and a plurality of fourth pads 34. The second wafer 42 is disposed on the second substrate 22 and has a plurality of second pads 52. The second pads 52 are electrically connected to the third pads 33 via the bonding wires 62. The second sealant 72 covers the second wafer 42, the bonding wires 62 and the third pads 33. The metal balls 81 are located between the first substrate 21 and the second substrate 22, and are electrically connected to the second pads 32 and the fourth pads 34. 201236119 In the above-mentioned prior art, when the thickness of the first wafer 41 is increased, in order to maintain the electrical connection between the first substrate 21 and the second substrate 22, the height of the metal balls 81 is not required to be increased. Since the metal ball 81 is a sphere, as the height Η increases, the width W of the metal ball 81 also increases. Under the same area of the first substrate 21 and the second substrate 22, the width W of the metal ball 81 limits the number of metal balls 81 that can be disposed, so that the number of conductive paths between the second wafer 42 and the first substrate 21 is limited. . Further, the height of the metal ball 81 is limited, and usually only one first wafer 41 can be provided, and the thickness of the first wafer 41 is small. Moreover, because the package structure 10 has no heat dissipation function, the thermal energy of the first wafer 41 and the second wafer 42 is often dissipated outside the package structure 10, and the normal operation of the first wafer 41 and the second wafer 42 is easily affected. At the same time, the package structure 10 also has no electromagnetic shielding function, so that the first wafer 41 and the second wafer 42 cannot be shielded from electromagnetic waves. Therefore, there is a need for a novel and progressive packaging structure to solve the above problems. SUMMARY OF THE INVENTION In view of the problems of the prior art, it is an object of the present invention to provide a package structure having a carrier. The carrier and the conductive line are electrically connected to the substrate and the substrate, and more or thicker wafers can be disposed, and the heat dissipation performance of each wafer is enhanced by the metal layer, and electromagnetic wave interference is shielded. To achieve the above objective, according to one aspect of the present invention, a package structure having a carrier includes a substrate, a first wafer, a first carrier, at least one second carrier, a plurality of conductive lines, and a second Wafer. The first wafer is on the substrate and electrically connected to the substrate. The first carrier is located above the first wafer and has a plurality of vias extending through the first carrier. The second carrier is located on the outer side of the first wafer and disposed on the substrate. The conductive lines extend from the first carrier board of the 201236119 to the second carrier board, and are electrically connected to the via holes and the substrate. The second wafer is located on the first carrier and electrically connected to the vias. According to an embodiment of the invention, the first carrier has a plurality of conductive materials, a first surface and a second surface. The first surface faces the first wafer, and the second wafer is located on the second surface. The conductive holes are formed through the first surface and the second surface. The conductive materials are respectively located in the conductive vias and electrically connected to the second wafer and Such conductive lines. According to an embodiment of the invention, the package structure further includes a plurality of solder balls, the substrate has a plurality of pads, the second carrier contacts the pads, and the second wafer has a plurality of pads, wherein the solder balls are located Between the pads and the vias, the conductive lines are each bent into an inverted L shape, and sequentially extend from the via holes, the first carrier, and the second carrier to the pads. According to an embodiment of the invention, the package structure further includes a first metal layer covering the first carrier and having a plurality of openings, the opening revealing the via holes, and the second chip is electrically isolated first Metal layer. According to an embodiment of the invention, the package structure further includes a second metal layer, the second carrier has a third surface and a fourth surface opposite to each other, the third surface faces the first wafer, and the second metal layer covers the second metal layer The fourth side. The first metal layer and the second metal layer are used for heat dissipation or electromagnetic wave shielding of the first wafer and the second wafer. According to an embodiment of the invention, the package structure further includes a first sealant and a second sealant. The first adhesive covers the substrate and the first wafer, and the second seal covers the first carrier and the second wafer. The first carrier is located above the first seal and the second carrier is located outside the first seal. According to an embodiment of the present invention, in the package structure, the two second carrier plates are located on two sides of the first carrier board, and form a gate-shaped shape with the first carrier board, and the conductive lines are along the first carrier. The plate and the second carrier are each bent into an inverted L shape. According to an embodiment of the present invention, in the above package structure, four second carrier plates are located around the first carrier board and form a cover type shape with the first carrier board, and the conductive lines are along the first carrier board. And the second carrier is each bent into an inverted L shape. According to another aspect of the present invention, a package structure having a carrier includes a substrate, a first wafer, a first carrier, at least a second carrier, a plurality of conductive lines, and a second wafer. The first wafer is on the substrate and electrically connected to the substrate. The first carrier is located above the first wafer. The second carrier is located on the outer side of the first wafer and disposed on the substrate. The conductive lines extend from the first carrier and the second carrier to the substrate in sequence. The second wafer is located on the first carrier and has a plurality of pads electrically connected to the substrate via the conductive lines. According to an embodiment of the invention, the package structure further includes a plurality of bonding wires, the substrate has a plurality of pads, the bonding wires electrically connecting the pads to the conductive lines, and the second carrier contacts the contacts The pads, each of the conductive lines are bent into an inverted L shape, and sequentially extend from the first carrier plate and the second carrier plate to the plurality of contacts. According to an embodiment of the invention, the package structure further includes a first metal layer, the first carrier has a first surface and a second surface, and the second wafer is located on the first surface and faces the first wafer. The first metal layer covers the second side of the Lu. According to an embodiment of the invention, the package structure further includes a second metal layer, the second carrier has a third surface and a fourth surface opposite to each other, the third surface faces the first wafer, and the second metal layer covers the second metal layer The fourth side. The first metal layer and the second metal layer are used for heat dissipation or electromagnetic wave shielding of the first wafer and the second wafer. According to an embodiment of the invention, the package structure further includes a first sealant and a second sealant. The first adhesive covers the substrate and the first wafer, and the second seal contacts the first seal and covers the first carrier and the second wafer. The first load 201236119 plate is located above the second sealant, and the second carrier plate is located outside the first sealant. According to an embodiment of the present invention, in the package structure, the two second carrier plates are located on two sides of the first carrier board, and form a gate-shaped shape with the first carrier board, and the conductive lines are along the first carrier. The plate and the second carrier are each bent into an inverted L shape. According to an embodiment of the present invention, in the package structure, the four second carrier plates are located around the first carrier board and form a cover type shape with the first carrier board, and the conductive lines are along the first carrier board. The second carrier plates are each bent into an inverted L shape. According to still another aspect of the present invention, a package structure having a carrier includes a substrate, a first wafer, a first carrier, at least a second carrier, a plurality of conductive lines, and a second wafer. The substrate has a plurality of pads. The first wafer is located on the substrate and electrically connected to the substrate. The first carrier is above the first wafer. The second carrier is located on the outer side of the first wafer and contacts the pads. The conductive line extends from the first carrier to the second carrier and is electrically connected to the pad. The second chip is located on the first carrier and electrically connected to the conductive lines. According to an embodiment of the invention, the package structure further includes a plurality of bonding wires, the substrate has a plurality of pads, and the second chip has a plurality of pads, the bonding wires electrically connecting the pads and the conductive lines The conductive lines are each bent into an inverted L shape. According to an embodiment of the invention, the package structure further includes a first metal layer, the first carrier has a first surface and a second surface, the first surface faces the first wafer, and the first metal layer covers the first metal layer On the first side, the second wafer is on the second side. According to an embodiment of the invention, the package structure further includes a second metal layer, the second carrier has a third surface and a fourth surface opposite to each other, the third surface faces the first wafer, and the second metal layer covers the second metal layer The third side. The first metal layer and the second metal layer are used to shield the first wafer and the second wafer from heat or electromagnetic waves. According to an embodiment of the invention, the package structure further includes a first encapsulant and a second encapsulant, the first encapsulant covers the substrate and the first wafer, and the second encapsulant covers the first carrier, the second wafer, The second carrier and the conductive lines, the first carrier is located above the first seal, and the second carrier is located outside the first seal. According to an embodiment of the present invention, in the package structure, the two second carrier plates are located on two sides of the first carrier board, and form a gate-shaped shape with the first carrier board, and the conductive lines are along the first carrier. The plate and the second carrier are each bent into an inverted L shape. According to an embodiment of the present invention, in the package structure, the four second carrier plates are located around the first carrier board and form a cover type shape with the first carrier board, and the conductive lines are along the first carrier board. The second carrier plates are each bent into an inverted L shape. In summary, the present invention replaces the metal balls of the prior art by a carrier and a conductive line for electrically connecting the wafer and the substrate. Since the width of the conductive trace is small, a larger number of conductive traces can be placed between the wafer and the substrate. At the same time, the conductive lines can be arbitrarily extended. When the height of the conductive lines is increased, the width of the conductive lines does not need to be increased, so that more or thicker wafers can be disposed. DETAILED DESCRIPTION OF THE INVENTION In order to make the description of the present invention more complete and complete, reference should be made to the accompanying drawings and the claims On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessarily limiting the invention. Referring to Fig. 2, there is shown a cross-sectional view showing a package structure with a carrier in the first embodiment of the present invention. The package structure 100 includes a substrate 110, 201236119, at least a first wafer 121, a first carrier 131, at least a second carrier 132, a plurality of conductive lines 151, and a second wafer 122. • The first wafer 121 is located on the substrate 110 and electrically connected to the substrate 11A. The first carrier 131 is located above the first wafer 121 and has a plurality of vias 133'. The vias 133 extend through the first carrier 131. The second carrier 132 is located on the outer side of the first wafer 121 and disposed on the substrate 11A. The conductive lines 151 extend from the first carrier 131 to the second carrier 132 and electrically connect the vias 133 and the substrate 110. The second wafer 122 is located on the first carrier 131 and electrically connected to the vias 133. The first carrier 131 further has a plurality of conductive materials 134, a pair of the first side 141 and a second side 142. The first surface 141 of the first carrier 131 faces the first wafer 121, and the second wafer 122 is located on the second surface 142 of the first carrier 131. The vias 133 extend through the first surface 141 of the first carrier 131. The second surface 142 is disposed in the conductive vias 133 and electrically connected to the second wafer 122 and the conductive traces 151. The package structure 100 further includes a plurality of solder balls 181 or a plurality of solder lines 182. The substrate 110 has a plurality of first pads 111. The first wafer 121 has a plurality of first pads 171, and the first pads 171 are The solder balls 181 or the bonding wires 182 are electrically connected to the first pads U1. The package structure 1 further includes a plurality of solder balls 183. The substrate 110 further has a plurality of second pads 112, and the second carrier 132 contacts the second pads 126. The second wafer 122 has a plurality of second pads 172. The solder balls 183 are located between the second pads 172 and the vias 133 for electrically connecting the second wafer 122 and the vias 133. . The conductive lines 151 are each bent into an inverted L shape, and sequentially extend from the through holes 133, the first surface 14 of the first carrier 131, and the third surface 143 of the second carrier 132 to the substrate 11. The second pad 112 of the cymbal is used for electrically connecting the via holes 133 and the substrate 11 (the actual conductive line 151 of the unfolded before 201236119 is a straight line, and may also be a diagonal line, a curved line, a rule The package structure 100 further includes a first metal layer 161 covering the second surface 142 of the first carrier 131 and having a plurality of openings 163. The opening 163 exposes the via holes 133, and the second wafer 122 electrically isolates the first metal layer ι 61. The package structure 100 further includes a second metal layer 162, and the second carrier 132 has a third side opposite 143 and a fourth surface 144, the third surface 143 faces the first wafer 121, and the second metal layer 162 covers the fourth surface 144 of the second carrier 132.
因此，藉由第一金屬層161與第二金屬層162，使第 一晶片121與第二晶片122所產生的熱能快速散發至封裝 結構100外，讓第一晶片121與第二晶片122具有良好的 散熱功能。同時，第一金屬層161與第二金屬層162亦對 第一晶片121與第二晶片122具有電磁波之屏蔽效用》 封裝結構100更包含一第一封膠丨91與一第二封膠 192。第一封膠191覆蓋基板11〇與第一晶片121，第二封 膠192覆蓋第一載板131與第二晶片122。第一載板131 位於第一封膠191之上方，第二載板132位於第一封膠191 之外側。 此外，第一金屬層161、第一載板131與導電線路151 與=形成上下三層的結構，第二金屬層162、第二載板132 g導電線路151大致形成左右三層的結構。而且，第一載 ^31與第二載板132可為同一載板分割而成，或為不同 的载板纽合而成。 晴參閱第3A圖，係繪示本發明第一實施例中載板與 電線路之第一態樣的展開示意圖。舉例而言，载板與導 €線路之製造方法 ，可先將同一載板分割為三個，或提供 201236119 三個載板，其中一個為第一載板131，另二個為第二載板 ‘ 132,且二個第二載板132位於第一載板131之兩侧。接著， . 將數個導通孔133形成於第一載板131中。再來，將數個 導電線路151依序自此些導通孔133處延伸至第一載板131 與第二载板132上。最後，如第2圖所示，將第一載板131 與二個第二載板132構成類似门字型之形狀，使此些導電 線路151沿著第一載板131與第二載板132各自彎折成倒 L型之形狀。 請參閱第3B圖，係繪示本發明第一實施例中載板與導 電線路之第二態樣的展開示意圖。第二態樣與第一態樣之 • 構造及製造方法相似。但是，在第二態樣中，第二載板132 共有四個，並分別位於第一載板131之四周，數個導通孔 133形成於第一載板131中，數個導電線路151自此些導 通孔133處延伸至第一載板131與第二載板132上。第一 载板131與四個第二載板132可構成類似蓋子型之形狀（圖 未示）。又如第2圖所示，此些導電線路151可沿著第一載 板131與第二載板132各自彎折成倒L型之形狀。 在第2圖、第3A圖與第3B圖之第一實施例中，藉由 第一載板131、第二載板132與導電線路151取代習知技 _ 術之金屬球，用以電性連接第二晶片122與基板110。由 於導電線路151的寬度W1較小，故可設置較多數量的導 電線路151於第二晶片122與基板110之間。加上，導電 線路151能任意延展，在導電線路151之高度H1增加時， 導電線路151之寬度W1並不需隨之增加，因此可設置較 多或較厚的第一晶片121。 請參閱第4圖，係繪示本發明第二實施例中具載板之 封裝結構的剖視示意圖。封裝結構200包含一基板210、 ' 至少一第一晶片221、一第一載板231、至少一第二載板 201236119 232、數個導電線路251以及一第二晶片222。 第一晶片221位於基板210上，並電性連接基板210。 第一載板231位於第一晶片221之上方。第二載板232位 於第一晶片221之外侧，並設置於基板210上。此些導電 線路251依序自第一載板231、第二載板232延伸至基板 210。第二晶片222位於第一載板231上，並經由此些導電 線路251電性連接基板210。 封裝結構200更包含數個銲線281或銲球（圖未示）， 基板210具有數個第一接墊211，第一晶片221具有數個 第一銲墊271 ’此些第一銲墊271可經由此些銲線281或 _ 銲球電性連接此些第一接墊211。 封裝結構200更包含數個銲線282或銲球（圖未示）， 基板210具有數個第二接墊212，第二載板232接觸此些 第二接墊212，此些導電線路251延伸至此些第二接墊 212。第二晶片222具有數個第二銲墊272，此些第二銲墊 272可經由此些銲線282或銲球電性連接此些導電線路251 與此些第二接墊212。 封裝結構200更包含一第一金屬層261，第一載板231 具有相對之一第一面241與一第二面242，第二晶片222 鲁 位於第一載板231之第一面241上並面向第一晶片221， 第一金屬層261覆蓋於第一載板231之第二面242上。 封裝結構200更包含一第二金屬層262,第二載板232 具有相對之一第三面243與一第四面244，第三面243面 向第一晶片221，第二金屬層262覆蓋於第二載板232之 第四面244上。 因此，藉由第一金屬層261與第二金屬層262，使第 . 一晶片221與第二晶片222所產生的熱能快速散發至封裝 . 結構200外’讓第一晶片221與第二晶片222具有良好^ 12 201236119 散熱功能。同時，第一金屬層261與第二金屬層262亦對 •第一晶片221及第二晶片222具有電磁波之屏蔽效用。 上述之導電線路251各自彎折成倒L形之形狀，並依 序自第一載板231之第一面241、第二載板232之第三面 243延伸至基板210之第二接墊212,用以電性連接第二晶 片222與基板210。實作上，未彎折前的導電線路251除 直線外，亦可為斜線、彎曲線、規則型線路、不規則型線 路或任意形狀的線路。 封裝結構200更包含一第一封膠291與一第二封膠 292。第一封膠291覆蓋基板210與第一晶片221。第二封 • 膠292可接觸第一封膠291，並覆蓋第一載板231與第二 晶片222。第一載板231位於第二封膠292之上方，第二 載板232位於第一封膠291之外側。 此外，第一金屬層261、第一載板231與導電線路251 大致形成上下三層的結構，第二金屬層262、第二載板232 與導電線路251大致形成左右三層的結構。而且，第一載 板231與第二載板232可為同一載板分割而成，或為不同 的載板組合而成。 請參閱第5A圖，係繪示本發明第二實施例中載板與 • 導電線路之第一態樣的展開示意圖。舉例而言，載板與導 電線路之製造方法，可先將同一載板分割為三個，或提供 三個載板，其中一個為第一載板231，另二個為第二載板 232,且二個第二載板232位於第一載板231之兩侧。接著’ 將數個導電線路251形成於第一載板231與第二載板232 上。最後，如第4圖所示’將第一載板231與二個第二載 板232構成類似门字型之形狀，使此些導電線路251沿著 第一載板231與第二載板232各自彎折成倒L型之形狀。 請參閱第5B圖，係繪示本發明第二實施例中載板與導 13 201236119 電線路之第二態樣的展開示意圖。第二態樣與第一態樣之 構造及製造方法相似。但是，在第二態樣中，第二載板232 共有四個，並分別位於第一載板231之四周，數個導電線 路251位於第一載板231及第二載板232上。第一載板231 與四個第二載板232可構成類似蓋子型之形狀（圖未示）。 又如第4圖所示，此些導電線路251可沿著第一載板231 與第二載板232各自彎折成倒L型之形狀。Therefore, the thermal energy generated by the first wafer 121 and the second wafer 122 is quickly dissipated outside the package structure 100 by the first metal layer 161 and the second metal layer 162, so that the first wafer 121 and the second wafer 122 have good Cooling function. At the same time, the first metal layer 161 and the second metal layer 162 also have electromagnetic wave shielding effect on the first wafer 121 and the second wafer 122. The package structure 100 further includes a first sealing layer 91 and a second sealing layer 192. The first adhesive 191 covers the substrate 11A and the first wafer 121, and the second seal 192 covers the first carrier 131 and the second wafer 122. The first carrier 131 is located above the first sealant 191, and the second carrier 132 is located outside the first sealant 191. In addition, the first metal layer 161, the first carrier 131 and the conductive line 151 and the upper and lower layers are formed, and the second metal layer 162 and the second carrier 132 g conductive line 151 are substantially three-layered. Moreover, the first carrier 31 and the second carrier 132 may be divided into the same carrier or may be formed by different carrier plates. Referring to Fig. 3A, there is shown a developmental view of a first aspect of the carrier and the electrical circuit in the first embodiment of the present invention. For example, the manufacturing method of the carrier board and the lead line may first divide the same carrier board into three, or provide 201236119 three carrier boards, one of which is the first carrier board 131 and the other two are the second carrier board. '132, and two second carrier plates 132 are located on both sides of the first carrier plate 131. Next, a plurality of via holes 133 are formed in the first carrier 131. Then, a plurality of conductive lines 151 are sequentially extended from the through holes 133 to the first carrier 131 and the second carrier 132. Finally, as shown in FIG. 2, the first carrier 131 and the two second carriers 132 form a gate-like shape, such that the conductive lines 151 are along the first carrier 131 and the second carrier 132. Each is bent into an inverted L shape. Referring to Fig. 3B, there is shown a developmental view of a second aspect of the carrier and the conductive line in the first embodiment of the present invention. The second aspect is similar to the construction and manufacturing method of the first aspect. However, in the second aspect, the second carrier 132 has four and is located around the first carrier 131. The plurality of vias 133 are formed in the first carrier 131, and the plurality of conductive lines 151 are The via holes 133 extend to the first carrier 131 and the second carrier 132. The first carrier plate 131 and the four second carrier plates 132 may be formed in a shape similar to a cover type (not shown). As shown in Fig. 2, the conductive lines 151 are each bent along the first carrier 131 and the second carrier 132 into an inverted L shape. In the first embodiment of FIG. 2, FIG. 3A and FIG. 3B, the first carrier 131, the second carrier 132 and the conductive line 151 are used to replace the metal ball of the prior art for electrical purposes. The second wafer 122 is connected to the substrate 110. Since the width W1 of the conductive line 151 is small, a larger number of conductive lines 151 can be disposed between the second wafer 122 and the substrate 110. In addition, the conductive line 151 can be arbitrarily extended. When the height H1 of the conductive line 151 is increased, the width W1 of the conductive line 151 does not need to be increased, so that a larger or thicker first wafer 121 can be disposed. Referring to Figure 4, there is shown a cross-sectional view of a package structure with a carrier in accordance with a second embodiment of the present invention. The package structure 200 includes a substrate 210, 'at least one first wafer 221, a first carrier 231, at least one second carrier 201236119 232, a plurality of conductive lines 251, and a second wafer 222. The first wafer 221 is located on the substrate 210 and electrically connected to the substrate 210. The first carrier 231 is located above the first wafer 221. The second carrier 232 is located on the outer side of the first wafer 221 and disposed on the substrate 210. The conductive lines 251 extend from the first carrier 231 and the second carrier 232 to the substrate 210 in sequence. The second wafer 222 is located on the first carrier 231 and electrically connected to the substrate 210 via the conductive lines 251. The package structure 200 further includes a plurality of bonding wires 281 or solder balls (not shown). The substrate 210 has a plurality of first pads 211, and the first wafer 221 has a plurality of first pads 271 'the first pads 271 The first pads 211 can be electrically connected via the bonding wires 281 or _ solder balls. The package structure 200 further includes a plurality of bonding wires 282 or solder balls (not shown). The substrate 210 has a plurality of second pads 212. The second carrier 232 contacts the second pads 212. The conductive lines 251 extend. So far the second pads 212. The second wafer 222 has a plurality of second pads 272. The second pads 272 can electrically connect the conductive lines 251 and the second pads 212 via the bonding wires 282 or solder balls. The package structure 200 further includes a first metal layer 261. The first carrier 231 has a first surface 241 and a second surface 242. The second wafer 222 is disposed on the first surface 241 of the first carrier 231. Facing the first wafer 221, the first metal layer 261 covers the second surface 242 of the first carrier 231. The package structure 200 further includes a second metal layer 262. The second carrier 232 has a third surface 243 and a fourth surface 244. The third surface 243 faces the first wafer 221, and the second metal layer 262 covers the second surface. The fourth side 244 of the second carrier 232 is on the second side. Therefore, the thermal energy generated by the first wafer 221 and the second wafer 222 is quickly dissipated to the package by the first metal layer 261 and the second metal layer 262. The first wafer 221 and the second wafer 222 are disposed outside the structure 200. Has good ^ 12 201236119 cooling function. At the same time, the first metal layer 261 and the second metal layer 262 also have electromagnetic wave shielding effects on the first wafer 221 and the second wafer 222. The conductive lines 251 are each bent into an inverted L shape, and sequentially extend from the first surface 241 of the first carrier 231 and the third surface 243 of the second carrier 232 to the second pad 212 of the substrate 210. The second wafer 222 and the substrate 210 are electrically connected. In practice, the conductive line 251 before bending may be a diagonal line, a curved line, a regular type line, an irregular type line, or an arbitrary shape line, in addition to a straight line. The package structure 200 further includes a first sealant 291 and a second sealant 292. The first adhesive 291 covers the substrate 210 and the first wafer 221. The second seal 292 can contact the first seal 291 and cover the first carrier 231 and the second wafer 222. The first carrier 231 is located above the second encapsulant 292, and the second carrier 232 is located outside the first encapsulant 291. In addition, the first metal layer 261, the first carrier 231, and the conductive line 251 are substantially three-layered, and the second metal layer 262, the second carrier 232, and the conductive line 251 are substantially three-layered. Further, the first carrier 231 and the second carrier 232 may be divided into the same carrier or may be formed by combining different carriers. Referring to Fig. 5A, there is shown a developmental view of a first aspect of a carrier and a conductive line in a second embodiment of the present invention. For example, the manufacturing method of the carrier board and the conductive line may first divide the same carrier board into three or provide three carrier boards, one of which is the first carrier board 231 and the other two are the second carrier board 232. The two second carrier plates 232 are located on opposite sides of the first carrier 231. Then, a plurality of conductive lines 251 are formed on the first carrier 231 and the second carrier 232. Finally, as shown in FIG. 4, the first carrier 231 and the two second carrier 232 are formed in a shape resembling a gate shape, such that the conductive lines 251 are along the first carrier 231 and the second carrier 232. Each is bent into an inverted L shape. Referring to Figure 5B, there is shown a developmental view of a second aspect of the carrier board and the conductor 13 201236119 in the second embodiment of the present invention. The second aspect is similar to the construction and manufacturing method of the first aspect. However, in the second aspect, the second carrier 232 has four and is located around the first carrier 231, and the plurality of conductive lines 251 are located on the first carrier 231 and the second carrier 232. The first carrier 231 and the four second carriers 232 may be formed in a shape similar to a cover type (not shown). As shown in FIG. 4, the conductive lines 251 can be bent into an inverted L shape along the first carrier 231 and the second carrier 232, respectively.
在第4圖、第5A圖與第5B圖之第二實施例中，藉由 第一載板231、第二載板232與導電線路251取代習知技 術之金屬球’用以電性連接第二晶片222與基板210。由 於導電線路251的寬度W2較小，故可設置較多數量的導 電線路251於第二晶片222與基板210之間。加上，導電 線路251能任意延展’在導電線路251之高度H2增加時， 導電線路251之寬度W2並不需隨之增加，因此可設置較 多或較厚的第一晶片221。 請參閱第6圖’係繪示本發明第三實施例中具載板之 封裝結構的剖視示意圖。封裝結構3〇〇包含一基板31〇、 =少一第-晶4 32卜-第一載板331、至少一第二載板 、數個導電線路351以及一第二晶片322。 笙晶片321位於基板310上，並電性連接基板310。 於；，二?於第一晶片321之上方’第二載板332位 外側’此些導電線路351自第一載板331 =至第一載板332。第二晶片322位於第 並電性連接此些導電線路351。 戰板上 A柄更包含數_球381或錦線(圖未示）， = 第一接塾311，第一晶片321具有數個 銲飧雷14 *拉1^些第一銲墊371可經由此些銲球381或 ~線電性連接此些第一接塾311。 201236119 封裝結構3〇〇更包含數個銲線382或銲球（圖未示）， 基板310具有數個第二接塾312，第二晶片322具有數個 • 第一銲墊372，此些第二録墊372可經由此錄線382或 録球電性連接此些導電線路351。 封裝結構300更包含一第一金屬層361，第一載板331 具有相對之一第一面341與一第二面342，第〆面341面 向第一晶片321，第一金屬層361覆蓋於第一载板331之 第一面341上，第二晶片322位於第一載板331之第二面 342 上。In the second embodiment of FIG. 4, FIG. 5A and FIG. 5B, the first carrier 231, the second carrier 232 and the conductive line 251 are substituted for the metal ball of the prior art for electrical connection. Two wafers 222 and a substrate 210. Since the width W2 of the conductive line 251 is small, a larger number of conductive lines 251 can be disposed between the second wafer 222 and the substrate 210. In addition, the conductive line 251 can be arbitrarily extended. When the height H2 of the conductive line 251 is increased, the width W2 of the conductive line 251 does not need to be increased, so that a larger or thicker first wafer 221 can be disposed. Referring to Fig. 6 is a cross-sectional view showing a package structure with a carrier in a third embodiment of the present invention. The package structure 3 includes a substrate 31, = a first crystal, a first carrier 331, an at least one second carrier, a plurality of conductive lines 351, and a second wafer 322. The germanium wafer 321 is located on the substrate 310 and electrically connected to the substrate 310. 2, above the first wafer 321 'the outer side of the second carrier 332', the conductive lines 351 from the first carrier 331 = to the first carrier 332. The second wafer 322 is electrically connected to the conductive lines 351. The A handle on the battleboard further includes a number _ ball 381 or a brocade line (not shown), = a first interface 311, the first wafer 321 has a plurality of solder slings 14 * pull 1 ^ some of the first pads 371 can be The solder balls 381 or ~ are electrically connected to the first interfaces 311. 201236119 The package structure 3 further includes a plurality of bonding wires 382 or solder balls (not shown), the substrate 310 has a plurality of second interfaces 312, and the second wafer 322 has a plurality of first pads 372, The two recording pads 372 can be electrically connected to the conductive lines 351 via the recording line 382 or the recording ball. The package structure 300 further includes a first metal layer 361. The first carrier 331 has a first surface 341 and a second surface 342. The second surface 341 faces the first wafer 321 and the first metal layer 361 covers the first surface. On the first side 341 of a carrier 331, the second wafer 322 is located on the second side 342 of the first carrier 331.
封裝結構300更包含一第二金屬層362，第二載板332 具有相對之一第三面343與一第四面344 ,第三面343面 向第一晶片321，第二金屬層362覆蓋於第二載板332第 二面343上，並接觸第一金屬層361。 因此’藉由第一金屬層361與第二金屬層362 ’使第 一晶片321與第二晶片322所產生的熱能快速散發至封裝 結構300外’讓第一晶片321與第二晶片322具有良好的 散熱f能。同時，第一金屬層361與第二金屬層362亦對 第一晶片321與第二晶片322具有電磁波之屏蔽效用。 上述之導電線路351各自彎折成倒L形之形狀，並依 序自第一載板331之第二面342、第二載板332之第四面 344延伸至基板31〇之第二接墊312，用以電性連接第二晶 片322與基板310。實作上，未彎折前的導電線路351除 直線外’亦可為斜線、料線、規則型線路、不規則型線 路或任意形狀的線路。 封裝結構300更包含一第一封膠391與一第二封膠 392。第一封膠391覆蓋基板310與第-晶片32卜第二封 膠392覆蓋第-載板331、第二晶片322、第二載板332與 此些導電線路351。第—載板331位於第一封膠391之上 15 201236119 方，第二載板332位於第一封膠391之外侧。 此外，導電線路351、第一載板331與第一金屬層361 大致形成上下三層的結構，導電線路351、第二載板332 與第二金屬層362大致形成左右三層的結構。而且，第一 載板331與第二載板332可為同一載板分割而成，或為不 同的載板組合而成。 請參閱第7A圖，係繪示本發明第三實施例中載板與 導電線路之第一態樣的展開示意圖。舉例而言，載板與導 電線路之製造方法，可先將同一載板分割為三個，或提供 三個載板，其中一個為第一載板331，另二個為第二載板 . 332’且二個第二載板332位於第一載板331之兩側，並各 自與第一載板331之間保持一間距D，以利二個第二載板 332及導電線路351彎折於第一載板331之兩側。接著， 將數個導電線路351形成於第一載板331與第二載板332 上。最後，如第6圖所示，將第一載板331與二個第二載 板332構成類似门字型之形狀，使此些導電線路351沿著 第一載板331與第二載板332各自彎折成倒L型之形狀。 請參閱第7B圖，係繪示本發明第三實施例中載板與導 電線路之第二態樣的展開示意圖。第二態樣與第一態樣之 鲁 構造及製造方法相似。但是，在第二態樣中，第二載板332 共有四個，並分別位於第一載板331之四周。第一載板331 與四個第二載板332之間皆保持一間距D，以利四個第二 載板332及導電線路351彎折於第一載板331之四周。數 個導電線路351位於第一載板331及第二載板332上。第 一載板331與四個第二載板332可構成類似蓋子型之形狀 (圖未示）。又如第6圖所示，此些導電線路351可沿著第 一載板331與第二載板332各自彎折成倒L型之形狀。 在第6圖、第7A圖與第7B圖之第三實施例中，藉由 201236119 —載板331、第二載板332與導電線路351取代習知技 二=金屬球，用以電性連接第二晶片322與基板310。由 ‘電線路351的寬度W3較小，故可設置較多數量的導 、、路351於第二晶片322與基板31〇之間。加上，導電 線路3 51轨v 導 知任意延展’在導電線路351之高度H3增加時， 夕& 351之寬度W3並不需隨之增加，因此可設置較 夕欢較厚的第一晶片321。 要兒月的疋，本發明上述各實施例之元件亦可以其他 承件取代之。例如：基板可為載體、載板、電路板、 封裝基板、玻璃基板、陶瓷基板、單層板、多層 Ϊ載:層f或疊層板等。載板可為基板、電路板、載ί、 等。曰片件、絕緣體、非導電體、封裝膠體或連接體 2=電路線、導線、金屬線、銅線或連接線等。 屏“了金屬線路層、金屬屏蔽層、電磁 導通孔可為導電孔、電=層貫接穿:層;地線層等。 開槽等，可為缺口、孔洞'凹孔、凹槽:二= 導線、金屬純▲遥®導電層、導電柱、導電條、 墊可為•連接ί屬:屬:屬 接塾、連接塾、金屬墊、接點或弓I指等。可為 金球、錫球、金屬塊、凸塊、接點、導電元7為金屬球、 :。：線可為導線、金屬線、金線、 =元： =『、環氧樹脂、熱固性塑膠、聚酿胺類= 17 201236119 雖然本發明已以實施方式揭露如上，在不脫離本發明 之精神和範圍内，舉凡依本發明申請範圍所述之形狀、構 造、特徵及精神當可做些許之變更，因此本發明之專利保 護範圍須視本說明書所附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之說明如下： 第1A圖係繪示習知技術中封裝結構的剖視示意圖。 | 第1B圖係繪示習知技術中封裝結構的俯視示意圖。 第2圖係繪示本發明第一實施例中具載板之封裝結 構的剖視示意圖。 第3A圖係繪示本發明第一實施例中載板與導電線路 之第一態樣的展開示意圖。 第3B圖係繪示本發明第一實施例中載板與導電線路 之第二態樣的展開示意圖。 第4圖係繪示本發明第二實施例中具載板之封裝結 構的剖視示意圖。 • 第5A圖係繪示本發明第二實施例中載板與導電線路 之第一態樣的展開示意圖。 第5B圖係繪示本發明第二實施例中載板與導電線路 之第二態樣的展開示意圖。 第6圖係繪示本發明第三實施例中具載板之封裝結 構的剖視示意圖。 第7A圖係繪示本發明第三實施例中載板與導電線路 之第一態樣的展開示意圖。 第7B圖係繪示本發明第三實施例中載板與導電線路 201236119 之第二態樣的展開示意圖。The package structure 300 further includes a second metal layer 362. The second carrier 332 has a third surface 343 and a fourth surface 344 opposite to each other. The third surface 343 faces the first wafer 321 and the second metal layer 362 covers the first surface. The second carrier 332 has a second surface 343 and contacts the first metal layer 361. Therefore, the thermal energy generated by the first wafer 321 and the second wafer 322 is quickly dissipated to the outside of the package structure 300 by the first metal layer 361 and the second metal layer 362'. The first wafer 321 and the second wafer 322 are good. The heat dissipation f can. At the same time, the first metal layer 361 and the second metal layer 362 also have electromagnetic wave shielding effects on the first wafer 321 and the second wafer 322. The conductive lines 351 are each bent into an inverted L shape, and sequentially extend from the second surface 342 of the first carrier 331 and the fourth surface 344 of the second carrier 332 to the second pad of the substrate 31. 312, for electrically connecting the second wafer 322 and the substrate 310. In practice, the conductive line 351 before bending may be a diagonal line, a material line, a regular type line, an irregular type line or an arbitrary shape line except for a straight line. The package structure 300 further includes a first sealant 391 and a second sealant 392. The first adhesive 391 covers the substrate 310 and the first wafer 32 and the second seal 392 covers the first carrier 331, the second wafer 322, the second carrier 332, and the conductive lines 351. The first carrier 331 is located on the first sealant 391 15 201236119 side, and the second carrier 332 is located on the outer side of the first sealant 391. Further, the conductive line 351, the first carrier 331 and the first metal layer 361 are substantially three-layered, and the conductive line 351, the second carrier 332 and the second metal layer 362 are substantially three-layered. Further, the first carrier 331 and the second carrier 332 may be divided into the same carrier or may be formed by combining different carriers. Referring to Fig. 7A, there is shown a developmental view of a first aspect of a carrier board and a conductive line in a third embodiment of the present invention. For example, the manufacturing method of the carrier board and the conductive line may first divide the same carrier board into three or provide three carrier boards, one of which is the first carrier board 331 and the other two are the second carrier board. And the two second carrier plates 332 are located on both sides of the first carrier plate 331 and are respectively spaced apart from the first carrier plate 331 by a distance D, so that the two second carrier plates 332 and the conductive lines 351 are bent. Both sides of the first carrier 331. Next, a plurality of conductive lines 351 are formed on the first carrier 331 and the second carrier 332. Finally, as shown in FIG. 6 , the first carrier 331 and the two second carriers 332 form a gate-like shape, such that the conductive lines 351 are along the first carrier 331 and the second carrier 332 . Each is bent into an inverted L shape. Referring to Fig. 7B, there is shown a developmental view of a second aspect of the carrier and the conductive line in the third embodiment of the present invention. The second aspect is similar to the first aspect of the construction and manufacturing method. However, in the second aspect, the second carrier 332 has a total of four and is located around the first carrier 331. A distance D is maintained between the first carrier 331 and the four second carriers 332, so that the four second carriers 332 and the conductive lines 351 are bent around the first carrier 331. A plurality of conductive lines 351 are located on the first carrier 331 and the second carrier 332. The first carrier 331 and the four second carriers 332 may be formed in a shape similar to a cover type (not shown). Further, as shown in Fig. 6, the conductive lines 351 can be bent into an inverted L shape along the first carrier 331 and the second carrier 332, respectively. In the third embodiment of FIG. 6 , FIG. 7A and FIG. 7B , the carrier board 331 , the second carrier 332 and the conductive line 351 are replaced by the conventional technology 2=metal ball for electrical connection. The second wafer 322 and the substrate 310. Since the width W3 of the electric circuit 351 is small, a large number of leads and paths 351 can be provided between the second wafer 322 and the substrate 31A. In addition, the conductive line 3 51 rail v is arbitrarily extended. When the height H3 of the conductive line 351 is increased, the width W3 of the eve & 351 does not need to be increased, so that the first wafer having a thicker thickness can be set. 321. The components of the above embodiments of the present invention may also be replaced by other components. For example, the substrate may be a carrier, a carrier, a circuit board, a package substrate, a glass substrate, a ceramic substrate, a single layer, or a plurality of layers: a layer f or a laminate. The carrier board can be a substrate, a circuit board, a carrier, or the like.曰 piece, insulator, non-conductor, encapsulant or connector 2 = circuit wire, wire, wire, copper wire or connecting wire. The screen "metal circuit layer, metal shielding layer, electromagnetic conduction hole can be a conductive hole, electricity = layer through: layer; ground layer, etc.. Slotting, etc., can be a notch, a hole 'a hole, a groove: two = wire, metal pure ▲ remote® conductive layer, conductive column, conductive strip, pad can be • connection 属 genus: genus: genus, connection 塾, metal pad, contact or bow I finger, etc. can be gold balls, Tin ball, metal block, bump, contact, and conductive element 7 are metal balls, ::: wire can be wire, metal wire, gold wire, = yuan: = ", epoxy resin, thermosetting plastic, polyamine The present invention has been described in the above embodiments, and the present invention may be modified in many ways, without departing from the spirit and scope of the invention. The scope of the patent protection is defined by the scope of the appended claims. The following description of the present invention and other objects, features, advantages and embodiments of the present invention will become more apparent. The description of the schema is as follows: Figure 1A shows the conventional technology FIG. 1B is a schematic cross-sectional view showing a package structure of a carrier according to a first embodiment of the present invention. FIG. 2B is a schematic cross-sectional view showing a package structure of a carrier according to a first embodiment of the present invention. The figure shows a development of the first aspect of the carrier and the conductive line in the first embodiment of the present invention. FIG. 3B is a view showing the second aspect of the carrier and the conductive line in the first embodiment of the present invention. Fig. 4 is a cross-sectional view showing a package structure with a carrier in a second embodiment of the present invention. Fig. 5A is a view showing a first aspect of the carrier and the conductive line in the second embodiment of the present invention. FIG. 5B is a schematic exploded view showing a second aspect of a carrier board and a conductive line in a second embodiment of the present invention. FIG. 6 is a diagram showing a package structure of a carrier board according to a third embodiment of the present invention. Figure 7A is a schematic exploded view showing a first embodiment of a carrier board and a conductive line in a third embodiment of the present invention. Figure 7B is a diagram showing a carrier board and a conductive line in a third embodiment of the present invention. The expansion of the second aspect of 201236119 .
【主要元件符號說明】 10 ： 封裝結構 122 、 222 、 322 第二晶片 21 ： 第一基板 131 > 231 ' 331 第一載板 22 ： 第二基板 132 、 232 、 332 第二載板 31 ： 第一接墊 133 :導通孔 32 ： 第二接墊 134 :導電材料 33 ： 第三接墊 141 ' 241 ' 341 第一面 34 ： 第四接墊 142、242、342 第二面 41 ： 第一晶片 143、243、343 第三面 42 ： 第二晶片 144、244、344 第四面 51 ： 第一銲塾 151 ' 251 ' 351 導電線路 52 ： 第二銲墊 161 ' 261 ' 361 ： 第一金屬層 61 ： 鲜球 162、262、362 :第二金屬層 62 ： 銲線 163 :開口 71 ： 第一封膠 171 ' 271 ' 371 第一銲墊 72 ： 第二封膠 172 、 272 、 372 第二銲墊 81 ： 金屬球 181 ' 183 ' 381 鲜球 Η ： 高度 182 > 281 ' 282 > 382 :銲線 W ： 寬度 19卜 291、391 :第一封膠 100 、200、300 :封裝結構 192、292、392 :第二封膠 110 、210、310 :基板 m、H2、H3 :高度 111 、211、311 :第一接墊 W1 > W2 > W3 ： 寬度 112 、212、312 :第二接墊 D :間距 121、221、321 :第一晶片 19[Main component symbol description] 10: package structure 122, 222, 322 second wafer 21: first substrate 131 > 231 '331 first carrier 22: second substrate 132, 232, 332 second carrier 31: A pad 133: via hole 32: second pad 134: conductive material 33: third pad 141 '241' 341 first face 34: fourth pad 142, 242, 342 second face 41: first chip 143, 243, 343 third face 42: second wafer 144, 244, 344 fourth face 51: first pad 151 '251 ' 351 conductive line 52: second pad 161 '261 ' 361 : first metal layer 61 : Fresh balls 162, 262, 362: second metal layer 62: bonding wire 163: opening 71: first glue 171 ' 271 ' 371 first bonding pad 72: second sealing 172, 272, 372 second welding Pad 81: Metal ball 181 '183 ' 381 Fresh ball Η : Height 182 > 281 ' 282 > 382 : Wire W : Width 19 291 , 391 : First sealant 100 , 200 , 300 : Package structure 192 , 292, 392: second sealant 110, 210, 310: substrate m, H2, H3: height 111, 211 311: first pad W1 > W2 > W3 : width 112, 212, 312: second pad D: pitch 121, 221, 321 : first wafer 19