TWM254725U - Stacked multi-chip packages - Google Patents

Description

M254725

[Technical field to which the new type belongs] This creation is about ^ _ ^ ^ About-a kind of chip is small and stacked, and the packaging structure 'is particularly [prior art] a large chip packaging structure on the stack. Polycrystalline-package body sealant is a conventional multi-chip stacked package structure. For example, a multi-chip package structure proposed in European Patent No. 1 01 462, which uses wafer stacking technology to combine multiple wafers into a β On a substrate, a glue-like adhesive such as epoxy or a film adhesive is used as a bonding agent between the wafers, but it is missing if the glue-like adhesive or the film cannot provide a contract. A pitch of 0 · 2mm is used as a spacer between the two wafers, and when the wafer stack is rich, it will be limited to being able to be stacked from large to small. "Multi-chip module package" (= two: two MCM package), such as combining two 256M2 ram memory chips with the package to get the 512M valley package structure, without the need to directly manufacture a 512m single chip, or A variety of chips with different functions, such as memory, logic chips, and microprocessors, are formed into a package body, and α achieves a complete function, that is, the so-called "System In Package" (SIP). In order to achieve the independence of the chip size when stacking wafers, another conventional multi-chip stacked package structure, such as disclosed in China Patent Bulletin No. 4 9 7 7 5 7 “Multi-chip Stacked Package Structure”, includes The plurality of small and large wafers are piled up, which uses a plurality of elastic and electrically insulating pads' to provide a pitch with sufficient wire height, however

M254725 IV. Creation instructions (2) When the pads are attached, the upper support is made so that the [new content book creation is located on the phase (large) crystal (large) of the main elastic filling wafer and a substrate between the wafer. The next time a flexible filling space structure 'utilizes one to provide the second creative structure, using another structure between the wafer and the second crystal to create the short circuit or open circuit when the electricity of a substrate is used. Fillingly connects some electrically adjacent two wafers. When there is no effective support under the pads around the bonding pads of the upper (large) wafer, there may be cracks or breaks during the wiring. The purpose is to provide a multi-chip stacked package junction glue which is provided on one of the second wafers stacked on a first wafer and covers the periphery of the back surface of the second wafer for wire bonding support. The purpose is to provide a multi-chip stacked package junction glue that surrounds a first wafer and a third layer formed on a first wafer and a third layer to avoid forming a hole (v o i d) between the first wafer when forming a colloid. The purpose is to provide a multi-chip stacked package junction filling glue to cover a plurality of electrical connections between a first chip and a device (such as a bonding wire), so as to avoid forming a colloidal connection device wire sweeping and creating a creative A multi-chip stacked package structure includes a substrate, a chip, a second chip, an elastic filler, and a gel. The substrate has an upper surface and a lower surface, and the first wafer is disposed on the substrate. The top surface of the soil is electrically connected to the substrate by a plurality of electrical connection devices. The second chip has an active surface and a back surface. The active surface of the second chip is larger than the active surface of the first chip. And a plurality of bonding pads are formed around the active surface of the second wafer, and the second wafer has the active surface facing upward

M254725

The mode is set on the first connection, the electrical connections on the first chip are filled on the periphery of the back of the first chip, and the rubber connection surrounds the electrical connection devices between the second chip. The device punch line (ψ glue system is used to protect the lower surface of the substrate. [Embodiment] A spacer layer is provided on the wafer and a plurality of bonding wires are electrically connected to the substrate and the second wafer. = Will contact the back of the second wafer, the elastic fill between the wafer and the substrate, and cover the second wafer to support the second wafer when wiring, and the elastic fill spacer layer to avoid the seal The colloid forms a hole (Void) in the first wafer, the elastic filling glue covers the covering, so as to avoid a short circuit or an open circuit caused by the electrical ire sweeping when a colloid is formed, the sealing the first A wafer and the second wafer are preferably connected with a plurality of solder balls. With reference to the attached drawings, the present invention will enumerate the following embodiment descriptions. According to a specific embodiment of the brother of this creation, as shown in FIG. 1, a multi-chip stacked packaging structure 100 is used to package at least two chips, mainly including a substrate 110, a first chip 120, and a second chip. 130. An elastic filler 140 and a colloid 150. The substrate 11 can be regarded as a micro circuit board with circuit distribution. It can be a single-layer board or a multi-layer board according to actual needs. The substrate 11 has an upper surface 111 and a lower surface 112 ′. The upper surface ill is used to carry the first chip 11 0 ′, and the lower surface 112 is used to implant a plurality of solder balls 1 70 which are electrically connected to the outside, such as a lead-tin alloy. The upper surface 111 of the substrate 11 has the solder balls corresponding to and electrically connected to the above-mentioned plurality of connection pads to electrically connect the first chip j 2〇 and the

M254725 Fourth, creation instructions (4) Two wafers 1 3 0. The first chip 120 has an active surface 121 formed with a plurality of bonding pads 122. The first chip 120 may be a dynamic random access memory (DRAM), a static random access memory Take § self-memory (static random access memory (SRAM), flash memory, flash memory, microprocessor (micro contro 1 1 er) or other functional chip of logic, the first chip i 20 series Adhesive or adhesive film is fixed on the upper surface of the substrate 11 〇, the internal electrical connection between the first chip 120 and the substrate 11 is connected with a plurality of electrical connection devices 123 such as bonding wires. The bonding pads 122 of the first wafer 120 and the corresponding connection pads on the upper surface 111 of the substrate 110. The second chip 130 has an active surface 131 and a back surface 132. A plurality of bonding pads 133 are formed around the active surface 131. The second chip 130 is connected to the second chip 130 by a plurality of bonding wires 134. The bonding pad 133 and the corresponding connection pad on the upper surface 111 of the substrate 110, the active surface 1 31 of the second wafer 13 is larger than the active surface 1 2 1 of the first wafer 1 2 0, and the second wafer 1 3 0 is arranged on the first wafer with the active surface 1 31 facing upward, and a spacer layer 140 is provided between the first wafer 120 and the second wafer 130, so that the second wafer 130 and The first wafer 120 forms a gap, and the spacer block 140 is a dummy wafer or a metal block to provide sufficient rigidity to avoid the back surface of the second wafer 130 when the second wafer 130 is disposed. 2 touches the electrical connection devices 1 2 3, the elastic filling glue 1 50 is disposed between the second chip 3 0 and the substrate 1 10 and covers the back of the second chip 1 3 0 1 3 2 periphery, and the elastic filling glue 1 50 surrounds the spacer layer 14 and covers the electrical contacts.

Page 10 M254725 IV. Creation instructions (5) --- Connecting device 123 'The material of the elastic filler 150 can be epoxy or silicone. When the wire is bonded, the elastic filler The 150 series has been cured to support the second wafer 13 and avoid cracks or breaks in the second wafer 130. When a colloid is formed, it is affected by the electrical connection devices due to mold flow. 2 3 It is difficult to completely cover the spacer layer I 4 0 ′ and form a void between the first wafer j 2 〇 and the second wafer 1 3 〇, since the elastic filling glue 15 ° surrounds the space The cushion layer 14o is covered with 4 electrical connection devices 1 2 3 to prevent the formation of holes (v oid) and to prevent the electrical connection devices 1 2 3 from being caused by die flow. ) A short circuit or an open circuit occurs. The sealing compound 160 is disposed on the upper surface 111 of the substrate II 0 to protect the first wafer 120 and the second wafer 130. The present invention exemplifies a second specific embodiment. As shown in FIG. 2, a multi-chip stacked package structure 20 0 mainly includes a substrate 21 0, a first wafer 220, a second wafer 230, and an elastic filling glue 240. And a piece of colloid 250. The substrate 2 10 has an upper surface 211 and a lower surface 212, the first wafer 220 has an active surface 221, and is bonded to the upper surface 211 of the substrate 210 with a plurality of bumps 221. The 230 series has an active surface 231 and a back surface 232 'The active surface 231 is formed with a plurality of welding pads 233' The second wafer 230 is disposed on the first wafer 220 with the active surface 231 facing upwards' The active surface 231 of the first chip 230 is larger than the active surface 221 of the first chip 220, and the second chip 230 is connected to the upper surface of the pad 2 33 and the substrate 2 10 of the second chip 230 with a plurality of bonding wires 233. 211. The elastic filler 240 is disposed between the second wafer 230 and the substrate 21.

Page 11 M254725 IV. Creation instructions (6) Cover the periphery of the back surface 232 of the second wafer 230 to support the second wafer 130 during wire bonding to avoid cracks or breaks in the second wafer 230 during wire bonding. The material of the elastic filler 240 may be epoxy or silicone. The sealant 250 is disposed on the upper surface 211 of the substrate 210 to protect the first chip 220 and the second chip. The wafer 23 0 is preferably formed with a plurality of solder balls 260 on the lower surface 212 of the substrate 2 10 after the sealing compound 250 is formed.

The scope of protection of this creation shall be determined by the scope of the attached patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of this creation shall fall within the scope of protection of this creation. .

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Schematic illustration 1 diagram · According to the first of this creation-and to do each # 九 丨 body 々 specific examples, a multi-chip stacked package structure; and Yin and [Schematic description] Figure 2: Based on this creation Xi Xi-The first specific embodiment created by Seiichi Yada, another kind of encapsulation structure. Moon stack element 100 110 120 123 130 133 140 150 160 170 200 210 220 230 233 240 250 Brief description of symbols: 111 top surface 112 bottom surface 121 active surface 122 pads 131 active surface 132 back surface 134 welding wire structure 211 upper surface 212 Lower surface 221 Active surface 222 Bump 231 Active surface 232 Back surface 234 Welding wire multi-chip stacking package structure substrate Di-chip electrical connection device Second wafer pad spacers Elastic filling gel sealant solder ball wafer wafer multi-chip stacking The first pad of the sealing substrate is elastically filled with the sealing compound.

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Claims (1)

M254725 5. Scope of patent application [Scope of patent application, one more substrate, one first substrate, a plurality of substrates; a second active active surface, a plurality of plates facing upwards; a space, a chip stacking package structure, It includes., Which has an upper surface and a lower surface. The chip 'has an active face, the first chip is provided on the upper surface; the electrical connection device, which is far from electric (2) The first chip and the chip are connected, which has an active surface B and a back surface, the second crystal surface is larger than the active surface of the first wafer, and a plurality of peripheral portions of the second wafer are formed. Soldering pads, the second wafer is provided on the first wafer in a main manner; bonding wires, which are electrically connected to the pads of the second wafer to the base pad layer, are provided on the first wafer and The second elastic filling glue of the second wafer is disposed between the second wafer and the substrate, and the flexible filling glue supports the second wafer when it covers the periphery of the back surface of the second wafer; and a colloid 'It is set in the Above the plate surface 'this tab 2 for protecting a wafer and the second wafer. /, &Quot; μ 珩 1 = The multi-chip stacked package described in item 丨 of the patent application scope 妗 3 ^, the elastic filling glue surrounds the spacer layer. Q, the multi-chip stacked package I g described in the first item of the patent application scope, wherein the elastic filling rubber-based package item covers the electrical connection devices in a relatively structured manner, M254725 V. Application for patent scope 4, if the application is for elasticity 5, if the application is for elasticity 6, if the application is for inclusion, it contains 7, a polycrystalline substrate, and a first crystal on the substrate. The active side of the active side has a plurality of welding plates with the circumferential side facing upwards; an elastic fill is used for a colloid, a chip and the 8, when applying for the special one, the elasticity 9, and the application for the elasticity benefit item 1 In the multi-chip stacked package structure, the material of the filling glue is epoxy resin (EP × Xy). The multi-chip stacked package structure described in the first item of the profit range, the material of the filling glue is silicon resin (Si 1 icone). The multi-chip stacked package structure described in the first item of the invention has a plurality of solder balls planted on the lower surface of the substrate. The chip stack package structure includes: it has an upper surface and a lower surface; the chip 'has an active surface, the first chip is provided on the surface; the chip has an active surface and a back surface, the The second crystal system is larger than the active surface of the first wafer, and a plurality of bonding pads are formed on the second wafer side. The second wafer is mainly arranged on the first wafer. The wires are electrically connected. The bonding pad of the second wafer to the base filler is provided between the second wafer and the substrate to support the second wafer; and it is provided on the upper surface of the substrate to protect the first wafer. Second wafer. The multi-chip stacked package structure described in the seventh item of the invention, the filling glue covers the periphery of the back surface of the second chip. The multi-chip stacked package structure described in item 7 of the scope of interest, the material of the filler is epoxy. 16 Page 16 M254725 5. Application scope of patent 10. The multi-chip stacked package structure described in item 7 of the scope of application for patent, wherein the material of the elastic filler is silicon resin (Si cone). 11. The multi-chip stacked package structure described in item 7 of the scope of patent application, further comprising a plurality of solder balls planted on the lower surface of the substrate. Page 17