TWM254725U - Stacked multi-chip packages - Google Patents
Stacked multi-chip packages Download PDFInfo
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- TWM254725U TWM254725U TW093202324U TW93202324U TWM254725U TW M254725 U TWM254725 U TW M254725U TW 093202324 U TW093202324 U TW 093202324U TW 93202324 U TW93202324 U TW 93202324U TW M254725 U TWM254725 U TW M254725U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
M254725M254725
【新型所屬之技術領域】 本創作係有關於^ _ ^ ^ 關於-種晶片由小而堆,封裝結構’特別是有 【先前技術】 大在上堆豐之多晶片封裝結構。 多晶-封裝體内封膠 一種習知之多晶片堆疊封裝結構,如歐盟專利案第 1 00 1 462號中提出一種多晶片封裝結構,其係利用晶片堆 鳌技術將複數個晶片結合於一 β G a基板上,並以如環氧樹 脂(epoxy)之膠狀黏著劑或膠膜(film adhesive)作為晶片 之間之結合劑,但其缺失為若膠狀黏著劑或膠膜無法提供 一約0· 2mm間距,以作為兩晶片間之間隔物(spacer),則 在晶片堆豐時將受限於僅能由大而小往上堆疊。 的「多晶片模組封裝」(=二:二 MCM package),如將兩25 6M2〇ram記憶體晶片結合封裝而 知到512M谷里之封裝結構,而不需直接製造512m之單晶 片,或將多種不同功能之晶片,如記憶體、邏輯晶片及微 處理器等晶片形成一封裝體内,α達到完整之功能,也就 是說所謂的「系統封裝」(System In Package,SIP)。 為了能夠達到堆豐晶片時不受晶片尺寸影響,另一種 習知之多晶片堆疊封裝結構,如我國專利公告第4 9 7 7 5 7號 「多晶片堆疊封裝結構」所揭示者,其係包含有複數個由 小而大往上堆豐之晶片,其係利用複數個具有彈性及電性 絕緣之墊塊’用以提供一間距而有足夠之打線高度,然而[Technical field to which the new type belongs] This creation is about ^ _ ^ ^ About-a kind of chip is small and stacked, and the packaging structure 'is particularly [prior art] a large chip packaging structure on the stack. Polycrystalline-package body sealant is a conventional multi-chip stacked package structure. For example, a multi-chip package structure proposed in European Patent No. 1 01 462, which uses wafer stacking technology to combine multiple wafers into a β On a substrate, a glue-like adhesive such as epoxy or a film adhesive is used as a bonding agent between the wafers, but it is missing if the glue-like adhesive or the film cannot provide a contract. A pitch of 0 · 2mm is used as a spacer between the two wafers, and when the wafer stack is rich, it will be limited to being able to be stacked from large to small. "Multi-chip module package" (= two: two MCM package), such as combining two 256M2 ram memory chips with the package to get the 512M valley package structure, without the need to directly manufacture a 512m single chip, or A variety of chips with different functions, such as memory, logic chips, and microprocessors, are formed into a package body, and α achieves a complete function, that is, the so-called "System In Package" (SIP). In order to achieve the independence of the chip size when stacking wafers, another conventional multi-chip stacked package structure, such as disclosed in China Patent Bulletin No. 4 9 7 7 5 7 “Multi-chip Stacked Package Structure”, includes The plurality of small and large wafers are piled up, which uses a plurality of elastic and electrically insulating pads' to provide a pitch with sufficient wire height, however
M254725 四、創作說明(2) 該些墊塊係 時,在該上 撐,使得該 【新型内容 本創作 位於相 (大)晶 上(大) 之主要 彈性填 晶片與一基板之間 晶片於 之次一 彈性填 之間隔 構’利用一 提供該第二 本創作 構,利用一 晶片之間 晶片與該 第二晶 本創作之再一 構,利用一 一基板之電 時,造成該 短路或斷路 彈性填 性連接 些電性 鄰兩晶片之間,當上(大)晶片打線接合 片周邊之該些銲墊下方不具有有效支 晶片可能在打線時產生裂縫或斷裂。 目的係在於提供一種多晶片堆疊封裝結 充膠設於堆疊在一第一晶片上之一第二 ’並覆蓋至該第二晶片之背面周邊,以 打線接合時之支撐。 目的係在於提供一種多晶片堆疊封裝結 充膠環繞於一形成於一第一晶片與一第 塾層’以避免形成一封膠體時,於該第 片之間形成孔洞(v 〇 i d )。 目的係在於提供一種多晶片堆疊封裝結 充膠包覆複數個電性連接一第一晶片與 裝置(如銲線),以避免形成一封膠體 連接裝置沖線(wire sweeping)而發生 一創作之多晶片堆疊封裝結構,其包含有一基板、 "曰曰片、一第二晶片、一彈性填充膠及一封膠體,其 ,基板具有-上表面及_下表面,㉟第—晶片係設於該 土反^上表面,以複數個電性連接裝置電性連接至該基 板,邊第二晶片係具有一主動面及一背面,該第二晶片之 主動面係大於該第一晶片之主動面,且該第二晶片之主動 面周邊係形成有複數個銲墊,該第二晶片係以主動面朝上M254725 IV. Creation instructions (2) When the pads are attached, the upper support is made so that the [new content book creation is located on the phase (large) crystal (large) of the main elastic filling wafer and a substrate between the wafer. The next time a flexible filling space structure 'utilizes one to provide the second creative structure, using another structure between the wafer and the second crystal to create the short circuit or open circuit when the electricity of a substrate is used. Fillingly connects some electrically adjacent two wafers. When there is no effective support under the pads around the bonding pads of the upper (large) wafer, there may be cracks or breaks during the wiring. The purpose is to provide a multi-chip stacked package junction glue which is provided on one of the second wafers stacked on a first wafer and covers the periphery of the back surface of the second wafer for wire bonding support. The purpose is to provide a multi-chip stacked package junction glue that surrounds a first wafer and a third layer formed on a first wafer and a third layer to avoid forming a hole (v o i d) between the first wafer when forming a colloid. The purpose is to provide a multi-chip stacked package junction filling glue to cover a plurality of electrical connections between a first chip and a device (such as a bonding wire), so as to avoid forming a colloidal connection device wire sweeping and creating a creative A multi-chip stacked package structure includes a substrate, a chip, a second chip, an elastic filler, and a gel. The substrate has an upper surface and a lower surface, and the first wafer is disposed on the substrate. The top surface of the soil is electrically connected to the substrate by a plurality of electrical connection devices. The second chip has an active surface and a back surface. The active surface of the second chip is larger than the active surface of the first chip. And a plurality of bonding pads are formed around the active surface of the second wafer, and the second wafer has the active surface facing upward
M254725M254725
方式設於該第_ 接,於該第一晶 該些電性連接& 充膠係設於該第 片之背面周邊, 充膠係環繞該間 該第二晶片之間 些電性連接裝置 連接裝置沖線(ψ 膠體係用以保護 基板之下表面植 【實施方式】 晶片上^並以複數個銲線與該基板電性連 片與該第二晶片之間設有一間隔墊層,使 置=會接觸該第二晶片之背面,該彈性填 一晶片與該基板之間,且覆蓋至該第二晶 用以打線時支撐該第二晶片,且該彈性填 隔墊層,以避免該封膠體在該第一晶片與 形成孔洞(V〇id),該彈性填充膠並包覆該 ,以避免形成一封膠體時,造成該些電性 ire sweeping)而發生短路或斷路,該封 該第一晶片與該第二晶片,較佳地,於該 接有複數個銲球。 參閱所附圖式,本創作將列舉以下之實施例說明。 依本創作之弟一具體實施例,如第1圖所示,一種多 晶片堆疊封裝結構1 〇 〇係用以封裝至少兩晶片,主要包含 有一基板110、一第一晶片120、一第二晶片13〇、一彈性 填充膠140及一封膠體150。其中該基板11〇係可視為一種 具有電路分佈之微型電路板,依實際需要可以是一單層板 或多層板(multi-layer board),該基板11〇具有一上表面 111及一下表面112 ’其中該上表面ill係用以承載該第一 晶片11 0 ’而該下表面11 2係用以植接複數個與外部電性連 接之銲球1 7 0,如鉛錫合金等,通常在該基板11 〇之上表面 111上具有對應並電性連接之該些銲球丨7〇至上述之複數個 連接墊(connect ion pad),以電性連接第一晶片j 2〇與第The mode is set on the first connection, the electrical connections on the first chip are filled on the periphery of the back of the first chip, and the rubber connection surrounds the electrical connection devices between the second chip. The device punch line (ψ glue system is used to protect the lower surface of the substrate. [Embodiment] A spacer layer is provided on the wafer and a plurality of bonding wires are electrically connected to the substrate and the second wafer. = Will contact the back of the second wafer, the elastic fill between the wafer and the substrate, and cover the second wafer to support the second wafer when wiring, and the elastic fill spacer layer to avoid the seal The colloid forms a hole (Void) in the first wafer, the elastic filling glue covers the covering, so as to avoid a short circuit or an open circuit caused by the electrical ire sweeping when a colloid is formed, the sealing the first A wafer and the second wafer are preferably connected with a plurality of solder balls. With reference to the attached drawings, the present invention will enumerate the following embodiment descriptions. According to a specific embodiment of the brother of this creation, as shown in FIG. 1, a multi-chip stacked packaging structure 100 is used to package at least two chips, mainly including a substrate 110, a first chip 120, and a second chip. 130. An elastic filler 140 and a colloid 150. The substrate 11 can be regarded as a micro circuit board with circuit distribution. It can be a single-layer board or a multi-layer board according to actual needs. The substrate 11 has an upper surface 111 and a lower surface 112 ′. The upper surface ill is used to carry the first chip 11 0 ′, and the lower surface 112 is used to implant a plurality of solder balls 1 70 which are electrically connected to the outside, such as a lead-tin alloy. The upper surface 111 of the substrate 11 has the solder balls corresponding to and electrically connected to the above-mentioned plurality of connection pads to electrically connect the first chip j 2〇 and the
M254725 四、創作說明(4) 二晶片1 3 0 。 該第一晶片120係具有一主動面121,該主動面121形 成有複數個銲墊122,該第一晶片1 20可以是動態隨機存取 記憶體(dynamic random access memory,DRAM)、靜態隨 機存取 §己憶體(static random access memory, SRAM)、 快閃記憶體(f lash memory)、微處理器(micro contro 1 1 er )或邏輯性之其他功能性晶片,該第一晶片i 20 係以黏膠或膠膜固接於基板11 〇之上表面丨丨1,該第一晶片 1 2 0與基板11 〇之内部電性連接係以複數個如銲線之電性連 接裝置123連接該第一晶片120之銲墊122與在基板110上表 面111之對應連接墊。 該第二晶片130具有一主動面131及一背面132,該主 動面131之週邊係形成有複數個銲墊133,該第二晶片13〇 係以複數個銲線134連接該第二晶片130之銲墊133與在基 板110上表面111之對應連接墊,該第二晶片13〇之主動面 1 3 1係大於該第一晶片1 2 0之主動面1 2 1,且該第二晶片1 3 0 係以主動面1 3 1朝上設於該第一晶片丨2 〇上,一間隔墊層 140設於該第一晶片120與該第二晶片13〇之間,使該第二 晶片130與該第一晶片120形成一間距,該間隔墊塊140係 為一虛晶片或金屬塊,以提供足夠剛性,避免設置該第二 晶片1 3 0時,該第二晶片1 3 0之背面1 3 2碰觸該些電性連接 裝置1 2 3,該彈性填充膠1 5 0係設於該第二晶片丨3 〇與該基 板11 0之間,且覆蓋至該第二晶片1 3 〇之背面1 3 2周邊,且 該彈性填充膠1 5 0係環繞該間隔墊層1 4 〇並包覆該些電性連M254725 Fourth, creation instructions (4) Two wafers 1 3 0. The first chip 120 has an active surface 121 formed with a plurality of bonding pads 122. The first chip 120 may be a dynamic random access memory (DRAM), a static random access memory Take § self-memory (static random access memory (SRAM), flash memory, flash memory, microprocessor (micro contro 1 1 er) or other functional chip of logic, the first chip i 20 series Adhesive or adhesive film is fixed on the upper surface of the substrate 11 〇, the internal electrical connection between the first chip 120 and the substrate 11 is connected with a plurality of electrical connection devices 123 such as bonding wires. The bonding pads 122 of the first wafer 120 and the corresponding connection pads on the upper surface 111 of the substrate 110. The second chip 130 has an active surface 131 and a back surface 132. A plurality of bonding pads 133 are formed around the active surface 131. The second chip 130 is connected to the second chip 130 by a plurality of bonding wires 134. The bonding pad 133 and the corresponding connection pad on the upper surface 111 of the substrate 110, the active surface 1 31 of the second wafer 13 is larger than the active surface 1 2 1 of the first wafer 1 2 0, and the second wafer 1 3 0 is arranged on the first wafer with the active surface 1 31 facing upward, and a spacer layer 140 is provided between the first wafer 120 and the second wafer 130, so that the second wafer 130 and The first wafer 120 forms a gap, and the spacer block 140 is a dummy wafer or a metal block to provide sufficient rigidity to avoid the back surface of the second wafer 130 when the second wafer 130 is disposed. 2 touches the electrical connection devices 1 2 3, the elastic filling glue 1 50 is disposed between the second chip 3 0 and the substrate 1 10 and covers the back of the second chip 1 3 0 1 3 2 periphery, and the elastic filling glue 1 50 surrounds the spacer layer 14 and covers the electrical contacts.
第10頁 M254725 四、創作說明(5) --- 接裝置123 ’該彈性填充膠150之材質係可為環氧樹脂 (Epoxy)或矽樹脂(Silicone),於打線接合時,該彈性填 充膠150係已固化,用以支撐該第二晶片13〇,避免該第二 晶片1 3 0產生裂縫或斷裂,在形成一封膠體丨6 〇時,因模流 被該些電性連接裝置丨2 3阻擋不易完全包覆該間隔墊層 I 4 0 ’而於該第一晶片j 2 〇與該第二晶片1 3 〇之間形成孔洞 (void),由於該彈性填充膠15〇係環繞該間隔墊層14〇並包 覆4些電性連接裝置1 2 3,可避免形成孔洞(v 〇 i d ),並避 免該些電性連接裝置1 2 3因模流而造成沖線(w丨r e sweeping)發生短路或斷路,該封膠體16〇係設於該基板 II 0之上表面111,用以保護該第一晶片1 2 〇與該第二晶片 130。 本創作例舉第二具體實施例,如第2圖所示,一種多 晶片堆疊封裝結構20 0主要包含有一基板21〇、一第一晶片 22 0、一第二晶片230、一彈性填充膠240及一封膠體250。 其中該基板2 10具有一上表面211及下表面212,該第一晶 片220係具有一主動面221,並以複數個凸塊221覆晶接合 至該基板210之上表面211,該第二晶片230係具有一主動 面231及一背面232 ’該主動面231上形成有複數個銲塾 233 ’該第二晶片230係以主動面231朝上方式設於該第一 曰曰片220上’该弟一晶片230之主動面231係大於該第一晶 片220之主動面221,且該第二晶片230係以複數個銲線233 連接該第二晶片230之銲墊2 33與基板2 10上表面211,該彈 性填充膠240係設於該第二晶片230與該基板21〇之間,且Page 10 M254725 IV. Creation instructions (5) --- Connecting device 123 'The material of the elastic filler 150 can be epoxy or silicone. When the wire is bonded, the elastic filler The 150 series has been cured to support the second wafer 13 and avoid cracks or breaks in the second wafer 130. When a colloid is formed, it is affected by the electrical connection devices due to mold flow. 2 3 It is difficult to completely cover the spacer layer I 4 0 ′ and form a void between the first wafer j 2 〇 and the second wafer 1 3 〇, since the elastic filling glue 15 ° surrounds the space The cushion layer 14o is covered with 4 electrical connection devices 1 2 3 to prevent the formation of holes (v oid) and to prevent the electrical connection devices 1 2 3 from being caused by die flow. ) A short circuit or an open circuit occurs. The sealing compound 160 is disposed on the upper surface 111 of the substrate II 0 to protect the first wafer 120 and the second wafer 130. The present invention exemplifies a second specific embodiment. As shown in FIG. 2, a multi-chip stacked package structure 20 0 mainly includes a substrate 21 0, a first wafer 220, a second wafer 230, and an elastic filling glue 240. And a piece of colloid 250. The substrate 2 10 has an upper surface 211 and a lower surface 212, the first wafer 220 has an active surface 221, and is bonded to the upper surface 211 of the substrate 210 with a plurality of bumps 221. The 230 series has an active surface 231 and a back surface 232 'The active surface 231 is formed with a plurality of welding pads 233' The second wafer 230 is disposed on the first wafer 220 with the active surface 231 facing upwards' The active surface 231 of the first chip 230 is larger than the active surface 221 of the first chip 220, and the second chip 230 is connected to the upper surface of the pad 2 33 and the substrate 2 10 of the second chip 230 with a plurality of bonding wires 233. 211. The elastic filler 240 is disposed between the second wafer 230 and the substrate 21.
第11頁 M254725 四、創作說明(6) 覆蓋至該第二晶片230之背面232周邊,於打線接合時用以 支撐該第二晶片130,避免該第二晶片230在打線過程產生 裂縫或斷裂,該彈性填充膠240之材質係可為環氧樹脂 (Epoxy)或矽樹脂(Silicone),該封膠體250係設於該基板 210之上表面211,用以保護該第一晶片220與該第二晶片 23 0,較佳地,形成該封膠體250後,於該基板2 10之下表 面212植接有複數個銲球260。Page 11 M254725 IV. Creation instructions (6) Cover the periphery of the back surface 232 of the second wafer 230 to support the second wafer 130 during wire bonding to avoid cracks or breaks in the second wafer 230 during wire bonding. The material of the elastic filler 240 may be epoxy or silicone. The sealant 250 is disposed on the upper surface 211 of the substrate 210 to protect the first chip 220 and the second chip. The wafer 23 0 is preferably formed with a plurality of solder balls 260 on the lower surface 212 of the substrate 2 10 after the sealing compound 250 is formed.
本創作之保護範圍當視後附之申請專利範圍所界定者 為準,任何熟知此項技藝者,在不脫離本創作之精神和範 圍内所作之任何變化與修改,均屬於本創作之保護範圍。The scope of protection of this creation shall be determined by the scope of the attached patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of this creation shall fall within the scope of protection of this creation. .
第12頁 M254725Page 12 M254725
圖式簡單說明 1圖·依據本創作之第—且辦每#九丨 体々 具體貝施例,一種多晶片堆疊 封裝結構;及 尹且 【圖式簡單說明】 第 第2 圖:依據本創作夕坌-曰祕一 田诹尽創作之第一具體實施例,另一種 璺封裝結構。 曰月堆 元件 100 110 120 123 130 133 140 150 160 170 200 210 220 230 233 240 250 符號簡單說明: 111 上表面 112 下表面 121 主動面 122 銲墊 131 主動面 132 背面 134 銲線 霞結構 211 上表面 212 下表面 221 主動面 222 凸塊 231 主動面 232 背面 234 銲線 多晶片堆疊封裝結構 基板 弟一晶片 電性連接裝置 第二晶片 銲墊 間隔墊層 彈性填充膠 封膠體 銲球 晶片 晶片 多晶片堆疊封 基板 第 第 銲墊 彈性填充膠 封膠體Schematic illustration 1 diagram · According to the first of this creation-and to do each # 九 丨 body 々 specific examples, a multi-chip stacked package structure; and Yin and [Schematic description] Figure 2: Based on this creation Xi Xi-The first specific embodiment created by Seiichi Yada, another kind of encapsulation structure. Moon stack element 100 110 120 123 130 133 140 150 160 170 200 210 220 230 233 240 250 Brief description of symbols: 111 top surface 112 bottom surface 121 active surface 122 pads 131 active surface 132 back surface 134 welding wire structure 211 upper surface 212 Lower surface 221 Active surface 222 Bump 231 Active surface 232 Back surface 234 Welding wire multi-chip stacking package structure substrate Di-chip electrical connection device Second wafer pad spacers Elastic filling gel sealant solder ball wafer wafer multi-chip stacking The first pad of the sealing substrate is elastically filled with the sealing compound.
第13頁 M254725Page 13 M254725
第14頁Page 14
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101964337A (en) * | 2010-08-26 | 2011-02-02 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure and manufacturing method thereof |
CN112397498A (en) * | 2019-08-01 | 2021-02-23 | 联发科技股份有限公司 | Semiconductor package |
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Publication number | Priority date | Publication date | Assignee | Title |
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CN101964337A (en) * | 2010-08-26 | 2011-02-02 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure and manufacturing method thereof |
CN101964337B (en) * | 2010-08-26 | 2012-07-25 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure and manufacturing method thereof |
CN112397498A (en) * | 2019-08-01 | 2021-02-23 | 联发科技股份有限公司 | Semiconductor package |
TWI729895B (en) * | 2019-08-01 | 2021-06-01 | 聯發科技股份有限公司 | Semiconductor package |
US11355450B2 (en) | 2019-08-01 | 2022-06-07 | Mediatek Inc. | Semiconductor package with EMI shielding structure |
US11869849B2 (en) | 2019-08-01 | 2024-01-09 | Mediatek Inc. | Semiconductor package with EMI shielding structure |
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