TW563234B - Multi-chip semiconductor package and fabrication method thereof - Google Patents

Abstract

A multi-chip semiconductor package and a fabrication method thereof are provided. A substrate having an upper surface and a lower surface is prepared. At least a first chip is mounted on the upper surface of the substrate. A non-conductive material is applied over predetermined area on the first chip and the upper surface of the substrate. At least a second chip is mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material. With the second chip being completely supported on the non-conductive material without causing a conventional chip-crack problem, structural intactness and reliability can be effectively assured for fabricated package products.

Description

563234 V. Description of the invention d) [Field of invention], Zeng Qu 2 is about a multi-chip semiconductor package, especially a kind of half-mr cow, which is connected to a chip carrier with a large number of chips, and Rongfeng v-body package manufacturing method. [Background Description] = Effectively improve electrical functions and operability & It is preferred to place most wafers in a previous package structure to form a multi-chip semiconductor package. As shown in FIG. 3, the conventional multi-chip semiconductor package 1 has a structure in which a substrate is used as a wafer-bearing component, so that the first chip 丨 0 is placed on the substrate ii and most of the first bonding wires 12 are electrically The second chip 3 connected to the substrate 1 is stacked on the first chip 10 and most of the second bonding wires 14 are electrically connected to the substrate 11. Then, the first and second wafers 10 and 13 and the first and second bonding wires 12 and 14 are covered with the encapsulating gel 15 formed on the substrate 11. Next, a plurality of solder balls 16 are implanted on a portion of the substrate 11 opposite to the packaging gel 15 so that the solder balls 6 serve as input / output terminals for electrically connecting the first and second chips. 10, 13 to external devices such as a printed circuit board (Printed Circuit Board, not shown). However, the disadvantage of this multi-chip semiconductor package 1 is that the size of the chip is limited, that is, the size of the second chip 13 needs to be smaller than the size of the first chip 10, so that the second chip 13 does not interfere with the first chip. Layout of the first bonding wire 12 for wafer 10 bonding. In view of this, as shown in FIGS. 4A and 4B, another multi-wafer semiconductor package Γ can solve the above-mentioned problem of wafer size limitation. It stacks the second wafer 13 on the first wafer 10 in a staggered manner. The second wafer 13 is partially brought into contact with the first wafer 10. This structure must be set flexibly

16811.ptd Page 7 563234 V. Description of the invention (2) How does the second wafer 13 with respect to the size of the first wafer 10 not interfere with the first bonding wire 12 connected to the first wafer 10? However, due to partial or incomplete contact between the first and second wafers 10 and 13, at least a part of the second wafer 3 cannot be supported by the first wafer 10 and becomes a suspension portion (Suspension Portion) 130 The pads 1 3 1 of the second wafer 13 to be soldered to the second bonding wire 14 are located at the suspended portion 13. When performing a wire-bonding operation to form the second bonding wire 14, a bonding machine (not shown) will apply a strong force to the bonding pad i 3 丨, which may cause the second chip i 3 The suspended portion 130 supported by a wafer 10 is cracked. In response to the above-mentioned wafer cracking problem, FIG. 5 shows another multi-chip semiconductor package Γ ′, which is exposed in the floating portion 1 30 and the substrate 丨 and a plurality of support members 17 are formed, so that the support members 7 are roughly arranged At the position corresponding to the pad 1 3 1 (the zinc is connected with the second bonding wire 丄 4) of the second wafer 丨 3, the mechanical strength and support of the second wafer 1 and the suspended portion i 30 can be improved. Therefore, when the second red f 1 4 is formed, the second wafer i 3 can better resist the bonding wire strength and avoid cracking of the easily suspended portion 130. Γ ,,;, and the above-mentioned multi-wafer semiconductor package f 1 using the support member 17 causes many problems. Douyi for the helmet, 円 ^, thousand and other baskets nailed thousand

Ef f Uά 8. 、 ;; / 5 (01 d) or the popcorn effect, due to the setting of the support member 17, a gap G is formed between the first and second parts, and the molding is performed ΓΜη1 H · said film 1〇 /, When the support member 17 is used, Qi Ji θ μ, and M dng are used to convert the resin 铷 r into the encapsulating gel i 5 that encapsulates the wafer, it is still u. The moon in the shape of the object turns into the air hole left in Fengshang colloid 15 in the "don't move" to make the semiconductor = in the gap G; the gas explosion phenomenon in the residue, which damages f ^ f 4 Part 1 becomes the reliability of the packaged product in the subsequent process M ^ I.

16811.ptd

563234 5. Description of the invention (3) [Summary of the invention] An object of the present invention is to provide a multi-chip semiconductor package and a method for manufacturing the same, so as to prevent the wafers contained in the semiconductor package from being cracked during the manufacturing process. Another object of the present invention is to provide a multi-chip semiconductor package and a manufacturing method thereof, so that a gap is not formed between a non-conductive material and a wafer on which the non-conductive material is laid, so that no air hole or gas explosion phenomenon is caused. . Still another object of the present invention is to provide a multi-chip semiconductor package and a method for manufacturing the same, which can improve the mechanical strength of the wafer and reduce the thermal stress applied to the wafer, and can make the wafer thinner to reduce the thickness of the overall package structure. Another object of the present invention is to provide a multi-chip semiconductor package and a method for manufacturing the same, so that a non-conductive material is laid on the wafer to prevent external moisture from invading the wafer, thereby ensuring the reliability of the semiconductor package. In order to achieve the disclosure and other objectives, the present invention discloses a multi-chip semiconductor package, including: a substrate having an upper surface and a relatively lower surface; at least one first wafer connected to the upper surface of the substrate; A non-conductive material is laid on the first wafer and a predetermined portion on the upper surface of the substrate; at least one second wafer is connected to the non-conductive material, and the second wafer is formed with at least one which will not interfere with the The suspended portion of the first wafer, wherein the area of the non-conductive material corresponds at least to the area of the second wafer, so that the suspended portion of the second wafer is supported on the non-conductive material; and an encapsulating gel, It is formed on the upper surface of the substrate to cover the first and second wafers.

16811.ptd Page 9 563234 V. Description of the invention (4) The method for manufacturing the above-mentioned multi-chip semiconductor package includes the following steps: preparing a substrate having an upper surface and a relatively lower surface; and connecting at least one first The wafer is on the upper surface of the substrate; a non-conductive material is laid on the first wafer and a predetermined portion on the upper surface of the substrate; at least one second wafer is placed on the non-conductive material, and the second wafer is formed There is at least one suspended portion that does not interfere with the first wafer, wherein the area of the non-conductive material corresponds to at least the area of the second wafer so that the suspended portion of the second wafer is supported by the non-conductive material And forming an encapsulating gel on the upper surface of the substrate so that the encapsulating gel covers the first and second wafers. The above-mentioned semiconductor package has many advantages. First, because the second wafer is completely supported on a non-conductive material, when the wire bonding operation is performed to form the second wire, the suspended portion of the second wafer must be prevented from being damaged when the wire bonding force is applied by the wire bonding machine. Can ensure the integrity of the structure of the second chip. Furthermore, the non-conductive material is directly deposited on the first wafer without forming a gap between the non-conductive material and the first wafer, so that no cavitation or gas explosion will be caused when forming the encapsulating gel. In addition, one surface of the second chip is adhered to a non-conductive material (such as an elastic adhesive), and one of the opposite surfaces of the second chip is covered with a sealing gel. The mechanical strength of the second chip and the non-conductive material (but flexible) can provide a buffer effect to help reduce the thermal stress applied by the encapsulant to the second chip in the subsequent high temperature environment, and further thin the second chip to reduce The thickness of the overall package structure. Furthermore, since the first wafer is not partially or completely covered with a conductive material, it is necessary to prevent outside water from invading the first wafer, and

16811.ptd Page 10 563234 V. Description of the invention (5) It can ensure the reliability of semiconductor packages. [Detailed description of the invention] Hereinafter, embodiments of the multi-chip semiconductor package and its manufacturing method disclosed in the present invention will be described in detail with the attached 1A to 1F and 2A to 2D drawings. Second step: Embodiments FIGS. 1A to 1F are process steps of the semiconductor package 2 according to the first embodiment of the present invention. As shown in FIG. 1A, first, a substrate sheet (Substrate P 1 a t e) 2 0 is prepared, which is formed by integrating a plurality of substrates 21, and adjacent substrates 21 are delimited by dotted lines in the figure. Each substrate 21 has an upper surface 2 1 0 and a relatively lower surface 21. The substrate sheet 20 is mainly made of a conventional resin material such as an epoxy resin (Epoxy Resin), a polyimide (Polyimide), a BT (Bismaleimide Triazine) resin, or a FR-4 resin. As shown in FIG. 1B, at least one first wafer 2 2 is placed on the upper surface 2 1 0 of each substrate 2 1. The first wafer 2 2 has an active surface 2 2 0 and an opposite non-active surface 2 2 2 which are provided with a plurality of electronic components and circuits (not shown) and a pad 2 2 1. The non-active surface 2 2 2 is adhered to the upper surface 210 of the corresponding substrate 21. Then, a wire-bonding operation is performed to form a plurality of first bonding wires 23 such as gold wires, and the first bonding wires 23 are soldered to the bonding pads 2 on the active surface 2 2 0 of the first wafer 2 2. 21 and the corresponding upper surface 2 1 of the substrate 21, so that the first chip 2 2 is electrically connected to the substrate 2 by the first bonding wire 2 3, as shown in FIG. 1C, laying a non-conductive material 2 4 If an elastic adhesive is applied to a predetermined position on each of the first wafer 22 and the substrate 21, and corresponding to

16811.ptd Page 11 563234 V. Description of Invention (6) The first wafer 22 is arranged in a staggered manner. The non-conductive material 24 has a wafer contact portion 2 4 0 formed on the active surface 2 2 0 of the corresponding first wafer 2 2 and at least one formed on the upper surface 2 1 0 of the corresponding substrate 21. The substrate contact portion 2 4 1; Furthermore, the area of the non-conductive material 2 4 corresponds to at least one area of a chip (not shown). The second chip is subsequently stacked on the first chip 2 in a staggered manner. 2 on.

The non-conductive material 24 can be laid by stencil printing (Stenci 1-Printing), which uses a conventional template (not shown) to selectively print the non-conductive material (with elastic adhesive) 24 on the first The wafer 22 and the substrate 21 are at predetermined positions. Since stencil printing technology is known, it will not be described here. Furthermore, the conventional DiSpensing technology can also be used for laying non-conductive materials 24. It should be noted that other methods or processes applicable to non-conductive materials 24 are also covered by the scope of the present invention.

As shown in FIG. 1D, at least one second wafer 25 is placed on the non-conductive material 24 'so as to be positioned above each of the first wafers 22. The second wafer '25 is provided with a plurality of electronic components and circuits (not shown) and a pad 251, an active surface 2 50 and an opposite non-active surface 2 5 2, so that the second wafer 25 is not The active surface 2 5 2 is adhered to the non-conductive material 24 and is completely supported by the non-conductive material 24 having an area corresponding to the second wafer 25. / The second wafer 25 aligned with the non-conductive material 24 is also set to the corresponding first wafer '22 in a wrong manner 'so that the second wafer 25 does not interfere with at least one suspended portion of the second wafer 253 It must be stably supported on the substrate contact portion 241 having no conductive material. Then ’performs a bonding wire operation to form a majority of the second bonding wires 26 such as gold

16811.ptd Page 12 563234 V. Description of the invention (7) The second bonding wire 2 6 is soldered to the bonding surface 251 on the active surface 2 5 0 of the second wafer 25 and the corresponding upper surface 210 of the substrate 21 The second chip 25 is electrically connected to the substrate 2 through the second bonding wire 26. As shown in FIG. 1E, a molding operation is performed to form a packaging gel 2 on the upper surface 2 1 0 of the substrate 2 1 7, so that the encapsulating gel 2 7 covers the first and second wafers 2 2, 2 5, the first bonding wire 2 3 (as shown in FIG. 1 D) and the second bonding wire 2 6 to protect these Components are protected from external moisture and contaminants. Fengshang Colloid 27 is made of a conventional resin compound such as epoxy resin. Then, a ball implantation operation (B a 1 1-I m p 1 a n t a t i ο η) is performed to plant a plurality of solder balls 2 8 on the lower surface 2 1 1 of the substrate 2 1. The solder ball 28 can be used as an input / output (I / O) terminal to electrically connect the first and second chips 2 2, 25 to an external device such as a printed circuit board (not shown). . Finally, as shown in FIG. IF, a Singulation operation is performed to cut the packaging colloid 27 and the substrate sheet 20 along the dotted line shown in FIG. 1E, and separate each substrate 21 to form a majority of semiconductor packages 2 . (2) The manufacturing steps of the semiconductor package 2 according to the second embodiment of the 2nd to 2D inventions of the 21st invention. As shown in the figure, the structure of the semiconductor package 2 is similar to that of the semiconductor package 2 of the first embodiment described above, and therefore the same components are indicated by the same reference numerals as those of the first embodiment. As shown in FIG. 2A, first, a substrate 21 is prepared with an upper surface 2 1 0 and a relatively lower surface 2 and at least one first wafer 2 2 is placed on the upper surface 2 1 0 of the substrate 21; A wafer 2 2 has an active surface 2 2 0 and a phase

16811.pid Page 13 563234 V. Description of the invention (8) The non-active surface 2 2 2 of the first wafer 22 is adhered to the upper surface 2 1 0 of the substrate 21. Form most of the first bonding wires 23, such as gold wires, to electrically connect the active surface 22o of the first wafer 22 to the upper surface 210 of the substrate 21, as shown in Figure 2B. Lay it out by stencil printing or dispensing. Conductive, material 24 such as-with an elastic adhesive to the first wafer 22 and the substrate 21, a fixed position 'and no conductive material _ 24 is arranged substantially parallel to the corresponding first wafer 22 f. The non-conductive material 24 has a wafer contact portion 2 4 0 formed on the active surface 2 2 0 of the first crystal 22 and at least one substrate contact portion 24 formed on the upper surface 2 1 0 of the substrate 21 1 Furthermore, the area of the non-conductive material 24 corresponds to at least the area of a second wafer (not shown), and the second wafer is subsequently stacked on the first wafer 22 in a parallel manner. The contact portion 2 4 0 of the non-electrical | ± material 2 4 may be completely or partially covered, and the active surface 2 2 0 of the first wafer 2 2 is to allow the non-conductive material 24 to carry Area of the second wafer. In addition, the conductive material 24 is at least partially covered with the first wafer 22 and the first bonding wire 23. As shown in the figure of material 2C, at least one second wafer 25 is placed on the non-conductive H ′ so that it is located above the first wafer 22. The second wafer 25 has a non-action meaning 250 and a relative non-action surface 252, so that the second wafer 25 has 52 and is adhered to the non-conductive material 24 and is completely different. The area is supported by a non-conductive material 24. The second wafer 25, which is aligned with the 2? Exposure 1 material 24, is also arranged in a flat manner with the corresponding first wafer, so that the second wafer 25 will not interfere with the first wafer.

16811.ptd Page 14 563234 V. Description of the Invention (9) ~ One The at least one suspended portion 2 5 3 is firmly supported on the substrate contact portion 241 of the non-conductive material 24. Then, a plurality of second bonding wires 26, such as gold wires, are formed to electrically connect the active surface 250 of the second wafer 25 to the acoustic surface 210 above the substrate 21. As shown in FIG. 2D, a strong colloid 27 is formed on the upper surface 2 of the substrate 2 to cover the first and second wafers 22, 25 and the first and second fresh lines 2 and 3. 2 6 'To protect these components from external moisture and pollutants. Then, most solder balls 28 are planted on the lower surface 211 of the substrate 21, and the solder balls must be electrically connected as output / input terminals. The first and second wafers 22 are held to an external device such as a printed circuit board (not shown); thus, the process of 2 is completed. Clothes Aa Note that if necessary, non-conductive materials 24 to 25 must be laid to carry more wafers thereon. The aforementioned semiconductor package 2, 2 'has many advantages. First, since the second wafer M is completely supported on the non-conductive material, the bonding wire 1 is used to form the second bonding wire 26, and the first: the suspended portion of the wafer 25: the non-conductive material 24 is directly laid. A Ba sheet 22 does not form a gap with non-conductive materials, so it forms a sealing film. 9 "t # κ: It will not cause air holes or gas explosions. The non-active surface 252 is adhered to a non-conductive material (such as an elastic adhesive) 24, and the second guide is a

2 0 0 is covered with encapsulating colloid. This kind of double-sided coating makes Λ the second and the mechanical strength of the sheet 25 and does not have a conductive chip:

16811.ptd Page 15 563234 V. Description of the invention (ίο) Provide buffer effect to help reduce the thermal stress of the encapsulant 2 7 applied to the second wafer 25 under the high temperature environment, and further thin the second wafer 2 5 It is beneficial to reduce the thickness of the overall packaging structure. Furthermore, as shown in FIG. 2B, the non-conductive material 2 4 at least partially covers the first bonding wire 23 to be soldered to the first wafer 22, thereby helping to locate the first bonding wire 23 to face The mold flow impact during the formation of the encapsulant 27 is protected from the problem of wire offset. In addition, as shown in FIG. 2B, since the non-conductive material 24 partially or completely covers the first wafer 22, it is necessary to prevent outside water from invading the first wafer 22, and to ensure the semiconductor package 2. 2 'Reliability. However, the above are only used to illustrate specific embodiments of the present invention, and are not intended to limit the implementable scope of the present invention. For those skilled in the art, it can be completed without departing from the spirit and principles indicated by the present invention. All equivalent changes or modifications should still be covered by the scope of patents mentioned later.

16811.pld Page 16 563234 Brief description of the drawings [Simplified description of the drawings] Figures 1 A to 1 F are schematic diagrams of the manufacturing process of the semiconductor package of the first embodiment of the present invention; Figures 2A to 2D are drawings of the present invention Schematic diagram of the manufacturing process of the semiconductor package of the second embodiment; FIG. 3 is a cross-sectional view of a conventional semiconductor package; FIG. 4A is a cross-sectional view of another conventional semiconductor package; and FIG. 4B is a view showing the semiconductor of FIG. 4A A top view of the chip layout of the package, and FIG. 5 are cross-sectional views of another conventional semiconductor package. [Explanation of component symbols: 1 1 semiconductor package 10 first wafer 11 substrate 12 first fresh line 13 second wafer 130 floating portion 131 pad 14 second bonding wire 15 encapsulation gel 16 solder ball 17 support 2 to 2, semiconductor Package 20 Substrate piece 21 Substrate 210 Upper surface 211 Lower surface 22 First wafer 220 Active surface 221 Solder pad 222 Non-active surface 23 First bonding wire 24 Non-conductive material 240 Wafer contact portion 241 Substrate contact portion 25 First wafer 250 Function surface

16811.ptd p. 17 563234 Schematic illustrations 251 Solder pads 252 Non-active surfaces 253 Suspended parts 26 Second bonding wires 27 Encapsulants 28 Glow balls G Clearance 16811.ptd p. 18

Claims (1)

563234 6. Scope of patent application 1. A multi-chip semiconductor package, comprising: a substrate having an upper surface and a relatively lower surface; at least one first wafer connected to the upper surface of the substrate; A conductive material is laid on the first wafer and a predetermined portion on the upper surface of the substrate; at least one second wafer is connected to the non-conductive material, and the second wafer is formed with at least one that does not interfere with the first The suspended portion of the wafer, wherein the area of the non-conductive material corresponds at least to the area of the second wafer, so that the suspended portion of the second wafer is supported on the non-conductive material; and an encapsulating gel is formed on The upper surface of the substrate is used to cover the first and second wafers. 2. For the semiconductor package of item 1 of the patent application scope, it includes: most of the solder balls are implanted on the lower surface of the substrate. 3. For the semiconductor package of item 1 of the patent application scope, wherein the non-conductive material is an elastic adhesive. 4. The semiconductor package of claim 1, wherein the non-conductive material is sandwiched between the first and second wafers. 5. For the semiconductor package of claim 1, the suspended portion of the second wafer is supported on a portion where the non-conductive material is laid on the substrate. 6. The semiconductor package of claim 1 in which the second chip is arranged in a staggered manner with the first chip. 7. The semiconductor package of claim 1 in the patent application scope, wherein the second 16811.ptd Page 19 563234 6. Scope of patent application The wafer is arranged in parallel with the first wafer. Wherein, the second wherein each of the first substrates. Include the following steps: 8. If the area of the semiconductor package of the patent application item 1 is greater than the area of the first wafer. 9. For example, the first semiconductor package and the second wafer of the patent application range are electrically connected to 10 by a plurality of bonding wires. A method of manufacturing a multi-chip semiconductor package is to prepare a substrate, the substrate having a At least one first wafer is connected to the upper surface and a relatively lower surface, and a non-conductive material is laid on the substrate to a predetermined position on the first surface; at least one second wafer is connected to form at least one Among them, the area without the second wafer, the non-conductive material is called sheet colloid 1 1 · Russian majority 1 2 · Russian material 1 3 · Russian material scope, the substrate, patent scope, The elastic glue is required to be sandwiched between the first and the third conductive materials so as to be placed on the elastic glue; the adhesive of the tenth item of the table below the tenth of the second crystal. An encapsulant is formed to cover the first and patented fresh balls. The area where the non-conductive material will interfere with the first material is the suspension of the second wafer and the upper surface sheet of the substrate. Manufacturing method, including surface. Manufacturing method, wherein manufacturing method, wherein, between two wafers. On the surface; on the sheet and on the substrate, the floating portion of the wafer corresponds to at least the floating portion on the support, so that the package is one step: grafting, non-conductive, non-conductive 16811.ptd Page 20 563234 VI. Application for patent scope 1 4. For the manufacturing method of patent application scope No. 10, wherein the suspended portion of the second wafer is supported by the portion where the non-conductive material is laid on the substrate . 15. The manufacturing method according to item 10 of the scope of patent application, wherein the second wafer is arranged in a staggered manner with the first wafer. 16. The manufacturing method according to item 10 of the scope of patent application, wherein the second wafer is arranged in parallel with the first wafer. 1 7. The manufacturing method according to item 10 of the patent application scope, wherein the area of the second wafer is larger than the area of the first wafer. 18. The manufacturing method of item 10 in the scope of patent application, wherein the non-conductive material is laid by printing. 19. The manufacturing method according to item 10 of the scope of patent application, wherein the non-conductive material is laid by dispensing. 20. The manufacturing method according to item 10 of the scope of patent application, wherein each of the first and second wafers is electrically connected to the substrate by a plurality of bonding wires. 1681] .pid p. 21