TW200908280A - Multi-chip stacked device with a composite spacer layer - Google Patents

Multi-chip stacked device with a composite spacer layer Download PDF

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Publication number
TW200908280A
TW200908280A TW096130065A TW96130065A TW200908280A TW 200908280 A TW200908280 A TW 200908280A TW 096130065 A TW096130065 A TW 096130065A TW 96130065 A TW96130065 A TW 96130065A TW 200908280 A TW200908280 A TW 200908280A
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TW
Taiwan
Prior art keywords
wafer
spacer layer
spacer
layer
chip
Prior art date
Application number
TW096130065A
Other languages
Chinese (zh)
Inventor
Hung-Hsin Hsu
Chih-Wei Wu
Chi-Chung Yu
Original Assignee
Powertech Technology Inc
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Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW096130065A priority Critical patent/TW200908280A/en
Publication of TW200908280A publication Critical patent/TW200908280A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
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    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

Disclosed is a multi-chip stacked device with a composite spacer layer, primarily comprising a chip carrier, a lower chip, at least an upper chip stacked above the lower chip, a plurality of bonding wires and a first spacer adhesive and a second spacer adhesive between the chips. The lower chip is disposed on the chip carrier and has a plurality of bonding pads at peripheries of its active surface, which are connected to the chip carrier by the bonding wires. The first spacer adhesive is disposed at peripheries of the active surface of the first chip to encapsulate one ends of the bonding wires. The second spacer adhesive is formed on the center of the back surface of the upper chip. When chip stacking, the thickness of the first spacer adhesive depends on the second spacer adhesive, the first and the second spacer adhesives complement each other in patterns to be a single layer structure. Accordingly, chip stacking height can be reduced and short problem of the bonding wires caused by contact of the second chip can be prevented.

Description

200908280 九、發明說明： 【發明所屬之技術領域】 本發明係有關於微間隙之多晶片堆疊構造，特別係 有關於一種複合式間隔之多晶片堆疊構造。 【先前技術】 隨著微小化以及高運作速度需求的增加，多個晶片 會整合在一封裝構造内，以達到兩倍以上之容量或更多 功能之需求，例如在以往的多晶片堆疊構造中，其係將 多個晶片堆疊並封膠在一封裝材料内’並在晶片與晶片 之間介設一間隔物（spacer)，如虛晶片、金屬片或黏性 膠片，以避免上方堆疊之晶片壓觸至下方已打線連接之 銲線，故整體的多晶片堆疊高度無法降低。為了降低堆 疊高度與提高黏晶強度，已知可以利用液態塗佈之覆線 膠體替代間隔物，以縮小晶片堆疊間隔。 請參閱第1圖所示，一種習知之多晶片堆疊構造 100，主要包含一晶片載體110、一第一晶片120、複數 個第一銲線1 3卜一第二晶片1 4 0以及一間隔膠層1 5 0。 該晶片載體1 1 0係具有複數個連接指1 1 1。該第一晶片 1 2 0之一第一背面1 2 2係黏貼於該晶片載體1 1 0。該第 一晶片1 2 0係具有複數個第一銲墊1 2 3，其係形成於該 第一晶片1 20之一第一主動面1 2 1之周邊。利用打線形 成之該些第一銲線131連接該些第一銲墊123至該些連 接指1 1 1。該第二晶片1 40係設於該第一晶片1 20上。 該間隔膠層1 5 0係形成於該第一晶片1 2 0與該第二晶片 6 200908280 1 4 0之間，其係為液態塗佈之覆線膠體，以黏著該第一 晶片120與該第二晶片140,並可覆蓋該些第一銲線131 之一端’故能縮小晶片堆疊間隔。該弟二晶片1 4 0係具 有一第二主動面141、一第二背面142以及複數個形成 於該第二主動面141之第二銲墊143。可藉由複數個第 二銲線1 3 2連接該些第二銲墊1 43至該些連接指1 1 1。 由於該間隔膠層1 5 0整個填滿該第一晶片1 2 0與該 第二晶片1 40之間隙，並在固化後可以提供該第二晶片 1 40之良好打線支撙。通常另以一封膠體1 60密封該第 一晶片120、該第二晶片140、該些第一銲線13 1與該 些第二銲線1 3 2。 雖然，藉由單層結構之該間隔膠層1 5 0可在預定封 裝厚度内堆疊更多數量之晶片，但在設置該第二晶片 140之黏晶製程中，該間隔膠層1 5 0尚未固化，無法準 確控制黏晶間隔。故該間隔膠層1 5 0之最終固化厚度會 受到黏晶壓力與溫度影響，而不容易控制在微高於該些 第一銲線1 3 1之打線弧高的間隙。故該第二晶片1 4 0之 該第二背面1 42極容易壓觸至該些第一銲線1 3 1，如第 1圖所示該些第一銲線1 3 1產生與第二晶片1 4 0接觸之 碰觸點 1 3 1 A ’造成晶片堆疊時壓線而產生鲜線短路之 情事。 我國發明專利證號第1243 453號「在晶粒表面形成 結合黏性之晶圓處理方法」，揭示一種具兩階段特性之 膠體，在預烤後可形成為一 B階段（B-stage)膠膜，且在 7 200908280 室溫下不具流動性，故上方晶片較不易壓觸下方銲線。 由於該兩階段之膠體係設於上方晶片之中央，使得上方 晶片之周邊區域未能得到該兩階段之勝體之充份支 撐，因此，容易在打線製程時造成上方晶片之斷折而產 生裂痕，導致晶片失效之問題。 【發明内容】 本發明之主要目的係在於提供一種複合式間隔之多 晶片堆疊構造’不需要在晶片堆豐之間設置間隔物，又 ( 可維持一更固定且較小之間隙，並可避免上方晶片壓觸 銲線，有效且高良率地降低多晶片堆疊構造之整體厚 度。 本發明之次一目的係在於提供一種複合式間隔之多 晶片堆疊構造，提高對上方晶片之打線支撐性，防止引 起上方晶片之斷裂。 本發明的目的及解決其技術問題是採用以下技術方 (, 案來實現的。依據本發明，一種複合式間隔之多晶片堆 疊構造主要包含一晶片載體、一第一晶片、複數個第一 銲線、一第二晶片、一第一間隔膠層以及一第二間隔膠 層。S亥晶片載體係具有一晶片設置區以及複數個鄰近在 該晶片設置區之連接指。該第一晶片係具有一第一主動 面與一相對之第一背面，該第一晶片之該第一背面係設 置該晶片載體之該晶片設置區，該第一晶片係具有複數 個位於該第一主動面周邊之第一銲墊。該些第一銲線係 連接該些第一銲墊至該些連接指。該第二晶片係疊設於 8 200908280 該第一晶片之上方，該第二晶片係具有一第二主動面與 一相對之第二背面，該第二晶片係具有複數個位於該第 二主動面之第二銲墊。該第一間隔膠層係設於該第一晶 片之該第一主動面之周邊，以密封該些第一銲線之一 端。該第二間隔膠層係設於該第二晶片之該第二背面之 中央，用以界定該第一間隔膠層之厚度，該第二間隔膠 層與該第一間隔膠層圖案互補並組成為同一層。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之複合式間隔之多晶片堆疊構造中，該第二 間隔膠層係可為一晶圓級晶背黏膠。 在前述之複合式間隔之多晶片堆疊構造中，該第二 間隔膠層係可為半固化黏晶膠膜。 在前述之複合式間隔之多晶片堆疊構造中，該第一 間隔膠層係可為一液態塗膠。 在前述之複合式間隔之多晶片堆疊構造中，該第一 間隔膠層與該第二間隔膠層係可填滿在該第一晶片與 第二晶片之間的間隙，並且該第一間隔膠層係稍溢出於 上述間隙之外。 在前述之複合式間隔之多晶片堆疊構造中，可另包 含複數個第二銲線，其係連接該些第二銲墊至該些連接 指。 在前述之複合式間隔之多晶片堆疊構造中，該第二 間隔膠層可另具有複數個支撐條，其係往該第二晶片之 9 200908280 該第二背面之角隅延伸。 【實施方式】 第2、3 A至31、4至6圖係相關於本發明之 體實施例，揭示一種複合式間隔之多晶片堆疊構 請參閱第2圖所示，一種複合式間隔之多晶 構造200主要包含一晶片載體210、一第一晶片 複數個第一銲線23 1、一第二晶片240、一第一 / 層2 5 1以及一第二間隔膠層2 5 2。請參閱第4圖 Ψ Ϊ 該晶片載體2 1 0係具有一晶片設置區2 1 1以及複 近在該晶片設置區2 1 1之連接指2 1 2。該晶片設置 之尺寸係對應於該第一晶片220之尺寸。通常該 體2 1 0係可為一印刷電路板，而具有適當的線路 在本實施例中，該晶片載體2 1 0係為一記憶卡之 該第一晶片220與該第二晶片240可為記憶體晶 該第一晶片220係具有一第一主動面221與 f 、 之第一背面222，其中該第一晶片220係具有複 於該第一主動面221周邊之第一銲墊223。可利 黏晶材料將該第一晶片220之該第一背面222黏 晶片載體2 1 0之上方，以使該第一晶片220係設 片載體2 1 0之該晶片設置區2 1 1。在黏晶之後， 線形成該些第一銲線2 3 1，其係連接該些第一銲 至該些連接指2 1 2，達到該第一晶片220與該晶 2 1 0之電性互連。 請參閱第2圖所示，該第一間隔膠層2 5 1係 第一具 造。 片堆疊 220、 間隔膠 所示， 數個鄰 區2 1 1 晶片載 圖案。 基板， 一相對 數個位 用已知 著在該 置該晶 利用打 墊223 片載體 設於該 10 200908280 第一晶片220之該第一主動面221之周邊，其係 塗佈之覆線膠體，以密封該些第一銲線23 1之一 本實施例中，該第一間隔膠層2 5 1係可為一液態 例如環氧樹脂。該第一間隔膠層2 5 1在固化後可 第二晶片240，更可固定該些第一銲線23 1之一 止該些第一銲線23 1在後續製程中斷裂。 該第二晶片240係具有一第二主動面241與 之第二背面242，該第二晶片240係具有複數個 f ( 第二主動面241之第二銲墊243,可如同該第一銲 一般，形成於該第二主動面 241之周邊。該第 240之該第二背面242係黏貼於該第一間隔膠層 該第二間隔膠層2 5 2上，使該第二晶片2 4 0係疊 第一晶片220之上方而不與該第一晶片220直接 此外，該些第二銲墊243係為朝上，可利用複數 銲線23 2以電性連接該些第二銲墊243至該些 〔212° 請再參閱第2圖所示，該第二間隔膠層252 s玄苐·一晶片240之該第二背面242之中央’用以 第一間隔膠層251之厚度，該第二間隔膠層252 一間隔膠層251圖案互補並組成為同一層。藉此 一間隔膠層2 5 1與該第二間隔膠層2 5 2係可共用 第二晶片240之該第二背面242，增加該第二晶 之黏晶強度而不易模封位移。此外，在該第二晶 之黏晶時，由該第二間隔膠層2 5 2維持晶片堆疊 為液悲 端ϋ在 塗膠， 黏貼該 端，防 一相對 位於該 墊223 二晶片 251與 設於該 接觸。 個第二 連接指 係設於 界定該 與該第 ，該第 黏接該 片240 片240 間隙， 11 200908280 該第二間隔膠層2 5 2之厚度可大於該些第一銲線2 3 1之 弧高，以防止該第二晶片240之該第二背面242壓觸該 些第一銲線2 3 1造成電性短路之缺陷，而該第一間隔膠 層25 1在固化後可用以提高對該第二晶片240之打線支 撐性，避免該第二晶片240斷裂。較佳地，該第二間隔 膠層2 5 2係可為一晶圓級晶背黏膠，能節省一次取放步 驟並減少黏晶之黏膠污染。或者，該第二間隔膠層2 5 2 係可為半固化黏晶膠膜。該第一間隔膠層2 5 1與該第二BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-wafer stack structure for micro-gap, and more particularly to a multi-wafer stack configuration of a composite spacer. [Prior Art] As the demand for miniaturization and high operating speed increases, multiple wafers are integrated into a package structure to achieve more than twice the capacity or more functions, such as in conventional multi-wafer stack constructions. , which stacks and seals a plurality of wafers in a package material and interposes a spacer between the wafer and the wafer, such as a dummy wafer, a metal sheet or a viscous film to avoid stacking the wafers above. The pressure is connected to the bonding wire that has been connected below, so the overall multi-wafer stack height cannot be reduced. In order to reduce the stack height and increase the bond strength, it is known to replace the spacers with liquid coated glues to reduce the wafer stack spacing. Referring to FIG. 1 , a conventional multi-wafer stack structure 100 mainly includes a wafer carrier 110 , a first wafer 120 , a plurality of first bonding wires 13 , a second wafer 1 400 , and a spacer rubber . Layer 1 50. The wafer carrier 110 has a plurality of connection fingers 1 1 1 . One of the first back surface 1 2 2 of the first wafer 120 is adhered to the wafer carrier 110. The first wafer 120 has a plurality of first pads 1 2 3 formed on the periphery of one of the first active surfaces 1 1 1 of the first wafer 120. The first bonding pads 123 formed by wire bonding are connected to the first bonding pads 123 to the connecting fingers 1 1 1 . The second wafer 140 is disposed on the first wafer 120. The spacer layer 150 is formed between the first wafer 120 and the second wafer 6 200908280 1 40 , which is a liquid coated coating glue to adhere the first wafer 120 and the The second wafer 140 can cover one end of the first bonding wires 131 so that the wafer stacking interval can be reduced. The second wafer 140 has a second active surface 141, a second back surface 142, and a plurality of second pads 143 formed on the second active surface 141. The second pads 1 43 may be connected to the connecting fingers 1 1 1 by a plurality of second bonding wires 132. Since the spacer layer 150 completely fills the gap between the first wafer 120 and the second wafer 140, and after curing, the good wiring support of the second wafer 140 can be provided. The first wafer 120, the second wafer 140, the first bonding wires 13 1 and the second bonding wires 13 2 are usually sealed by a single colloid 1 60. Although, by the single-layer structure, the spacer layer 150 can stack a larger number of wafers within a predetermined package thickness, in the bonding process of disposing the second wafer 140, the spacer layer 1 50 has not yet been Curing, unable to accurately control the adhesion spacing. Therefore, the final cured thickness of the spacer layer 150 is affected by the die pressure and temperature, and is not easily controlled to be slightly higher than the line arc height of the first bonding wires 133. Therefore, the second back surface 1 42 of the second wafer 110 is easily pressed against the first bonding wires 133. As shown in FIG. 1, the first bonding wires 143 are generated and the second wafer. 1 4 0 Contact bump contact 1 3 1 A ' Causes the line to be wound when the wafer is stacked and a short circuit occurs. China's invention patent number No. 1243 453 "Processing method for forming a viscous wafer on the surface of a crystal grain" reveals a two-stage gel which can be formed into a B-stage glue after pre-baking. The film, and at 7 200908280, has no fluidity at room temperature, so the upper wafer is less likely to press the lower bonding wire. Since the two-stage rubber system is disposed at the center of the upper wafer, the peripheral region of the upper wafer is not fully supported by the two-stage winning body, so that it is easy to cause the upper wafer to be broken and cracked during the wire bonding process. , causing problems with wafer failure. SUMMARY OF THE INVENTION The main object of the present invention is to provide a composite spacer multi-wafer stack structure that does not require spacers between the wafer stacks, and can maintain a more fixed and small gap and can be avoided. The upper wafer is pressed against the bonding wire, and the overall thickness of the multi-wafer stacking structure is effectively and highly reduced. The second object of the present invention is to provide a composite spacer multi-wafer stacking structure, which improves the wire-supporting property of the upper wafer and prevents it from being prevented. The object of the present invention and the technical problem thereof are solved by the following technical method. According to the present invention, a composite spacer multi-wafer stack structure mainly comprises a wafer carrier and a first wafer. And a plurality of first bonding wires, a second wafer, a first spacer layer and a second spacer layer. The S-chip carrier has a wafer setting region and a plurality of connecting fingers adjacent to the wafer setting region. The first wafer has a first active surface and an opposite first back surface, and the first back surface of the first wafer is provided with the wafer The first wafer system has a plurality of first pads located around the first active surface, and the first bonding wires are connected to the first pads to the connecting fingers. The second wafer has a second active surface and a second opposite surface, and the second wafer has a plurality of second active surfaces. a second soldering pad is disposed on a periphery of the first active surface of the first wafer to seal one end of the first bonding wires. The second spacer layer is disposed on the second wafer The center of the second back surface is used to define the thickness of the first spacer layer, and the second spacer layer is complementary to the first spacer layer pattern and is formed into the same layer. The object of the present invention and solving the technical problem thereof The following technical measures can be further implemented. In the foregoing composite spacer multi-wafer stack configuration, the second spacer layer can be a wafer-level crystal back adhesive. In the construction, the second interval The layer may be a semi-cured adhesive film. In the above-described composite spacer multi-wafer stack configuration, the first spacer layer may be a liquid glue. In the aforementioned composite spacer multi-wafer stack configuration The first spacer layer and the second spacer layer may fill a gap between the first wafer and the second wafer, and the first spacer layer slightly overflows outside the gap. The composite spacer multi-wafer stack structure may further include a plurality of second bonding wires connecting the second pads to the connecting fingers. In the foregoing composite spacer multi-wafer stack configuration, The second spacer layer may further have a plurality of support strips extending to the corners of the second back surface of the second wafer 9 200908280. [Embodiment] Figures 2, 3 A to 31, 4 to 6 are related In the embodiment of the present invention, a composite spacer multi-wafer stack structure is disclosed. Referring to FIG. 2, a composite spacer polycrystalline structure 200 mainly includes a wafer carrier 210 and a first wafer. Welding wire 23 1 , a second crystal 240, a first / layer 251 and a second adhesive layer 252 spacer. Please refer to FIG. 4 Ψ Ϊ The wafer carrier 210 has a wafer setting area 2 1 1 and a connecting finger 2 1 2 in the wafer setting area 2 1 1 . The dimensions of the wafer arrangement correspond to the dimensions of the first wafer 220. Generally, the body 210 can be a printed circuit board, and the appropriate circuit is provided. In this embodiment, the first wafer 220 and the second wafer 240 of the memory carrier are a memory card. The first wafer 220 has a first active surface 221 and a first back surface 222. The first wafer 220 has a first bonding pad 223 that is adjacent to the periphery of the first active surface 221 . The first back surface 222 of the first wafer 220 is adhered over the wafer carrier 2 10 such that the first wafer 220 is provided with the wafer setting region 2 1 1 of the wafer carrier 210. After the die bonding, the wires form the first bonding wires 233, and connect the first bonding wires to the connecting fingers 2 1 2 to achieve electrical mutual interaction between the first wafer 220 and the crystal 2 10 even. Referring to Figure 2, the first spacer layer 2 5 1 is the first one. The wafer stack 220, the spacer glue, shows a number of adjacent 2 1 1 wafer-loaded patterns. a substrate, a relatively plurality of bits are known to be disposed on the periphery of the first active surface 221 of the 10 200908280 first wafer 220 by using the wafer 223 chip carrier, which is coated with a coating gel, In order to seal one of the first bonding wires 23 1 , the first spacer layer 25 1 may be a liquid such as an epoxy resin. The first spacer layer 251 can be cured after the second wafer 240, and one of the first bonding wires 23 1 can be fixed to break the first bonding wires 23 1 in a subsequent process. The second wafer 240 has a second active surface 241 and a second back surface 242. The second wafer 240 has a plurality of f (second bonding pads 243 of the second active surface 241, which can be like the first soldering Formed on the periphery of the second active surface 241. The second back surface 242 of the 240th layer is adhered to the second spacer layer 2 52 of the first spacer layer, so that the second wafer is The second solder pads 243 are disposed upwardly, and the second solder pads 243 are electrically connected to the second solder pads 243. [212° Please refer to FIG. 2 again, the second spacer layer 252 s 苐 苐 · the center of the second back surface 242 of a wafer 240 is used for the thickness of the first spacer layer 251, the second The spacer layer 252 has a pattern of complementary adhesive layers 251 and is formed into the same layer. The spacer layer 251 and the second spacer layer 252 can share the second back surface 242 of the second wafer 240. Increasing the bond strength of the second crystal without easily molding the displacement. Further, when the second crystal is bonded, the second spacer layer is 2 2 2 Holding the wafer stack as a liquid sorrow, applying glue to the end, preventing the opposite side from being located on the pad 223 and the second wafer 251 is disposed in the contact. The second connecting finger is disposed to define the first and the second bonding The sheet 240 has a gap of 240, and the thickness of the second spacer layer 252 can be greater than the arc height of the first bonding wires 213 to prevent the second back surface 242 of the second wafer 240 from being pressed. The first bonding wires 231 cause a short circuit of the electrical short circuit, and the first spacer layer 25 1 can be used after curing to improve the wire bonding support of the second wafer 240 to prevent the second wafer 240 from being broken. Preferably, the second spacer layer 252 can be a wafer-level crystal back adhesive, which can save the pick-and-place step and reduce the adhesion of the adhesive. Alternatively, the second spacer layer 25 The 2 series may be a semi-cured adhesive film. The first spacer layer 2 5 1 and the second

C 間隔膠層2 5 2應皆為電絕緣性，以避免不當的電性短 路。在本實施例中，該第一間隔膠層2 5 1與該第二間隔 膠層252係可填滿在該第一晶片220與第二晶片240之 間的間隙，並且該第一間隔膠層2 5 1係可稍溢出於上述 間隙之外。 因此，該第二間隔膠層2 5 2係可維持並限制該第一 間隔膠層25 1之厚度，避免該第二晶片240過度下沉而 t 壓觸該些第一銲線2 3 1，其中該第一間隔膠層2 5 1係形 成該第一晶片220之周邊更包覆該些第一銲線23 1之一 端，對於該第二晶片240可提供良好打線支持，且不需 要在多晶片堆疊製程中設置間隔物，藉此降低該多晶片 堆疊構造200之堆疊高度。此外，該第一間隔膠層25 1 與該第二間隔膠層 2 5 2可維持一更固定且較小之間 隙，不會因晶片堆疊不正或傾斜之現象導致該第二晶片 240壓觸到該些第一銲線23 1。 具體而言，該多晶片堆疊構造200可另包含有一封 12 200908280 膠體2 6 0，其係形成於該晶片載體2 1 0之 該第一晶片220、該第二晶片240、該些 與該些第二銲線232，使該多晶片堆疊構 元件與外界隔離，以避免受外界水氣或污 第3Α至31圖係用以說明該多晶片堆 具體形成方法。首先，請參閲第3Α及4 一晶片載體2 1 0，且該晶片載體2 1 0係具 .. 區21 1以及複數個鄰近在該晶片設置區 C " 212。接著，請參閱第3Β圖所示，設置一 於該晶片載體210上，該第一晶片220係 動面221、一相對之第一背面222以及複 223。通常積體電路元件係製作於該第一 該些第一銲墊2 2 3係位於該第一晶片2 2 0 面221之周邊。請參閱第3C圖所示，以 數個第一銲線23 1係電性連接該些第一銲 ^ 連接指2 1 2。 接著，請參閱第3 D圖所示，一第一 可液態塗佈在該第一晶片220之該第一主 邊，以密封該些第一銲線2 3 1之一端。在 可利用點膠技術藉由一點膠針頭2 0提供 一間隔膠層2 5 1，點塗在該第一晶片2 2 0 面22 1之周邊。 請參閱第3 Ε圖所示，疊設一第二晶片 晶片220之上方，該第二晶片240係具有 上方，以密封 第一銲線2 3 1 造2 00之内部 染物侵害。 疊構造之第一 圖所示，提供 有'一晶片設置 2 1 1之連接指 第一晶片220 具有一第一主 數個第一鲜塾 主動面 221， 之該第一主動 打線方式使複 墊223至該些 間隔膠層 2 5 1 動面221之周 本實施例中， 尚為液態之第 之該第一主動 2 4 0於該第一 一第二主動面 13 200908280 24 1、一相對之第二背面242以及複數個位於該第二主 動面241之第二銲墊24 3。其中，在堆疊該第二晶片240 之製程之前，該第二晶片24〇之該第二背面242之中央 已預設有一第二間隔膠層252。 請參閱第3 F圖所示，該第二間隔膠層2 5 2係用以界 定該第一間隔膠層2 5 1之厚度，該第二間隔膠層2 5 2與 該第一間隔膠層2 5 1圖案互補並組成為同一層。藉此， /該第二晶片240不會與該第一晶片220直接接觸並具有 f ~ 良好打線支持力與水平面。 接著，請參閱第3 G圖所示，打線形成之複數個第二 銲線23 2係電性連接該些第二銲墊243至該些連接指 2 1 2。之後，請參閱第3 Η圖所示，以壓模形成一封膠體 260於該晶片載體210之上方，以密封該第一晶片220、 該第二晶片240、該些第一銲線23 1與該些第二銲線 2 3 2。最後，請參閱第31圖所示，利用切割刀3 0沿著 、 該晶片載體2 1 0之複數個切割道2 1 3切割該晶片載體 2 1 0與該封膠體2 6 0，以分離出複數個多晶片堆疊構造 200(如第2圖所示）。 因此，在上述製程中，不需要在該第一晶片220與 該第二晶片2 4 0之間設置間隔物，以降低堆疊高度，而 在更微小的堆疊間隙内也不會有該第二晶片 2 4 0壓觸 該些第一銲線2 3 1的問題。 本發明進一步說明該第二間隔膠層2 5 2之預形成方 法。請參閱第5圖所示，提供一晶圓10，該晶圓1 〇係 14 200908280 具有一表面，其係可為積體電路之形成表面或晶圓背 面，其中該表面係具有複數個沿著行方向（X軸）與列方 向（Y軸）之切割道1 1，該些切割道1 1係用以定義出複 數個苐二晶片240。在該晶圓10之該表面均勻塗佈一 層之該第二間隔膠層252，如網版印刷（screenprinting) 或鋼版印刷（stencil printing)或轉貼方式，使該第二間 隔膠層 2 5 2以特定圖案局部塗佈於該晶圓1 〇之該表 面，即該第二晶片240之第二背面424之中央。之後，C The spacer layer 2 5 2 should be electrically insulating to avoid improper electrical short circuits. In this embodiment, the first spacer layer 251 and the second spacer layer 252 can fill a gap between the first wafer 220 and the second wafer 240, and the first spacer layer The 2 5 1 system can overflow slightly beyond the above gap. Therefore, the second spacer layer 252 can maintain and limit the thickness of the first spacer layer 25 1 to prevent the second wafer 240 from excessively sinking and t to touch the first bonding wires 2 3 1 . The first spacer layer 251 forms a periphery of the first wafer 220 and further covers one end of the first bonding wires 23 1 , which can provide good wire bonding support for the second chip 240 and does not need to be much Spacers are provided in the wafer stacking process, thereby reducing the stack height of the multi-wafer stack construction 200. In addition, the first spacer layer 25 1 and the second spacer layer 252 can maintain a more fixed and small gap, and the second wafer 240 is not pressed by the phenomenon that the wafer stack is not positive or inclined. The first bonding wires 23 1 . Specifically, the multi-wafer stack structure 200 may further include a 12200908280 colloid 260, which is formed on the first wafer 220, the second wafer 240, and some of the wafer carrier 210. The second bonding wire 232 isolates the multi-wafer stacking component from the outside to avoid the external moisture or dirt pattern to illustrate the specific forming method of the multi-chip stack. First, please refer to the third and fourth wafer carriers 2 10 , and the wafer carrier 2 10 is equipped with a region 21 1 and a plurality of adjacent regions in the wafer setting region C " 212 . Next, as shown in FIG. 3, the first wafer 220 is disposed on the wafer carrier 210, and the first wafer 220 is opposite to the first back surface 222 and the second surface 222. Usually, the integrated circuit components are formed on the first of the first pads 2 2 3 at the periphery of the first wafer 2 2 0 surface 221 . Referring to FIG. 3C, the first bonding wires 23 1 are electrically connected to the first bonding wires 2 1 2 . Next, referring to FIG. 3D, a first liquid can be applied to the first main side of the first wafer 220 to seal one end of the first bonding wires 213. A spacer layer 2 5 1 is provided by a dispensing technique to dispense a perimeter of the first wafer 2 2 surface 22 1 . Referring to FIG. 3, a second wafer wafer 220 is stacked above the second wafer 240 to seal the first solder wire 2 3 1 to make an internal stain of 200 Å. As shown in the first figure of the stack structure, the connection of the first wafer 220 having the first wafer 220 has a first main number of the first fresh-rolling active surface 221, and the first active wire-bonding method enables the composite pad. 223 to the spacer layer 2 5 1 of the moving surface 221 in this embodiment, the liquid is the first of the first active 240 in the first first active surface 13 200908280 24 1 , a relative The second back surface 242 and a plurality of second pads 24 3 located on the second active surface 241. Before the process of stacking the second wafer 240, a second spacer layer 252 is preset in the center of the second back surface 242 of the second wafer 24 . Referring to FIG. 3F, the second spacer layer 252 is used to define the thickness of the first spacer layer 251, the second spacer layer 252 and the first spacer layer. 2 5 1 The patterns are complementary and composed of the same layer. Thereby, the second wafer 240 does not directly contact the first wafer 220 and has f ~ good wire bonding force and horizontal plane. Next, referring to FIG. 3G, a plurality of second bonding wires 23 2 formed by wire bonding electrically connect the second pads 243 to the connecting fingers 2 1 2 . Thereafter, referring to FIG. 3, a glue 260 is formed over the wafer carrier 210 by stamping to seal the first wafer 220, the second wafer 240, and the first bonding wires 23 1 and The second bonding wires 2 3 2 . Finally, referring to FIG. 31, the wafer carrier 2 1 0 and the encapsulant 2 60 are cut by the dicing blade 30 along the plurality of dicing streets 2 1 3 of the wafer carrier 2 10 to separate the wafer carrier 2 1 0 and the encapsulant 210 . A plurality of multi-wafer stack configurations 200 (as shown in Figure 2). Therefore, in the above process, it is not necessary to provide a spacer between the first wafer 220 and the second wafer 220 to reduce the stack height, and the second wafer does not exist in a smaller stack gap. 2 4 0 is pressed against the problems of the first bonding wires 2 3 1 . The present invention further illustrates the method of pre-forming the second spacer layer 252. Referring to FIG. 5, a wafer 10 is provided. The wafer 1 has a surface which can be a surface of a integrated circuit or a back surface of the wafer, wherein the surface has a plurality of The scribe lines 1 1 in the row direction (X-axis) and the column direction (Y-axis) are used to define a plurality of second wafers 240. The second spacer layer 252 is evenly coated on the surface of the wafer 10, such as screen printing or stencil printing or rewinding, so that the second spacer layer 2 2 2 The surface of the wafer 1 is partially applied to the center of the wafer 1 , that is, the center of the second back surface 424 of the second wafer 240 . after that,

C 預烤該晶圓1 0，使該第二間隔膠層2 5 2在室溫達到固 態及具有不易塌散的外形，以利界定該第一間隔膠層 2 5 1之厚度。在該晶圓1 0上之該第二間隔膠層2 5 2可 為半固化黏晶膠膜，以供翻轉或黏晶機吸附之加工。沿 著該些切割道1 1切割該晶圓1 0後，可以得到如第6圖 所示預形成有該第二間隔膠層252之第二晶片240。在 切割該晶圓10時，不會切割到該第二間隔膠層2 5 2， ί 以減少膠體污染並避免不當固化。 本發明之第二具體實施例，揭示另一種複合式間隔 之多晶片堆豐構造之上晶片與第二間隔膠層，主要架 構，如晶片載體、第一晶片及第二晶片等等，可與第一 具體實施例大致相同，不再贅述。請參閱第7及8圖所 示，在本實施例中，一第二間隔膠層2 5 2 ’係設於該第二 晶片240之該第二背面242之中央，用以界定一第一間隔膠 層之厚度，如同第一實施例一般，該第二間隔膠層525 ’與第 一間隔膠層圖案互補並組成為同一層。該第二間隔膠層 15 200908280 252’可另具有複數個支撑條253,其係往該負 之該第二背面242之角隔延伸，進而可以增 片240之黏晶平穩度又不影響下方的銲線， 第二晶片2 4 0之黏晶支撑性。其中，該些支 邊緣係可與該第二晶片240角隅邊緣切齊。 二晶片2 4 0 —體形成於—晶圓1 〇，並切割立 片尺寸。該第二間隔膠層2 5 2，係可利用印刷 光顯影等技術，圖案化形成於該晶圓1 0之C pre-baked the wafer 10 such that the second spacer layer 252 reaches a solid state at room temperature and has a shape that is not easily collapsed to define the thickness of the first spacer layer 251. The second spacer layer 2 5 2 on the wafer 10 may be a semi-cured adhesive film for processing by inversion or die attaching. After the wafer 10 is cut along the scribe lines 11, a second wafer 240 pre-formed with the second spacer layer 252 as shown in Fig. 6 can be obtained. When the wafer 10 is diced, the second spacer layer 2 5 2, ί is not cut to reduce colloidal contamination and avoid improper curing. In a second embodiment of the present invention, another composite spacer multi-wafer stack structure wafer and a second spacer layer are disclosed, and the main structures, such as a wafer carrier, a first wafer, a second wafer, etc., are The first embodiment is substantially the same and will not be described again. Referring to FIGS. 7 and 8, in the present embodiment, a second spacer layer 2 5 2 ′ is disposed in the center of the second back surface 242 of the second wafer 240 to define a first interval. The thickness of the glue layer, as in the first embodiment, the second spacer layer 525' is complementary to the first spacer layer pattern and is composed of the same layer. The second spacer layer 15 200908280 252 ′ may further have a plurality of support strips 253 extending to the corners of the negative second back surface 242 , so that the adhesion of the wafer 240 can be stabilized without affecting the underside. Solder wire, 2400 wafer adhesion support. Wherein, the edge portions are aligned with the corner edges of the second wafer 240. The two wafers 240 are formed on the wafer 1 and cut into the size of the wafer. The second spacer layer 252 can be patterned and formed on the wafer by using a technique such as printing light development.

I 兩相鄰的第二晶片2 4 〇係以穿過該些切割g 支撐條2 5 3相互連接。 以上所述，僅是本發明的較佳實施例而 本發明作任何形式上的限制，本發明技術方 所附申請專利範圍為準。任何熟悉本專業的 利用上述揭示的技術内容作出些許更動或 變化的等效實施例，但凡是未脫離本發明技 ^ 容，依據本發明的技術實質對以上實施例所 單修改、等同變化與修飾，均仍屬於本發明 範圍内。 【圖式簡單說明】 第1圖：一種習知多晶片堆疊構造之截面示 第2圖：依據本發明之第一具體實施例，-隔之多晶片堆疊構造之截面示意圖， 第3A至31圖：依據本發明之第一具體實於 片堆疊構造在製程令依其晶片載體 ^二晶片240 加該第二晶 並可提高該 撐條2 5 3之 當複數個第 i 11界定晶 丨、黏貼或曝 背面’在兩 I 11之該些 已，並非對 案範圍當依 技術人員可 修飾為等同 術方案的内 作的任何簡 技術方案的 意圖。 -種複合式間 i例，該多晶 之截面示意 16 200908280 圖。 第4圖：依據本發明之第一具體實施例，該多晶片堆疊 構造之一晶片載體之頂面示意圖。 第5圖：依據本發明之第一具體實施例，該多晶片堆疊 構造之一上晶片於晶圓階級之背面示意圖。 第6圖：依據本發明之第一具體實施例，該多晶片堆疊 構造之上晶片之立體圖。I Two adjacent second wafers 24 are connected to each other through the cutting g support strips 253. The above is only a preferred embodiment of the present invention and the present invention is not limited to any form, and the scope of the patent application of the present invention is subject to the scope of the patent application. Any equivalent embodiments that are susceptible to variations and modifications of the subject matter of the present invention will be apparent to those skilled in the art without departing from the scope of the present invention. All remain within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a conventional multi-wafer stack structure. FIG. 2 is a cross-sectional view showing a multi-wafer stack structure according to a first embodiment of the present invention, FIGS. 3A to 31: According to the first embodiment of the present invention, the wafer stacking structure is configured to add the second crystal to the wafer carrier 240 and to increase the number of the ribs, pastes, or Exposing the back 'in the case of the two I 11 is not intended to be in the scope of any simple technical solution that can be modified by the skilled person as an equivalent. - In the case of a compound type, the cross section of the polycrystal is shown in Fig. 16 200908280. Figure 4 is a top plan view of a wafer carrier of the multi-wafer stack configuration in accordance with a first embodiment of the present invention. Figure 5 is a schematic illustration of the wafer on one side of the wafer level in one of the multi-wafer stack configurations in accordance with a first embodiment of the present invention. Figure 6 is a perspective view of a wafer above the multi-wafer stack construction in accordance with a first embodiment of the present invention.

第7圖：依據本發明之第二具體實施例，另一種多晶片 堆豐構造之一上晶片於晶圓階級之背面不意 圖。 第8圖：依據本發明之第二具體實施例，適用於多晶片 堆疊構造之另一種上晶片之立體圖。 【主要元件符號說明】 1 〇 晶圓 11 切割道 20 點膠針頭 30 切割刀 100多晶片堆疊構造 110晶片載體 120第一晶片 123第一銲墊 13 1第一銲線 140第二晶片 143第二銲墊 150間隔膠層 111連接指 121第一主動面 1 3 1A碰觸點 141第二主動面 160封膠體 122第一背面 1 3 2第二銲線 142第二背面 200多晶片堆疊構造 17 200908280Figure 7: In accordance with a second embodiment of the present invention, the wafer on one of the other multi-wafer stack structures is not intended to be on the back side of the wafer level. Figure 8 is a perspective view of another upper wafer suitable for use in a multi-wafer stack construction in accordance with a second embodiment of the present invention. [Main component symbol description] 1 〇 wafer 11 dicing street 20 dispensing needle 30 dicing blade 100 multi wafer stacking structure 110 wafer carrier 120 first wafer 123 first pad 13 1 first bonding wire 140 second wafer 143 second Pad 150 spacer layer 111 connection finger 121 first active surface 1 3 1A bump contact 141 second active surface 160 encapsulant 122 first back surface 1 3 2 second bonding wire 142 second back surface 200 multi wafer stack structure 17 200908280

210晶片載體 213切割道 220第一晶片 223第一銲墊 231第一銲線 240第二晶片 243第二銲墊 251第一間隔膠層 252第二間隔膠層 260封膠體 2 11晶片設置區 221第一主動面 232第二銲線 241第二主動面 252’第二間隔膠層 212連接指 222第一背面 242第二背面 253支撐條 18210 wafer carrier 213 dicing street 220 first wafer 223 first bonding pad 231 first bonding wire 240 second wafer 243 second bonding pad 251 first spacer layer 252 second spacer layer 260 encapsulant 2 11 wafer setting area 221 The first active surface 232, the second bonding wire 241, the second active surface 252 ′, the second spacer layer 212, the connecting finger 222, the first back surface 242, the second back surface 253, the support strip 18

Claims (1)

200908280 十、申請專利範圍： 1 一種複合式間隔之多晶片堆疊構造，包含： 曰曰片載體，其係具有—晶片設置區以及複數個鄰近在 5亥晶片設置區之連接指； 第日日>}’其係、具有一帛—主動面與一相對之第—背 面，該第一晶片之該第一背面係言史置該晶片載體之該 r B曰曰片設置區，該第一晶片係具有複數個位於該第一主 〔 動面周邊之第一銲墊； 複數個第-銲線，其係連接該些第一鲜塾至該些 ^ ; —第二晶片，其係疊設於該第一晶片之上方，該第二曰 ΒΘ 片係具有一第二主動面與一相對之第二背面該第二 晶片係具有複數個位於該第二主動面之第二銲墊； —第一間隔膠層，其係設於該第一晶片之該第一主動面 、之周邊’以密封該些第一銲線之一端；以及 —第二間隔膠層，其係設於該第二晶片之該第二背面之 中央，用以界定該第一間隔膠層之厚度，該第二間隔 勝層與該第一間隔膠層圖案互補並組成為同一層。 2'如申請專利範圍第1項所述之複合式間隔之多晶片堆 叠構造’其中該第二間隔膠層係為一晶圓級晶背黏膠。 3 > 、如申請專利範圍第2項所述之複合式間隔之多晶片堆 疊構造’其中該第二間隔膠層係為半固化黏晶膠瞑。 4如申請專利範圍第1或2項所述之複合式間隔之多曰 /日g 片堆疊構造’其中該第一間隔膠層係為一液態塗膠。 19 200908280 5、如申請專利範圍第】項所述之複合相隔之多晶片堆 疊構造，其中該第一間隔膠層與該第二間隔膠層係填滿 在&第曰曰片與第二晶片之間的間隙，並且該第一間隔 膠層係稍溢出於上述間隙之外。 6、如中請#利範®第1項所述之複合相隔之多晶片堆 疊構造，另包含複數個第二銲線，其係連接該些第二銲 墊至該些連接指。 卜如申請專利範圍帛1項所述之複合式間隔之多晶片堆 疊構造，其中該第二間隔膠層另具有複數個支撐條，其 係在該第一晶片之該第二背面之角隅延伸。 20200908280 X. Patent Application Range: 1 A composite spacer multi-wafer stack structure, comprising: a wafer carrier having a wafer setting area and a plurality of connection fingers adjacent to the 5 kel wafer setting area; day day &gt ???the system has a 帛-active surface and an opposite first-back surface, the first back surface of the first wafer is said to set the r B 设置 chip setting region of the wafer carrier, the first wafer Having a plurality of first pads located around the first main surface; a plurality of first bonding wires connecting the first fresh sputums to the second dies; the second wafers are stacked on Above the first wafer, the second die has a second active surface and an opposite second back surface. The second wafer has a plurality of second pads on the second active surface; a spacer layer disposed on the periphery of the first active surface of the first wafer to seal one end of the first bonding wires; and a second spacer layer disposed on the second wafer The center of the second back surface is used to define the first interval The thickness of the layer, the second spacer layer and the first spacer winning pattern complementary to and subbing layer consisting of the same layer. 2' The composite spacer multi-wafer stack structure as described in claim 1, wherein the second spacer layer is a wafer level crystal back adhesive. 3) The composite spacer multi-wafer stack construction as described in claim 2, wherein the second spacer layer is a semi-cured adhesive. 4. The multi-layer/day g-sheet stack structure as described in claim 1 or 2 wherein the first spacer layer is a liquid glue. The composite spacer multi-wafer stack structure of claim 1, wherein the first spacer layer and the second spacer layer are filled in the & second and second wafers. A gap between the gaps and the first spacer layer is slightly out of the gap. 6. The composite multi-wafer stacking structure of claim 1 wherein the plurality of second bonding wires are connected to the second bonding pads to the connecting fingers. The composite spacer multi-wafer stack structure of claim 1, wherein the second spacer layer further has a plurality of support strips extending at a corner of the second back surface of the first wafer . 20
TW096130065A 2007-08-14 2007-08-14 Multi-chip stacked device with a composite spacer layer TW200908280A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9184153B2 (en) 2012-03-09 2015-11-10 Industrial Technology Research Institute Chip stack structure and method for fabricating the same
US9543273B2 (en) 2015-01-19 2017-01-10 International Business Machines Corporation Reduced volume interconnect for three-dimensional chip stack

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9184153B2 (en) 2012-03-09 2015-11-10 Industrial Technology Research Institute Chip stack structure and method for fabricating the same
US9543273B2 (en) 2015-01-19 2017-01-10 International Business Machines Corporation Reduced volume interconnect for three-dimensional chip stack
US9679875B2 (en) 2015-01-19 2017-06-13 International Business Machines Corporation Reduced volume interconnect for three-dimensional chip stack

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