TW200926314A - Method for forming a die attach layer during semiconductor packaging processes - Google Patents

Method for forming a die attach layer during semiconductor packaging processes Download PDF

Info

Publication number
TW200926314A
TW200926314A TW096147095A TW96147095A TW200926314A TW 200926314 A TW200926314 A TW 200926314A TW 096147095 A TW096147095 A TW 096147095A TW 96147095 A TW96147095 A TW 96147095A TW 200926314 A TW200926314 A TW 200926314A
Authority
TW
Taiwan
Prior art keywords
die
layer
substrate
printing
bonding
Prior art date
Application number
TW096147095A
Other languages
Chinese (zh)
Other versions
TWI353642B (en
Inventor
Wen-Jeng Fan
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW096147095A priority Critical patent/TWI353642B/en
Publication of TW200926314A publication Critical patent/TW200926314A/en
Application granted granted Critical
Publication of TWI353642B publication Critical patent/TWI353642B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

Disclosed is a method for forming die attach layer during semiconductor packaging processes. A chip carrier includes a substrate core and a stiffener. The substrate core includes a plurality of exposed unit die-bond areas and a peripheral area covered by the stiffener. Moreover, a non-planar stencil having a reduced thickness at peripheries is provided. When the non-planar stencil is pressed on the chip carrier, the non-planar stencil can be smoothly in contact with the substrate core and the stiffener without collapse and has a plurality of printing openings exposing the die-bond areas. Next, a die attach material is filled in the printing openings by printing to form on the substrate core. Accordingly, the warpage of the chip carrier can be suppressed to avoid die-bonding flood. This is why the die attach material can be low-cost fabricated on the die-bonding reinforced chip carrier.

Description

200926314200926314

九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體晶片封I技術， 於一種半導體封裝製程中形成黏晶層之方法。 【先前技術】 在一般的半導體封裝構造中， 利用黏晶材料p 晶片黏著固定在一基板上。逢曰 點日日材料主要區別為 類，一為以印刷或師形成之液態或㈣態之" 一為以ϋ態貼附之黏晶料。其+，印刷形成之浓 膠稠態之膠體具有黏晶材料節省與調整塗施面彩 大之優‘點，但對於基板^曲度甚為敏感，易有I, 膠之問題。習知的基板會在其上下表面各形成有一 層，故基板之翹曲問題尚不嚴重。然而當基板之矣 所改變時，就會影響到黏晶材料之選用。 請參閱第1圖所示，一種習知半導體封裝構土 主要包含一黏晶強化型基板1 1 0、一晶片i 2 〇、一 膠帶130、複數個銲線140以及一封膠體15〇β智 110係包含有一基板核心層111以及僅有一層之1 層11 2，該下防銲層Π 2係形成於該基板核心層 下表面1 1 4。該基板核心層1 1 1之上表面1 1 3則异 層，故該黏晶膠帶1 3 0直接貼附於該基板核心層 特別係 有關 以黏接該晶片1 2 0。該些銲線1 4 0係通過該基板1 打線槽孔1 1 5以電性連接該晶片1 2 0之複數個銲售 至該基板110之對應接指116。該封膠體150係密 將一 兩大 ί，另 .態或 彈性 晶溢 防鲜 構有 r 100 黏晶 :基板 防銲 11之 防銲 1 1 1 > 10之 ^ 121 封該 6 200926314 晶片1 2 0與該些銲線1 4 0。複數個銲球1 6 0係設置於該 基板1 1 0之球墊11 7。通常該基板1 1 〇之該基板核心層 1 11之材質係為玻纖布含浸樹脂’對於該黏晶膠帶1 3 〇 或其它黏晶材料有著較佳黏著效果，藉以加強該晶片 12〇之接合強度。然而該基板11〇因僅在該下表面U4 形成有一下防焊層11 2，特別是使用基板條進行半導體 封裝時’該基板11 〇的翹曲程度會更加明顯，使得在製 φ 程中無法以印刷方式直接在該基板核心層1 1 1上塗佈 液態之黏晶材料的困難度較高，並且翹曲嚴重之基板條 不便於製程傳輸與被封裝機台固定。目前一種習知半導 體封裝構造1 00之製造方法是先將該基板i丨〇分割成單 顆，以降低翹曲度，但已無法提供一大面積之印刷表 面，仍無法使用由印刷形成之液態或膠稠態之膠體作為 黏晶材料，並且不利於製程傳輸與基板定位。此外，製 程成本亦是大幅增加。 ® 【發明内容】 本發明之主要目的係在於提供一種半導體封裝製程 中 忠 晶材料之溢 方式形成黏 战黏晶層之方法，藉由模板印刷（stencil Printing) 層式使黏晶材料直接塗佈於一晶片載體之基板核心 x加強黏晶強度。利用一晶片載體上之加勁件以及 a 4板印刷模板可以抑制晶片載體之翹曲以避免黏 ’故能在黏晶強化型晶片載體上以低成本 ί晶材料。 的目的及 本發明 的及解決其技術問題是採用以下技術方 7 200926314 案來實現的。依據本發明之一種半導體封裝製程中形 黏晶層之方法’首先，提供一晶片載體，該晶片載體 包含一基板核心層與一加勁件，該基板核心層之一上 面包含有複數個單元黏晶區以及一圍繞該些單元黏 區之周邊區，其中該加勁件係局部形成於該基板核心 之該上表面，以覆蓋該周邊區，但顯露該些單元黏 區。接著，提供一非平板印刷模板，該非平板印刷模IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor wafer encapsulation technique for forming a die bond layer in a semiconductor package process. [Prior Art] In a general semiconductor package structure, a die-bonding material p wafer is adhered to a substrate. Every day, the main difference between the materials is the class, one is the liquid or the (4) state formed by the printing or the division, and the other is the adhesive crystal attached by the state. Its +, the gel-formed colloid formed by the printing has the advantage of the retention of the bonded crystal material and the adjustment of the coating surface color, but it is very sensitive to the substrate curvature, and it is easy to have the problem of I and glue. Conventional substrates have a layer formed on each of their upper and lower surfaces, so the warpage of the substrate is not serious. However, when the enthalpy of the substrate is changed, the selection of the viscous material is affected. Referring to FIG. 1 , a conventional semiconductor package structure mainly comprises a die-bonded substrate 110 , a wafer i 2 , a tape 130 , a plurality of bonding wires 140 , and a colloid 15 . The 110 series includes a substrate core layer 111 and only one layer 11 2 . The lower solder mask layer 2 is formed on the lower surface 1 14 of the substrate core layer. The surface 1 1 3 of the substrate core layer 11 1 is a different layer. Therefore, the die bond tape 130 is directly attached to the substrate core layer to bond the wafer 120. The bonding wires 140 are electrically soldered to the corresponding fingers 116 of the substrate 110 through the substrate 1 wire slot 1 1 5 to electrically connect the plurality of wafers 120. The encapsulant 150 is densely packed with one or two large, another state or elastic crystal overflow anti-fresh with r 100 adhesive crystal: substrate solder mask 11 anti-welding 1 1 1 > 10 ^ 121 seal the 6 200926314 wafer 1 2 0 with these weld lines 1 400. A plurality of solder balls 160 are disposed on the ball pad 11 7 of the substrate 110. Generally, the substrate core layer 11 of the substrate 1 1 is made of a fiberglass cloth impregnated resin, which has a better adhesion effect on the adhesive tape 13 or other adhesive material, thereby reinforcing the bonding of the wafer 12 strength. However, the substrate 11 has a solder resist layer 11 2 formed only on the lower surface U4, and particularly when the substrate strip is used for semiconductor packaging, the degree of warpage of the substrate 11 is more pronounced, making it impossible to perform the process. It is difficult to apply liquid crystalline material directly on the substrate core layer 11 1 by printing, and the substrate strip with severe warpage is inconvenient for process transfer and fixing to the packaged machine. At present, a conventional semiconductor package structure 100 is manufactured by first dividing the substrate into a single piece to reduce warpage, but it is unable to provide a large area of printing surface, and it is still impossible to use a liquid formed by printing. Or a colloidal colloid as a die-bonding material, and is not conducive to process transfer and substrate positioning. In addition, the cost of the process has also increased significantly. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for forming a viscoelastic layer by means of a smectic material overflow in a semiconductor packaging process, and directly coating the die-bonding material by stencil printing layering The core strength of the substrate on a wafer carrier x enhances the bond strength. The use of a stiffener on a wafer carrier and a 4 plate print stencil can suppress warpage of the wafer carrier to avoid sticking, so that a low cost crystalline material can be deposited on the viscosified wafer carrier. The object and the technical problem of the present invention are solved by the following technique 7 200926314. A method of forming a die-shaped layer in a semiconductor package process according to the present invention. First, a wafer carrier is provided. The wafer carrier comprises a substrate core layer and a stiffener, and one of the core layers of the substrate comprises a plurality of unit cells. And a peripheral region surrounding the cell bonding regions, wherein the stiffening member is partially formed on the upper surface of the substrate core to cover the peripheral region, but the cell bonding regions are exposed. Next, a non-lithographic template is provided, the non-lithographic printing die

係具有一非平坦壓貼面，其中該非平坦壓貼面 為厚度減少，用以補償該加勁件之厚度，該非 模板更具有複數個印刷開孔。之後，壓附該非 模板至*亥晶片載體’以使該些印刷開孔顯露該 層之該些單元黏晶區，並且該非平板印刷模板 陷地貼觸至該基板核心層與該加勁件。最後， 平板印刷模板之該些印刷開孔，印刷一黏晶材 板核心層之該些單元黏晶區。 本發月的目的及解決其技術問題還可採用 措施進一步實現。 之周邊 平板印 平板印 基板核 係為無 通過該 料至該 以下技 成 係 表 晶 層 晶 板 係 刷 刷 心 塌 非 基 術 在前述的半導體封裝製程中形成黏晶層之方》' 該加勁件係可為環形框。 在則述的丰導壯也』 干导體封裝㈣中形成黏晶層之方》、 該晶片載體係r 了為—印刷電路板並具有-下防焊 下防焊層係大致覆蓋兮I 復益該基板核心層之一下表 4 辉層之覆蓋面積係大# _ 價係大於該加勁件之覆蓋面積。 在前述的半導體封裝製 牧聚程中形成黏晶層之方 該 防 8 200926314 該加勁件係可為—士„ Μ Λ 為加厚型圖案化防焊層，而不覆蓋該基 板核心層之該4b單开赴Β Γ5· ^ —早兀黏日日£，並且該加勁件之厚度係大 於該下防焊層。 在刖述的半導體封裝製程中形成黏晶層之方法中， 可另包含-預棋烤步驟，以使該黏晶材料部分固化為一 在該基板核心層上之均厚黏晶層。 ❹The utility model has a non-flat pressing surface, wherein the non-flat pressing surface is reduced in thickness to compensate the thickness of the stiffening member, and the non-template further has a plurality of printing openings. Thereafter, the non-template is attached to the *-wafer carrier to cause the printing openings to expose the unit die regions of the layer, and the non-lithographic template is in contact with the substrate core layer and the stiffener. Finally, the printing openings of the stencil are printed on the die-bonding regions of the core layers of the die bond. The purpose of this month and the resolution of its technical problems can be further achieved by measures. The periphery of the slab-printed substrate nucleus is such that the material is not passed through to the following technical layer, and the crystal layer is brushed, and the slab is formed in the semiconductor packaging process described above. The piece can be a ring frame. In the description of the Feng Zhuang also "dry conductor package (four) in the formation of a layer of the adhesion layer", the wafer carrier is a - printed circuit board and has - under the under-weld under the welding layer is roughly covered 兮I complex One of the core layers of the substrate is shown in Table 4 below. The coverage area of the layer is greater than the coverage area of the stiffener. In the foregoing semiconductor package grazing grazing process, the layer of the viscous layer is formed. The anti-corrosion element can be a thickened patterned solder mask without covering the core layer of the substrate. 4b single open to Β · 5 · ^ - early 兀 sticky day, and the thickness of the stiffener is greater than the lower solder mask. In the method of forming a viscous layer in the semiconductor packaging process described above, may additionally include - a chess baking step to partially cure the die-bonding material into a uniform thickness layer on the core layer of the substrate.

在前述的半導體封裝製程中形成黏晶層之方法中， 該晶片載體係可為一基板條，且在每一單元黏晶區内開 α至J 一打線槽孔，並在印刷時該非平板印刷模板係完 全封閉該些打線槽孔。 【實施方式】 依據本發明之一具體實施例，揭示一種半導體封裝 製程中形成黏晶層之方法。第2Α至2Ε圖係有關於該 半導體封裝製程中形成黏晶層之方法。首先，請參閱第 2Α及3圖所示’提供一晶片載體21〇，該晶片載體21〇 係包含一基板核心層2 11與一加勁件2丨2，該基板核心 層211之一上表面213包含有複數個單元黏晶區215以 及一圍繞該些單元黏晶區215之周邊區216。請再參閱 第3圖所示，其中該加勁件2丨2係局部形成於該基板核 心層211之該上表面213’以覆蓋該周邊區216，但顯 露该些單元黏晶區2 1 5，用以增加該晶片載體2 1 〇之強 度’並避免該晶片載體210翹曲’以利後續之半導體封 裝製程。在本實施例中’該晶片載體2丨〇係可為一印刷 電路板並具有一下防焊層217，該下防焊層217係大致 9 200926314 覆蓋該基板核心層211之一下表面214,該下防特 之覆蓋面積係大於該加勁件212之覆蓋面積。在 例中’如第3圖所示’該加勁件2 12係可為環形 加勁件21 2係可為一加厚型圖案化防焊層，而不 基板核心層2 1 1之該些單元黏晶區2 1 5並且該 212之厚度係大於該下防浑層217之厚度。再如 所示’在本實施例中’該晶片載體2丨〇係可為 條，且在每一單元黏晶區2 1 5内開設至少一打 ❹ 218 〇 接著，請參閱第2B圖及4所示，提供一非平 模板2 2 0 ’該非平板印刷模板2 2 〇係具有—非平 面221，其中該非平坦壓貼面221之周邊222係 減少，用以補償該加勁件2 1 2之厚度，該非平板 板220更具有複數個印刷開孔223 »該些印刷探 係對準於該基板核心層2丨丨之該些單元黏晶區： ❹ 之後，請參閱第2C圖所示，壓附該非平板印 220至該晶片載體210 ’以使該些印刷開孔223 基板核心層2 1 1之該些單元黏晶區2丨5，並且該 印刷模板220係為無塌陷地貼觸至該基板核心為 該加勁件212。再如第2C圖所示，該非平板印 2 2 0係完全封閉該基板核心層2 1 1之該些打線槽 最後，请參閱第2D及3圖所示，通過該非平 模板220之該些印刷開孔223，印刷一黏晶材料 該基板核心層2 1 1之該些單元黏晶區2丨5。在模 層21 7 本實施 框。該 覆蓋該 加勁件 第3圖 一基板 線槽孔 板印刷 坦壓貼 為厚度 印刷模 孔22 3 :15 〇 刷模板 顯露該 非平板 21 1與 刷模板 孔 218〇 板印刷 230至 板印刷 10 200926314 (stencil printing)過程中，該黏晶材料230係以一 240刮過並填充在該非平板印刷模板220之該些印 孔2 2 3中’以印刷形成在該基板核心層2 11上，該 板印刷模板220係可控制該黏晶材料230之形成月 由於該黏晶材料23 0係直接形成於該基板核心層 上’故具有加強黏晶強度之功效。較佳地，該黏晶 23 0係可選用液態膠體或膠稠態膠體，如液態環氧 或是膠稠態B階黏膠，以降低製造成本。在本實 中，請參閱第2D與3圖所示，由於該非平板印刷 220係完全封閉該些打線槽孔2丨8，故在印刷時可 該黏晶材料2 3 0流入該些打線槽孔2 1 8，而影響後 裝製程。 具體而言’請參閱第2E圖所示，該半導體封裝 中形成黏晶層之方法中係可另包含一預烘烤步驟， 該黏晶材料230部分固化為一在該基板核心層21 i 均厚黏晶層。較佳地，該黏晶材料23〇係可為在室 成為不具有流動性與黏性之B ，但在加熱後 具有黏接晶片之黏性。 因此， 式使該黏 加強黏晶強度，又可 由上述可知該方法不僅可以利用模板印 I材料230直接塗佈於該基板核心層21 以抑制該晶片載體 2 1 0之翹曲 免該黏晶材料23 0之溢流 半導體封裝使用。 不但可以低成本製造亦 刮刀 刷開 非平 .度。 211 材料 樹脂 施例 模板 避免 續封 製程 以使 上之 溫下 仍然 刷方 .，以 並避 可供 第5A至5E圖繪示 則述方法運用於半導體封裝製 200926314 程。請參閱第5A圖所示，將複數個具有銲墊311之晶 片3 1 0设置於s玄晶片載體2 1 0上，利用適當加熱後會具 有黏性之該黏晶材料230將該些晶片3 10分別黏貼至該 基板核心層2 1 1之該些單元黏晶區2丨5。該些晶片3工〇 係以其形成有該些銲墊3 1 1之主動面朝向該晶片載體 210的方式设置於該晶片載體21〇上，並且每一晶片31〇 之該些録塾311係分別對準於每一單元黏晶區215之該 ⑩打線槽孔218内。接著，請參閱第5B圖所示，形成複 數個打線形成之銲線3 2 0 ’以達到該些晶片3 1 〇與該晶 片載體2 1 0之間之電性連接。在本實施例中，該些銲線 320係通過每一單元黏晶區2丨5之該打線槽孔2丨8以連 接s亥晶月3 1 0之該些銲墊3 1 1至該基板核心層2丨丨之對 應接指。 接著’請參閱第5C圖所示’形成一封膠體33〇於該 基板核心層211之該上表面213與該下表面214之局部 ❹區域，以密封該些晶片3 1 0以及該些銲線3 2〇。在封膠 後’凊參閱第5D圖所示，將複數個銲球34〇設置於該 基板核心層211之該下表面214，以供對外接合至一印 刷電路板（圖中未繪出）》最後，請參閱第5E圖所示， 利用一切割刀具350切穿該封膠體33〇與該晶片載體 210,便可獲得複數個半導體封裝構造。再如第5E圖所 示，在切割時，該加勁件212會一同被切除，故並不會 改變最終之半導體封裝結構。 因此’本發明之形成黏晶層之方法不僅可選用低材 12 200926314 料成本與可低成本印刷方法形成之液態膠體或膠稠態 膠艘作為黏晶材料2 3 0，；重田*tv决L a & ^ JU運用於黏晶強化之晶片載體來 降低製造成本與提高產品可靠度，亦可抑制該晶片載體 210之麵曲以避免因勉曲所造成之傳輸與基板定位問 題，以利於後續+導體封褒製程，同時提高半導體封裝 構造之產能與穩定性。此外，另可避免該黏晶材料0 之溢",L，使所製成之半導體封裝構造在該些銲線3 Μ接 • a的。卩位不會有不良溢膠，以確保品質之可靠度。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭不的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 谷依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 φ 範圍内。 【圖式簡單說明】 第1圖：習知半導體封裝之截面示意圖。 第2Α至2Ε圖：依據本發明之一具體實施例，繪示一 種半導體封裝製程中形成黏晶層之方法中一晶片 載體之截面示意圖。 第圖·依據本發明之一具體實施例，在該方法中所使 用之晶片載體之上表面示意圖。 第4圖·依據本發明之—具體實施例，在該方法中所使 13 200926314 用之非平面鋼板之非平面壓貼面示意圏。 第5A至5E圖：依據本發明之一具體實施例，該方法運 用之半導體封裝製程之該晶片載體之戴面示意 圖。 【主要元件符號說明】In the method for forming a die bond layer in the foregoing semiconductor package process, the wafer carrier may be a substrate strip, and a to-line slot is opened in each of the unit die-bonding regions, and the non-lithographic printing is performed during printing. The template system completely closes the wire slot holes. [Embodiment] According to one embodiment of the present invention, a method of forming a die bond layer in a semiconductor package process is disclosed. The second to second drawings are directed to a method of forming a die layer in the semiconductor packaging process. First, please refer to FIGS. 2 and 3 to provide a wafer carrier 21, which includes a substrate core layer 2 11 and a stiffener 2丨2, and an upper surface 213 of the substrate core layer 211. A plurality of unit die-bonding regions 215 and a peripheral region 216 surrounding the unit die-bonding regions 215 are included. Referring to FIG. 3 again, the stiffener 2 丨 2 is partially formed on the upper surface 213 ′ of the substrate core layer 211 to cover the peripheral region 216 , but the cell bonding regions 2 1 5 are exposed. It is used to increase the strength of the wafer carrier 2 并 and to prevent the wafer carrier 210 from warping for the subsequent semiconductor packaging process. In the present embodiment, the wafer carrier 2 can be a printed circuit board and has a lower solder resist layer 217. The lower solder resist layer 217 is substantially 9 200926314 covering a lower surface 214 of the substrate core layer 211. The coverage area of the anti-feature is greater than the coverage area of the stiffener 212. In the example, as shown in FIG. 3, the stiffener 2 12 can be a ring stiffener 21 2 can be a thickened patterned solder mask, and the cell core layer 2 1 1 is not sticky. The crystal region 2 15 and the thickness of the 212 is greater than the thickness of the lower anti-mite layer 217. Further, as shown in the 'in this embodiment, the wafer carrier 2 can be a strip, and at least one dozen 218 is opened in each of the unit die-bonding regions 2 15 . Next, please refer to FIG. 2B and FIG. As shown, a non-flat template 2 2 0 ' is provided. The non-lithographic template 2 2 has a non-planar surface 221, wherein the perimeter 222 of the non-flat pressing surface 221 is reduced to compensate for the thickness of the stiffener 2 1 2 The non-plate plate 220 further has a plurality of printing openings 223. The printing probes are aligned with the unit die-bonding regions of the substrate core layer 2: ❹ After that, refer to FIG. 2C for embossing. The non-lithographic printing 220 is applied to the wafer carrier 210' such that the plurality of unit die-bonding regions 221 of the substrate core layer 2 1 1 are printed, and the printing template 220 is attached to the substrate without collapse. The core is the stiffener 212. As shown in FIG. 2C, the non-lithographic printing 2 2 0 completely seals the wire grooves of the substrate core layer 21 1 . Finally, please refer to the printing of the non-flat template 220 as shown in FIGS. 2D and 3 . Opening 223, printing a die-bonding material of the substrate core layer 2 1 1 of the unit die-bonding region 2丨5. In the mold layer 21 7 this implementation box. The cover is covered by the stiffener. FIG. 3 is a substrate line slot plate printing press paste for thickness printing die hole 22 3 : 15 〇 brush template reveals the non-plate 21 1 and the brush template hole 218 〇 plate printing 230 to plate printing 10 200926314 ( During the stencil printing process, the die-bonding material 230 is scraped and filled in the plurality of printing holes 2 2 3 of the non-lithographic printing template 220 to be formed on the substrate core layer 2 11 by printing. The template 220 can control the formation of the die-bonding material 230. Since the die-bonding material 230 is directly formed on the core layer of the substrate, it has the effect of enhancing the strength of the die bond. Preferably, the die bond 30 0 is selected from a liquid colloid or a gel-like colloid, such as a liquid epoxy or a gel-like B-stage adhesive, to reduce manufacturing costs. In the present embodiment, as shown in FIGS. 2D and 3, since the non-lithographic printing 220 completely closes the wire slot holes 2丨8, the die bonding material 2300 flows into the wire slot holes during printing. 2 1 8, and affect the post-installation process. Specifically, as shown in FIG. 2E, the method for forming a die layer in the semiconductor package may further include a prebaking step, and the die bonding material 230 is partially cured to be in the substrate core layer 21 i. Thick sticky layer. Preferably, the viscous material 23 can be B which does not have fluidity and viscosity in the chamber, but has the viscosity of the bonded wafer after heating. Therefore, the adhesive strength of the adhesive can be strengthened. From the above, the method can be applied to the substrate core layer 21 directly by using the template printing material 230 to suppress the warpage of the wafer carrier 210. 23 0 overflow semiconductor package used. Not only can it be manufactured at low cost, but also the blade can be opened. 211 Material Resin Application Template Avoid the suffocation process so that the temperature is still brushed at the upper temperature. To avoid the availability, the method described in Figure 5A to Figure 5E is applied to the semiconductor packaging system. Referring to FIG. 5A, a plurality of wafers 310 having pads 311 are disposed on the s-wafer carrier 210, and the wafers 3 are viscous by appropriate heating. 10 are respectively adhered to the unit die-bonding regions 2丨5 of the substrate core layer 2 1 1 . The wafers 3 are disposed on the wafer carrier 21 以 in such a manner that the active surfaces of the pads 31 are formed toward the wafer carrier 210, and the wafers 311 are attached to each of the wafers 31. They are respectively aligned in the 10 wire slot 218 of each unit die bond region 215. Next, as shown in Fig. 5B, a plurality of wire bonding wires 3 2 0 ' are formed to achieve electrical connection between the wafers 3 1 〇 and the wafer carrier 210 . In this embodiment, the bonding wires 320 pass through the wire slot 2 丨 8 of each unit die bonding region 2 丨 5 to connect the pads 3 1 1 of the singapore moon 3 to the substrate. Corresponding fingers of the core layer 2丨丨. Then, please refer to FIG. 5C to form a colloid 33 on the upper surface 213 of the substrate core layer 211 and a partial germanium region of the lower surface 214 to seal the wafers 310 and the bonding wires. 3 2〇. After the encapsulation, a plurality of solder balls 34 are disposed on the lower surface 214 of the substrate core layer 211 for external bonding to a printed circuit board (not shown). Finally, referring to FIG. 5E, a plurality of semiconductor package structures can be obtained by cutting through the encapsulant 33 and the wafer carrier 210 by a cutting tool 350. Further, as shown in Fig. 5E, the stiffener 212 is cut together during cutting, so that the final semiconductor package structure is not changed. Therefore, the method for forming a viscous layer of the present invention can be used not only as a low-temperature material, but also as a viscous material in the form of a liquid colloid or a gel-like colloidal material formed by a low-cost printing method; a & ^ JU is applied to the die-hardened wafer carrier to reduce manufacturing cost and improve product reliability, and also suppress the surface curvature of the wafer carrier 210 to avoid transmission and substrate positioning problems caused by distortion, so as to facilitate subsequent + Conductor sealing process, while improving the productivity and stability of semiconductor package construction. In addition, the adhesion of the die-bonding material 0 can be avoided, and the fabricated semiconductor package structure is connected to the bonding wires 3 . There will be no bad glue in the position to ensure the reliability of the quality. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the above-mentioned technical content, but the present invention does not deviate from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications made are still within the scope of φ of the technical solution of the present invention. [Simple description of the drawing] Fig. 1: Schematic diagram of a conventional semiconductor package. 2A to 2D are schematic cross-sectional views showing a wafer carrier in a method of forming a die bond layer in a semiconductor package process in accordance with an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS A top view of a wafer carrier used in the method in accordance with an embodiment of the present invention. Figure 4 - In accordance with a specific embodiment of the present invention, the non-planar pressure veneer of the non-planar steel sheet used in the method of 2009 200914 is shown. 5A through 5E are schematic views of the wafer carrier of the semiconductor package process in accordance with an embodiment of the present invention. [Main component symbol description]

100 半導體封裝構造 110 基板 111 基板核心層 112 下 防焊層 113 上表面 114 下表 面 115 打 線槽孔 116 接指 117 球墊 120 晶片 121 銲墊 130 點 晶膠帶 140 銲線 150 封膠 體 160 銲球 210 晶片載體 211 基板核心層 212 加 勁件 213 上表面 214 下表 面 215 留 早 凡*黏晶 216 周邊區 217 下防 焊層 218 打線槽孔 220 非平板印刷模板 221 非平坦壓貼面 222 周邊 223 印刷開孔 230 黏晶 材料 240 刮 刀 310 晶片 311 銲墊 320 銲線 330 封膠 體 340 銲球 350 切割 刀具 14100 Semiconductor package structure 110 substrate 111 substrate core layer 112 lower solder mask 113 upper surface 114 lower surface 115 wire slot 116 finger 117 ball pad 120 wafer 121 pad 130 crystal tape 140 wire 150 capping body 160 solder ball 210 Wafer carrier 211 substrate core layer 212 stiffener 213 upper surface 214 lower surface 215 left early * sticky crystal 216 peripheral region 217 under solder mask 218 wire slot 220 non-lithographic template 221 non-flat pressure surface 222 perimeter 223 printing Hole 230 Bonding material 240 Scraper 310 Wafer 311 Pad 320 Bonding wire 330 Sealing body 340 Solder ball 350 Cutting tool 14

Claims (1)

200926314 十、申請專利範圍： 1、 一種半導體封裝製程中形成黏晶層之方法，包含： 提供晶片載體，係包含一基板核心層與一加勁件，該 基板核心層之一上表面包含有複數個單元黏晶區以及 圍繞該些單元黏晶區之周邊區，其中該加勁件係局 部形成於該基板核心層之該上表面’以覆蓋該周邊 區’但顯露該些單元黏晶區； 〇 提供一非平板印刷模板，係具有一非平坦壓貼面，其中 該非平坦壓貼面之周邊係為厚度減少，用以補償該加 勁件之厚度，該非平板印刷模板更具有複數個印刷開 孔； 壓附該非平板印刷模板至該晶片載體，以使該些印刷開 孔顯露該基板核心層之該些單元黏晶區，並且該非平 板印刷模板係為無塌陷地貼觸至該基板核心層與該加 勁件；以及 . 通過該非平板印刷模板之該些印刷開孔，印刷一黏晶材 料至該基板核心層之該些單元黏晶區。 2、 如申請專利範圍第〗項所述之半導體封裝製程中形成 黏晶層之方法’其中該加勁件係為環形框。 3、 如申請專利範圍帛i項所述之半導體封裝製程中形成 黏SB層之方法，其中該晶片載體係為一印刷電路板並 具有一下防焊層，該下防焊層係大致覆蓋該基板核心 層之一下表面，該下防焊層之覆蓋面積係大於該加勁 件之覆蓋面積》 15 200926314 4、 如申請專利範圍第3項所述之半導體封裝製程中形成 黏晶層之方法’其中該加勁件係為一加厚型圖案化防 焊層，而不覆蓋該基板核心層之該些單元黏晶區並且 該加勁件之厚度係大於該下防焊層。 5、 如申請專利範圍第i項所述之半導體封裝製程中形成 黏晶層之方法，另包含-預烘烤步驟，以使該黏晶材 料。卩刀固化為一在該基板核心層上之均厚黏晶層。 © 6、如中請專利範圍第1項所述之半導體封裝製程中形成 $晶層之方法，其中該晶片載體係為一基板條，且在 每—單元黏晶區内開設至少—打線槽孔，並在印刷時 s亥非平板印刷模板係完全封閉該些打線槽孔。 囈 16200926314 X. Patent Application Range: 1. A method for forming a bonding layer in a semiconductor packaging process, comprising: providing a wafer carrier, comprising a substrate core layer and a stiffening member, wherein an upper surface of one of the substrate core layers comprises a plurality of a unit die-bonding region and a peripheral region surrounding the unit die-bonding regions, wherein the stiffening member is partially formed on the upper surface of the substrate core layer to cover the peripheral region but reveals the unit die-bonding regions; A non-lithographic printing template has a non-flat pressing surface, wherein the periphery of the non-flat pressing surface is reduced in thickness to compensate the thickness of the stiffening member, and the non-lithographic printing template has a plurality of printing openings; Attaching the non-lithographic template to the wafer carrier such that the printing openings expose the unit die-bonding regions of the substrate core layer, and the non-lithographic template is attached to the substrate core layer without collapsing and the stiffening And printing the die-bonding material to the plurality of substrates of the substrate through the printing openings of the non-lithographic template Meta-bonded crystal region. 2. A method of forming a viscous layer in a semiconductor packaging process as described in claim </ RTI> wherein the stiffener is a ring frame. 3. A method of forming a viscous SB layer in a semiconductor packaging process as described in the scope of the patent application, wherein the wafer carrier is a printed circuit board and has a lower solder resist layer, the lower solder resist layer substantially covering the substrate a lower surface of the core layer, the coverage area of the lower solder resist layer is larger than the coverage area of the stiffener. 15 200926314 4. A method for forming a die bond layer in a semiconductor package process as described in claim 3 of the patent application The stiffener is a thickened patterned solder mask without covering the cell die regions of the substrate core layer and the stiffener has a thickness greater than the lower solder mask. 5. A method of forming a die bond layer in a semiconductor package process as described in claim i, further comprising a pre-baking step to cause the die bond material. The file is cured into a uniform thickness layer on the core layer of the substrate. 6. The method of forming a crystal layer in a semiconductor packaging process as described in claim 1, wherein the wafer carrier is a substrate strip, and at least a wire slot is formed in each of the unit die bonding regions. And at the time of printing, the non-lithographic stencil template completely closes the wire slot holes.呓 16
TW096147095A 2007-12-10 2007-12-10 Method for forming a die attach layer during semic TWI353642B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW096147095A TWI353642B (en) 2007-12-10 2007-12-10 Method for forming a die attach layer during semic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096147095A TWI353642B (en) 2007-12-10 2007-12-10 Method for forming a die attach layer during semic

Publications (2)

Publication Number Publication Date
TW200926314A true TW200926314A (en) 2009-06-16
TWI353642B TWI353642B (en) 2011-12-01

Family

ID=44729666

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096147095A TWI353642B (en) 2007-12-10 2007-12-10 Method for forming a die attach layer during semic

Country Status (1)

Country Link
TW (1) TWI353642B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI706526B (en) * 2015-09-25 2020-10-01 美商英特爾股份有限公司 Combination of semiconductor die with another die by hybrid bonding
TWI735525B (en) * 2016-01-31 2021-08-11 美商天工方案公司 Sputtering systems and methods for packaging applications

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI706526B (en) * 2015-09-25 2020-10-01 美商英特爾股份有限公司 Combination of semiconductor die with another die by hybrid bonding
TWI735525B (en) * 2016-01-31 2021-08-11 美商天工方案公司 Sputtering systems and methods for packaging applications

Also Published As

Publication number Publication date
TWI353642B (en) 2011-12-01

Similar Documents

Publication Publication Date Title
TWI555100B (en) Chip scale package and fabrication method thereof
TWI508245B (en) Package of embedded chip and manufacturing method thereof
TWI311352B (en) Fabricating process of leadframe-based bga packages and leadless leadframe utilized in the process
TW201212189A (en) Chip scale package structure and fabrication method thereof
TWI236110B (en) Flip chip on leadframe package and method for manufacturing the same
TW200409252A (en) Packaging process for improving effective die-bonding area
TWI244145B (en) Method for fabricating semiconductor package
TWI471952B (en) Method of forming chip scale package
TW200926314A (en) Method for forming a die attach layer during semiconductor packaging processes
TWI353664B (en) Back-to-back stacked multi-chip package and method
TWI291751B (en) Semiconductor package for prevent contamination of bonding pads of chip by chip-attach material and the substrate utilized
TW200908280A (en) Multi-chip stacked device with a composite spacer layer
TW200828458A (en) Semiconductor package and fabrication method thereof and stack structure
TWI275167B (en) Package structure and manufacturing method thereof
TWI250597B (en) Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips
TWI382506B (en) Method and structure of multi-chip stack having central pads with upward active surfaces
TW200532873A (en) Process for packaging and stacking multiple chips with the same size
TWI440146B (en) Semiconductor package having internal heatsink prevented from contamination of mold flash
CN100428454C (en) Tape lower chip packaging structure and its producing method
TWI362727B (en) Window bga package and method for fabricating the same
TW567564B (en) Semiconductor package having a die carrier to prevent delamination and method for fabricating the package
TW200839983A (en) Semiconductor package with wire-bonding connections
JP4473668B2 (en) Semiconductor device and manufacturing method thereof
TW579584B (en) Fabrication method of window-type ball grid array semiconductor package
TWI326907B (en) Ball grid array package for preventing mold flash

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees