TW567564B - Semiconductor package having a die carrier to prevent delamination and method for fabricating the package - Google Patents

Abstract

A semiconductor package having a die carrier to prevent the die delamination, and a method for fabricating this semiconductor package, are provided. The package includes a die carrier with a die attach area and a die mounted on the die attach area. The die attach area can be coated with an epoxy dam having a controlled height and shape, wherein the epoxy dam can effectively prevent the propagation of die delamination and improve adhesion between the die and the die carrier. In addition, this low cost package fabricating method can be operated easily, and avoid the product yield problems during the fabrication process.

Description

567564 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a semiconductor package, especially a semiconductor package for a wafer carrier with a delaminated wafer, and / or prevents [Background of the Invention] ... decay. In the general semiconductor device packaging process, due to Attach, Molding, Air Air Ί wnr $ 17α 夕 ί (M〇U Cure) and other steps: The guilty degree test after the sealing is completed # and the edge components are subjected to a rapid high and low temperature cycle change, which often results in semiconductor packages that are separated into small hoppers and recognized as fine materials. For example, as shown in FIG. 8, a semiconductor package using a lead frame (Lead Frameu μ 2 t ^ contact u Zong Cong Gan Shi Yue u 〇aa trame) as a wafer carrier is shown in FIG. 8. The thermal expansion coefficients of materials such as the die pad 31 and silver paste 33 (Silver Paste) are different (wafer is about 6ppm, wafer pad is about 16Ppm, silver glue is about 30ppi ^ 40ppm), it is easy to In the process or test, the phenomenon of cracking and peeling of the material joints, which leads to a reduction in the guilt of the product, such as = the wafer 34 and the wafer holder 31. When the thermal stress between deformation is greater than the adhesive force of the silver glue 33, then the wafer 34 and the silver glue 33, or the wafer holder 31 and the silver Between glue 33, there is often a phenomenon of delamination (Del ami nation). In addition, with the development of computer-based electronic components toward high speed and multifunctionality, the size of the chip in the component must be increased to increase the capacity, and the amount of silver glue applied on it will increase. As a result, greater thermal stress is generated between the wafer, the silver glue, and the wafer holder, and the problems of delamination and reduced reliability faced by the formed semiconductor package have become increasingly serious.

567564 V. Description of the invention (2) US Patent No. 6,3 0 3, 9 8 5 proposes a semiconductor coating member that can prevent delamination 'as shown in Figure 9', which is stamping method or In the chemical and engraving method, a metal sheet is made into a lead frame as shown in the figure. The wafer holder 41 on the wire holder is respectively made with a wrinkled portion 4 8 at both ends, and the wafer holder 4 can be added. The contact area between 1 and the silver glue 4 3, and the thermal stress caused by the different thermal expansion coefficient of the material by the crease portion 48 and the collection and release to avoid the delamination between the wafer holder 41 and the wafer 44; ^ [Although the method has resolved the problem caused by thermal stress, the process of manufacturing the wrinkled portion 48 consumes extremely low costs. The wafer is made of an adhesive such as silver glue. Therefore, the problem of the layer as described above will also occur; for the aforementioned case. However, the package of the chip carrier that it proposed to modify, because there is no way to apply it to the limits of the technical implementation. 3Conductor seal "The product which is costly charged in the manufacturing process by the packager and the packager is indeed the semiconductor package outside the leadframe package, because it is adhered to the substrate (Substrate). The delamination method shown in the US Patent No. 6,303,985, shown in Figure 9 due to the different thermal expansion coefficients of materials, is only applicable to the use of lead frames and cannot be used to process the substrate in the same way. Ball grid array On the package, this is also an important issue for the technology, so how to design a method to prevent delamination so that it can be applied to different packages, minimized, and simplify the manufacturing process. [Summary of the Invention] Therefore, it is an object of the present invention to provide a semiconductor package with a delaminated wafer carrier and a method for preventing and manufacturing the wafer.

16958.ptd Page 6 567564 V. Description of the invention (3) Another semiconductor package of the present invention A reprint of the present invention 'simultaneous operation of the wafer carrier which achieves the aforementioned and delamination' is a wafer with a carrier on its surface In the receiving area, the wafer of the delaminated expansion carrier of the carrier is connected to the wafer carrier chip and the wafer carrier. A half object of the present invention is to provide a method and a manufacturing method thereof. One purpose is to provide an easy semiconductor package. For other purposes, the semiconductor package of the present invention has a wafer receiving area; a wafer; at the same time, it can prevent the wafer from delaminating and spreading. The chip carriers are part of a package. When there is at least one piece of cloth on the sheet, the adhesive is smaller than the carrier member, so that the gel is encapsulated by the encapsulant agent and the majority of the resisting areas on the crystal area are dispersed, and the conductive conductor cover is connected to the barrier. Adhesion agent and the barrier; soldering the wafer to cover the mounting area of the viscous conductive component of the spacer; more coatings to be made and one less reduction method for the wafer. Provided with the 'system includes: a chip is placed on the wafer to support the wafer, the wafer is electrically connected to cover at least one' in the preventable adhesive; the component; the method of packaging the wafer bearing the barrier filling the thickness of the cloth Several conductive wafer carriers, wafers and a colloid. It includes a carrier; the part hardens the barrier to prevent the component from being carried on the carrier and the electric carrier is low-packaged to prevent the wafer from carrying the wafer of the wafer carrier and the wafer to the wafer and then the wafer is covered with the wafer. The following steps: After the wafer receiving area, between the wafer holders, it is coated with the wafer to fully adhere the wafer and the wafer is sexually connected; and during the high-temperature packaging process or reliability test of the shape and conductive elements, the wafer is carried The thermal expansion coefficient of materials

16958.ptd

567564 V. Description of the invention (4) Different layers generate thermal stress, and delamination starts from the four corners where the thermal stress is greatest. This delamination phenomenon will extend inward from the four corners with its thermal stress. At this time, the barrier will be able to Moderately block the continued diffusion of the delamination, so as to prevent the overall delamination of the wafer; at the same time, the binding force of the barrier and the adhesive coated with epoxy resin is greater than that of the wafer or wafer carrier and the adhesive The binding force, therefore, can also exert its effect of enhancing the adhesion of the wafer. There is no particular limitation on the shape and size of the barrier, and it can be a closed continuous piece or a non-closed discontinuous piece. Generally, if the shape of the barrier piece is designed, the wafer receiving area can be divided into With more sections, the barrier to delamination inward diffusion must be greater, and the effect of preventing delamination will be better. In the manufacturing method of the package, the thickness of the adhesive layer of the adhesive is not less than the coating thickness of the barrier member, so as to prevent the wafer from failing to fully adhere to the wafer carrier when the wafer is placed on the whole; The manufacturing cost of the component is extremely low, the manufacturing method is simple and applicable to any package with a wafer carrier, and at the same time, it can improve the reliability of the product. [Detailed description of the invention] As shown in FIG. 1, the first embodiment of the present invention is a semiconductor package 1 with a lead frame as a wafer carrier. The device includes a wafer holder 1. 1 and the majority of the lead frame 12 of the lead frame, silver adhesive 1 3 and other conventional adhesives are used to adhere to the wafer holder of the lead frame 1 1 the first surface 1 1 a chip 1 4, most of the conductive connection to the chip 1 The gold wire 15 between 4 and the lead pin 12 of the lead frame, and the encapsulation gel 16 covering the chip holder 11, the lead pin 1, 2, the chip 14 and the gold wire 15. Wherein, the first surface 1 1 a of the wafer holder 1 1

16958.ptd Page 8 567564 V. Description of the invention (5) There is a wafer receiving area C1 on which the second surface 14b of the wafer 14 is placed, and at the same time, as shown in FIG. In the wafer receiving area C1, a certain distance d from the sides around the wafer receiving area C1 is formed by using an adhesive epoxy material to form a convex first barrier 17a. The first blocking member 17a has a thickness h (see FIG. 1), and is enclosed by a width w into an octagonal closed area, which is a smaller area corresponding to the wafer receiving area C1. Area of the first surrounding area C 2 to prevent the wafer 14 from coming out of the edge of the wafer receiving area C 1 and causing delamination of the wafer 14 from the wafer holder 1 or cracking of the silver glue 13 Internal diffusion to prevent the delamination or cracking from extending inwardly into the first surrounding area C 2; at the same time, in the first surrounding area C 2 surrounded by the first barrier 17 a, A certain distance d 1 from each side of the surrounding area C 2 is coated with a second barrier member 17 b of the same material. The second barrier member 17b is also enclosed in an octagonal closed area with a thickness h and a width w1, and this area is a second enclosed area C3 corresponding to a smaller area corresponding to the first enclosed area C2. In order to prevent the delamination and cracking phenomenon in the first surrounding area C 2 from spreading to the second surrounding area C 3, dl and wl may be equal to or different from d and w. As shown in Figures 3A and 3B, after the inside of the wafer receiving area C1 is segmented by surrounding the first barrier 17a and the second barrier 17b, the barrier can be blocked from the Delamination phenomena η that begin to occur in the four corners of the wafer receiving area C 1 (with the greatest thermal stress s) and extend inward, prevent delamination or cracks from continuing to spread inward. In addition, the coating of the barrier can be enclosed in other closed shapes, such as the square and circle shown in Figures 4A and 4B; it can also be an unclosed discontinuous piece, as shown in Figures 4C and 4D. The unclosed barrier shape shown.

16958.ptd Page 9 567564 V. Description of the invention (6)-The manufacturing method of the semiconductor package 1 is as shown in Figures ^ to 5 (; as shown in the figure, in Figure 5 A, 'First prepare a wafer Block 丨 丨 is made from most of the guide pins 1. This lead frame is the same as the conventional one, and the chip holder 丨 丨 is connected with a chip receiving area C1. Then in Figure 5B, the chip In the wafer receiving area C1 on the first surface 11a of the seat n, an adhesive epoxy resin material is coated on the glue dispensing tip, and the shape and size of the coating are shown in FIG. 2 This is the barrier member 17 for preventing delamination and inward diffusion on the semiconductor package 丨. As shown in FIG. 5C, after the barrier member i 7 is hardened, it is coated on the first surface 1 1 aJl of the wafer holder 11. An adhesive composed of silver glue 13. The silver glue 13 is coated in the wafer receiving area C1, and the coating thickness should be at least the same as the thickness h of the edge barrier 17 to avoid the wafer i. 4 cannot be fully adhered to the wafer holder 1 when placed on the top. Figure 5D shows that a wafer 14 is placed on the-纟 face la of the wafer holder 11 to make the second of the crystal # 14 The surface 14b is adhered to the wafer holder by the silver glue 13. The 5E and 5F diagrams are the conventional steps of curing and wire bonding, respectively, at 15 0 C. After high-temperature baking, the chip is electrically connected with gold wire 5 and its corresponding guide pins 12 2 ^ ^ Finally, as shown in Figure 5G, the semi-finished product that has completed the wire bonding operation is placed in the mold 18 The encapsulation resin covers the wafer 14, the wafer holder u, and the gold wire 15 to form an encapsulation gel 16, and each of the guide pins 12 and 2 series parts are exposed from the encapsulation gel 16. It is connected to an external device (not shown) of the printed circuit board, and the chip 14 is electrically connected to the outside. This is a conventional step of molding (Mo 1 di ng). After the packaging gel 6 is formed, Then the conventional baking curing, trimming, marking and

16958.ptd Page 10 567564

This leads to the use of a lead frame as a wafer. 5. Description of the invention (7) After the steps of forming and other steps, the semiconductor package 1 of the carrier. As shown in FIG. 6, the second embodiment of the present invention is a semiconductor package 2 of a ball grid array (BGA) package. The device includes a conventional adhesive such as base% j, silver glue 23 and the like. On the first surface "a", a wafer 24 is used, and most of the gold wires conductively connecting the substrate 20 and the wafer 24 cover the substrate 20, the wafer 24, and the packaging gel 26 of the gold wire 25, And most of the solder balls 29 implanted on the second surface 20 b of the substrate 20. Among them, a second surface 24b of the wafer 24 is connected to the first surface 20 a of the substrate 20 The wafer receiving area D1 placed thereon, and as shown in FIG. 7, the wafer receiving area D 1 is located at a distance d ′ from the sides of the wafer receiving area D 1 at a certain distance. An adhesive epoxy material is applied to form a raised first barrier 27a, the first barrier 27a has a thickness of h '(see Fig. 6), and is surrounded by a width w' An octagonal closed area is set, which is a first surrounding area D2 'corresponding to a smaller area corresponding to the wafer receiving area D1 to prevent the wafer from being generated from the wafer receiving area. The edge of the area D1 causes the wafer 24 and the substrate 20 to be delaminated or the cracks generated by the silver glue 23 to diffuse inward to prevent the delamination or cracking from extending inward to the first enclosure. In the area D2, at the same time, in the first surrounding area D2 surrounded by the first blocking member 27a, a certain distance d1 from the sides of the surrounding area D2 is coated in the same way. The second barrier 27b of material is also enclosed in an octagonal closed area with a thickness h 'and a width wl', and this area corresponds to the first surrounding area D 2 A smaller area of the second surrounding area D3 to prevent the second surrounding area D2

16958.ptd Page 11 567564 V. Description of the invention (8) Delamination and cracking spread to the second surrounding area D 3, where d ', w' may be equal to or not equal to d 1 ', w 1 '. In addition, the shape of the barrier is not limited to the aforementioned octagon, and the shapes of the closed and non-closed barriers shown in FIGS. 4A to 4D can also be applied in this embodiment. The manufacturing method of the ball grid array semiconductor package 2 of the second embodiment of the present invention is the same as that of the first embodiment, and a barrier member 27 is coated on the substrate 20 of this example to prevent the delamination from spreading inward. This example can be completed by referring to the aforementioned first embodiment process and the conventional ball grid array semiconductor package process, so it will not be described in detail herein. In summary, the semiconductor package of the present invention does have the effect of moderately controlling the delamination diffusion, and can strengthen the adhesion between the wafer and the wafer carrier; meanwhile, the manufacturing method of the package is also very simple and can reduce the manufacturing cost To a minimum, and can be applied to any semiconductor package with a wafer carrier. In addition, in addition to the octagonal, square, and circular closed shapes shown in the figure, the barrier can also be other closed enclosure shapes, and is not limited to a continuous piece of closed shape, but also a separate phase between each part. The discontinuities are separated by an appropriate distance, and the number of layers of the barriers is not limited. Any shape that can segment the wafer receiving area and produce the effect of preventing the inward diffusion of the delamination layer can be used as the design of the barrier of the present invention. At the same time, the wafer can be connected without considering the material and manufacturing costs. The area is divided into more sections, and the more complicated barrier design has better effect of preventing delamination and diffusion. The wafer holder or substrate of the present invention can be used to attach more than two wafers, and only needs to be coated on the wafer receiving area according to the shape and size of the design before coating silver glue to adhere the plurality of wafers. The barrier is sufficient.

16958.ptd Page 12 567564 V. Description of the invention (9) However, the above are only specific examples of this creation, and are not intended to limit the scope of this creation. For those who are familiar with this skill, they will be disclosed in this creation. All equivalent changes or modifications made under the spirit and principle of the invention shall still be covered by the scope of patents mentioned later.

16958.ptd Page 13 567564 Brief description of the drawings [Simplified description of the drawings] Fig. 1 is a sectional view of the first embodiment of the semiconductor package of the present invention, and Fig. 2 is a wafer holder of the semiconductor package shown in Fig. 1 Top view; Figure 3A is a schematic cross-sectional view of the semiconductor package shown in Figure 1 to prevent the delamination phenomenon from spreading; Figure 3B is the stress distribution of the wafer holder of the semiconductor package shown in Figure 1 is not intended, 4A to 4D are top views of other barrier member embodiments of the semiconductor package of the present invention, and FIGS. 5A to 5G are manufacturing flowcharts of the semiconductor package shown in FIG. 1 and FIG. 6 is a semiconductor of the present invention. Sectional view of the second embodiment of the package; FIG. 7 is a top view of the substrate of the semiconductor package shown in FIG. 6; FIG. 8 is a cross-sectional view of a conventional semiconductor package; and FIG. 9 is a U.S. Patent No. 6,3 Sectional view of the semiconductor package No. 0 3, 9 8 5. [Description of component symbols] 1.2 Semiconductor packages 1 Bu 3 Bu 4 1 Chip holder 11a First surface of the chip holder 12 Guide pins 1 3, 2 3, 3 3, 4 3 Silver glue

16958.ptd Page 14 567564

The drawing briefly explains 14, 2 [3 [44 wafer 14b, 24b second surface of the wafer 15 '25 gold wire 16> 26 encapsulation gel 17, 27 barrier 17a, 27a first barrier 17b, 27b second barrier 18 mold 20 substrate 2 0a substrate first —— * surface 20b substrate second surface 29 solder ball 48 wrinkled portion Cl > D1 wafer receiving area C2, D2 first surrounding area C3, D3 second surrounding area s thermal stress n Delamination phenomenon d, d, the distance between the first barrier member and the periphery of the wafer receiving area cU, άΓ The distance between the second barrier member and the first barrier member w, w. The width of the first barrier member w 1, w 1 ′ The width of the second barrier 16958.ptd Page 15

Claims (1)

567564 Case No. 91123795 > Rev. cP, Y. Year 6, Application Patent Scope 1. A semiconductor package 0 with a wafer carrier preventing wafer delamination, comprising: ^ at least one wafer; f a wafer carrier, which Having a wafer receiving area for the wafer / wafer to be placed on; at least one barrier member 'set in the wafer receiving area of the wafer carrier' so that the barrier member and each edge of the wafer receiving area A peripheral region is formed between the wafer and the wafer carrier to prevent delamination diffusion between the wafer and the peripheral region outside the barrier; an adhesive agent is used to adhere the wafer to the wafer of the wafer carrier. On the contact area, the adhesive is coated and filled in the wafer contact area, and the coating thickness of the adhesive is not less than the thickness of the barrier; most conductive elements are used to electrically connect the chip. And the wafer carrier; and a packaging gel for covering a part of the wafer, the wafer carrier and the conductive element. 2. The semiconductor package of claim 1 in which the wafer carrier is a wafer holder. 3. For example, the semiconductor package of claim 1, wherein the wafer carrier is a substrate. 4. For the semiconductor package of item 1 of the patent application scope, the resistive element can be a continuous element to enclose a closed area. 5. If the semiconductor package of the first scope of the application for a patent, wherein the barrier 16958 石 夕 品 .ptc Page 1 2003.08.28.016 567564 _ Case No. 91123795 Amended on the 9th day of cf month β_ Six, the scope of the patent application can be a discontinuous piece, and the departments are spaced apart by an appropriate distance. . 6. For the semiconductor package of the first scope of the patent application, if the number of the barriers is plural, each of the barriers can be concentrically arranged in the chip receiving area. 7. The semiconductor package of claim 4 in which the enclosed area enclosed by the barrier is one of a square, a circle and an octagon. 8. For the semiconductor package of the first scope of the patent application, the material of the barrier is an adhesive epoxy resin. 9. The semiconductor package of claim 1 in which the adhesive is a silver glue. 10. The semiconductor package according to item 1 of the patent application scope, wherein the conductive element is a gold wire. 1 1. A method for manufacturing a semiconductor package with a wafer carrier for preventing delamination of wafers, comprising the following steps: preparing a wafer carrier having a wafer receiving area; and connecting at least one of the wafer receiving areas A barrier, forming a peripheral region between the barrier and each edge of the wafer receiving area, so as to block delamination diffusion between the wafer and the wafer carrier in the peripheral region outside the barrier; An adhesive is coated on the wafer carrier, so that the adhesive fills the wafer receiving area, and the coating thickness of the adhesive is not less than the thickness of the barrier, so as to fully adhere the wafer to the wafer. Bear 16958 Shi Xipin.ptc Page 2 2003.08. 28.017 567564 _Case No. 91123795 Modified Year / Month / Day Modification_ Six. Apply for a patent on the carrier; solder most conductive components between the wafer and the wafer carrier to Electrically connecting the wafer to the wafer carrier; and forming a packaging gel to cover the wafer, the wafer carrier, and a part of the conductive element. 12. The manufacturing method according to item 11 of the scope of patent application, wherein the wafer carrier is a wafer holder. 13. The manufacturing method according to item 11 of the scope of patent application, wherein the wafer carrier is a substrate. 14. The manufacturing method according to item 11 of the scope of patent application, wherein the barrier member can be a continuous member to surround a closed area. 15. The manufacturing method according to item 11 of the scope of patent application, wherein the barrier member may be a discontinuous member, and the respective parts are spaced apart by an appropriate distance. 16. According to the manufacturing method of item 11 in the scope of patent application, if the number of the blocking members is plural, each of the blocking members can be concentrically arranged in the wafer receiving area. 17. The manufacturing method according to item 14 of the scope of patent application, wherein the enclosed area surrounded by the barrier is one of a square, a circle and an octagon. 18. The manufacturing method according to item 11 of the scope of patent application, wherein the material of the barrier member is an adhesive epoxy resin. 19. The manufacturing method according to item 11 of the scope of patent application, wherein the adhesive is a silver glue. 2 0. The manufacturing method according to item 11 of the scope of patent application, wherein the conductive element is 16958 Shi Xipin · ptc Page 3 2003.08. 28.018 567564 Case No. 91123795 Xiyue Yue Amendment 6. The scope of patent application is gold thread. 1B1 16958 Silicone.ptc Page 4 2003.08.28.019