JP2002270627A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method

Info

Publication number
JP2002270627A
JP2002270627A JP2001069864A JP2001069864A JP2002270627A JP 2002270627 A JP2002270627 A JP 2002270627A JP 2001069864 A JP2001069864 A JP 2001069864A JP 2001069864 A JP2001069864 A JP 2001069864A JP 2002270627 A JP2002270627 A JP 2002270627A
Authority
JP
Japan
Prior art keywords
dam
semiconductor device
liquid resin
resin
dam material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001069864A
Other languages
Japanese (ja)
Inventor
Akio Monma
彰夫 門馬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP2001069864A priority Critical patent/JP2002270627A/en
Publication of JP2002270627A publication Critical patent/JP2002270627A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the planarity of a seal resin surface formed by a potting mold for increasing the number of semiconductor devices which can be obtained from an aggregate substrate. SOLUTION: The method comprises double application of a dam material by a dispenser to form a dam 11 surrounding semiconductor elements 5 mounted on an aggregate substrate 30, dropping liquid resin on regions sectioned by the dam 11 so as to cover the semiconductor element 5 with a dropping quantity which is adjusted so that the height of the liquid resin surface over the central portion of the region, after completing the dropping, is aligned with the arcuate center of an approximately arcuate inner side of the dam 11 top, thereby expanding the area of a flat surface of the liquid resin.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、液状樹脂を用いた樹脂
封止法で形成した半導体装置の製造方法に関し、特に封
止樹脂表面の平坦性を得ることができるものに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device formed by a resin encapsulation method using a liquid resin, and more particularly to a method capable of obtaining a flat surface of an encapsulation resin.

【0002】[0002]

【従来の技術】リードフレームや配線基板上に搭載され
た半導体素子を腐食等から保護するため、従来からトラ
ンスファモールドやポッティングモールドによる樹脂封
止が行われている。前者は金型にて一度に大量のパッケ
ージを形成するもので、リードフレーム上に搭載された
半導体素子の樹脂封止に適している。一方、後者のポッ
ティングモールドは、半導体素子上に液状樹脂を滴下
し、硬化させてパッケージを形作るものであり、大量生
産には適さないが、前述のトランスファモールドのよう
に過度の熱履歴や注入圧を与えない分、素子の特性変化
などの虞がない。また、携帯性の機器などには、いわゆ
るチップサイズパッケージ(CSP)が求められている
ように、パッケージの小型化は今後ますます進む方向に
ある。しかるにそのような小型のパッケージをトランス
ファモールドで形成すると、キャビティの微細化に伴っ
てゲート等の樹脂流路も狭小化するため、かなりの注入
圧力を要する。そのため樹脂の未充填やボイドの混入、
更にはワイヤの破断等種々の問題を引き起こす虞があ
る。その点、ポッティングモールドによれば確実に樹脂
を塗布することができ、しかも素子や配線に余分な応力
を与えずに済むため、物理的な問題が殆どなく、その意
味では極めて小さいパッケージを形成するのに適してい
ると言える。
2. Description of the Related Art In order to protect a semiconductor element mounted on a lead frame or a wiring board from corrosion or the like, resin sealing by transfer molding or potting molding has been conventionally performed. The former forms a large amount of packages at a time in a mold, and is suitable for resin sealing of a semiconductor element mounted on a lead frame. On the other hand, the latter potting mold is a method of forming a package by dropping a liquid resin on a semiconductor element and curing it, and is not suitable for mass production.However, as in the transfer mold described above, excessive heat history and injection pressure Is not given, there is no risk of a change in the characteristics of the element. In addition, as portable devices and the like require a so-called chip size package (CSP), the miniaturization of the package is in the direction of progress in the future. However, when such a small package is formed by transfer molding, a considerable injection pressure is required because a resin flow path such as a gate is narrowed with miniaturization of a cavity. As a result, resin is not filled, voids are mixed,
Further, various problems such as breakage of the wire may be caused. In that respect, the potting mold allows the resin to be applied reliably, and furthermore, it is not necessary to apply extra stress to the element and the wiring, so that there is almost no physical problem, and in that sense, an extremely small package is formed. It can be said that it is suitable for.

【0003】以下に、ポッティングモールドを用いた従
来の半導体装置の製造方法について、図4を用いて説明
する。なお、(a)は半導体装置の製造過程におけるポ
ッティングモールド完了後の状態を示す断面図を、
(b)は(a)の上面図を、(c)は最終的に得られた
半導体装置の斜視図をそれぞれ示している。本図におい
て、1は基板、2aはメタル配線、2bはダイパッド、
2cは電極、3はスルーホール、4はボンディングワイ
ヤ、5は半導体素子、6は封止樹脂、7はレジスト膜、
11はダム、30は集合基板、31は半導体装置を示
す。
A conventional method for manufacturing a semiconductor device using a potting mold will be described below with reference to FIG. (A) is a cross-sectional view showing a state after the completion of the potting mold in the manufacturing process of the semiconductor device.
(B) is a top view of (a), and (c) is a perspective view of the finally obtained semiconductor device. In this figure, 1 is a substrate, 2a is a metal wiring, 2b is a die pad,
2c is an electrode, 3 is a through hole, 4 is a bonding wire, 5 is a semiconductor element, 6 is a sealing resin, 7 is a resist film,
Reference numeral 11 denotes a dam, 30 denotes an aggregate substrate, and 31 denotes a semiconductor device.

【0004】この種の製造方法は、第1に集合基板30
を形成する工程、第2にスルーホール3の開口を被蓋す
る工程、第3に半導体素子5を搭載する工程、第4にダ
ム11を形成する工程、第5に封止樹脂6を形成する工
程があり、最後に単体の半導体素子31に個別化する工
程からなる。
[0004] This type of manufacturing method is based on firstly the collective substrate 30
, Secondly, the step of covering the opening of the through hole 3, thirdly, the step of mounting the semiconductor element 5, fourthly, the step of forming the dam 11, and fifthly, the sealing resin 6 is formed. There is a step, and finally, a step of individualizing the semiconductor element 31 into a single unit.

【0005】第1の集合基板基板30を形成する工程
は、ガラスエポキシ等の絶縁体からなる基板1の表裏に
銅箔のエッチング等でメタル配線2a、ダイパッド2b
及び電極2cを形成し、これらを電気的に接続するスル
ーホール3をメッキ等で形成することが主になる。
[0005] The process of forming the first collective substrate substrate 30 includes the steps of forming metal wiring 2a and die pad 2b on the front and back of the substrate 1 made of an insulator such as glass epoxy by etching a copper foil or the like.
And an electrode 2c, and a through hole 3 for electrically connecting them is mainly formed by plating or the like.

【0006】第2のスルーホール3の開口を被蓋する工
程では、集合基板1の表面全面にドライフィルム状のソ
ルダーレジストをラミネートし、露光・現像してスルー
ホール3の開口を被蓋するようレジスト膜7を選択的に
形成する。
In the step of covering the opening of the second through hole 3, a dry film solder resist is laminated on the entire surface of the collective substrate 1, and is exposed and developed to cover the opening of the through hole 3. A resist film 7 is selectively formed.

【0007】第3の半導体素子5を搭載する工程は、ダ
イパッド2b上への銀ペーストの塗布、チップマウンタ
による半導体素子5のダイボンディング、ワイヤボンダ
ーによる半導体素子5とメタル配線2a間のボンディン
グワイヤ4を介した電気的接続が主に行われる。但し、
半導体素子5をフリップチップとし、フリップチップボ
ンディングによる方法が採用される場合もある。
The steps of mounting the third semiconductor element 5 include applying a silver paste on the die pad 2b, die bonding of the semiconductor element 5 by a chip mounter, and bonding wires 4 between the semiconductor element 5 and the metal wiring 2a by a wire bonder. Electrical connection is mainly performed via the. However,
The semiconductor element 5 may be a flip chip, and a method by flip chip bonding may be adopted.

【0008】第4のダム11を形成する工程では、ディ
スペンサーによるダム材の塗布・硬化が主である。即
ち、シリコン等の樹脂が主な材料であるダム材をシリン
ジに充填し、そのダム材を集合基板30表面の外周に沿
って移動しながら一定の吐出圧で押し出し、所定の温度
で硬化させ、ダム11を形成する。
In the step of forming the fourth dam 11, application and hardening of the dam material using a dispenser is mainly performed. That is, a resin such as silicon is filled into a syringe with a dam material, which is a main material, and the dam material is extruded at a predetermined discharge pressure while moving along the outer periphery of the surface of the collective substrate 30, and is cured at a predetermined temperature. The dam 11 is formed.

【0009】第5の封止樹脂6の形成工程では、液状樹
脂をダム11で囲まれた領域に塗布して硬化させる、い
わゆるポッティングモールドを行う。
In the step of forming the fifth sealing resin 6, a so-called potting mold, in which a liquid resin is applied to a region surrounded by the dam 11 and cured, is performed.

【0010】最後の個別化工程では、図4(b)に示す
ように単位半導体装置形成領域8(未だ分割されていな
い1個の半導体装置)毎に区画するようマトリクス状に
ダイシングラインを決め、そのダイシングラインに沿っ
てブレード等で切断し、図4(c)に示すような個片の
半導体装置31を得る。なお、このようにして得られた
半導体装置31は、側面にサイドスルー10が表出した
LCC(Lead-less Chip Carrier)構造となってい
る。
In the last individualization step, as shown in FIG. 4B, dicing lines are determined in a matrix so as to be divided into unit semiconductor device forming regions 8 (one semiconductor device which has not been divided yet). The semiconductor device 31 is cut along the dicing line with a blade or the like to obtain individual semiconductor devices 31 as shown in FIG. The semiconductor device 31 thus obtained has an LCC (Lead-less Chip Carrier) structure in which the side through 10 is exposed on the side surface.

【0011】[0011]

【発明が解決しようとする課題】しかしながら、上記第
4の工程で形成したダム11で囲まれる領域に第5の工
程でポッティングモールドを行うと、形成された封止樹
脂6はダム11の中心から封止樹脂6が平坦になるまで
長さLsを要する。この長さLsは、樹脂の性質にもよ
るが、一般的に用いられるエポキシ系のもので約7〜1
0mm程度になる。即ち、ダム付近では封止樹脂6の表
面が傾いているため、ダム付近に位置した単位半導体装
置形成領域8から分離して得た半導体装置31は、図4
(c)に示したようにパッケージの厚さが一様でなくな
ってしまう。封止樹脂6表面が平坦な領域だけを使って
半導体装置31を形成すると、取り個数が少なくなりコ
スト高となる上、廃棄する部材が増加するといった問題
にもなる。それに加え、樹脂6はダム11に接する部分
が一番低いため樹脂中に含まれるボイドが、集合基板3
0の中央に凝集しやすく、その部分の半導体装置が不良
になるといった問題もある。
However, when potting molding is performed in the fifth step in a region surrounded by the dam 11 formed in the fourth step, the formed sealing resin 6 is moved from the center of the dam 11. The length Ls is required until the sealing resin 6 becomes flat. Although the length Ls depends on the properties of the resin, it is generally about 7 to 1 in an epoxy type generally used.
It is about 0 mm. That is, since the surface of the sealing resin 6 is inclined near the dam, the semiconductor device 31 obtained by separating from the unit semiconductor device formation region 8 located near the dam is shown in FIG.
As shown in (c), the thickness of the package is not uniform. If the semiconductor device 31 is formed using only the region where the surface of the sealing resin 6 is flat, the number of components to be formed is reduced, the cost is increased, and more members are discarded. In addition, since the resin 6 has the lowest part in contact with the dam 11, voids contained in the resin
There is also a problem that the semiconductor device easily aggregates at the center of the zero and the semiconductor device at that portion becomes defective.

【0012】更に、ダム材と基板との熱膨張差が大きい
ためダム11を硬化する際に集合基板30が反ってしま
うといった問題がある。低弾性の樹脂でダム11を構成
するなどの対策があるが、樹脂硬化時間が5h以上掛か
るなどの問題がある。また、ダム領域を狭くする方法も
あるが半導体装置31の取り個数が減るといった問題に
つながる。
Furthermore, since the difference in thermal expansion between the dam member and the substrate is large, there is a problem that the aggregate substrate 30 is warped when the dam 11 is cured. Although there is a countermeasure such as forming the dam 11 with a low elastic resin, there is a problem that the resin hardening time takes 5 hours or more. Further, there is a method of narrowing the dam region, but this leads to a problem that the number of semiconductor devices 31 to be manufactured is reduced.

【0013】[0013]

【課題を解決するための手段】上記課題を解決するた
め、第一の発明は、集合基板上に搭載された半導体素子
を取り囲むようにディスペンサーにてダム材を塗布して
ダムを形成し、前記半導体素子を被覆するよう前記ダム
で区画される領域に液状樹脂を滴下する半導体装置の製
造方法において、 前記ダム材を二重に塗布し、上層内
側面が断面略円弧となったダムを形成し、前記液状樹脂
を滴下する際に、滴下完了後の前記領域中心部の前記液
状樹脂表面の高さを前記略円弧の略中心と一致させ、前
記液状樹脂表面平坦面の面積を広げるよう滴下量を調整
することを特徴とする。かかる構成により、液状樹脂が
二重となったダムの上層(後から塗布されてできた部
分)の内側面の前記円弧中心付近の高さで接し、その接
した位置では濡れ性の影響が小さくなるため、液状樹脂
表面の変形量が少なくなる。
Means for Solving the Problems To solve the above problems, a first invention is to form a dam by applying a dam material with a dispenser so as to surround a semiconductor element mounted on a collective substrate, In a method of manufacturing a semiconductor device in which a liquid resin is dropped into a region defined by the dam so as to cover a semiconductor element, the dam material is double-coated to form a dam having an inner surface with a substantially circular arc cross section. When the liquid resin is dropped, the height of the liquid resin surface at the center of the area after the completion of the drop is made to coincide with the substantially center of the substantially circular arc, and the drop amount is increased so as to increase the area of the flat surface of the liquid resin surface. Is adjusted. With this configuration, the inner surface of the upper layer of the dam where the liquid resin is doubled (the portion formed by application later) contacts the inner surface at a height near the center of the arc, and at the contact position, the influence of wettability is small. Therefore, the amount of deformation of the liquid resin surface is reduced.

【0014】第2の発明は、第1の発明において、前記
ダム材を二重に塗布する際、最初に塗布するダム材より
も後から塗布するダム材の量を多くし、最初に塗布した
ダム材がコアとなったダムを形成することを特徴とす
る。かかる構成で、後から塗布するダム材は、集合基板
よりも先に塗布したダム材との濡れ性がよく、集合基板
にあまり濡れ広がらず、しかも後から塗布したダム材の
表面張力によって断面がより円に近い形状となる。
According to a second aspect of the present invention, in the first aspect, when the dam material is applied twice, the amount of the dam material to be applied later is larger than that of the dam material to be applied first, and the dam material is applied first. It is characterized in that the dam material forms a core dam. With such a configuration, the dam material applied later has good wettability with the dam material applied earlier than the collective substrate, does not spread much on the collective substrate, and has a cross section due to the surface tension of the dam material applied later. The shape becomes closer to a circle.

【0015】第3の発明は、前記第1または第2の発明
において、前記液状樹脂を滴下する際、滴下された前記
液状樹脂表面の高さを前記ダムと接する部分で最も高く
なるようにしたことを特徴とし、塗布完了後の液状樹脂
中心部(半導体形成領域中心部)にボイドが集まらず
に、逆に最も外側へ集められる構成とした。
According to a third aspect, in the first or second aspect, when the liquid resin is dropped, the height of the surface of the dropped liquid resin is highest at a portion in contact with the dam. It is characterized in that voids do not collect at the center of the liquid resin (the center of the semiconductor formation region) after the application is completed, but are instead collected to the outermost side.

【0016】第4の発明は、前記第1乃至第3の発明に
おいて、前記ダムを単位半導体装置形成領域毎に形成
し、隣り合う前記単位半導体装置形成領域毎の前記ダム
間に沿って前記集合基板を切断し、個片の半導体装置と
することを特徴とし、ダムが集合基板に与える応力を各
単位半導体装置形成領域に分散する構成とした。
In a fourth aspect based on the first to third aspects, the dam is formed for each unit semiconductor device formation region, and the dam is formed along the gap between the adjacent unit semiconductor device formation regions. The substrate is cut into individual semiconductor devices, and the stress applied to the collective substrate by the dam is distributed to each unit semiconductor device formation region.

【0017】[0017]

【発明の実施の形態】以下に、本発明の実施の形態を図
面に沿って説明する。なお、図面において、既に説明し
た図4の符号と同一の符号のものは、同一または相当す
るものを示す。
Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals as those in FIG. 4 described above indicate the same or corresponding components.

【0018】図1は本発明の実施の形態を示し、(a)
は樹脂封止工程完了後を示す断面図、(b)はダイシン
グ工程におけるダイシングライン選定の様子を示す平面
図、(c)は切断工程終了後に得られた半導体装置の斜
視図である。
FIG. 1 shows an embodiment of the present invention, in which (a)
FIG. 7 is a cross-sectional view showing a state after completion of a resin sealing step, (b) is a plan view showing a state of dicing line selection in a dicing step, and (c) is a perspective view of a semiconductor device obtained after completion of a cutting step.

【0019】次に製造方法について説明する。なお、半
導体素子5を集合基板30に搭載する工程までは従来と
変わらないので説明を省略し、ダムの形成工程から説明
する。まず、図示しないディスペンサーの動作シーケン
ス及び吐出圧を予め設定しておく。この際、ディスペン
サーのシリンジが集合基板30の外周縁に沿って移動す
るように設定するが、これを2回繰り返すようにプログ
ラミングしておく。また、シリンジの動作速度と吐出圧
は、後に説明する液状樹脂の滴下量も考慮し、十分に半
導体素子5やワイヤ4を被覆できるようこれらよりも充
分な高さのダムとなるよう設定する。次に、シリンジに
ダム材を充填するが、この際採用するダム材は、ダム表
面が崩れず曲面を残すような速乾性のものがよく、液状
樹脂との濡れ性がよく、かつ硬化後の残留応力が極めて
低いものが望ましい。例えば一般的に液状樹脂として用
いられるエポキシ系のものであれば、シリコン樹脂を主
剤とする速乾性のダム材を使用する。本例では、粘度7
0Pa・sのダウ・コーニング・シリコーン(商標名、
東レ社製)を使用した。これは10分程度自然硬化する
だけで使用可能であり、生産性がよい。
Next, the manufacturing method will be described. Since the steps up to the step of mounting the semiconductor element 5 on the collective substrate 30 are the same as those in the related art, the description will be omitted, and the description will be started from the step of forming the dam. First, an operation sequence and a discharge pressure of a dispenser (not shown) are set in advance. At this time, the syringe of the dispenser is set so as to move along the outer peripheral edge of the collective substrate 30, and it is programmed to repeat this twice. In addition, the operating speed and the discharge pressure of the syringe are set so as to provide a dam having a height higher than these so that the semiconductor element 5 and the wire 4 can be sufficiently covered in consideration of the amount of the liquid resin to be described later. Next, the syringe is filled with dam material, and the dam material employed at this time is preferably a quick-drying material that leaves a curved surface without damaging the dam surface, has good wettability with the liquid resin, and after curing. It is desirable that the residual stress is extremely low. For example, in the case of an epoxy-based resin generally used as a liquid resin, a quick-drying dam material mainly composed of a silicon resin is used. In this example, the viscosity 7
0 Pa · s Dow Corning Silicone (trade name,
(Manufactured by Toray Industries, Inc.). This can be used only by natural curing for about 10 minutes, and the productivity is good.

【0020】以上に述べた準備の後、先に設定したシー
ケンスに従ってディスペンサーを移動させると共に集合
基板30上へダム材を吐出し、二重になったダム11を
形成する。このダム11は図1(a)に示すようなダル
マ状の2層のダムで、上層表面の断面が円弧を描く。但
し、本発明で必要な面は液状樹脂が接する内側面のみで
あり、この部分さえ断面が円弧になっていればよい。な
お、真円に近い円弧を安定的に得られればよいが、ディ
スペンサーの吐出圧変動やダム材粘度の変動等により、
若干楕円弧に近い形状となることもある。
After the preparation described above, the dispenser is moved in accordance with the previously set sequence, and at the same time, the dam material is discharged onto the collective substrate 30 to form the double dam 11. This dam 11 is a two-layer dam-shaped dam as shown in FIG. 1 (a), and the cross section of the upper layer surface draws an arc. However, the surface required in the present invention is only the inner surface in contact with the liquid resin, and it is sufficient that even this portion has a circular cross section. It is sufficient that an arc close to a perfect circle can be obtained stably, but due to fluctuations in the discharge pressure of the dispenser, fluctuations in the viscosity of the dam material, and the like,
The shape may be slightly similar to an elliptical arc.

【0021】次に、液状樹脂をダム11で囲まれた領域
にディスペンサーにて滴下する。この際、滴下量は、滴
下完了後の液状樹脂がダム11の上層に接し、半導体素
子5及びワイヤ4を充分に被覆する量に調整する。滴下
量は、滴下完了後のダム11で区画された領域中心部の
液状樹脂表面の高さが、前述した円弧の中心とほぼ一致
することを目安とするが、滴下した液状樹脂の表面がダ
ム11近傍で変形するため、ダム11近傍と中心部とで
は必ずしも高さが一致しない。極端な場合は図1(a)
に点線で示したように液状樹脂がダムの下層にしか接触
しない場合もあるので、液状樹脂のダム近傍における変
形が最小限度、即ち、液状樹脂表面の平坦面が最大限広
がるように予め実験等により滴下量を把握しておくこと
が肝要である。なお、図1(a)に示したものは、後述
するような意図があるため、故意に液状樹脂をダム11
に這い上がったような形に変形させているが、調整のし
かたによってはこの変形を殆ど無くすことができ、Ls
の値は、例えば従来の7〜10mmに対して0〜3mm
とすることができる。
Next, the liquid resin is dropped into a region surrounded by the dam 11 by a dispenser. At this time, the dripping amount is adjusted to an amount such that the liquid resin after the dripping is in contact with the upper layer of the dam 11 and sufficiently covers the semiconductor element 5 and the wire 4. The amount of dripping is based on the fact that the height of the liquid resin surface at the center of the area defined by the dam 11 after the completion of dripping substantially coincides with the center of the arc described above. Since the deformation occurs near 11, the height does not always match between the vicinity of the dam 11 and the center. In extreme cases, FIG. 1 (a)
In some cases, the liquid resin contacts only the lower layer of the dam, as shown by the dotted line, so that the deformation of the liquid resin near the dam should be minimized, that is, experiments should be performed in advance to maximize the flat surface of the liquid resin surface. It is important to know the amount of dripping by using this method. In addition, since the thing shown in FIG. 1A has the intention described later, the liquid resin is intentionally applied to the dam 11.
Deformation is performed in such a way as to crawl up, but depending on the adjustment method, this deformation can be almost eliminated, and Ls
Is, for example, 0 to 3 mm compared to the conventional 7 to 10 mm.
It can be.

【0022】次に、滴下した液状樹脂を所定の温度と時
間で硬化させる。この際、ボイドが液状樹脂表面の最も
高くなった箇所に移動してゆく。ここでボイドとは、液
状樹脂の滴下時に巻き込まれた空気や元々液状樹脂に溶
け込んでいたガス等により発生する気泡である。上述し
たように、液状樹脂表面が最も高くなった箇所はダム1
1に接する変形した部分であるため、そこに熱膨張で浮
力を増したボイドが集まってゆくことになる。
Next, the dropped liquid resin is cured at a predetermined temperature and time. At this time, the void moves to the highest point on the liquid resin surface. Here, the voids are bubbles generated by air or the like that is entrained when the liquid resin is dropped or gas originally dissolved in the liquid resin. As described above, the place where the surface of the liquid resin is highest is the dam 1
Since the deformed portion is in contact with 1, voids having increased buoyancy due to thermal expansion gather there.

【0023】次に、図1(b)の平面図に示すように、
単位半導体素子領域8に区画するよう、マトリクス状に
ダイシングラインを決め、これに沿ってブレードを走ら
せて切断し、図1(c)に示すような個片の半導体装置
31を形成する。この際、厚さが最も厚くなった封止樹
脂6の部分、即ちダム11近傍のボイドを含む部分を半
導体装置31に組み込まないようにダイシングする。
Next, as shown in the plan view of FIG.
A dicing line is determined in a matrix so as to be divided into the unit semiconductor element regions 8, and a blade is run along the dicing line to cut the dicing lines, thereby forming individual semiconductor devices 31 as shown in FIG. At this time, dicing is performed so that the portion of the sealing resin 6 having the largest thickness, that is, the portion including the void near the dam 11 is not incorporated into the semiconductor device 31.

【0024】本実施形態は以上のような構成であるた
め、同一の集合基板30から取れた全ての半導体装置3
1の封止樹脂厚を均一にすることができる。または、ダ
ム11近傍の樹脂表面が変形した部分が少なくなるた
め、均一な厚さの半導体装置31の取れ個数を向上する
ことができる。しかも、ボイドを集合基板30の不要な
部分とともにダイシングして除去するため、歩留まりも
向上することができる。
Since the present embodiment is configured as described above, all the semiconductor devices 3 taken from the same collective substrate 30
1 can make the thickness of the sealing resin uniform. Alternatively, since the portion of the resin surface near the dam 11 where the resin surface is deformed is reduced, the number of semiconductor devices 31 having a uniform thickness can be increased. Moreover, since the voids are diced and removed together with unnecessary portions of the collective substrate 30, the yield can be improved.

【0025】図2はBGA構造の半導体装置を例にした
別の実施の形態を示す断面図である。この場合の製造方
法は、二重に形成したダム11を単位半導体形成領域毎
にその外周縁を囲むように形成される点と、ダイシング
前にボールマウンタにてハンダボール21が電極2c上
に搭載される点が異なり、その他は上述の実施の形態と
同じである。なお、スルーホール3は穴埋め樹脂22に
よって埋められている。
FIG. 2 is a cross-sectional view showing another embodiment using a semiconductor device having a BGA structure as an example. The manufacturing method in this case is such that a double-formed dam 11 is formed for each unit semiconductor formation region so as to surround the outer peripheral edge thereof, and that a solder ball 21 is mounted on the electrode 2c by a ball mounter before dicing. The other points are the same as those of the above-described embodiment. The through hole 3 is filled with a filling resin 22.

【0026】このようにダム11を単位半導体形成領域
毎に形成することによって、集合基板30とダム11の
熱膨張差による集合基板30の反りの問題を抑制してい
る。即ち、従来はダムを連続した枠状に形成していたた
め、集合基板が長さ方向、特に長尺方向へ大きな曲げ応
力を受けたが、本例ではダムが小領域に応力を与えるの
みであるから、集合基板全体を反らせるような曲げ応力
が働かない。なお、ダイシングは隣り合う単位半導体形
成領域毎に形成されたダム間に沿って行われ、図2に示
すように半導体装置31にダム11が残存する。しか
し、上述のように封止樹脂6の表面平坦性を向上でき、
しかも封止樹脂6が小領域毎に区画されているため、ボ
イド絶対量が少なく、問題がない程度のものである。従
って外観不良等を発生させることはなく、そのままダム
11が残存した状態で市場に投入することが可能であ
る。
By forming the dam 11 in each unit semiconductor formation region, the problem of warpage of the collective substrate 30 due to a difference in thermal expansion between the collective substrate 30 and the dam 11 is suppressed. That is, conventionally, since the dam was formed in a continuous frame shape, the aggregate substrate was subjected to a large bending stress in the length direction, particularly in the long direction, but in this example, the dam only applies stress to a small area. Therefore, a bending stress that warps the entire collective substrate does not work. Note that dicing is performed between the dams formed in adjacent unit semiconductor formation regions, and the dams 11 remain in the semiconductor device 31 as shown in FIG. However, the surface flatness of the sealing resin 6 can be improved as described above,
In addition, since the sealing resin 6 is divided into small areas, the absolute amount of voids is small and there is no problem. Therefore, it does not cause appearance defects or the like, and can be put on the market with the dam 11 remaining as it is.

【0027】以上、発明の実施の形態について述べた
が、これに限らず特許請求の範囲の趣旨で種々の変更が
可能である。例えば、上記第1の実施の形態において、
最初に塗布するダム材よりも後に塗布するダム材の量を
多く塗布することで、図3に示すように下層のダム材2
3をコアとし、これを上層のダム材24が覆うようなダ
ムを形成する構成とする。この際、上層のダム材が集合
基板に濡れ広がりづらくなり、ダム材の表面張力によっ
てダムの上層内側面断面がより真円に近い円弧となる。
また、ダムは、搬送過程で外力を受けて脱落しないよ
う、ワイヤボンド後に形成することが望ましいが、ダイ
ボンド前の基板製造時に形成することも可能である。
Although the embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications can be made within the spirit of the claims. For example, in the first embodiment,
By applying a larger amount of dam material to be applied later than the dam material to be applied first, as shown in FIG.
3 is a core, and a dam is formed such that the dam is covered by an upper dam material 24. At this time, the dam material in the upper layer is less likely to wet and spread on the collective substrate, and the inner layer cross section of the upper layer of the dam becomes a circular arc closer to a perfect circle due to the surface tension of the dam material.
The dam is desirably formed after wire bonding so that the dam does not fall off due to an external force during the transportation process. However, the dam may be formed during substrate manufacturing before die bonding.

【0028】[0028]

【発明の効果】上述したように、本発明はポッティング
モールドを利用するものであるから、高価な金型などを
用いずに低コストで簡単にダムを構成することができ
る。そして、更には以下のような効果を有する。
As described above, since the present invention utilizes a potting mold, a dam can be easily formed at low cost without using an expensive mold or the like. Further, it has the following effects.

【0029】樹脂の平坦な部分を広げることが可能にな
るため、半導体装置の厚さばらつきを抑制することがで
き、廃棄する部材を削減することができる。これはま
た、半導体装置の取り個数が増加することにもなるの
で、コストを低減化できる。
Since the flat portion of the resin can be expanded, the thickness variation of the semiconductor device can be suppressed, and the number of members to be discarded can be reduced. This also leads to an increase in the number of semiconductor devices to be obtained, so that costs can be reduced.

【0030】また、ダムを二重に形成する際、図3に示
すように最初に塗布するダム材よりも後から塗布するダ
ム材の量を多くし、最初に塗布したダム材がコアとなっ
たダムを形成することで、ダム内側面に液状樹脂を接触
させるのに良好な面を安定的に形成することができる。
When a dam is formed in a double form, as shown in FIG. 3, the amount of dam material to be applied later is made larger than that of dam material to be applied first, and the dam material applied first becomes a core. By forming the dam, a good surface for bringing the liquid resin into contact with the inner surface of the dam can be stably formed.

【0031】また、ダムに接する部分で封止樹脂の厚さ
を最も厚くする構成とすれば、ボイド発生箇所を、製品
にならない部分か、または半導体素子やボンディングワ
イヤに水分進入等の影響を与えない片隅部分とすること
ができるため、歩留まりを向上させることができる。
If the thickness of the sealing resin is set to be the largest at the portion in contact with the dam, the location where the voids are generated may be affected by the entry of moisture into the portion that does not become a product or the semiconductor element or the bonding wire. Since there is no corner, the yield can be improved.

【0032】また、ダムを単位半導体装置形成領域毎に
形成し、隣り合う前記単位半導体装置形成領域毎のダム
間に沿って集合基板を切断し、個片の半導体装置とする
ことで、集合基板の反りが抑制され、取れ個数の大きな
大面積の集合基板を使用した場合であっても、ハンドリ
ングの不具合等を発生させずに済み、生産性を向上させ
ることができる。
Further, a dam is formed for each unit semiconductor device forming region, and the collective substrate is cut along the dam between the adjacent unit semiconductor device forming regions to form individual semiconductor devices. Even when a large-area collective substrate with a large number of pieces to be removed is used, handling troubles and the like do not occur, and productivity can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る半導体装置用基板と半導体装置の
実施の形態を示す図である。
FIG. 1 is a diagram showing an embodiment of a semiconductor device substrate and a semiconductor device according to the present invention.

【図2】本発明に係る半導体装置用基板と半導体装置の
他の例を示す図である。
FIG. 2 is a view showing another example of a semiconductor device substrate and a semiconductor device according to the present invention.

【図3】本発明に係る半導体装置用基板上のダム形状の
実施の形態を示す図である。
FIG. 3 is a diagram showing an embodiment of a dam shape on a semiconductor device substrate according to the present invention.

【図4】従来のLCC構造の半導体装置用基板と半導体
装置を示す図である。
FIG. 4 is a view showing a conventional semiconductor device substrate having an LCC structure and a semiconductor device.

【符号の説明】[Explanation of symbols]

1:基板、2a:メタル配線、2b:ダイパッド、2
c:電極、3:スルーホール、4:ボンディングワイ
ヤ、5:半導体素子、6:封止樹脂、7:ドライフィル
ム状のソルダーレジスト、8:単位半導体装置形成領
域、10:サイドスルー、11:ダム、21:半田ボー
ル、22:穴埋め樹脂、23:一回目に塗布したダム、
24:2回目に塗布したダム、30:集合基板、31:
半導体装置
1: substrate, 2a: metal wiring, 2b: die pad, 2
c: electrode, 3: through hole, 4: bonding wire, 5: semiconductor element, 6: sealing resin, 7: dry film solder resist, 8: unit semiconductor device formation region, 10: side through, 11: dam , 21: solder ball, 22: filling resin, 23: dam applied first time,
24: Dam applied second time, 30: Collective substrate, 31:
Semiconductor device

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 集合基板上に搭載された半導体素子を取
り囲むようにディスペンサーにてダム材を塗布してダム
を形成し、前記半導体素子を被覆するよう前記ダムで区
画される領域に液状樹脂を滴下する半導体装置の製造方
法において、 前記ダム材を二重に塗布し、上層内側面が断面略円弧と
なったダムを形成し、前記液状樹脂を滴下する際に、滴
下完了後の前記領域中心部の前記液状樹脂表面の高さを
前記略円弧の略中心と一致させ、前記液状樹脂表面平坦
面の面積を広げるよう滴下量を調整することを特徴とす
る半導体装置の製造方法。
1. A dam material is applied by a dispenser so as to surround a semiconductor element mounted on an aggregate substrate to form a dam, and a liquid resin is applied to a region defined by the dam so as to cover the semiconductor element. In the method for manufacturing a semiconductor device to be dropped, the dam material is double-coated, a dam having an upper inner side surface having a substantially circular cross section is formed, and when dropping the liquid resin, the center of the region after the dropping is completed. A height of the liquid resin surface of the portion is made substantially coincident with a substantially center of the substantially circular arc, and a dripping amount is adjusted so as to increase an area of the flat surface of the liquid resin surface.
【請求項2】 前記ダム材を二重に塗布する際、最初に
塗布するダム材よりも後から塗布するダム材の量を多く
し、最初に塗布したダム材がコアとなったダムを形成す
ることを特徴とする請求項1に記載の半導体装置の製造
方法。
2. When the dam material is applied twice, the amount of the dam material to be applied later is made larger than that of the dam material to be applied first, so that the dam material applied first forms a core. 2. The method for manufacturing a semiconductor device according to claim 1, wherein:
【請求項3】 前記液状樹脂を滴下する際、滴下された
前記液状樹脂表面の高さを前記ダムと接する部分で最も
高くなるようにしたことを特徴とする請求項1または2
に記載の半導体装置の製造方法。
3. The method according to claim 1, wherein, when the liquid resin is dropped, the height of the surface of the liquid resin dropped is highest at a portion in contact with the dam.
13. The method for manufacturing a semiconductor device according to item 5.
【請求項4】 前記ダムを単位半導体装置形成領域毎に
形成し、隣り合う前記単位半導体装置形成領域毎の前記
ダム間に沿って前記集合基板を切断し、個片の半導体装
置とすることを特徴とする請求項1乃至3に記載の半導
体装置の製造方法。
4. The method according to claim 1, wherein the dam is formed for each unit semiconductor device formation region, and the aggregate substrate is cut along the gap between the adjacent unit semiconductor device formation regions to form individual semiconductor devices. The method for manufacturing a semiconductor device according to claim 1, wherein:
JP2001069864A 2001-03-13 2001-03-13 Semiconductor device manufacturing method Pending JP2002270627A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196657A (en) * 2005-01-13 2006-07-27 New Japan Radio Co Ltd Manufacturing method of semiconductor device
WO2007083481A1 (en) 2006-01-19 2007-07-26 Rohm Co., Ltd. Semiconductor display device and process for manufacturing the same
US7781089B2 (en) 2005-05-11 2010-08-24 Ricoh Company, Ltd. Protection circuit module for a secondary battery and a battery package using same
JP2010283036A (en) * 2009-06-02 2010-12-16 Murata Mfg Co Ltd Method for manufacturing substrate
JP2013118284A (en) * 2011-12-02 2013-06-13 Hitachi Appliances Inc Light emitting diode module
CN103378045A (en) * 2012-04-20 2013-10-30 新光电气工业株式会社 Lead frame, semiconductor package, and manufacturing method of the same
CN114242870A (en) * 2021-12-22 2022-03-25 鸿利智汇集团股份有限公司 Wafer support, wafer support plate and wafer packaging method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196657A (en) * 2005-01-13 2006-07-27 New Japan Radio Co Ltd Manufacturing method of semiconductor device
US7781089B2 (en) 2005-05-11 2010-08-24 Ricoh Company, Ltd. Protection circuit module for a secondary battery and a battery package using same
WO2007083481A1 (en) 2006-01-19 2007-07-26 Rohm Co., Ltd. Semiconductor display device and process for manufacturing the same
JP2010283036A (en) * 2009-06-02 2010-12-16 Murata Mfg Co Ltd Method for manufacturing substrate
JP2013118284A (en) * 2011-12-02 2013-06-13 Hitachi Appliances Inc Light emitting diode module
CN103378045A (en) * 2012-04-20 2013-10-30 新光电气工业株式会社 Lead frame, semiconductor package, and manufacturing method of the same
JP2013225595A (en) * 2012-04-20 2013-10-31 Shinko Electric Ind Co Ltd Lead frame, semiconductor package, and manufacturing methods of lead frame and semiconductor package
CN114242870A (en) * 2021-12-22 2022-03-25 鸿利智汇集团股份有限公司 Wafer support, wafer support plate and wafer packaging method

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