JP2006196657A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP2006196657A
JP2006196657A JP2005006260A JP2005006260A JP2006196657A JP 2006196657 A JP2006196657 A JP 2006196657A JP 2005006260 A JP2005006260 A JP 2005006260A JP 2005006260 A JP2005006260 A JP 2005006260A JP 2006196657 A JP2006196657 A JP 2006196657A
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Prior art keywords
semiconductor element
semiconductor
mounting substrate
resin
semiconductor device
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Hironori Terasaki
浩則 寺崎
Kenji Yamaura
健児 山浦
Kenji Tanaka
健司 田中
Shinji Hara
慎治 原
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New Japan Radio Co Ltd
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New Japan Radio Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device for providing a rectangular parallelopiped semiconductor device which may be formed thinner and small in size. <P>SOLUTION: A plurality of semiconductor elements 1 are joined in the face-down attitude on a mounting substrate 3 and a dam 7 is formed in the periphery of the semiconductor element mounting area where such semiconductor elements 1 are joined. A resin 4 is coated on the mounting substrate surrounded with the dam and the semiconductor element is sealed with resin in the manner that the rear surface thereof is exposed from the sealing resin surrounding the circumference thereof. The exposed rear surface of the semiconductor element and the sealing resin are polished. Thereafter, or after the polished surface is covered with a protection film, the almost rectangular parallelopiped semiconductor device is formed by cutting into pieces the polished sealing resin provided between adjacent semiconductor elements and mounting substrate or the protection film. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は半導体装置の製造方法に関し、特に半導体装置を小型化、薄型化するための製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a manufacturing method for reducing the size and thickness of a semiconductor device.

半導体装置を搭載する電子装置の小型化、薄型化に伴い、半導体装置自体の小型化、薄型化の要請が高まってきている。そのため、実装基板の薄型化、半導体素子の薄型化、封止樹脂の薄型化など種々の方法が試みられている。   With the downsizing and thinning of electronic devices on which semiconductor devices are mounted, there is an increasing demand for downsizing and thinning of semiconductor devices themselves. For this reason, various methods have been attempted, such as thinning the mounting substrate, thinning the semiconductor element, and thinning the sealing resin.

図３は従来のこの種の半導体装置の製造方法の説明図である。まず、比較的厚い（たとえば３００〜７００μｍ厚）半導体基板を個片化して形成した半導体素子１を用意する。半導体素子１表面にはバンプ電極等の電極２が形成されている。複数個の半導体素子１の電極２を、実装基板３上に形成された配線（図示せず）に、フェイスダウン姿勢で接合する。次にアンダーフィルと呼ばれるフィラーを含んだ液状樹脂を、半導体素子１表面と実装基板３の間に充填し、硬化させる（図３ａ）。   FIG. 3 is an explanatory view of a conventional method of manufacturing this type of semiconductor device. First, a semiconductor element 1 formed by dividing a relatively thick (for example, 300 to 700 μm) semiconductor substrate into pieces is prepared. Electrodes 2 such as bump electrodes are formed on the surface of the semiconductor element 1. The electrodes 2 of the plurality of semiconductor elements 1 are joined to a wiring (not shown) formed on the mounting substrate 3 in a face-down posture. Next, a liquid resin containing a filler called an underfill is filled between the surface of the semiconductor element 1 and the mounting substrate 3 and cured (FIG. 3a).

次に、フィラーを含まない別の液状樹脂を、半導体素子１の側壁部分のみに被着させ、硬化させることで、半導体素子１の周囲を取り囲むように樹脂５を形成する（図３ｂ）。   Next, another liquid resin not containing a filler is applied only to the side wall portion of the semiconductor element 1 and cured to form the resin 5 so as to surround the semiconductor element 1 (FIG. 3 b).

その後、半導体素子１の露出する裏面と樹脂５を研磨し、半導体素子１の厚さが１００〜２００μｍ程度となるまで薄型化する。続いて、ダイシングソーを用いて、隣接する半導体素子１間に露出する実装基板３を図３（ｃ）に破線で示す位置で切断して個片化し、半導体装置が完成する（図３ｄ）。（特許文献１図５参照）   Thereafter, the exposed back surface of the semiconductor element 1 and the resin 5 are polished, and the semiconductor element 1 is thinned to a thickness of about 100 to 200 μm. Subsequently, by using a dicing saw, the mounting substrate 3 exposed between the adjacent semiconductor elements 1 is cut into pieces at a position indicated by a broken line in FIG. 3C to complete a semiconductor device (FIG. 3D). (See Patent Document 1 FIG. 5)

また、別の従来のこの種の半導体装置の製造方法として、図４に示す製造方法が提案されている。前述の製造方法同様、まず、比較的厚い（たとえば３００〜７００μｍ厚）半導体基板を個片化して形成した半導体素子１を用意する。半導体素子１表面にはバンプ電極等の電極２が形成されている。半導体素子１の電極２を、実装基板３上に形成された配線（図示せず）に、フェイスダウン姿勢で接合する（図４ａ）。次にアンダーフィルと呼ばれるフィラーを含んだ液状樹脂を、半導体素子１表面と実装基板３の間に充填し、樹脂４で封止する。このとき、樹脂４が半導体素子１の側壁部分を取り囲むように封止する（図４ｂ）。その後、半導体素子１の露出する裏面と樹脂４を研磨し、半導体素子１を薄型化する。その後、実装基板３を所定の位置で切断して個片化し、半導体装置が完成する（図４ｃ）。（特許文献２図８参照）
特開２００２−３６７９４２号公報 特開２００２−９３８３１号公報 As another conventional method for manufacturing this type of semiconductor device, a manufacturing method shown in FIG. 4 has been proposed. Similar to the above-described manufacturing method, first, a semiconductor element 1 formed by dividing a relatively thick (for example, 300 to 700 μm thick) semiconductor substrate into pieces is prepared. Electrodes 2 such as bump electrodes are formed on the surface of the semiconductor element 1. The electrode 2 of the semiconductor element 1 is joined to a wiring (not shown) formed on the mounting substrate 3 in a face-down posture (FIG. 4a). Next, a liquid resin containing a filler called underfill is filled between the surface of the semiconductor element 1 and the mounting substrate 3 and sealed with the resin 4. At this time, the resin 4 is sealed so as to surround the side wall portion of the semiconductor element 1 (FIG. 4B). Thereafter, the exposed back surface of the semiconductor element 1 and the resin 4 are polished to thin the semiconductor element 1. Thereafter, the mounting substrate 3 is cut at a predetermined position and separated into individual pieces, thereby completing the semiconductor device (FIG. 4c). (See Patent Document 2 FIG. 8)
JP 2002-367842 A JP 2002-93831 A

従来の半導体装置の製造方法では、実装基板３上に樹脂４及び樹脂５が形成されない部分が残り、小型化を図る上で好ましくなかった。また、半導体素子１を取り囲む樹脂の厚さは、半導体装置周辺に向かって薄くなっており、試験工程や搬送工程等で半導体素子の割れ、樹脂の剥離、実装基板の破損等の不具合が生じてしまう場合があった。さらに、研磨した半導体素子１の裏面に保護用フィルムを貼り付ける際、表面に保護用フィルムを密着させることが難しかった。本発明はこのような不具合を解消するため、薄型化、小型化ができ、かつ直方体形状の半導体装置を提供することができる半導体装置の製造方法を提供することを目的とする。   In the conventional method for manufacturing a semiconductor device, a portion on which the resin 4 and the resin 5 are not formed remains on the mounting substrate 3, which is not preferable for downsizing. In addition, the thickness of the resin surrounding the semiconductor element 1 is reduced toward the periphery of the semiconductor device, and problems such as cracking of the semiconductor element, peeling of the resin, and damage to the mounting substrate occur in the test process and the transport process. There was a case. Furthermore, when a protective film is affixed to the back surface of the polished semiconductor element 1, it is difficult to adhere the protective film to the surface. In order to eliminate such problems, an object of the present invention is to provide a method of manufacturing a semiconductor device that can be thinned and reduced in size and can provide a rectangular parallelepiped semiconductor device.

上記目的を達成するため、請求項１に係る本発明の製造方法は、実装基板上の配線に、半導体素子表面の電極がフェイスダウン姿勢で接合し、該半導体素子の裏面を該半導体素子の周囲を取り囲む封止樹脂から露出する構造の半導体装置の製造方法において、複数個の前記半導体素子を、前記実装基板上にフェイスダウン姿勢で接合する工程と、前記複数個の半導体素子を接合した半導体素子搭載部周囲に、ダム部を形成する工程と、該ダム部で囲まれた前記実装基板上に樹脂を塗布し、前記半導体素子の裏面を周囲を取り囲む封止樹脂から露出するように樹脂封止する工程と、前記半導体素子の露出する裏面及び前記封止樹脂を、前記実装基板上の高さが略均一となるように研磨する工程と、隣接する前記半導体素子間の前記研磨した封止樹脂及び前記実装基板を切断して個片化し、略直方体形状の半導体装置を形成する工程とを含むことを特徴とするものである。   In order to achieve the above object, in the manufacturing method of the present invention according to claim 1, the electrode on the surface of the semiconductor element is bonded to the wiring on the mounting substrate in a face-down posture, and the back surface of the semiconductor element is surrounded by the periphery of the semiconductor element. In a method of manufacturing a semiconductor device having a structure exposed from a sealing resin surrounding the semiconductor device, a step of bonding a plurality of the semiconductor elements on the mounting substrate in a face-down posture, and a semiconductor element obtained by bonding the plurality of semiconductor elements A step of forming a dam portion around the mounting portion, a resin is applied on the mounting substrate surrounded by the dam portion, and the resin sealing is performed so that the back surface of the semiconductor element is exposed from the sealing resin surrounding the periphery. Polishing the exposed back surface of the semiconductor element and the sealing resin so that the height on the mounting substrate is substantially uniform, and the polished sealing between the adjacent semiconductor elements. Singulation by cutting the fat and the mounting substrate, is characterized in that a step of forming a semiconductor device having a substantially rectangular parallelepiped shape.

また請求項２に係る本発明の製造方法は、実装基板上の配線に、半導体素子表面の電極がフェイスダウン姿勢で接合し、該半導体素子の裏面を該半導体素子の周囲を取り囲む封止樹脂から露出する構造の半導体装置の製造方法において、複数個の前記半導体素子を、前記実装基板上にフェイスダウン姿勢で接合する工程と、前記複数個の半導体素子を接合した半導体素子搭載部周囲に、ダム部を形成する工程と、該ダム部で囲まれた前記実装基板上に樹脂を塗布し、前記半導体素子の裏面を周囲を取り囲む封止樹脂から露出するように樹脂封止する工程と、前記半導体素子の露出する裏面及び前記封止樹脂を、前記実装基板上の高さが略均一となるように研磨する工程と、該研磨した表面を保護用フィルムで被覆する工程と、隣接する前記半導体素子間の前記保護用フィルム、前記研磨した封止樹脂及び前記実装基板を切断して個片化し、略直方体形状の半導体装置を形成する工程とを含むことを特徴とするものである。   Further, in the manufacturing method of the present invention according to claim 2, the electrode on the surface of the semiconductor element is bonded to the wiring on the mounting substrate in a face-down posture, and the back surface of the semiconductor element is made of the sealing resin surrounding the periphery of the semiconductor element. In a method of manufacturing a semiconductor device having an exposed structure, a step of bonding a plurality of the semiconductor elements on the mounting substrate in a face-down posture, and a dam around a semiconductor element mounting portion where the plurality of semiconductor elements are bonded Forming a portion, applying a resin on the mounting substrate surrounded by the dam portion, and sealing the resin so that the back surface of the semiconductor element is exposed from a sealing resin surrounding the periphery, and the semiconductor A step of polishing the exposed back surface of the element and the sealing resin so that the height on the mounting substrate is substantially uniform, a step of covering the polished surface with a protective film, and the adjacent half The protective film between the body elements, said to be polished cutting the sealing resin and the mounting substrate singulation, it is characterized in that a step of forming a semiconductor device having a substantially rectangular parallelepiped shape.

本発明の製造方法は、半導体素子搭載部の周囲にダム部を形成することで、半導体素子間に厚く樹脂を塗布することができ、半導体素子の裏面を研磨すると同時に半導体素子間の封止樹脂も研磨し、個片化するため、特別な装置を必要とせず、簡便に半導体装置の外形を直方体形状にすることができる。   In the manufacturing method of the present invention, by forming a dam part around the semiconductor element mounting part, a thick resin can be applied between the semiconductor elements, and the back surface of the semiconductor element is polished and simultaneously the sealing resin between the semiconductor elements In addition, since the semiconductor device is polished and separated into individual pieces, the external shape of the semiconductor device can be easily changed to a rectangular parallelepiped shape without requiring a special device.

また本発明の製造方法は、研磨した面はほぼ同一面となるため、保護用フィルムを簡便に被着することができる。   Moreover, since the polished surface becomes substantially the same surface in the production method of the present invention, a protective film can be easily applied.

本発明の製造方法により形成した半導体装置は、ほぼ直方体形状であるので、従来のように周辺部に薄い樹脂部がないため、破損等が生じることもなく、また保護用フィルムを被着すればさらに破損等が防止でき、信頼性上優れている半導体装置を提供することができる。   Since the semiconductor device formed by the manufacturing method of the present invention has a substantially rectangular parallelepiped shape, there is no thin resin portion in the peripheral portion as in the prior art, so there is no damage or the like, and if a protective film is applied Furthermore, damage and the like can be prevented, and a semiconductor device with excellent reliability can be provided.

以下、本発明の実施例について、詳細に説明する。   Examples of the present invention will be described in detail below.

まず、従来例同様、比較的厚い（たとえば３００〜７００μｍ厚）半導体基板を個片化して形成した半導体素子１を用意する。半導体素子１表面にはバンプ電極等の電極２が形成されている。複数個の半導体素子１の電極２を、実装基板３上に形成された配線（図示せず）に、フェイスダウン姿勢で接合する。次に本発明では、複数の半導体素子１を接合した半導体素子搭載部６の周囲を取り囲むようにダム部７を形成する。このダム部７の高さは、後工程で塗布する少なくとも半導体装置として残る部分の樹脂４の厚さが、研磨後の半導体素子１の裏面までの高さより厚くなるように適宜設定する。つまり、樹脂４が半導体素子１の裏面と共に研磨される厚さに塗布できる高さに設定する。ダム部７は、ディスペンサを使って、樹脂を一回あるいは複数回塗布することで形成することができる（図１ａ）。なお、実装基板１上の半導体素子搭載部６は、全ての半導体素子１が等間隔に配置されている場合に限定されるものでないことは言うまでもない。たとえば図１（ｄ）に示すように、隣接する半導体素子１間の間隔の一部が広くなっていてもかまわない。但し、隣接する半導体素子１間の間隔が広くなることによって、少なくとも半導体装置として残る部分の樹脂４の厚さが、研磨後の半導体素子１の裏面までの高さより厚くなるように配置する必要があり、樹脂４の厚さが研磨後の半導体素子１の裏面までの高さより薄くなる場合には、半導体素子間の間隔を狭くするか、半導体素子１間に別のダム部７を形成すればよい。   First, as in the conventional example, a semiconductor element 1 formed by dividing a relatively thick (for example, 300 to 700 μm) semiconductor substrate into pieces is prepared. Electrodes 2 such as bump electrodes are formed on the surface of the semiconductor element 1. The electrodes 2 of the plurality of semiconductor elements 1 are joined to a wiring (not shown) formed on the mounting substrate 3 in a face-down posture. Next, in the present invention, the dam portion 7 is formed so as to surround the periphery of the semiconductor element mounting portion 6 to which the plurality of semiconductor elements 1 are joined. The height of the dam portion 7 is appropriately set so that the thickness of the resin 4 at least remaining as a semiconductor device to be applied in a subsequent process is thicker than the height to the back surface of the semiconductor element 1 after polishing. That is, the height is set such that the resin 4 can be applied to a thickness that can be polished together with the back surface of the semiconductor element 1. The dam portion 7 can be formed by applying a resin once or a plurality of times using a dispenser (FIG. 1a). Needless to say, the semiconductor element mounting portion 6 on the mounting substrate 1 is not limited to the case where all the semiconductor elements 1 are arranged at equal intervals. For example, as shown in FIG. 1D, a part of the interval between adjacent semiconductor elements 1 may be widened. However, it is necessary to dispose the resin 4 at least in a portion remaining as a semiconductor device such that the thickness between the adjacent semiconductor elements 1 becomes larger than the height to the back surface of the semiconductor element 1 after polishing. If the thickness of the resin 4 is thinner than the height to the back surface of the semiconductor element 1 after polishing, the interval between the semiconductor elements can be reduced, or another dam portion 7 can be formed between the semiconductor elements 1. Good.

次にアンダーフィルと呼ばれるフィラーを含んだ液状樹脂を、ディスペンサ８を用いて、半導体素子１表面と実装基板３の間に充填し、樹脂４で封止する。ここで、樹脂４の厚さは、前述の説明の通り、研磨後の半導体素子の裏面の高さより厚くなっていることが本発明の特徴となる（図１ｂ）。   Next, a liquid resin containing a filler called underfill is filled between the surface of the semiconductor element 1 and the mounting substrate 3 by using the dispenser 8 and sealed with the resin 4. Here, as described above, the thickness of the resin 4 is greater than the height of the back surface of the polished semiconductor element, which is a feature of the present invention (FIG. 1b).

その後、半導体素子１の露出する裏面と樹脂４を研磨し、半導体素子１の厚さが１００〜２００μｍ程度となるまで薄型化する。続いて、ダイシングソーを用いて、半導体素子１間の樹脂４及び実装基板３を図中破線で示す位置で切断して個片化し、半導体装置が完成する（図１ｃ）。   Thereafter, the exposed back surface of the semiconductor element 1 and the resin 4 are polished, and the semiconductor element 1 is thinned until the thickness of the semiconductor element 1 becomes about 100 to 200 μm. Subsequently, using a dicing saw, the resin 4 and the mounting substrate 3 between the semiconductor elements 1 are cut into pieces at positions indicated by broken lines in the drawing, and the semiconductor device is completed (FIG. 1c).

このように形成した半導体装置は、個片化後の形状が、ほぼ直方体形状となり、半導体素子の周囲を比較的厚い樹脂で取り囲む構造となるため、試験工程や搬送工程等で半導体素子の割れ、樹脂の剥離、実装基板の破損等の不具合が生じることがない。   The semiconductor device formed in this way has a substantially rectangular parallelepiped shape after being singulated, and has a structure that surrounds the periphery of the semiconductor element with a relatively thick resin. There are no problems such as peeling of the resin and damage to the mounting board.

次に別の実施例について説明する。第１の実施例同様、比較的厚い（たとえば３００〜７００μｍ厚）半導体基板を個片化して形成した半導体素子１を用意する。半導体素子１表面にはバンプ電極等の電極２が形成されている。複数個の半導体素子１の電極２を実装基板３上に形成された配線（図示せず）に、フェイスダウン姿勢で接合する。次に複数の半導体素子１を接合した半導体素子搭載部６の周囲を取り囲むようにダム部７を形成する。このダム部７の高さは、後工程で塗布する少なくとも半導体装置として残る部分の樹脂４の厚さが、研磨後の半導体素子１の裏面までの高さより厚くなるように適宜設定する。つまり、樹脂４が半導体素子１の裏面と共に研磨される厚さに塗布できる高さに設定する。ダム部７は、ディスペンサを使って、樹脂を一回あるいは複数回塗布することで形成することができる（図１ａ）。なお、前述の説明通り、実装基板１上の半導体素子搭載部６は、図１（ｄ）に示すように、必ずしも全ての半導体素子１を等間隔で配列する必要はなく、隣接する半導体素子１間の間隔の一部が、広くなっていてもかまわない。但し、隣接する半導体素子１間の間隔が広くなることによって、少なくとも半導体装置として残る部分の樹脂４の厚さが、研磨後の半導体素子１の裏面までの高さより厚くなるように配置する必要があり、樹脂４の厚さが研磨後の半導体素子１の裏面までの高さが薄くなる場合には、半導体素子１間に別途ダム部７を形成する必要がある。   Next, another embodiment will be described. As in the first embodiment, a semiconductor element 1 is prepared which is formed by dividing a relatively thick (for example, 300 to 700 μm) semiconductor substrate into pieces. Electrodes 2 such as bump electrodes are formed on the surface of the semiconductor element 1. The electrodes 2 of the plurality of semiconductor elements 1 are joined to a wiring (not shown) formed on the mounting substrate 3 in a face-down posture. Next, the dam portion 7 is formed so as to surround the periphery of the semiconductor element mounting portion 6 to which the plurality of semiconductor elements 1 are joined. The height of the dam portion 7 is appropriately set so that the thickness of the resin 4 at least remaining as a semiconductor device to be applied in a subsequent process is thicker than the height to the back surface of the semiconductor element 1 after polishing. That is, the height is set such that the resin 4 can be applied to a thickness that can be polished together with the back surface of the semiconductor element 1. The dam portion 7 can be formed by applying a resin once or a plurality of times using a dispenser (FIG. 1a). As described above, the semiconductor element mounting portion 6 on the mounting substrate 1 does not necessarily have to arrange all the semiconductor elements 1 at equal intervals as shown in FIG. A part of the interval may be wide. However, it is necessary to dispose the resin 4 at least in a portion remaining as a semiconductor device such that the thickness between the adjacent semiconductor elements 1 becomes larger than the height to the back surface of the semiconductor element 1 after polishing. If the thickness of the resin 4 is as thin as the back surface of the semiconductor element 1 after polishing, it is necessary to separately form a dam portion 7 between the semiconductor elements 1.

次にアンダーフィルと呼ばれるフィラーを含んだ液状樹脂を、半導体素子１表面と実装基板３の間に充填し、樹脂４で封止する。ここで、樹脂４の厚さは、前述の説明の通り、研磨後の半導体素子の裏面の高さより厚くなっている（図１ｂ）。   Next, a liquid resin containing a filler called underfill is filled between the surface of the semiconductor element 1 and the mounting substrate 3 and sealed with the resin 4. Here, as described above, the thickness of the resin 4 is greater than the height of the back surface of the polished semiconductor element (FIG. 1b).

その後、半導体素子１の露出する裏面と樹脂４を研磨し、半導体素子１の厚さが１００〜２００μｍ程度となるまで薄型化する。続いて、本実施例では、研磨した表面を保護用フィルム９で被覆する。保護用フィルム９は、接着剤が付着した粘着フィルムあるいは熱硬化型フィルム等を使用することができる。研磨した表面がほぼ平面であるので、熱硬化性の樹脂フィルムを用いた場合、簡単に被覆することができ、特に好適である。   Thereafter, the exposed back surface of the semiconductor element 1 and the resin 4 are polished, and the semiconductor element 1 is thinned until the thickness of the semiconductor element 1 becomes about 100 to 200 μm. Subsequently, in this embodiment, the polished surface is covered with a protective film 9. As the protective film 9, a pressure-sensitive adhesive film or a thermosetting film to which an adhesive is attached can be used. Since the polished surface is substantially flat, when a thermosetting resin film is used, it can be easily covered and is particularly suitable.

その後、ダイシングソーを用いて、半導体素子１間の保護用フィルム９、樹脂４及び実装基板３を図中破線で示す位置で切断し、個片化し、半導体装置が完成する（図２）。   Thereafter, using a dicing saw, the protective film 9, the resin 4 and the mounting substrate 3 between the semiconductor elements 1 are cut at the positions indicated by the broken lines in the figure and separated into individual pieces, thereby completing the semiconductor device (FIG. 2).

このように形成した半導体装置は、個片化後の形状が、ほぼ直方体形状となり、半導体素子の周囲を比較的厚い樹脂で取り囲む構造となるため、試験工程や搬送工程等で半導体素子の割れ、樹脂の剥離、実装基板の破損等の不具合が生じることがなくなる。また、露出する半導体素子１の裏面を保護用フィルム９で被覆する構造となっているため、さらに半導体素子１の破損を防止することができる。   The semiconductor device formed in this way has a substantially rectangular parallelepiped shape after being singulated, and has a structure that surrounds the periphery of the semiconductor element with a relatively thick resin. Problems such as resin peeling and breakage of the mounting board are not caused. Further, since the back surface of the exposed semiconductor element 1 is covered with the protective film 9, the semiconductor element 1 can be further prevented from being damaged.

本発明の実施例を説明する図である。It is a figure explaining the Example of this invention. 本発明の別の実施例を説明する図である。It is a figure explaining another Example of this invention. 従来の半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the conventional semiconductor device. 従来の別の半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of another conventional semiconductor device.

符号の説明Explanation of symbols

１；半導体素子、２；電極、３；実装基板、４；樹脂、５；樹脂、
６；半導体素子搭載部、７；ダム部、８；ディスペンサ、９；保護用フィルム
DESCRIPTION OF SYMBOLS 1; Semiconductor element, 2; Electrode, 3; Mounting substrate, 4; Resin, 5; Resin,
6; Semiconductor element mounting portion, 7; Dam portion, 8; Dispenser, 9; Protective film

Claims (2)

実装基板上の配線に、半導体素子表面の電極がフェイスダウン姿勢で接合し、該半導体素子の裏面を該半導体素子の周囲を取り囲む封止樹脂から露出する構造の半導体装置の製造方法において、
複数個の前記半導体素子を、前記実装基板上にフェイスダウン姿勢で接合する工程と、
前記複数個の半導体素子を接合した半導体素子搭載部周囲に、ダム部を形成する工程と、
該ダム部で囲まれた前記実装基板上に樹脂を塗布し、前記半導体素子の裏面を周囲を取り囲む封止樹脂から露出するように樹脂封止する工程と、
前記半導体素子の露出する裏面及び前記封止樹脂を、前記実装基板上の高さが略均一となるように研磨する工程と、
隣接する前記半導体素子間の前記研磨した封止樹脂及び前記実装基板を切断して個片化し、略直方体形状の半導体装置を形成する工程とを含むことを特徴とする半導体装置の製造方法。 In the method of manufacturing a semiconductor device having a structure in which the electrode on the surface of the semiconductor element is bonded to the wiring on the mounting substrate in a face-down posture, and the back surface of the semiconductor element is exposed from the sealing resin surrounding the periphery of the semiconductor element.
Bonding a plurality of the semiconductor elements on the mounting substrate in a face-down posture;
Forming a dam portion around a semiconductor element mounting portion obtained by bonding the plurality of semiconductor elements;
Applying a resin onto the mounting substrate surrounded by the dam portion, and sealing the resin so that the back surface of the semiconductor element is exposed from the sealing resin surrounding the periphery; and
Polishing the exposed back surface of the semiconductor element and the sealing resin so that the height on the mounting substrate is substantially uniform;
And cutting the polished sealing resin between the adjacent semiconductor elements and the mounting substrate into individual pieces to form a substantially rectangular parallelepiped semiconductor device. 実装基板上の配線に、半導体素子表面の電極がフェイスダウン姿勢で接合し、該半導体素子の裏面を該半導体素子の周囲を取り囲む封止樹脂から露出する構造の半導体装置の製造方法において、
複数個の前記半導体素子を、前記実装基板上にフェイスダウン姿勢で接合する工程と、
前記複数個の半導体素子を接合した半導体素子搭載部周囲に、ダム部を形成する工程と、
該ダム部で囲まれた前記実装基板上に樹脂を塗布し、前記半導体素子の裏面を周囲を取り囲む封止樹脂から露出するように樹脂封止する工程と、
前記半導体素子の露出する裏面及び前記封止樹脂を、前記実装基板上の高さが略均一となるように研磨する工程と、
該研磨した表面を保護用フィルムで被覆する工程と、
隣接する前記半導体素子間の前記保護用フィルム、前記研磨した封止樹脂及び前記実装基板を切断して個片化し、略直方体形状の半導体装置を形成する工程とを含むことを特徴とする半導体装置の製造方法。
In the method of manufacturing a semiconductor device having a structure in which the electrode on the surface of the semiconductor element is bonded to the wiring on the mounting substrate in a face-down posture, and the back surface of the semiconductor element is exposed from the sealing resin surrounding the periphery of the semiconductor element.
Bonding a plurality of the semiconductor elements on the mounting substrate in a face-down posture;
Forming a dam portion around a semiconductor element mounting portion obtained by bonding the plurality of semiconductor elements;
Applying a resin onto the mounting substrate surrounded by the dam portion, and sealing the resin so that the back surface of the semiconductor element is exposed from the sealing resin surrounding the periphery; and
Polishing the exposed back surface of the semiconductor element and the sealing resin so that the height on the mounting substrate is substantially uniform;
Coating the polished surface with a protective film;
A step of cutting the protective film between the adjacent semiconductor elements, the polished sealing resin, and the mounting substrate into individual pieces to form a substantially rectangular semiconductor device. Manufacturing method.
JP2005006260A 2005-01-13 2005-01-13 Manufacturing method of semiconductor device Pending JP2006196657A (en)

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