CN104347542A - Five-side packaged CSP (chip scale package) structure and manufacturing process - Google Patents
Five-side packaged CSP (chip scale package) structure and manufacturing process Download PDFInfo
- Publication number
- CN104347542A CN104347542A CN201410504932.XA CN201410504932A CN104347542A CN 104347542 A CN104347542 A CN 104347542A CN 201410504932 A CN201410504932 A CN 201410504932A CN 104347542 A CN104347542 A CN 104347542A
- Authority
- CN
- China
- Prior art keywords
- wafer
- welding point
- passivation layer
- pressure welding
- bread
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000003466 welding Methods 0.000 claims abstract description 39
- 238000002161 passivation Methods 0.000 claims abstract description 32
- 238000004806 packaging method and process Methods 0.000 claims abstract description 24
- 239000013078 crystal Substances 0.000 claims abstract description 23
- 239000004020 conductor Substances 0.000 claims abstract description 20
- 239000003822 epoxy resin Substances 0.000 claims abstract description 16
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 16
- 235000008429 bread Nutrition 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 19
- 239000004033 plastic Substances 0.000 claims description 18
- 239000012528 membrane Substances 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 4
- 238000007731 hot pressing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 235000013339 cereals Nutrition 0.000 claims description 2
- 239000002245 particle Substances 0.000 abstract 4
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 238000005538 encapsulation Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a five-side packaged CSP (chip scale package) structure, which comprises a crystal particle, a press welding point, a passivation layer and a conducting body, wherein the press welding point is attached on the surface of the crystal particle, the conductor is attached on the press welding point, the passivation layer covers a region, not covered by the press welding point, on the upper surface of the crystal particle, and in addition, the passivation layer also covers a region, not covered by the conductor, of the press welding point. The five-side packaged CSP structure is characterized in that the bottom surface and the peripheral side surface of the crystal particle and the peripheral side surface of the passivation layer are packaged by epoxy resin. The invention also discloses a manufacturing process of the five-side packaged CSP structure. The five-side packaged CSP structure has the advantages that five sides (except the front side of a wafer) of a pipe core is packaged by the epoxy resin, the reliability of an electronic device and an integrated circuit can be favorably improved, in addition, WLCSP (wafer level chip scale package) packaging is adopted, and the miniaturization of an electronic product can be favorably realized. Meanwhile, the manufacturing process is simple and reliable.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, particularly five bread envelope CSP structure and manufacturing process
Background technology
Usually, semiconductor components and devices and integrated circuit start encapsulation after wafer frontside operation completes; The area of usual encapsulation is more much larger than the area of chip, and this runs counter to now miniaturized development trend; So developed wafer-level packaging (WLCSP) afterwards.
Common WLCSP only at the front projection (Bumping) of wafer or copper post (Cu Pillar) as line, whole wafer is all nude substantially, protects semiconductor element without any material, has the risk of reliability.
Summary of the invention
One of the object of the invention is the CSP structure providing a kind of five bread envelopes for above-mentioned the deficiencies in the prior art, its by five of tube core (except wafer frontside) with epoxy resin enclosed, be conducive to the reliability improving electronic device and integrated circuit, and be WLCSP encapsulation, be conducive to the miniaturization of electronic product.
Two of the object of the invention is the manufacturing process of the CSP structure providing above-mentioned five bread envelopes.
In order to realize foregoing invention object, the technical solution adopted in the present invention is as follows:
A kind of CSP structure of five bread envelopes, the electric conductor comprising crystal grain and be attached to the pressure welding point of described grain surface, passivation layer and be attached in described pressure welding point, described passivation layer covers described its upper surface and is not bonded the region of Vertex cover and described passivation layer also covers described pressure welding point not by the region that electric conductor covers, the bottom surface of described crystal grain and the surrounding side of surrounding side and passivation layer epoxy resin enclosed; The surrounding of described crystal grain and the epoxy resin of bottom surface are commaterials.
In a preferred embodiment of the invention, the described crystal grain back side is provided with a metal layer, and described metal layer is also encapsulated by plastic packaging layer; The surrounding of described crystal grain and the epoxy resin of bottom surface are commaterials.
The manufacturing process of the CSP structure of above-mentioned five bread envelopes, specifically comprises the steps:
1) wafer is prepared;
2) on the first surface of described wafer, pressure welding point and the passivation layer of some packaging and routings is adhered at interval, wherein passivation layer cover described wafer first surface on all regions except pressure welding point part covers described pressure welding point;
3) in each pressure welding point described, adhere to electric conductor and form some tube cores;
4) carry out reduction processing to the second face of wafer, upper paste scribing film after reduction processing by second of wafer, second of described wafer is relative two sides with first surface;
5) from the first surface direction of wafer to being formed with some tube cores and carrying out first time cutting at second wafer posting scribing film of wafer, but do not cut off described scribing film, the some tube cores be cut into still are attached on described scribing film, between some tube cores, form dicing lane;
6) in a supporting wafer, paste the two-sided glued membrane of one deck continuous print, then the electric conductor of some tube cores and passivation layer are attached on the another side of described two-sided glued membrane, make second of described wafer to face up;
7) remove scribing film, adopt in the dicing lane of epoxy resin on second of wafer and between tube core and form plastic packaging;
8) two-sided glued membrane and supporting wafer are peeled off;
9) carry out second time cutting from the first surface direction of wafer, cut off the plastic packaging between adjacent tube core, form the tube core of many.
In a preferred embodiment of the invention, in described step 3), it is described that in each pressure welding point described, adhere to the method that electric conductor forms some tube cores be the method growth nickel-gold layer adopting electric plating method to grow copper post, golden projection, tin ball in described pressure welding point or adopt chemical plating.
In a preferred embodiment of the invention, in described step 4) in, after reduction processing is carried out to the second face of wafer, carry out metallic deposition in the second face of wafer, form metal layer, then paste scribing film by described metal layer.
In a preferred embodiment of the invention, in described step 7) in, the mode forming plastic packaging is that the method with hot pressing or the method with printing form plastic packaging.
In a preferred embodiment of the invention, in described step 7) in, described plastic packaging carries out reduction processing to specific thickness.
In a preferred embodiment of the invention, in described step 9) in, second time cutting is the central cutout from described dicing lane.
Owing to have employed technique scheme, the present invention by five of tube core (except wafer frontside) with epoxy resin enclosed, be conducive to the reliability improving electronic device and integrated circuit, and be again WLCSP encapsulation, be conducive to the miniaturization of electronic product.Its manufacturing process is simple simultaneously, reliably.
Accompanying drawing explanation
Fig. 1 is the CSP structural representation of the embodiment of the present invention 1 five bread envelope.
Fig. 2 to Fig. 9 is the schematic diagram of the CSP structure tube core of the preparation embodiment of the present invention 1 five bread envelope.
Figure 10 is the CSP structural representation of the embodiment of the present invention 2 five bread envelope.
Figure 11 to Figure 18 is the schematic diagram of the CSP structure tube core of the preparation embodiment of the present invention 2 five bread envelope.
Embodiment
Embodiment 1
See Fig. 1, the CSP structure of a kind of five bread envelopes provided in figure, the electric conductor 40 comprising crystal grain 10 and be attached to the pressure welding point 20 on crystal grain 10 surface, passivation layer 30 and be attached in pressure welding point 20, passivation layer 30 cover crystal grain 10 upper surface be not bonded a little 20 cover regions and passivation layer 30 also covers pressure welding point 20 not by the region that electric conductor 40 covers, the bottom surface of crystal grain 10 and the surrounding side of surrounding side and passivation layer 30 are encapsulated by epoxy resin 50.
The manufacturing process of the tube core of this embodiment, specifically comprises the steps:
1) wafer is prepared;
2) see Fig. 2, on the first surface 110 of wafer 100, pressure welding point 20 and the passivation layer 30 of some packaging and routings is adhered at interval, wherein passivation layer 30 cover wafer 100 first surface 110 on all regions except pressure welding point 20 part covers pressure welding point 20;
3) see Fig. 3, each pressure welding point 20 adheres to electric conductor 40 and forms some tube cores; Concrete grammar is the method growth nickel-gold layer adopting electric plating method to grow copper post, golden projection, tin ball in described pressure welding point or adopt chemical plating.
4) see Fig. 4, carry out reduction processing, paste scribing film 200 after reduction processing by the second face 120 of wafer 100 to the second face 120 of wafer 100, the second face 120 of wafer 100 is relative two sides with first surface 110;
5) see Fig. 5, from first surface 110 direction of wafer 100 to being formed with some tube cores and the wafer posting scribing film 200 in the second face 120 of wafer 100 carries out first time cutting, but do not cut off scribing film 200, make the some tube cores be cut into still be attached on scribing film 200, between some tube cores, form dicing lane 300;
6) see Fig. 6, a supporting wafer 400 is pasted the two-sided glued membrane 500 of one deck continuous print, then the electric conductor 40 of some tube cores and passivation layer 30 is attached on the another side of two-sided glued membrane 500, make the second face 120 of wafer 100 upward;
7) see Fig. 7, remove scribing film 200, adopt in the dicing lane of same epoxy resin 600 on the second face 120 of wafer 100 and between tube core and form plastic packaging by the method for hot pressing or by the method for printing, then reduction processing is carried out to specific thickness to plastic packaging.
8) see Fig. 8, two-sided glued membrane 500 and supporting wafer 400 are peeled off;
9) see Fig. 9, carry out second time cutting from first surface 110 direction of wafer 100 along the central authorities of dicing lane, cut off the plastic packaging between adjacent tube core, form the tube core of many.
Embodiment 2
See Figure 10, the CSP structure of a kind of five bread envelopes provided in figure, the electric conductor 40 comprising crystal grain 10 and be attached to the pressure welding point 20 on crystal grain 10 surface, passivation layer 30 and be attached in pressure welding point 20, passivation layer 30 covers crystal grain 10 upper surface and is not bonded a little 20 regions covered and passivation layer 30 also covers pressure welding point 20 not by region that electric conductor 40 covers, crystal grain 10 back side is provided with a metal layer 60, and the surrounding side of the bottom surface of metal layer 60 and the surrounding side of crystal grain 10 and passivation layer 30 is encapsulated by epoxy resin 50.
The manufacturing process of the tube core of this embodiment, specifically comprises the steps:
1) wafer is prepared;
2) see Figure 11, on the first surface 110 of wafer 100, pressure welding point 20 and the passivation layer 30 of some packaging and routings is adhered at interval, wherein passivation layer 30 cover wafer 100 first surface 110 on all regions except pressure welding point 20 part covers pressure welding point 20;
3) see Figure 12, each pressure welding point 20 adheres to electric conductor 40 and forms some tube cores; Concrete grammar is the method growth nickel-gold layer adopting electric plating method to grow copper post, golden projection, tin ball in described pressure welding point or adopt chemical plating.
4) see Figure 13, after reduction processing is carried out to the second face 120 of wafer 100, carry out metallic deposition in the second face 120 of wafer 100, form metal layer 700, then paste scribing film 200 by metal layer 700.Second face 120 of wafer 100 is relative two sides with first surface 110;
5) see Figure 14, from first surface 110 direction of wafer 100 to being formed with some tube cores and the wafer posting scribing film 200 in the second face 120 of wafer 100 carries out first time cutting, but do not cut off scribing film 200, make the some tube cores be cut into still be attached on scribing film 200, between some tube cores, form dicing lane 300;
6) see Figure 15, a supporting wafer 400 is pasted the two-sided glued membrane 500 of one deck continuous print, then the electric conductor 40 of some tube cores and passivation layer 30 is attached on the another side of two-sided glued membrane 500, make the second face 120 of wafer 100 upward;
7) see Figure 16, remove scribing film 200, adopt in the dicing lane of same epoxy resin 600 on the second face 120 of wafer 100 and between tube core and form plastic packaging by the method for hot pressing or by the method for printing, then reduction processing is carried out to specific thickness to plastic packaging.
8) see Figure 17, two-sided glued membrane 500 and supporting wafer 400 are peeled off;
9) see Figure 18, carry out second time cutting from first surface 110 direction of wafer 100 along the central authorities of dicing lane, cut off the plastic packaging between adjacent tube core, form the tube core of many.
Claims (8)
1. the CSP structure of a bread envelope, the electric conductor comprising crystal grain and be attached to the pressure welding point of described grain surface, passivation layer and be attached in described pressure welding point, described passivation layer covers described its upper surface and is not bonded the region of Vertex cover and described passivation layer also covers described pressure welding point not by region that electric conductor covers, it is characterized in that, the bottom surface of described crystal grain and the surrounding side of surrounding side and passivation layer epoxy resin enclosed; The surrounding of described crystal grain and the epoxy resin of bottom surface are commaterials.
2. the CSP structure of five bread envelopes as claimed in claim 1, it is characterized in that, the described crystal grain back side is provided with a metal layer, and described metal layer is also encapsulated by plastic packaging layer; The surrounding of described crystal grain and the epoxy resin of bottom surface are commaterials.
3. a manufacturing process for the CSP structure of five bread envelopes, is characterized in that, specifically comprise the steps:
1) wafer is prepared;
2) on the first surface of described wafer, pressure welding point and the passivation layer of some packaging and routings is adhered at interval, wherein passivation layer cover described wafer first surface on all regions except pressure welding point part covers described pressure welding point;
3) in each pressure welding point described, adhere to electric conductor and form some tube cores;
4) carry out reduction processing to the second face of wafer, upper paste scribing film after reduction processing by second of wafer, second of described wafer is relative two sides with first surface;
5) from the first surface direction of wafer to being formed with some tube cores and carrying out first time cutting at second wafer posting scribing film of wafer, but do not cut off described scribing film, the some tube cores be cut into still are attached on described scribing film, between some tube cores, form dicing lane;
6) in a supporting wafer, paste the two-sided glued membrane of one deck continuous print, then the electric conductor of some tube cores and passivation layer are attached on the another side of described two-sided glued membrane, make second of described wafer to face up;
7) remove scribing film, adopt in the dicing lane of epoxy resin on second of wafer and between tube core and form plastic packaging;
8) two-sided glued membrane and supporting wafer are peeled off;
9) carry out second time cutting from the first surface direction of wafer, cut off the plastic packaging between adjacent tube core, form the tube core of many.
4. the manufacturing process of the CSP structure of five bread envelopes as claimed in claim 1, it is characterized in that, in described step 3), it is described that in each pressure welding point described, adhere to the method that electric conductor forms some tube cores be the method growth nickel-gold layer adopting electric plating method to grow copper post, golden projection, tin ball in described pressure welding point or adopt chemical plating.
5. the manufacturing process of the CSP structure of five bread envelopes as claimed in claim 1, is characterized in that, in described step 4) in, after reduction processing is carried out to the second face of wafer, carry out metallic deposition in the second face of wafer, form metal layer, then paste scribing film by described metal layer.
6. the manufacturing process of the CSP structure of five bread envelopes as claimed in claim 1, is characterized in that, in described step 7) in, the mode forming plastic packaging is that the method with hot pressing or the method with printing form plastic packaging.
7. the manufacturing process of the CSP structure of five bread envelopes as claimed in claim 1, is characterized in that, in described step 7) in, described plastic packaging carries out reduction processing to specific thickness.
8. the manufacturing process of the CSP structure of five bread envelopes as claimed in claim 1, is characterized in that, in described step 9) in, second time cutting is the central cutout from described dicing lane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410504932.XA CN104347542A (en) | 2014-09-26 | 2014-09-26 | Five-side packaged CSP (chip scale package) structure and manufacturing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410504932.XA CN104347542A (en) | 2014-09-26 | 2014-09-26 | Five-side packaged CSP (chip scale package) structure and manufacturing process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104347542A true CN104347542A (en) | 2015-02-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410504932.XA Pending CN104347542A (en) | 2014-09-26 | 2014-09-26 | Five-side packaged CSP (chip scale package) structure and manufacturing process |
Country Status (1)
| Country | Link |
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| CN (1) | CN104347542A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105405819A (en) * | 2015-11-06 | 2016-03-16 | 南通富士通微电子股份有限公司 | Metallized wafer level packaging method |
| CN110223924A (en) * | 2019-07-15 | 2019-09-10 | 珠海格力电器股份有限公司 | A kind of wafer-level packaging method and wafer |
| CN113131890A (en) * | 2019-12-30 | 2021-07-16 | 中芯集成电路（宁波）有限公司 | Manufacturing method of packaging structure |
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| JPH10335567A (en) * | 1997-05-30 | 1998-12-18 | Mitsubishi Electric Corp | Semiconductor integrated-circuit device |
| GB2345383A (en) * | 1998-12-29 | 2000-07-05 | Hyundai Electronics Ind | A semiconductor package |
| CN101179056A (en) * | 2006-11-08 | 2008-05-14 | 海力士半导体有限公司 | Wafer level package configured to compensate size difference in different types of packages |
| CN102903642A (en) * | 2011-07-29 | 2013-01-30 | 万国半导体(开曼)股份有限公司 | Chip scale packaging method capable of encapsulating bottom and periphery of chip |
| CN103928417A (en) * | 2014-04-18 | 2014-07-16 | 江阴长电先进封装有限公司 | Low-cost wafer-level CSP method and structure |
-
2014
- 2014-09-26 CN CN201410504932.XA patent/CN104347542A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10335567A (en) * | 1997-05-30 | 1998-12-18 | Mitsubishi Electric Corp | Semiconductor integrated-circuit device |
| GB2345383A (en) * | 1998-12-29 | 2000-07-05 | Hyundai Electronics Ind | A semiconductor package |
| CN101179056A (en) * | 2006-11-08 | 2008-05-14 | 海力士半导体有限公司 | Wafer level package configured to compensate size difference in different types of packages |
| CN102903642A (en) * | 2011-07-29 | 2013-01-30 | 万国半导体(开曼)股份有限公司 | Chip scale packaging method capable of encapsulating bottom and periphery of chip |
| CN103928417A (en) * | 2014-04-18 | 2014-07-16 | 江阴长电先进封装有限公司 | Low-cost wafer-level CSP method and structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105405819A (en) * | 2015-11-06 | 2016-03-16 | 南通富士通微电子股份有限公司 | Metallized wafer level packaging method |
| CN105405819B (en) * | 2015-11-06 | 2018-12-11 | 通富微电子股份有限公司 | Metallize wafer-level packaging method |
| CN110223924A (en) * | 2019-07-15 | 2019-09-10 | 珠海格力电器股份有限公司 | A kind of wafer-level packaging method and wafer |
| CN113131890A (en) * | 2019-12-30 | 2021-07-16 | 中芯集成电路（宁波）有限公司 | Manufacturing method of packaging structure |
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Application publication date: 20150211 |
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