TW201232673A - Partially patterned lead frames and methods of making and using the same in semiconductor packaging - Google Patents

Partially patterned lead frames and methods of making and using the same in semiconductor packaging Download PDF

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Publication number
TW201232673A
TW201232673A TW100105312A TW100105312A TW201232673A TW 201232673 A TW201232673 A TW 201232673A TW 100105312 A TW100105312 A TW 100105312A TW 100105312 A TW100105312 A TW 100105312A TW 201232673 A TW201232673 A TW 201232673A
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TW
Taiwan
Prior art keywords
wafer
lead
lead frame
package
electrical
Prior art date
Application number
TW100105312A
Other languages
Chinese (zh)
Other versions
TWI397964B (en
Inventor
Antonio Romarico S San
Michael H Mckerreghan
Anang Subagio
Allan C Toriaga
Original Assignee
Unisem Mauritius Holdings Ltd
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Publication date
Priority claimed from US13/009,362 external-priority patent/US8236612B2/en
Application filed by Unisem Mauritius Holdings Ltd filed Critical Unisem Mauritius Holdings Ltd
Publication of TW201232673A publication Critical patent/TW201232673A/en
Application granted granted Critical
Publication of TWI397964B publication Critical patent/TWI397964B/en

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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Description

1 201232673 六、發明說明： 【發明所屬之技術領域】 本發明-般而言係關於電子封裝，且更特定而言，係關 於一部分圖案化之引線框架及製作與使用其之方·法。該部 分圖案化之引線框架比習用引線框架牢固且穩定。該部分 圖案化之引線框架之堅固會改良製造引線框架封裝之製= 並增強最終產品之總可靠性。引線框架亦為裝置整合及增 加之功能性提供一高度靈活性。 本申請案係於2010年9月3曰提出申請之美國專利申請案 序列號12/875,248之一部分接續申請案，美國專利申請案 序列號12/875,248係於2007年10月24日提出申請之申請案 序列號11/877,732(現在的美國7,790,500)之一接續案，美 國7,790,500係於2006年10月27日提出申請之申請案序列號 11/553,664(現在的美國7,799,611)之一部分接續案，美國 7,799,61 1係於2005年8月4日提出申請之申請案序列號 11/197,944(現在的美國7,622,332)之一接續案，美國 7，622,3 32係於2004年8月10曰提出申請之申請案序列號 10/916,093(現在的美國7，129，116)之一接續案，美國 7,129,116係於2002年4月29日提出申請之申請案序列號 10/134,882(現在的美國6,812,552)之一接續案，此等全部 申請案以全文引用之方式併入本文中。 【先前技術】 在製作使用引線框架之電子封裝中，存在若干製程步 驟’其使引線框架經歷機械及熱應力。目前引線框架之較 153285.doc 201232673 細小幾何形狀以及半導體晶片上的電路之不斷增加之整合 性已產生將更大應力置於引線框架上之處理。精細組態之 引線框架通常類似於極精緻的刺繡或模板狀金屬結構，其 傾向於輕易彎曲、斷裂、毀形及變形。（參見圖“及^)。 此類習用引線框架係在行業中用以建立各種晶片封裝，包 含線接合及覆晶（FC)封裝。（參見圖23至2d以及圖“至 3b)。 習用引線框架一般缺乏結構剛性。引線框架的指狀部分 可相當脆弱且難以固持在適當位置。此導致組裝製程中的 處理缺陷、損壞及扭曲以及複雜線接合情形。因此，必須 最佳化接合參數以補償接合製程期間的引線框架跳動。未 能最佳化接合參數以補償引線框架之機械不穩定性可產生 較差的接合黏著性，並因此產生較差品質及較差可靠性之 接合。 典型引線框架之較大金屬板部分自一中心部分延伸， 該中心部分稱為晶片接收區域，且亦稱為晶片墊。晶片通 常係在背側向下之情形下附接至該接收區域，並且前側面 向上而定位，其中端子係以周邊形式定位於晶片之周長 上，或以一陣列形式定位於晶片之表面上方。該接收區域 通常具有約5 mmx5 mm之尺寸，並且自晶片墊區域向外延 伸之引線具有約1 〇 mm長xl mmtx〇 2 mm厚之典型尺寸。 通常藉由一真空夾頭及機械夾具來固持引線框架。必須針 對不同大小及形狀的引線框架來改裝夾頭及夾具。本發明 緩解此問題。 153285.doc 201232673 先前技術尚未顯示可承受目前半導體封裝製程中遇到的 應力以及可採用成本效益方式加以製造之任何引線框架。 本發明藉由以下方式達成此目的：提供一部分圖案化之弓丨 線框架’其不僅改良引線框架本身之可製造性，而且改良 自其形成之電子封裝之整體性及可靠性。本發明亦解決習 用引線框架不能提供之對增加之裝置複雜度之一持續需 求，諸如高I/O計數、多晶片設計、系統級封裝（system h package)以及選路靈活性。 電腦晶片之大小亦持續縮小。對於具有特定尺寸之一引 線框架而言，使用具有不斷更小之大小之晶片致使晶片端 子與電著陸點之間之線接合變得更長。對更長線之需要可 在處理期間造成線搖晃且很有可能使某些類型之晶片尺寸 封裝有線短路之傾向。 增加線長度亦影響單元成本。通常，使用金製線將電腦 晶片連接至著陸點。在過去的五年裏金的價格已幾乎翻至 二倍，且隨著晶片大小減小，金線量增加，從而對晶片封 裝製造商造成了重大的價格壓力。雖然經塗佈線係金製線 之一替代性方案，但其要昂貴2至3倍。 有時可調整引線在引線框架上之佈置，但修改引線佈置 之能力相依於引線框架之組態且取決於製造商之生產能 力 固疋的引線位置很有可能在接合線時需要專門的迴 路技術，從而減緩了接合製程而未完全消除線短路之可能 性。 一些電腦封裝需要無線電頻率屏蔽（RF屏蔽）以在操作時 I53285.doc 201232673 防止電磁场干擾封裝之正常運行。層壓式裝置通常具有此 RF屏蔽，但其係—極昂貴的特徵。對一濕敏性裝置可曝露 至室溫條件之時間量有行業公認之電子學標準（「濕敏位 準」）許夕層屋製品額定為MSL 3。在msl 3，須在自一 濕氣障蔽袋移除之後的168個小時内安裝並回焊組件。 通申4吏用鑛切來單個化引線框架以形成個別晶片尺寸封 裝且刀切割成引線框架以曝露預期金屬層以供連接至特 定特徵，諸如ΕΜΙ(電磁干擾）屏蔽㈣。然而，多次使用 一鋸可影響生產率及生產良率。由於曝露之金屬表面通常 厚5至18 μηι，因此對鋸切製程之一高位準控制對於確保恰 當之刀片高度係重要的。 【發明内容】 引線框架係由具有一頂部表面及一底部表面之一膜組 成。該膜之一第一區係自該頂部表面部分圖案化但並非完 王透過該膜至該底部表面。未自該頂部表面圖案化之該膜 之一第二區形成用以支撐一積體電路（IC)晶片之一晶片接 收區域，以及用以提供至該IC晶片的電連接之複數個引線 觸點。該第一區在該膜中形成溝渠並建立一網式結構，其 與未自該頂部表面部分圖案化之該第二區互連。本發明亦 係關於製造部分圖案化之引線框架之一方法及利用該等引 線框架製作之電子封裝。本發明之引線框架因其網狀或網 式結構而具有經改良之結構剛性。 根據本發明，一金屬膜（引線框架欲自其形成）之頂部表 面係首先使用標準光微影技術或類似技術而圖案化以確定 153285.doc 201232673 將對應於一晶片接收區域及引線之區域之外形。在下一步 驟中’在具有該外形之區域外面的該膜之第一區中自該膜 之頂部表面部分透過下伏膜之厚度來執行蝕刻，以在該膜 中建立一引線框架圖索。在部分圖案化之後，未自該頂部 表面圖案化之剩餘區域形成一第二區，其將用作沿該頂部 表面之一晶片接收區域及引線。該第一區在該膜之頂部表 面下面形成一凹入網式區。該第一區之網式結構將引線部 分彼此連接並與該晶片接收區域連接。因此，部分圖案化 膜看起來類似於網式腳並保持其剛性及強度，因此其可承 受後續製程步驟之力。特定而言，部分圖案化之引線框架 可承受在線接合及囊封製程期間所遇到的力。在某些實施 例中，可自該第二區之相同部分形成該晶片接收區域及電 引線（舉例而言，在電引線支撐積體晶片以及提供至其的 電連接之情形下）。 本發明亦提供使用部分圖案化之引線框架製造複數個電 子封裝之一獨##法。财法涉及具有一頂冑表面及一底 -ρ表面之一膜。在該第一區+，該膜係自該頂部表面但並 非完全透過該膜至該底部表面而部分圖案化。該膜上未自 P表面。卩为圖案化之剩餘第二區形成複數個部分圖案 化之引線框架。該等引線框架中之每-者因此具有用以支 撑積體電路（IC)晶片之一晶片接收區域以及用以提供至 該1C晶片之電連接之複數個電引線。 3之該第-區形成—網式結構，其將每—引線框架之 該等晶片接收區域與電引線互連。該第一區亦在該膜之街 153285.doc 201232673 道料分中將複數個引線框架彼此連接。 提供複數個4，每—晶片具有複數個電端子 一對應的引線框架。每-晶片係附接至-對應引線框竿上 之曰曰片接收區域且—電連接形成於每-個晶片之至少一個 線框架之電引線中之-者之間。然後，在引線框 表及该膜之街道形部分上方施加—囊封材料以完全覆蓋該 膜之頂部…旦洪乾該囊封材料，則在該第-區中自該膜 • p表面執仃一背面圖案化製程以移除網式結構以及該 膜之街道料分。_單個化安置於㈣之㈣形部分上 方之該囊封材料以形成個別封裝。 ,在一較佳實施例中，該方法包含在-區塊/視窗圖案之 形式的矩陣中將引線框架形成至該膜中，且涉及生產晶片 尺寸封裝。 右干個優點係由本發明之部分圖案化之引線框架引起。 引線框架之扁平及實心的未經㈣底部表面在線接合製程 '用作極佳的散熱片。此提供均句的熱轉移以達成較 ^且較》的接合品質。另外，該實心結構為一通用真空 員提ί、連續表面以固持引線框架，從而在後續製程步 /門使Β曰片附接製程更穩定且使引線更牢固。消除難以 /夾緊引線框架之外部邊緣以在不需要轉換之情形下允許進 "車歹J矩陣引線框架设計及處理。由於部分圖案化之引 線框架之底部侧係一扁平連續表面，因此一通用真空夾頭 可用以固持許多不同大小的框架。此移除每次在封裝製程 中運用不同尺寸之一引線框架時必須改裝真空夾頭之複雜 153285.doc 201232673 性。而且’不進一步需要夾緊。使用一通用真空夾頭且消 除夾緊使得在第二區上能夠構造雙或三列交錯引線以達成 較高引線數。 本發明係關於不僅適應線接合晶片而且適應焊料凸塊覆 晶之部分圖案化之引線框架。另外，本發明教示以下方 法：使用部分圖案化之引線框架來製作使用線接合之經蝕 刻引線框架封裝（ELP)、具有覆晶之ELP(ELPF)、以及具有 著陸點柵格陣列（LGA)墊之ELP或ELPF以形成經蝕刻著陸 點柵格陣列（ELGA)封裝，如本發明之實施例中進一步闡 述。 覆晶（FC)技術係朝一晶片上之電端子至下一級封裝，即 至一陶瓷或塑膠基板，或至稍後連結至該基板之一晶片微 載體之完全自動化連結之又一個步驟。僅稍大於該晶片本 身之該微載體現在稱為晶片尺寸封裝（csp)。FC技術自膠 帶自動化接合（TAB)發展而來，該接合依次使其原 點處於 線接s (WB)中。然而在WB及TAB中，將晶片定位於其背 表面上且與疋位於其頂部表面上之周長周圍之端子電連 接’在FC技術中，倒轉晶片之定向。將晶片面向下而放置 且將晶片之背侧向上定向。此覆晶定向具有-重大優點， 此乃因其將電功能集中在晶片之下側上，&而使頂側保持 自由以用於進行一尚度有效率的熱轉移設計。 在FC製程中’用晶片之表面上方之不同類型之凸塊來密 閉晶片端子或接合墊’ &中可在一區域陣列、周邊圖案或 其他圖案中展開該等圖案。可用以下方式將晶片附接至下 153285.doc 201232673 一級：a)FC附接至一引線框架；b)FC附接至稱作—插入物 之層/基板，以對一引線框架上之連接間距進行重新選 路；c)FC附接至一引線框架上之一預附接插入物；或d)使 用包含晶片回焊方法之習用技術將FC附接至一印刷電路 板。 使用習用技術之晶片附接在製作QFN(四方扁平無引線） 封裝及其衍生物（諸如VFQPF-N)中施加至QFN引線框架時 變知尤其困難。此乃因習用引線框架一般缺乏結構剛性。 引線框架之指狀部分可相當脆弱且難以固持在一個精確位 置中。此導致組裝製程中的處理缺陷、損壞及扭曲以及複 雜的晶片接合情形^ PC連結製程需要將凸塊焊料頭與懸掛 物及引線框架之脆弱引線端精確對準。此外，濕潤的焊料 端須在透過浑料回焊製程放置之後保持其位置。因此，必 須最佳化回焊參數以補償晶片連結期間的引線框架跳動， 其在未得到適當完成之情形下可造成較差連結部，並因此 造成最終產品之較差品質及較差可靠性。 通常在實務上藉由以下方式來形成習用模板狀引線框 架：圖案化-金屬條帶或金屬膜上之一光阻劑，並透過圖 案而蝕刻以形成自晶片接收區域向外延伸之指狀引線。亦 習慣於使用指狀物之間&「連杆」以使手指在各個製程步 驟期間保持隔開，如圖M3b所顯示。本發明藉由替代一 :莫板狀引線框架而形成一網狀部分圖案化之引線框架來緩 解引線框架缺乏結構剛性之問題。 根據本發明之—方法，自欲變為1線《之膜之-個 153285.doc -11- 201232673 側執行形成-半導體封裝之所有主要製程步驟。另一側 (即底部側）在—表面（諸如一 A空夹頭之表面）上保持扁平 且未接觸。此包含囊封及密封該封裝之部分形成之前側之 步驟。纟70成囊封’則對底部表面進行背面触刻以選擇 性地移除將引皮此連接且與該晶片#收區域連接之網式 部分。在使該晶片與該晶片接收區域處一晶片墊進行背面 接合且藉助線接合而進行與晶片端子之電連接之ELp情形 下，透過蝕刻來切斷所有的中間網式部分以使晶片墊及處 於線接合端之引線觸點現在係藉由圍繞該晶片、該等線以 及線接合觸點區域之前表面之模製材料而彼此隔離。然 而，在ELPF封裝之情形下，僅透過蝕刻切斷將引線彼此 連接之網式部分，此乃因與晶片焊料頭凸塊連接之引線本 身提供與下一級封裝之電連接。 透過網式部分中之鋸厚度或街道形而移除嵌入之金屬具 有若干優點，其包含消除在整個引線框架結構中傳播之鋸 力，並因此防止金屬-塑膠介面處之分層。而且，透過背 面触刻進行的電隔離達成任何雜切或單個化或者因彼事件 在任何進一步的處理步驟之前的條帶測試。在背面圖案化 之後’然後可透過沈浸錫浸溃或無電鍍鎳鍍覆藉助任一數 目個可焊材料以閃光方式完成底部表面上的剩餘及曝露金 屬部分。ELGA封裝使用ELPF封裝之pc，然而將LGA墊用 於與下一級封裝之連接。 為在製造期間防止模製材料與封裝之其他組件之間的任 一分離’本發明亦教示如何在部分經蝕刻之引線框架之凹 153285.doc •12· 201232673 入網式部分之曝露的垂直壁上（諸如在引線之側壁上）形成 鎖定特徵，該等鎖定特徵將與模製材料（諸如一樹脂）接 觸。作為一替代性方案，亦教示在晶片墊及引線觸點之邊 緣上形成「唇狀物」以便捕獲每一唇狀物下面之模製材 料，從而使模製材料難以自配合表面分離。 從前文將明白部分經蝕刻之引線框架提供結構與附帶剛 性及強度之聯合以恰當地承受在製作電子封裝中之各個製 造製程之應力及應變。由於此等獨特機械特性，因此一部 分經蝕刻之引線框架封裝亦可承受線至封裝底部之超聲波 接合之嚴密以與下一級封裝連接，此迄今尚不可能採用習 用塑膠封裝來達成。 本發明之一個態樣提供用於形成電子封裝之一方法。該 方法包括形成具有選擇性地預鍍覆之頂部及底部表面之部 分經蝕刻之引線框架之區塊。該等引線框架包括網式部分 且由街道形部分而彼此分離。 一第一晶片集附接至引線框架上之晶片墊區域。為方便 (見支撐一積體晶片（1C)或一 1C晶片所黏附至的一引線 框架之區域將稱為—晶片塾區域或—晶片接收區域，無論 此區域係用於線接合晶片、覆晶還是此項技術中已知的任 何：他類型之晶片。可使用一黏合劑、樹脂或與兩種成分 相夺的其他材料將此等第一晶片集與晶片接收區域進行背 面接σ冑例而言，可使用環氧樹脂、非導電環氧、膠帶 或焊料膏來元成該背面接合。其他適合材料在此項技術中 習知。 153285.doc -13- 201232673 然後將-第二晶片集晶粒堆疊至對應的第一晶片集之頂 部上。在將第二晶片集晶粒堆疊至第一晶片集之頂部上之 後，可將一個或多個另外晶片集晶粒堆疊至第二晶片集之 頂部上，從而提供由疊加於彼此頂部之二個、三個或更多 個晶片組成之封裝。在本發明之某些實施例中，並非來自 第一晶片集之所有晶片均可具有晶粒堆疊於其上的晶片。 在此等實施例中，引線框架將具有一個或多個單個（未堆 疊）晶片及一個或多個晶粒堆疊晶片集。 在第晶片中之每一者之端子與對應引線框架之電引線 部分之間形成電連接。電引線部分係與晶片墊區域電分 離。亦形成至第二或額外晶片集的電連接。在已將晶片晶 粒堆疊於引線框架上之後，可同時形成電連接。另一選擇 為，第一晶片集可附接於引線框架並與其電連接，且隨後 第二或額外晶片集可晶粒堆疊至第一晶片集之頂部並與引 線框架電連接。 在將晶片晶粒堆疊至引線框架上並與引線框架電連接之 後，然後藉由在引線框架及分離引線框架之街道形部分上 方施加一囊封材料來囊封引線框架。在囊封之後，對引線 框架之底部表面進行背面圖案化以移除網式部分以及街道 形部分。彳藉由#一方便的方法（諸如藉由#刻）來執 面圖案化。 右將一預鍍覆材料施加於引線框架之底部（例如用作一 光阻劑），則可在背面圖案化之後移除此預鍍覆材料。 可以在背面圖案化之後於引線框架之底部上形成隔離圖 153285.doc • 14· 201232673 案。可藉助一材料來鍍覆或塗佈此等隔離圖案以保護其表 面。適合材料之實例包含無電鍍Ni/沈浸Au '沈浸Ag、沈 浸sn、一有機表面保護劑（0SP)及其他可焊材料。此完成 或鍍覆步驟促進提供額外穩定性至晶片封裝之背表面且可 ' 切至電腦板、插座或放置晶片封裝之其他位置的經改良 之連接性。 早個化安置於#f if形部分上方之囊封材料以形成個別晶 片尺寸封裝以用於半導體行業中之各個應用。可使用可用 以分離個別晶片封裝之任何方便構件來完成單個化。在一 個實施例中，可藉由使用一鑛或磨耗性喷水來切開囊封物 而執行單個化。 本發明之另—態樣提供包括—晶片墊區域及引線且具有 變更之-引線框架。變更可視為定位在引線框架之結構特 徵上之元件，其在與不具有變更之引線框架相比時提供一 增加的表面積。變更促進在單個化之前施加於引線框架上 方之一囊封材料之保持力。變更可以係任一形式，諸如引 線框架之電引線上之切口。 第二晶片f中之每一者可具有與對應的第一晶片相同之 纟小或-不同之大小。另外，附接於引線框架之第一晶片 . 帛並不需要全部相同，且因此此等第一晶片集可包含較大 及較小的明#通吊’最大晶片將附接於晶片墊區域而不 斷更小的晶片將晶粒堆疊於此晶片之頂部上。在替代性實 施例中，最大晶片將不附接於該晶片塾區域而將在晶粒堆 疊晶片之中間或頂部上。經晶粒堆疊之晶片亦可全部係同 I53285.doc 201232673 一大小0 可使用此項技術中習知之任何方便構件將第二及額外晶 片集堆疊並接合至對應第一晶片以使晶片彼此接合。舉例 而言，可使用一非導電環氧樹脂或一絕緣材料（諸如一膠 帶）來堆疊晶片以防止晶片之間或中間的干擾或電移動。 在另一實施例中，可使用一膠帶、導電黏合劑或一導電環 氧樹脂將第二晶片集黏附至對應第一晶片。 使用習知技術將第一晶片集電連接至引線框架。舉例而 吕，可使用線接合技術或使用覆晶技術將該等晶片連接至 引線框架。 可在將第二晶片集晶粒堆疊至第一晶片上之前將第一晶 片集電連接至引線框架。另一選擇為，可在將第二或額外 晶片集晶粒堆疊至對應第一晶片集上之後將第一晶片集電 連接至引線框架。可藉由將該晶片上的端子連接至延伸至 S曰片區域之電引線之端部分來完成形成電連接之步驟。可 使用任何方便或適當技術形成該等電連接。舉例而言，若 晶片係線接合晶片，則可使用諸如熱聲波接合之線接合技 '标來形成連接β將通常使用覆晶技術將覆晶電連接至引線 才[架線接合與覆晶技術之組合係亦在本發明之範疇内。 田將覆晶直接附接至引線框㈣，對應引線可經鑛覆或未 經鍍覆。 2 一晶片集接收電力以執行計算或其他功能。此第二晶 曰卞可電連接至對應第-晶片、引線框架或兩者。在各個 /、引線框架之間形成之該等連接將取決於手邊的具體 153285.doc 201232673 情形及所形成之特定電子封裝。 树明中所使用之晶片類型將亦取決於特定情況。舉例 而。，曰曰片可以係線接合晶片、覆晶或適用於電子晶片封 裝之任何其他種類之晶片。在一個實施例中，第一晶片集 包括覆晶或線接合晶片或兩I，且第二及任何後續晶片集 包括線接合晶片。該等晶片中之任—者亦可包括—半導體 裝置。 根據本發明藉由晶粒堆4晶片形成之電子封裝將在囊封 及單個化之後具有一特定高度。為減小電子封裝之高度， 晶片塾區域可凹人以減小所獲得之封裝之高度。亦即^可 藉助-降低的内部來形成引線框架區域上之晶片墊以便允 許晶.片擬合於此區域内且從而提供具有一降低高度 片。 -日日 .根據所揭示方法而形成之電子封裝係牢固且穩定的。為 在應力條件及製造期間提供封裝之進一步的可靠性，可使 用變更來增加囊封物之保持力。變更可沿晶片墊之周邊、 引線或兩者而定位。 底部引線框架之選擇性預鍍覆可用以界定引線框架之底 部特徵。此選擇性預錄覆可在引線框架之項部及底部表面 兩者上提供-類似圖案。可使用任何方便材料來^成選擇 性預錄覆。在-個實施例中，可使用—NiPdAu或銀合金來 預鍍覆引線框架。 在囊封之後，晶粒堆疊晶片將藉由一固體囊封物所圍繞 以防止晶片與引線框架之間的電連接移動或弱化。可藉由 153285.doc •17* 201232673 囊子物來覆蓋整個堆疊晶片集。另—選擇為，最高晶片 之y部分（諸如一背面或頂部表面）可在囊封之後保持曝 露舉例而言，最高晶片之表面可透過囊封物而曝露且晶 片之剩餘。p分嵌人於囊封物甲。以此方式，可減少囊封物 量而不引人注目地影響最終封裝之穩定性。另夕卜，若最高 晶^之頂部或背表面包含朗資訊，則可形成封裝以便此 資訊並^藉由囊封物所覆蓋且可輕易地由使㈣觀察。 :先刖所陳述，晶片及晶粒堆疊晶片電附接至引線框架 以提供電力至晶片。除了諸如覆晶或線接合晶片之晶片以 外’其他元件亦可連接至引線框架。此等額外元件可以係 為裝提供增加支撐或穩定性之結構元件。額外元件亦可 係：兀件’其支撐晶片或晶片封裝之功能。此等額外元件 之貫例係無源組件、隔離墊、電源環、接地環及選路。晶 片封裝中之此等及其他結構S件或電元件之任何組態係在 本發明之範疇内。 囊封材料可餘何種類之物f，其可施加至晶粒堆疊晶 片且凝固以形成一耐久固體。在一個實施例中，囊封物可 係圍繞晶片並硬化以產生晶片之一液體樹脂。一囊封物之 -實例係-環氧樹脂。該囊封物通常將係一非導電物質以 防止囊封之材料内之電信號從-個晶片跨越至另-晶片。 當額外元件包括電元件時，此等元件可直接或間接電連 接至引線框架。此等額外元件亦可電連接至封裝中之—個 或多個晶片’且此等實施例將取決於正形成之具體晶片尺 寸封裝。 153285.doc 201232673 可，用此項技術中習知之生產技術來形成弓丨線框架。舉 例而吕’可使用化學蝕刻、衝壓或壓印技術來形成引線框 架。 可用一材料（諸如一導電材料）之一膜來塗佈或部分塗佈 引線框架。與沒有此一膜之一引線框架相比，該膜可在引 二框架與附接至該引線框架之晶片之間提供一增加的電通 里在個貫施例中，該膜係由銅或一銅合金形成。雖然 該膜將必須足夠厚以具有機械穩定性，但通常該膜之厚度 並不重要。在一個實施例中，該膜之厚度係大於或等於約 0.05 mm。 本發明之另一態樣提供包括一晶片墊區域及引線之一引 線框架。引線框架具有變更’其提供覆蓋引線框架之一囊 封材料之一增加的保持力。晶片將通常係附接於晶片墊區 域且與引線電連接。 變更可經結構設計及組態以為一囊封物之保持力提供一 增加的表面積《變更可採取提供囊封物之一增加的保持力 之任何類型之形式。舉例而言，變更可採用定位在引線框 架或引線框架之一部分上之一空腔、低降或切口之形狀。 變更亦可出現在上面形成至晶片之電連接的引線上。 支更可在引線框架之任何部分上。舉例而言，變更可在 晶片墊區域之周邊或引線或兩者上。變更亦可以採用晶片 墊區域之周邊、引線或兩者之一粗糙化的形式。 除提供用於囊封物之經改良之保持力的變更以外，可粗 糙化引線框架之表面以提供增加之表面積。經粗糙化之表 153285.doc 201232673 面將促進囊封物至引線框架之表面的黏著。 可視需要使用一夾子來替代線接合以增加至晶片之電力 流並從而改良晶片之效能。 在本發明之另-實施例巾，提供形《具有超聲波接合線 之電子封裝之一方法。形成部分經蝕刻之引線框架之一區 塊，其中包括網式部分且藉由街道形部分加以彼此分離之 引線框架具有-連續底部表面。將晶片附接至引線框架上 之晶片接收區域。在每一個晶片之端子與對應引線框架之 電引線。ρ刀之間形成電連接。線係超聲波接合至引線框架 & Ρ表面藉由在引線框架（包含分離引線框架之街道 形部分）上方施加一囊封材料來囊封引線框架。其次執行 底部表面之背面目帛化以移除網式部分以及街道形部分。 然後在街道形部分上方單個化經囊封之引線框架以形成在 底部表面上具有超聲波接合線之個別晶片尺寸封裝。 本發明之—個實施例提供形成晶片尺寸封裝之—方法。 該方法包括形成部分經蝕刻之引線框架之一區塊，該等引 線忙架匕括式部分、—晶片安裝區域、複數個電引線部 :以及街道形部分。將一積體電路晶片附接至該膜之第一 區之曰曰:片安裝區域。然後在晶片上之一個或多個端子與引 ，框架上之-個或多個電引線部分之間形成電連接。然後1 201232673 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to electronic packaging, and more particularly to a partially patterned lead frame and a method of making and using the same. The partially patterned lead frame is stronger and more stable than conventional lead frames. The robustness of the partially patterned lead frame improves the manufacturing of the lead frame package and enhances the overall reliability of the final product. The leadframe also provides a high degree of flexibility for device integration and added functionality. This application is a continuation-in-part of U.S. Patent Application Serial No. 12/875,248, filed on Sep. 3, 2010, which is hereby incorporated by reference. One of the serials of the serial number 11/877,732 (now the US 7,790,500), the US 7,790,500 is a part of the application serial number 11/553,664 (now the US 7,799,611) filed on October 27, 2006, the United States 7,799 , 61 1 is an application filed on August 4, 2005, serial number 11/197,944 (now US 7,622,332), and US 7,622,3 32 was filed on August 10, 2004. One of the applications Serial No. 10/916,093 (now USA 7,129,116) is one of the continuation cases, and US 7,129,116 is one of the applications serial number 10/134,882 (now USA 6,812,552) filed on April 29, 2002. In the continuation of the case, all of these applications are incorporated herein by reference in their entirety. [Prior Art] In the fabrication of an electronic package using a lead frame, there are several process steps which cause the lead frame to undergo mechanical and thermal stress. The current integration of leadframes 153285.doc 201232673 The small geometry and the increasing integration of circuits on semiconductor wafers have resulted in the handling of greater stress on the leadframe. Finely configured lead frames are often similar to very delicate embroidery or stencil-like metal structures that tend to bend, break, deform, and deform easily. (See Figures and ^). Such custom leadframes are used in the industry to create a variety of wafer packages, including wire bond and flip chip (FC) packages (see Figures 23 through 2d and Figures " to 3b"). Conventional lead frames generally lack structural rigidity. The finger portion of the lead frame can be quite fragile and difficult to hold in place. This results in processing defects, damage and distortion in the assembly process, as well as complex wire bonding situations. Therefore, the bonding parameters must be optimized to compensate for lead frame bounce during the bonding process. Failure to optimize the bonding parameters to compensate for the mechanical instability of the leadframe can result in poor bond adhesion and thus poor bonding and poor reliability bonding. The larger metal plate portion of a typical lead frame extends from a central portion, referred to as a wafer receiving region, and is also referred to as a wafer pad. The wafer is typically attached to the receiving area with the back side down and the front side positioned upwardly, wherein the terminals are positioned circumferentially on the perimeter of the wafer or in an array above the surface of the wafer . The receiving area typically has a size of about 5 mm x 5 mm, and the leads extending from the wafer pad area have a typical size of about 1 〇 mm long x l mmt x 〇 2 mm thick. The lead frame is typically held by a vacuum chuck and mechanical clamp. The chucks and clamps must be modified for lead frames of different sizes and shapes. The present invention alleviates this problem. 153285.doc 201232673 The prior art has not shown any lead frames that can withstand the stresses encountered in current semiconductor packaging processes and that can be fabricated in a cost effective manner. The present invention achieves this object by providing a partially patterned bow frame which not only improves the manufacturability of the lead frame itself, but also improves the integrity and reliability of the electronic package from which it is formed. The present invention also addresses the continuing need for increased device complexity not provided by conventional lead frames, such as high I/O count, multi-chip design, system h package, and routing flexibility. The size of the computer chip has also continued to shrink. For a lead frame having a particular size, the use of wafers of ever smaller size results in longer wire bonds between the wafer terminals and the electrical landing sites. The need for longer lines can cause line wobble during processing and is highly likely to cause some types of wafer size packages to be wired shorted. Increasing line length also affects unit cost. Typically, a gold wire is used to connect the computer chip to the landing site. In the past five years, the price of gold has almost doubled, and as the size of the wafers has decreased, the amount of gold wire has increased, causing significant price pressure on wafer packaging manufacturers. Although it is an alternative to coated wire-based gold wire, it is 2 to 3 times more expensive. Sometimes the arrangement of the leads on the lead frame can be adjusted, but the ability to modify the lead arrangement depends on the configuration of the lead frame and depends on the manufacturer's throughput. The position of the lead is likely to require special loop technology when bonding wires. , thereby slowing down the bonding process without completely eliminating the possibility of a line short. Some computer packages require radio frequency shielding (RF shielding) to prevent electromagnetic fields from interfering with the proper operation of the package during operation I53285.doc 201232673. Laminated devices typically have this RF shielding, but they are extremely expensive features. The amount of time that a moisture sensitive device can be exposed to room temperature is recognized by industry-recognized electronics standards ("wet sensitive level"). In msl 3, the components must be installed and reflowed within 168 hours of removal from a moisture barrier bag. The dies are singulated to form individual wafer size packages and the knives are cut into lead frames to expose the desired metal layers for attachment to specific features, such as ΕΜΙ (electromagnetic interference) shielding (4). However, using a saw several times can affect productivity and production yield. Since the exposed metal surface is typically 5 to 18 μm thick, a high level of control of the sawing process is important to ensure proper blade height. SUMMARY OF THE INVENTION A lead frame is composed of a film having a top surface and a bottom surface. A first zone of the film is patterned from the top surface portion but is not completely passed through the film to the bottom surface. A second region of the film that is not patterned from the top surface forms a wafer receiving region for supporting an integrated circuit (IC) wafer, and a plurality of lead contacts for providing electrical connections to the IC wafer . The first zone forms a trench in the film and establishes a mesh structure interconnected with the second zone that is not patterned from the top surface portion. The present invention is also directed to a method of fabricating a partially patterned lead frame and an electronic package fabricated using the lead frame. The lead frame of the present invention has improved structural rigidity due to its mesh or mesh structure. In accordance with the present invention, the top surface of a metal film from which the lead frame is intended to be formed is first patterned using standard photolithography techniques or the like to determine 153285.doc 201232673 will correspond to a wafer receiving area and the area of the lead. shape. In the next step, etching is performed by passing the thickness of the underlying film from the top surface portion of the film in the first region of the film outside the region having the outer shape to establish a lead frame pattern in the film. After partial patterning, the remaining regions not patterned from the top surface form a second region that will serve as a wafer receiving region and leads along the top surface. The first zone forms a recessed mesh zone below the top surface of the film. The mesh structure of the first region connects the lead portions to each other and to the wafer receiving region. Thus, the partially patterned film looks similar to the mesh foot and maintains its rigidity and strength so it can withstand the forces of subsequent processing steps. In particular, the partially patterned lead frame can withstand the forces encountered during the wire bonding and encapsulation process. In some embodiments, the wafer receiving area and electrical leads can be formed from the same portion of the second region (for example, where the electrical leads support the integrated wafer and the electrical connections provided thereto). The present invention also provides for the fabrication of a plurality of electronic packages using a partially patterned lead frame. The financial method involves a film having a top surface and a bottom-p surface. In the first zone +, the film is partially patterned from the top surface but not completely through the film to the bottom surface. The film is not on the P surface. The remaining second region of the pattern is formed into a plurality of partially patterned lead frames. Each of the lead frames thus has a plurality of electrical leads for supporting one of the wafer receiving regions of the integrated circuit (IC) wafer and for providing electrical connections to the 1C wafer. The first-region forming-network structure of 3 interconnects the wafer receiving regions of each of the lead frames with the electrical leads. The first zone also connects a plurality of lead frames to each other in the film street 153285.doc 201232673. A plurality of 4 are provided, each wafer having a plurality of electrical terminals and a corresponding lead frame. Each wafer system is attached to a corresponding one of the chip receiving regions on the lead frame and is electrically connected between the electrical leads of at least one of the wire frames of each of the wafers. Then, an encapsulating material is applied over the lead frame table and the street-shaped portion of the film to completely cover the top of the film. Once the encapsulating material is dried, the surface of the film p is practised in the first region. A backside patterning process to remove the mesh structure and the street material of the film. The encapsulating material disposed above the (four) shaped portion of (4) is singulated to form an individual package. In a preferred embodiment, the method includes forming a leadframe into the film in a matrix in the form of a block/window pattern and involves producing a wafer size package. The advantage of the right stem is caused by the partially patterned lead frame of the present invention. The flat and solid unbonded (four) bottom surface in-line bonding process of the leadframe 'is used as an excellent heat sink. This provides a heat transfer of the average sentence to achieve a better and better joint quality. In addition, the solid structure provides a universal vacuum for the continuous surface to hold the lead frame, thereby making the slab attachment process more stable and making the leads stronger during subsequent processing steps/doors. Eliminate the hard/clamping of the outer edge of the leadframe to allow for the design and handling of the J-frame leadframe without the need for conversion. Since the bottom side of the partially patterned lead frame is a flat continuous surface, a universal vacuum chuck can be used to hold many different sized frames. This removal requires the modification of the vacuum chuck each time a lead frame of a different size is used in the packaging process. 153285.doc 201232673 Sex. And 'no further clamping is required. The use of a universal vacuum chuck and elimination of the clamp enables the construction of double or triple staggered leads on the second zone to achieve a higher number of leads. SUMMARY OF THE INVENTION The present invention relates to lead frames that are not only adapted to wire bond wafers but also to portions of the solder bump overlay. In addition, the present invention teaches a method of fabricating an etched lead frame package (ELP) using wire bonding, an ELP (ICPF) with flip chip, and a landing dot grid array (LGA) pad using a partially patterned lead frame. The ELP or ELPF is formed to form an etched landing dot grid array (ELGA) package, as further illustrated in the embodiments of the present invention. Flip-chip (FC) technology is a further step towards a fully automated connection of an electrical terminal on a wafer to a next-level package, i.e., to a ceramic or plastic substrate, or to a wafer microcarrier that is later attached to the substrate. The microcarriers, which are only slightly larger than the wafer itself, are now referred to as wafer size packages (csp). The FC technology evolved from the tape automated bonding (TAB), which in turn placed its origin in line s (WB). In WB and TAB, however, the wafer is positioned on its back surface and electrically connected to the terminals around the perimeter of the crucible on its top surface. In FC technology, the orientation of the wafer is reversed. The wafer is placed face down and the back side of the wafer is oriented upward. This flip chip orientation has a significant advantage because it concentrates the electrical function on the underside of the wafer, & the top side remains free for a still efficient heat transfer design. These patterns can be developed in an array of regions, peripheral patterns or other patterns in the FC process by using different types of bumps over the surface of the wafer to seal the wafer terminals or pads. The wafer can be attached to the lower 153285.doc 201232673 in the following manner: a) the FC is attached to a lead frame; b) the FC is attached to a layer/substrate called an interposer to the connection pitch on a lead frame Performing a re-routing; c) attaching the FC to one of the pre-attachment inserts on a lead frame; or d) attaching the FC to a printed circuit board using conventional techniques including wafer reflow methods. Wafer attachment using conventional techniques is particularly difficult to apply when applied to QFN leadframes in the fabrication of QFN (quadruple flat no-lead) packages and their derivatives, such as VFQPF-N. This is because conventional lead frames generally lack structural rigidity. The finger portion of the lead frame can be quite fragile and difficult to hold in a precise position. This results in processing defects, damage and distortion in the assembly process, and complex wafer bonding conditions. The PC bonding process requires precise alignment of the bump solder bumps with the suspension and the fragile lead ends of the leadframe. In addition, the wet solder ends must remain in place after being placed through the dip reflow process. Therefore, the reflow parameters must be optimized to compensate for lead frame bounce during wafer bonding, which can result in poor joints without proper completion and, therefore, poor quality and poor reliability of the final product. Conventionally, a template-like lead frame is conventionally formed by patterning a metal strip or a photoresist on a metal film and etching through the pattern to form a finger lead extending outward from the wafer receiving region. . It is also customary to use <links" between the fingers to keep the fingers spaced apart during each process step, as shown in Figure M3b. The present invention solves the problem of lack of structural rigidity of the lead frame by replacing the first: a plate-like lead frame to form a mesh-shaped patterned lead frame. According to the method of the present invention, all major process steps of forming-semiconductor package are performed from the side of the film to the one-line "film 153285.doc -11-201232673 side." The other side (i.e., the bottom side) remains flat and untouched on the surface (such as the surface of an A empty chuck). This includes the step of encapsulating and sealing the portion of the package forming the front side. The 纟 70 is encapsulated' and the bottom surface is back-touched to selectively remove the mesh portion that will connect the bond to the wafer. In the case of ELp which causes the wafer to be back-bonded to a wafer pad at the wafer receiving area and electrically connected to the wafer terminal by wire bonding, all intermediate mesh portions are cut by etching to make the wafer pad and The lead contacts of the wire bond ends are now isolated from one another by the molding material surrounding the wafer, the wires, and the front surface of the wire bond contacts. However, in the case of an ELPF package, the mesh portions connecting the leads to each other are cut only by etching, because the leads themselves connected to the solder bumps of the wafer provide electrical connection with the next package. The removal of the embedded metal through the saw thickness or the street shape in the mesh portion has several advantages, including the elimination of the sawing force propagating throughout the lead frame structure and thus the delamination at the metal-plastic interface. Moreover, electrical isolation through the back touch strikes to achieve any miscellaneous or singularity or strip test prior to any further processing steps. After the backside patterning, the remaining and exposed metal portions on the bottom surface can then be flashed by any number of solderable materials by immersion tin impregnation or electroless nickel plating. The ELGA package uses an ELPF packaged PC, however the LGA pad is used to connect to the next level of package. To prevent any separation between the molding material and other components of the package during manufacture, the present invention also teaches how to expose the exposed vertical wall of the partially etched lead frame to the recessed portion of the 153285.doc •12·201232673 Upper features, such as on the sidewalls of the leads, form locking features that will contact the molding material, such as a resin. As an alternative, it is also taught to form "lips" on the edges of the wafer pads and lead contacts to capture the molding material under each lip, thereby making it difficult to separate the molding material from the mating surface. It will be apparent from the foregoing that a partially etched leadframe provides a combination of structure and incident rigidity and strength to properly withstand the stresses and strains of the various fabrication processes in the fabrication of the electronic package. Due to these unique mechanical properties, a portion of the etched leadframe package can withstand the tightness of the wire to the bottom of the package to interface with the next package, which has not been possible with conventional plastic packages. One aspect of the invention provides a method for forming an electronic package. The method includes forming a portion of a partially etched leadframe having selectively pre-plated top and bottom surfaces. The lead frames include a mesh portion and are separated from each other by a street-shaped portion. A first set of wafers is attached to the wafer pad area on the leadframe. For convenience (see the area where a lead frame to which an integrated wafer (1C) or a 1C wafer is attached will be referred to as a wafer defect region or a wafer receiving region, regardless of whether the region is used for wire bonding wafers, flip chip Any of the types known in the art: a type of wafer. The first wafer set can be back-contacted with the wafer receiving region using a binder, a resin, or other material that is compatible with the two components. The backside bond can be formed using an epoxy, non-conductive epoxy, tape or solder paste. Other suitable materials are well known in the art. 153285.doc -13- 201232673 Then the second wafer is crystallized The particles are stacked on top of the corresponding first wafer set. After stacking the second wafer set die on top of the first wafer set, one or more additional wafer set grains can be stacked to the second wafer set On top, thereby providing a package consisting of two, three or more wafers superimposed on top of each other. In some embodiments of the invention, not all wafers from the first wafer set may have die stacking Wafers thereon. In such embodiments, the leadframe will have one or more individual (unstacked) wafers and one or more die-stacked wafer sets. Terminals and corresponding leads in each of the first wafers Electrical connections are made between the electrical lead portions of the frame. The electrical lead portions are electrically separated from the wafer pad regions. Electrical connections to the second or additional wafer sets are also formed. After the wafer dies have been stacked on the lead frame, An electrical connection is formed. Alternatively, the first set of wafers can be attached to and electrically connected to the lead frame, and then the second or additional set of wafers can be stacked on top of the first set of wafers and electrically coupled to the leadframe. After the wafer dies are stacked onto the leadframe and electrically connected to the leadframe, the leadframe is then encapsulated by applying an encapsulation material over the street-shaped portions of the leadframe and the separate leadframe. After encapsulation, The bottom surface of the lead frame is back patterned to remove the mesh portion and the street portion. 执 By a convenient method (such as by #刻) to face the pattern Applying a pre-plated material to the bottom of the lead frame (for example, as a photoresist) to the right, the pre-plated material can be removed after the back patterning. It can be patterned at the bottom of the lead frame after the back side is patterned. The isolation pattern 153285.doc • 14·201232673 can be formed by plating or coating the isolation pattern to protect the surface by a material. Examples of suitable materials include electroless Ni/immersion Au 'immersion Ag, immersion sn, An organic surface protectant (0SP) and other solderable materials. This finishing or plating step facilitates the provision of additional stability to the back surface of the wafer package and can be 'cut to the computer board, socket or other location where the chip package is placed. Connectivity The encapsulation material disposed over the #f if portion is pre-formed to form individual wafer size packages for various applications in the semiconductor industry. Simplification can be accomplished using any convenient component that can be used to separate individual wafer packages. In one embodiment, singulation can be performed by cutting the encapsulant using a mine or abrasive spray. Another aspect of the invention provides a die pad region and leads and a modified lead frame. The change can be viewed as an element positioned on the structural features of the leadframe that provides an increased surface area when compared to a leadframe that does not have a change. The change promotes the retention of one of the encapsulating materials applied to the top of the lead frame prior to singulation. The change can be in any form, such as a cut in the electrical leads of the lead frame. Each of the second wafers f may have the same size as the corresponding first wafer or a different size. In addition, the first wafers attached to the lead frame do not need to be all the same, and thus the first wafer set can include larger and smaller ones. The largest wafer will be attached to the wafer pad area. The ever smaller wafers stack the dies on top of this wafer. In an alternative embodiment, the largest wafer will not be attached to the wafer defect region and will be in the middle or top of the die stack wafer. The die-stacked wafers may also all be identical to I53285.doc 201232673. A size 0 The second and additional wafer sets may be stacked and bonded to the corresponding first wafer using any convenient means known in the art to bond the wafers to each other. For example, a non-conductive epoxy or an insulating material such as a tape can be used to stack the wafers to prevent interference or electrical movement between or in the middle of the wafer. In another embodiment, the second wafer set can be adhered to the corresponding first wafer using a tape, a conductive adhesive, or a conductive epoxy. The first wafer is electrically connected to the lead frame using conventional techniques. For example, the wafers can be attached to the leadframe using wire bonding techniques or using flip chip technology. The first wafer can be electrically connected to the lead frame prior to stacking the second wafer set die onto the first wafer. Alternatively, the first wafer can be electrically connected to the leadframe after the second or additional wafer set dies are stacked onto the corresponding first wafer set. The step of forming an electrical connection can be accomplished by attaching the terminals on the wafer to the end portions of the electrical leads that extend to the S-chip region. These electrical connections can be formed using any convenient or suitable technique. For example, if the wafer is wire bonded to the wafer, a wire bonding technique such as thermosonic bonding can be used to form the connection β. The flip chip is typically electrically connected to the leads using flip chip technology [wire bonding and flip chip technology] Combinations are also within the scope of the invention. The field will be directly attached to the lead frame (4), and the corresponding leads may be coated or unplated. 2 A set of chips receives power to perform calculations or other functions. This second wafer can be electrically connected to the corresponding first wafer, lead frame or both. The connections formed between the individual / lead frames will depend on the particular 153285.doc 201232673 situation at hand and the particular electronic package formed. The type of wafer used in Shuming will also depend on the specific situation. For example. The cymbal can be wire bonded to the wafer, flip chip or any other type of wafer suitable for electronic wafer packaging. In one embodiment, the first wafer set comprises a flip chip or wire bond wafer or two I, and the second and any subsequent wafer sets comprise wire bond wafers. Any of these wafers may also include a semiconductor device. An electronic package formed by a die stack 4 wafer in accordance with the present invention will have a particular height after encapsulation and singulation. To reduce the height of the electronic package, the area of the wafer can be recessed to reduce the height of the package obtained. That is, the wafer pad on the lead frame area can be formed by means of a reduced interior to allow the wafer to fit within this area and thereby provide a reduced height sheet. - Day. The electronic package formed according to the disclosed method is robust and stable. To provide further reliability of the package during stress conditions and manufacturing, changes can be used to increase the retention of the encapsulant. The changes can be located along the perimeter of the wafer pad, the leads, or both. Selective pre-plating of the bottom leadframe can be used to define the bottom features of the leadframe. This selective pre-recording provides a similar pattern on both the top and bottom surfaces of the lead frame. Any convenient material can be used to make selective pre-recording. In one embodiment, the lead frame can be pre-plated using -NiPdAu or a silver alloy. After encapsulation, the die-stacked wafer will be surrounded by a solid encapsulant to prevent the electrical connection between the wafer and the leadframe from moving or weakening. The entire stacked wafer set can be covered by a 153285.doc •17* 201232673 capsule. Alternatively, the y portion of the highest wafer (such as a back or top surface) may remain exposed after encapsulation. For example, the surface of the highest wafer may be exposed through the encapsulant and the remainder of the wafer. p is embedded in the capsule. In this way, the amount of encapsulation can be reduced without compromising the stability of the final package. In addition, if the top or back surface of the highest crystal contains Lang information, a package can be formed for this information and covered by the encapsulant and can be easily observed by (4). : As stated earlier, the wafer and die stack wafers are electrically attached to the leadframe to provide power to the wafer. Other components may be connected to the lead frame except for wafers such as flip chip or wire bonded wafers. These additional components may be structural components that provide increased support or stability. Additional components may also be: a component that supports the function of a wafer or wafer package. Examples of such additional components are passive components, spacers, power rings, grounding rings, and routing. Any configuration of such and other structural S or electrical components in a wafer package is within the scope of the present invention. What kind of material f can be left in the encapsulating material, which can be applied to the die-stacked wafer and solidified to form a durable solid. In one embodiment, the encapsulant can be wrapped around the wafer and hardened to produce a liquid resin of one of the wafers. An encapsulant - an example system - epoxy resin. The encapsulant will typically be a non-conductive material to prevent electrical signals within the encapsulated material from spanning from one wafer to another. When additional components include electrical components, such components can be electrically or directly connected to the leadframe. These additional components may also be electrically connected to one or more of the wafers in the package' and such embodiments will depend on the particular wafer size package being formed. 153285.doc 201232673 Alternatively, a bow-and-loop frame can be formed using the production techniques known in the art. For example, a metal frame can be formed using chemical etching, stamping or stamping techniques. The lead frame may be coated or partially coated with a film of a material such as a conductive material. The film can provide an increased electrical flux between the lead frame and the wafer attached to the lead frame in a uniform embodiment, the film being made of copper or one, compared to a lead frame without such a film. Copper alloy is formed. Although the film will have to be thick enough to have mechanical stability, the thickness of the film is generally not critical. In one embodiment, the film has a thickness greater than or equal to about 0.05 mm. Another aspect of the invention provides a lead frame comprising a wafer pad region and a lead. The lead frame has a modification that provides increased retention of one of the encapsulating materials covering one of the lead frames. The wafer will typically be attached to the wafer pad area and electrically connected to the leads. The alterations can be structurally designed and configured to provide an increased surface area for the retention of an encapsulant. The alteration can take the form of any type that provides increased retention of one of the encapsulants. For example, the change can take the form of a cavity, low drop or slit positioned on a portion of the leadframe or leadframe. Variations may also occur on the leads formed on the electrical connections to the wafer. The support can be on any part of the lead frame. For example, the changes can be on the perimeter of the wafer pad area or on the leads or both. The modification may also take the form of a roughened portion of the periphery of the wafer pad region, the leads, or both. In addition to providing improved retention of retention for the encapsulant, the surface of the leadframe can be roughened to provide increased surface area. The roughened surface 153285.doc 201232673 will promote adhesion of the encapsulant to the surface of the lead frame. Instead of wire bonding, a clip can be used as needed to increase the power flow to the wafer and thereby improve the performance of the wafer. In a further embodiment of the invention, a method of forming an electronic package having ultrasonic bonding wires is provided. A portion of the partially etched lead frame is formed, wherein the lead frame including the mesh portion and separated from each other by the street portion has a continuous bottom surface. The wafer is attached to a wafer receiving area on the lead frame. Electrical leads at the terminals of each wafer and corresponding lead frames. An electrical connection is made between the knives. The wire is ultrasonically bonded to the lead frame & The Ρ surface encapsulates the lead frame by applying an encapsulating material over the lead frame (including the street-shaped portion of the separate lead frame). Next, perform the back side of the bottom surface to remove the mesh portion and the street portion. The encapsulated leadframe is then singulated over the street shaped portion to form an individual wafer size package having ultrasonic bonding wires on the bottom surface. One embodiment of the present invention provides a method of forming a wafer size package. The method includes forming a block of a portion of the etched leadframe, the wire-wrap portion, a wafer mounting region, a plurality of electrical leads, and a street-shaped portion. An integrated circuit wafer is attached to the first region of the film: a sheet mounting area. An electrical connection is then made between one or more terminals on the wafer and the lead or one or more electrical lead portions on the frame. then

積體電路晶片之引線框架 晶片安裝區域’藉以移除下伏於 之所有或一實質部分。然後單個 153285.doc 201232673 女置於引線框架之街道形部分上方之囊封材料 別晶片尺寸封裝。任何類型之任 部分圖案化引線框架。 -片均可黏附至 可用一預鍍覆材料來選擇性地預鐘覆引線框架，或可在 囊封之前用其頂部側、底部側或兩者上之一遮蔽材料來遮 蔽該等引線框架。若該等引線框架經遮蔽，則可為用以連 接至-印刷電路板（PCB)之預期¥陸點而在—禪料 提供開口。 ^ 可使用任何方便或習用物質來選擇性地預鑛覆線框 架。此類物質之實例包含試鍍型Ni/Pd/Au、沈浸&、The lead frame of the integrated circuit chip, the wafer mounting area, is used to remove all or a substantial portion of the underlying layer. Then a single 153285.doc 201232673 female is placed over the street-shaped portion of the lead frame to encapsulate the material in a wafer size package. Any type of partially patterned lead frame. - The sheets may be adhered to a pre-plated material to selectively pre-lap the lead frame, or the lead frames may be masked with one of the top side, the bottom side or both of them prior to encapsulation. If the lead frames are shielded, an opening can be provided in the zen material for the intended land point to be connected to the printed circuit board (PCB). ^ Any convenient or customary material can be used to selectively pre-mine the covered wire frame. Examples of such materials include test-coated Ni/Pd/Au, immersion &

Sn/Pb、無鉛焊料、沈浸錫無電鍍鎳、銀(Ag)以及試鍍型 Au(金）。 亦可使用任何方便或習用遮蔽物質（諸如一可印刷油 墨、一模板油.墨、一環氧樹脂油墨）或一有機物質來選擇 性地遮蔽引線框架。 可在任何適合的時間（諸如在背面圖案化之後）自引線框 架之底部移除預鍍覆材料或遮蔽材料。 引線框架可係由此項技術中習知之任何適合的物質形 成。舉例而& ’引線框架可包括銅或一銅合金或另一金屬 或金屬合金之一膜。 如先刖所陳述，將一積體電路晶片附接至引線框架之晶 片安裝區域。可使用在此項技術中習知之一黏合劑或其他 觸液或固定劑物質來附接晶片。舉例而言，該黏合劑可係 一樹脂、一環氧樹脂、一焊料膏或一膠帶。 153285.doc 21 201232673 衝壓或壓印）來形 可使用s用製程（例如藉由化學蝕刻 成引線框架。 可使用適合的電連接手段(諸如藉由線接合)將晶片電連 接至引線框架。 在一另外實施例中，本發明方法准許在晶片安裝區域處 曰曰拉堆疊多個晶片。舉例而t，該方法可包含晶粒堆疊一 個或多個第二晶片至黏附至引線框架的積體電路晶片之頂 匕等第一 s曰片可電連接至引線框架或至黏附至引線 框架之積體電路晶片或兩者。此等連接方法之組合係可能 的。第二晶片亦可彼此電連接。 本發明之另一態樣提供用以製造一電子封裝之一部分圖 案化之引線框架。 部分圖案化之引線框架可由具有—頂部表面及一底部表 面之-膜組成1膜可具有__頂部表面，其具有⑷自該頂 部表面但並非完全透過該膜至該底部表面之部分圖案化之 第區，及（b)未自該頂部表面部分圖案化之一第二區。 該第二區可形成用以支撐一積體電路（IC)晶片之一晶片墊 區域，及用以提供至該1C晶片的電連接之複數個電引線。 該晶片墊區域與複數個電引線可經由該第一區進行連接， 但並非透過該頂部表面進行連接。該膜之底部表面亦可自 該底部表面但並非完全透過該膜至該頂部表面而部分圖案 化。 可採用任一特定方式來圖案化引線框架之頂部及底部表 面。舉例而言，可在一互補圖案中圖案化頂部及底部表 153285.doc •22· 201232673 面’以使兩個表面在引線框架之兩側上具有大致相同之特 徵。 可用影線、通道或兩者來圖案化引線框架之底部表面。 此類影線或通道有利地准許側通風口及側通風，因此在回 焊期間不存在捕獲空氣。 本發明之另一態樣之一另外實施例提供用以形成晶片尺 寸封裝之一方法。該方法包括提供一部分圖案化之引線框 架’其具有（a)自底部表面但並非完全透過該引線框架至底 部表面而部分圖案化之一第一區，及（b)未自頂部表面部分 圖案化之一第二區。該第二區形成（a)用以支撐一積體電路 (1C)晶片之一晶片墊區域，及（b)用以提供至該1(：晶片的電 連接之複數個電引線。該晶片墊區域與複數個電引線可經 由該第一區進行連接，但並非透過該頂部表面進行連接。 然後將一積體電路晶片附接至引線框架之第一區之晶片 墊區域。然後在晶片上之一個或多個端子與引線框架上之 一個或多個電引線部分之間形成電連接。然後藉由將一囊 封材料施加於引線框架及街道形部分上方來囊封該引線框 架°然後對引線框架之底部表面進行f面圖案化以移除網 式部分以及街道形部分。亦移除晶片墊區域之底部表面之 一小部分以形成透過晶片墊區域之—個或多個通道。此等 通道有利地准許側通風σ及側通風，因此在回焊期間不存 在捕獲空氣。錢單個化安置於引線框架之街道形部分上 方之囊封材料’以形成準備後續使用之個別晶片尺寸封 153285.doc -23- 201232673 晶片墊區域之通道橫跨整個晶片墊區域之長度而延伸， 或其可橫跨晶片墊區域之-部分而延伸。此等通道可採用 影線或其他類似結構之形式。 本發明之另一態樣提供用以製造—電子封裝之一部分圖 案化之引線框架。引線框架包括具有—頂部表面及一底部 表面之ϋ膜係自該頂部表面但並非完全透過該膜至 該底部表面而部分圖案化。該膜亦係自該底部表面但並非 完全透過該膜至該頂部表面而部分圖案化。該頂部表面上 之圖案化比該底部表面上之圖案化深。所得的引線框架之 圖案化在其頂部上比在其底部上深。雙側㈣准許最終將 移除之引線框架之部分具有一減小的厚度且從而使所得的 電子封裝之處理及製造流線化。 本發明之另一態樣提供具有帶有通道之一底部表面之一 晶片尺寸封裝該晶片尺寸封裝包括—個或多個囊封的電 腦晶片，且該等通道用作通氣口以減小或消除回焊期間之 捕獲空氣。 本發明之特徵提供優於現存技術之重大優點。本發明提 供諸如系統級封裝之特徵，且提供隨著減小之封裝大小之 增加之電效能、熱效能及I/O。本發明之靈活性允許創新 型ELP型封裝以適應不斷複雜之要求。 雖然上文所論述之本發明之實施例提供具有重大效用及 優於先前技術之改良之晶片尺寸封裝，但額外特徵可在特 定例項中提供優點。 舉例而言，本發明之另一態樣之一實施例提供使用引入 153285.doc •24- 201232673 引線形成電子封裝之一方法。該等引入引線允許電著陸點 更罪近晶片附接區域或甚至在晶片下面而放置，且允許更 簡單的電連接。 該等引入引線通常比普通電著陸點具有一更大表面積， 且因此在線接合或覆晶附接方面允許更大靈活性。該等引 入引線亦允許使用更少的用於線接合之線。由於線通常係 昂貝的金製線，因此減小此線之量提供重大的成本節約， 即使用於引線或跡線之金屬量稍微增加。 該方法包括形成具有選擇性地經預鍍覆之頂部及底部平 面之部分經蝕刻之引線框架之一區塊，該等引線框架包括 網式部分、晶片附接區域及之形式為引人引線之電著陸點 ^刀。该等電引線部分與該等晶片附接區域電分離，且該 等引線框架藉由街道形部分而彼此分離。可結合認為有必 要或期望用於引線框架或所得的晶片尺寸封裝之適當功能 之焊料抗钱劑由墨或任何其他材料來使用該等引入引 線。 將s日片附接至一引線框架之一對應晶片附接區域，且 在該晶片t一個或多個端子與該對應引線框架之一個或多 個電引線部分之間形成—個或多個電連接'然後藉由將一 囊封材料施加於引線框架及街道形部分上方來囊封引線框 架從而刀離料引線框架。將晶片附接至該晶片附接區域 之步驟可視需要包括將該晶片放置於將在缺少__晶片塾之 情形下支撐該晶片之主動引線(或而是將在最終晶片尺寸 封装中係、主動之引線）之頂部上，及使用-非導電黏合劑 153285.doc •25· 201232673 (諸如-非導電環氧樹脂)或一晶粒附接膜黏合劑來黏附該 晶片。在此貫施例中’將在該等主動引線與該積體電路晶 片之間形成電連接。 然後將該等弓i線框架之底部表面背面圖案化以 部分及街道形部分，且藉由㈣ϋ安置於街道形部分I方t 囊封材料來單個化該等引線框架以形成個別晶 裝0 引線框架之晶片附接區域(亦稱作一晶片接收區域或一 晶月安裝區域)可具有用以接收一電腦晶片之任一特定结 構。舉例而言，該晶片附接區域可係該引線框架之一晶片 塾區域或一無墊部分。 可將本發明之實施例t之引入引線配置成在—各別晶片 附接區域關或附近之任-方便的配^舉例而言，引入 引線可配置成一晶片周圍之一單個列，或其可配置成引線 框架之各別晶片附接區域周圍之多個列。 該等電引線亦可係、不同類型之引線之任—組合。舉例而 言’該等引線可全部係引入引線，或該等引線可係引入引 線與電著陸點之一組合。 可使用任一方法或實用方法來執行該背面圖案化步驟。 舉例而言，可使用部分蝕刻或溢流式蝕刻（fl〇〇d etching) 來進行背面圖案化》類似地，可使用任何方便手段（諸如 藉由區塊模製或個別單元模製）來進行囊封步驟。 引線框架之晶片附接可具有任一方便的結構。舉例而 言，晶片附接區域可係實心（諸如一實心晶片墊區域），或 153285.doc •26· 201232673 該晶片附接區域（或引線框架之任一部分）可包括—個戋夕 個熱通孔（一印刷電路板設計中之不同導體層之間的一垂 直電連接）。 在單個化之後，可將一可焊材料（諸如焊料球或焊料面 層）黏附至單個化之前或之後的晶片尺寸封 么 < —個或多 個電著陸點。該可焊材料促進晶片尺寸封裝連接至電路板 或其他種類之電子軟體。可焊材料可具有任一新穎或習用 組分，諸如錫、銅、銀、絲、銦、鋅及/或銻。 附接至引線框架之ic晶片可具有任一適合或習用結構。 不同種類之晶片亦可接合至同一引線框架上之不同晶片附 接區域。舉例而言，可使用線接合晶片及覆晶，且某些引 線框架可支撐多個種類之晶片以及晶粒堆疊。可使用任一 適合的構件將該等晶片附接至晶片附接區域。適合的技術 之實例包含使用-導電環氧樹脂、非導電環氧樹脂或晶粒 附接膜黏合劑。 類似地，可使用任一適合種類之技術來完成電連接。舉 例而言，可使用線接合技術、覆晶技術或兩者之一組合來 形成電連接。可藉由將該晶片上之端子連接至自引線框架 延伸之電引線部分之端部分來完成形成電連接之步驟，且 該等引線部分可經鍍覆或未經鍍覆。用以將晶片電連接至 引線框架之具體技術將取決於製造時之特定組態及本發明 之實施例。 本發明方法可進一步包括在背面圖案化之後將一非導電 塗層施加至引線框架之底部表面。此非導電塗層可用以保 153285.doc •27· 201232673 護引線框架免受機械磨蝕或磨損之影響，且因此可增加所 得的晶片尺寸封裝之耐久性。該塗層係意欲在PCB安裝期 間保護主動引入引線免受短路之影響。電著陸點或墊之預 期位置將保持開放且未經覆蓋以提供必要的電連接。 在本發明之另外實施例中，本發明方法可進一步包括在 單個化之前或之後將一電磁干擾（EMI)屏蔽施加至晶片尺 寸封裝。該電磁干擾屏蔽消除或至少顯著減小可發生在電 氣設備中之不期望輻射電磁能之耦合。製備先前技術晶片 尺寸封裝通常需要部分切割引線框架基板或層壓以曝露所 希望之金屬層以用於將EMI屏蔽連接至一接地。由於有機 基板之金屬跡線之厚度通常為5至18 μιη，因此製程控制很 重要。相比而言，本發明之ELP平臺特別適用於施加一 EMI屏蔽，此乃因由於使用較厚框架其比其他種類之引線 框架具有更寬泛的製程控制。另外，本發明ELp平臺亦具 有在囊封期間使用袋式模製之選擇權以避免部分切割成引 線框架。在此實施例中’袋式模製製程不囊封整個引線框 架，而是保持該引線框架之金屬之一部分曝露且可供連接 至用於接地之EMI屏蔽。 可使用任-方便製程來施加該電磁干擾屏蔽，諸如藉由 無電錄覆、電解鐘覆、噴塗、浸潰、喷滅沈積或一網版印 刷製程。 从已參考黏附至-引線框架之-晶片附接區域之_單晶片 論述了本發明。在本發明之此態樣之另外實施例中^方 法可包括在囊封引線框架之前晶粒堆疊複數個晶片。舉例 1532S5.doc -28- 201232673 而δ，一個晶片可黏附至一晶片附接區域，且一第二晶片 可黏附至$第-晶片之頂部β可堆疊任—數目個晶片以形 成本發明之晶片尺寸封裝。每一晶片將電連接至引線框 木、忒堆疊中之另一晶片或兩者。可使用線接合技術、覆 s曰技術或兩者以及此項技術中之任何其他技術來連接該等 晶片，且此等配置將取決於製造期間的特定實施例及組 態，且可將任何此等實施例組合至一單個引線框架上。 【實施方式】 現在將參照圖闡述本發明，其中相同數字指代相同元 件。圖4至15b及圖16至24b顯示形成具有可與近晶片尺寸 封裝（CSP)之引線數相嫂美之引線數之一部分經圖案化引 線框架封裝之不同實施例。本發明之方法改良製造線的自 動化及自其製作封裝之品質及可靠性。此係藉由執行製造 製程步驟之一主要部分而完成，其中一部分經圖案牝之金 屬膜形成至一個側上之一網狀引線框架中。與習用沖穿模 板狀引線框架相反，本發明中所使用之引線框架在一個側 上部分圖案化而在另一側上係實心及扁平的。此結構藉由 機械及熱方式兩者加以改良，並且在晶片附接、線接合以 及囊封製程期間表現得無扭曲或變形。可遮蔽或以其他方 式標記底部表面以描繪將最終藉由背面蝕刻而移除之區。 在完成晶片附接及線接合製程步驟並將晶片及線接合黏附 且密封地囊封於一模製材料中之後，在未藉由底部表面之 選擇性預鍍覆層所遮蔽之區域中透過該膜而部分钱刻該底 部表面’以使引線觸點與晶片墊隔離且彼此隔離。隨後， 153285.doc •29- 201232673 單個化所得的經囊封封裝而不必將其切割成任何額外金 屬。 更具體而言’圖4至15b顯示用於一線接合晶片之一部分 經圖案化之引線框架的形成及使用其以用於形成一 ELp型 電子封裝之一方法。另一方面，圖16至22顯示用於一覆晶 之一部分經圖案化之引線框架的形成及使用其以用於形成 一 ELPF型電子封裝之一方法。亦結合圖24a及24b闡述使用 瞬時的部分經圖案化之引線框架形成一 ELGA型電子封裝 之一方法。 圖4係一膜（較佳地係一金屬薄片，且較佳地係銅）之一 剖視圖’該膜係不僅形成於一引線框架中，而且亦在破保 形成引線框架之製程步驟期間用作一穩定載體。金屬條帶 之厚度係等於或大於約〇_05 mm。在另一實施例中，該厚 度的範圍可係在約〇.〇5至〇·5 mm之間。 形成一引線框架通常涉及切穿金屬條帶，像切割一模板 一樣，並然後藉助極細小指狀引線進行操作。為將此一精 緻結構固持在適當位置’可使用一真空夾頭。然而，習用 真空夹頭通常並非經調適用以為此等精緻裝置提供吸力而 且必須通常在周邊上對引線框架施加壓力。必須從各類型 及大小的引線框架改裝用於此目的之任何索具。然而，本 發明緩解此改裝步驟。由於部分經圖案化之引線框架之底 部表面為實心且連續的，因此一習用真空夾頭可在處理期 間輕易地將引線框架固持在適當位置。此外，可在製造引 線框架中普遍使用可適應各種工業用引線框架之一種大小 153285.doc -30- 201232673 的金屬條帶。可藉助欲形成之引線框架上之甚小應力及應 變來完成晶片附接及線接合之後續製程步驟。可輕易製造 具有甚細小幾何形狀的引線框架，此乃因藉由網狀結構將 引線固持在m該等引線框架至直最终步驟才彼此分 可以若干方式完成在？丨線框架上形成各種圖案。一種方 法可係將圖案衝壓/壓印至金屬巾。其他方法可包含化學 或電化學研磨及放電加印魔）。另—方面，較佳地使用 光微影圖案化，其係半導體製造的主要方式。在本發明 中’在光微影圖案化之前在前(或頂部)側及背(或底部)側 兩者上預鍍覆圖4中所顯示之金屬條帶（1〇〇)。可藉助達成 接合以及可焊性之-材料來分別預鐘覆前表面及背表面中 之任-者或兩者。在一個實施例中，藉助一可接合材料 (諸如試鍍型Ni/Pd/Au或Ag)來預鍍覆前表面。在另一實施 例中，藉助一可焊材料（諸如Sn/Pb、無鉛烊料、沈浸錫無 電鍍鎳或試鍍型Au)來預鍍覆背表面。在另一實施例中， 藉助與頂部側相同的材料預鑛覆背表自，該材料然後可在 背面圖案化期間充當一抗蝕劑。稍後可在最終完成之前剝 離此抗蝕劑類鍍覆層。在期望之情形下可在一稍後步驟中 執行預鍍覆。 在下一步驟中，光微影圖案化預鍍覆之前側（11〇)以形成 對應於晶片墊區域周圍之晶片塾⑴5)及電觸點（113)之區 域。一電觸點（113)之特徵可為一引線之端部分，其係透過 形成網狀結構t中間凹入部分之第一區連接i晶片塾區域 153285.doc -31- 201232673 (115)。當自背面蝕刻金屬膜（1〇〇)時，在一稍後時間移除 此等中間凹入網狀部分，以便端部分與晶片墊部分將彼此 隔離°包括一晶片墊（U5)及周圍觸點（1】3)之區域有時稱 作晶片位置。可在以鏈輪方式至一卷軸之一連續銅薄片輥 上形成複數個晶片位置以輕易地使包括一個或多個晶片位 置之引線框架之形成自動化。圖5圖解說明兩個晶片位 置，其將形成至兩個對應引線框架中，該等引線框架又將 係自其將形成之兩個封裝之部分。 針對圖5中所圖解說明之兩個晶片位置所顯示之圖案然 後藉由蝕刻轉印至膜條帶（1〇〇)中。如圖6中所顯示，本發 明之一主要特徵係僅部分透過該金屬之厚度執行蝕刻，其 在本文中稱作部分圖案化。在該膜之一第一區中執行部分 圖案化以形成一網式結構（130)，其連接每-引線框架之引 線觸點⑴3)之晶片墊⑴5)。該第—區亦在該膜之街道形 部分（136)中將引線框架彼此連接。 如圖6a至6c中所顯* ’可在一區塊/視窗膜（138)中形成 -矩陣或此等引線框架（例如’ 16，。圖崎心顯示該第 -區包含網式結構（139) ’其連接每一引線框架之晶片墊與 引線觸點。該第-區亦在該膜之街道形部分（136)中將複數 個引線框架彼此連接。 在-個實施例中，部分圖案化可自該膜之厚度的bp 90%發生變化。，然而’部分圖案化可實際上為該膜之厚: 的任-百分比，且可藉由考量影響可製造性參數之她 素來確定部分Θ案化之量，”錢包含魏、剛性以^ 153285.doc -32 - 201232673 熱厚度（或導熱率P可基於給定晶片大小以及線接合或其 他連接媒介（其可用於一給定封裝中或下一級封裝中之封 裝之間之層級間或層級内連接）所需之小型化的程度來確 定引線觸點區域（113)及晶片墊區域（115)之橫向尺寸。尤 其應注意，由於指狀引線之網狀結構，對引線框架之細小 特徵及尺寸穩定性的製造性關注現在不那麼重要。 如圖7中所顯示，其次使用任何方便構件（諸如環氧樹脂 (150))將BB片（14〇)附接至晶片墊區域。根據本發明，顯示 附接之晶片與晶片墊之間之連結部包括環氧樹脂或焊料。 可用導電粒子填充環氧樹脂（150)以增強晶片之冷卻。在替 代性方案中，亦可使用焊料膏（15〇_)來替代環氧樹脂（15〇) 以提供晶片與晶片墊之間的一較牢固接合，以及至周圍環 境的一更有效冷卻路徑兩者。環氧樹脂得以固化，且如圖 8中所顯示，在晶片附接之後，使用熟知的線接合技術將 線（160)接合至端子（145)及對應引線觸點〇13)，如圖8中所 顯示。由於根據本發明而形成之引線框架具有（諸如）藉由 一真空夾頭（未顯示）而牢固地座落並固持於一扁平表面上 之一實心、連續背側，因此引線之網狀結構並不在線接合 期間顫動或跳動。此造成極佳接合’這改良最終產品之可 靠性。即使背側為實心且連績的，其仍可具有關於何處將 出現背面蝕刻的指示器。舉例而言，背側可具有破裂或其 他指示器，其可係該膜之表面之部分，或可用一預錄覆材 料（120)遮蔽該背側以描繪將被背面钱刻之預期區。舉例而 言，可在區域（113)下面遮蔽預鍍覆材料（120)以指示引線 153285.doc •33· 201232673 框架之對應部分將在稍後的蝕刻期間保留且將移除區域 (130)及（136)下面之區域。 在圖9中，在連接晶片及對應觸點之後，然後（例如）藉 由一樹脂將金屬膜之前側上之所有組件密封地囊封於一模 製材料中。在該膜及所有曝露表面上方形成囊封物（丨7〇)， 該等曝露表面包含引線框架及其相關聯之線（16〇)、晶片 (140)及觸點（113)以及網式結構（13〇)及街道形部分（136)。 當提起所得的經模製封裝時，乾淨的背側現在可用於進一 步處理。藉助此所揭示之方法消除至封裝之下側上之覆蓋 區的模製閃光通常所遇到之問題。先前可已藉助將促進後 續處理或蝕刻之一物質來鍍覆該乾淨的背側。 如圖10中所顯示，引線觸點（113)及晶片墊（115)兩者現 在可輕易地彼此隔離以藉由透過封裝之背側蝕刻第一區之 網式結構U35)來形成其自己的島狀物。在此刻，亦背面钱 刻街道形部分（136)。使用諸如—可印刷油墨或―有機材料 之一物質的預鑛覆（12G)可用作__遮罩或抗㈣以形成期望 之底部特徵（123、125)β在其他實施例令，可使用一有機 材料替代金屬或可焊材料來作為飯刻遮罩。可在背面钮刻 之前於任一方便步驟中將有機材料印刷或施加至引線框架 屬的㈣ 達到模製材料。用於背面㈣ 屬的钱刻方法可不同於用於前側的餘 银刻時間可端視於自前側執 用於前側⑽刻時間…因此^㈣之程度而不同方 b ’ W5分蝕刻今|線框架之初女 )532S5.doc -34- 201232673 形成可經定製以適合對最終封裝之自動化、品質、可靠性 及功能性之製造要求。在用作—化學抗㈣之底部上之預 鍍覆層（120)可經剝離以曝露金屬條帶（1 〇〇)。 為保護材料且易於安裝至印刷電路板，可將可烊材料 (諸如無電鍍Ni/沈浸Au、沈浸Sn或其他此等材料）鍍覆至 金屬條帶（100)。可保留或剝離掉任何預鍍覆層，此係視為 適合於特定情況。 作為一最終步驟，單個化引線框架之間的衔道形部分 (136)上方之囊封物（170)以形成兩個個別封裝，如圖η中 所顯示。此係以若干種方式完成，包含鋸切、喷水切割、 雷射切割或其組合，或尤其適用於切割塑膠之其他技術。 換言之，不存在需切穿之其他金屬且因此不存在分層以及 與切割組合的塑膠及金屬相關聯的其他問題。將此^習用 封裝比較，在習用封裝中必須在單個化封裝之㈣切割街 道形之間的橋接金屬。許多次當同時切割金屬及塑膠兩者 時’金屬晶月中之某些可使線及觸點短路，從而造成鋸條 上不合需要及不可預測的磨損。如圖以中所顯示，亦可應 用此方法以自一引線框架矩陣生產大量封裝。 圖12a中顯示透過一單個化ELP之囊封物所俯視之—俯視 剖視圖。圖I2b顯示晶片與觸點中之一者之間的封裝之一 拐角之-放大視圖，該等觸點包括原始金屬條帶（⑽）、經 預鑛覆以形成可接合層⑴3)之-頂部表面、及經預鑛覆以 形成可谭層⑽）之-底部表面之-部分。在圖12{)卜一 <=»狀物」係顯示在晶片之觸點及拐角兩者上。觸點（11 3) 1532S5.doc -35- 201232673 及晶片（140)係顯示為在其自己的島狀物上彼此隔離，但僅 透過已進行線接合之線（160)而彼此連接。 封裝之下側上的可焊預鍍覆表面（120)在未經剝離之情 形下現在可用於若干個目的。首先，至晶片墊（14〇)之背面 (125)的直接外部存取提供用於冷卻之額外熱路徑。其次， 接近晶片大小封裝（CSP)之覆蓋區内的觸點（123)使以下成 為可能：在下一級封裝中安裝緊密隔開的封裝’並因此增 加同一區域之效能。 本發明之另一態樣提供用以減少模製材料與其應黏著至 的表面之間的分層之可能性的一構件。此係藉由半蝕刻晶 片墊及接觸區域周圍的邊緣以形成一搭接物或一「唇狀 物j (諸如圖12b申之編號（105)所指代）而完成。亦可能形 成圖12c中所顯示之不規則形狀的空腔（1〇7)以增強與模製 材料接觸之表面之聯鎖機制。圖13&至13£中亦顯示各個其 他空腔之放大視圖，且此等表面增強之形成可輕易地併入 自前側的部分_中。此對於自背側進行㈣而言將沒有 必要’此乃因模製材料僅囊封自前側部分形成之表面。 。圖14將本發明之方法概述為以自前側部分蝕刻一引線框 架（200)至-金屬條帶巾開始，並以採用形成期望晶片塾及 周ϋ觸點之此-方式背面圖案触刻（25())同—金屬條帶結 束曰曰片附接（21〇)、環氧樹脂固化（220)、線接合（230)及 —G)之+間步驟係、全部在—機械及熱穩定引線框架上 成此乃因引線仍透過金屬膜中之一部分經姓刻之網狀 或網式結構上的中間凹入部分之第一區而連接。注意到以 153285.doc •36- 201232673 下亦很重要，僅在已將封裝之所有組件固定在一囊封物中 之後才透過背面圖案蝕刻（250)來移除中間凹入部分之第一 區，而且使周邊觸點以及晶片墊彼此分離以進行適當隔 離。在最終步驟之前，可執行剝離預鍍覆層（12〇)及施加可 焊材料。因此，不需要在單個化（26〇)成單一接近晶片大小 封裝期間切穿任何金屬。 本發明之方法可用以形成各種封裝，諸如用於一電子封 裝之一陣列類型之一引線框架。一陣列型封裝（4〇〇)之一俯 視圖係在圖15b中顯示為鄰近於圖15a中所顯示之標準周邊 型封裝（300) 〇儘管編號（3〇5)指代晶片端子之一周邊配 置，但編號（405)指代可經組態成直列或交錯式端子之一陣 列型配置。使用如藉由參考編號（31〇)及（41〇)所指示之所 揭示之刀圖案化發明來形成兩種封裝。在陣列型ELp 中，顯示内部引線（440)及外部引線（445)。兩種封裝係囊 封於模製材料（320)或（420)中。藉由（330)及（430)指示背面 圖案蝕刻以使觸點與晶片隔離。編號（45〇)繪示一接地環特 徵，其係蝕刻至與模具相同之位準。編號（46〇W^ELp之仰 視圖上之陣列型輸入/輸出組態。 圖式16至24b中所顯示之第二實施例揭示形成一部分圖 案化之VFQFP-N型引線框架之一方法，其係尤其適合於批 量生產FC電子封裝。經製作以適應覆晶之引線框架將在下 文中稱作FCL以將其與習用引線框架區分。此乃因，不像 習用引線框架，FCL更堅固且更適應於自動化製造線，如 下文所闡述。 153285.doc •37- 201232673 與習用通用沖穿型模板狀引線框架相比，FCI^^為網狀 結構。一網KFCL·之前側具有凹入區段（包含部分圖案化引 線），而背側係實心及扁平的。此提供機械剛性以在製造 製程期間表現得無扭曲或變形。在完成晶片附接及封裝之 密封之後，蝕刻背侧以將引線觸點彼此隔離。可藉由無電 鍍或沈浸製程來完成移除預鍍覆層或藉助其他可焊材料重 新鍍覆。隨後，單個化所得的經囊封封裝而不必將其切割 成任何額外金屬。因此，應明白可輕易地製造具有甚細小 幾何形狀（諸如具有VFQFP_N封裝）2FCL ,此乃因引線係 藉由網狀或網式結構固持在一起而直至最終的單個化步驟 才完全彼此分離。 像已經揭示的第一實施例之部分圖案化之引線框架一 樣，第二實施例之FCL亦係由一金屬薄片（較佳地係如圖4 中所顯示之銅膜）形成，其中預鍍覆前表面及背表面兩 者’或如前文所陳述，可將鍍覆延緩至一稍後步驟。（應 注意’由於用於兩項實施例之製程步驟係類似的，因此參 考編號已酌情保持為相同，表示具有撇號的第二實施例之 彼等參考編號除外。同一參考編號（100)已針對用於兩項實 施例之金屬膜而保持一致）。然後，以光微影方式圖案化 經預鍍覆之前側（110，）以形成晶片接收區域（115，）、圍繞晶 片接收區域之引線部分（113’）及其他中間區域（in·)。在下 文所揭示之一後續製程步驟中，將引線之一個端部分連接 至一PC之端子’而將另一端部分連接至下一級封裝。包括 一晶片接收區域及周圍引線之區域有時稱作一晶片位置， 153285.doc • 38 - 201232673 類似於具有線接合晶片之晶片位置。可在以鏈輪方式連續 至卷軸之i%續銅薄片輥上形成包括複數個晶片位置之 複數個引線框架以輕易地使包括一個或多個晶片位置之引 線框架之形成自動化。圖16圖解說明兩個晶片位置，其將 形成至1¾個對應的引線框架中’該等引線框架又將係自其 將形成之兩個封裝之部分。 然後藉由透過钮刻之部A圖案化而將針對圖16中所圖解 說月之兩個日日片位置而顯示之圖案轉移至金屬膜（⑽）中。 圖Π中所顯示之部分圖案化可最多為金屬條帶之厚度的一 半、四/刀之一，或者就此而言任何比率，且可藉由考量影 響包含撓性、剛性及熱厚度（或導熱率）之製造性參敷的各 種因素來確；刻量。可基於包含晶片大小之給定晶 片位置及引線（其可用於一給定封裝中或下一級封裝中之 封裝之間之層級間或層級内連接）所需之小型化之程度來 確定引線觸點區域（113’）及晶片區域（115，）之橫向尺寸。尤 其應注意，由於指狀引線之網式結構，對引線框架之細小 特徵及尺寸穩定性的製造性關注現在不那麼重要。 然後翻轉覆晶（FC)( 130')使得晶片之前側上之端子（丨35,) 位於如圖1 8中所顯示之引線之一個端部分上。在一稍後步 驟中’引線之相對端將形成至電觸點中，以供連接至下一 級封裝（諸如一卡或一板）。然而，首先，透過如該技術中 所實踐之一晶片連結爐發送圖18中所顯示之網狀引線框架 結構上所組裝之晶片。對焊料球進行回谭以使回焊受 限制，從而形成焊料柱。由於根據本發明所形成之引線框 153285.doc •39· 201232673 架具有穩固座落並固持在一扁平表面上之一實心、連續背 側，因此引線之網狀結構並不在晶片連結爐周圍顫動或跳 動’從而產生極佳的晶片連結。因此，所揭示之方法改良 最終產品之可靠性’即VFQFP-Ν型封裝之可靠性。 在晶片連結之後，然後晶片連同原始金屬膜之前側上的 部分圖案化之引線（例如）藉由一樹脂密封地囊封於一模製 材料中，如圖中所顯示。囊封物（14〇，）形成於包含引線 (113·)之表面的所有曝露表面周圍、焊料球（135，）周圍、晶 片下面、沿凹人晶片接收區域⑴5.)之垂直壁以及凹入區 域⑴7，)之垂直壁’牢固地固持至一扁平表面上之金屬條 帶（1〇〇)之未經姓刻、實心及扁平背側除外。當提起所得的 ㈣製封裝時，乾淨的㈣現在可用於進—步處理。在此 貫施例中亦消除至封裝之下側上之覆蓋區的模製閃光之通 常所遇到的問題。 現在可藉由在製程開始時，透過與自前侧部分地触刻之 圓案對準之封裝之背側進行圖案化而使引線（113,)輕易地 彼㈣離。背面钮刻會繼續，直至達到模製材料。此係顯 20中’其中移除引線框架之網狀部分(即區域⑴n =)=片區域⑴5.)彼此斷開，且使引線⑽)彼 Γ 案化金屬之㈣方法可或可不與用於 '丁。p分蝕刻之方法相同。而且，自背側之蝕列時 間可端視於自前側所. ㈣之钮刻時 前側之㈣時間之部分敍刻之程度而不同於用於 經定製以適合對最心』分蝕刻引線框架之初始形成可 最終封裝之自動化、品質、可靠性及功能 153285.doc 201232673 性之製造要求。在用作一化學抗姓劑之底部上之預鑛覆層 (120)可經剝離以曝露金屬條帶⑽)。為保護材料且便於 安裝至印刷電路板，可將可谭材料（諸如無電鑛Ni/沈浸 Au、沈浸Sn或其他材料）鍍覆至金屬條帶（1〇〇)。 作為一最終步驟，其次將具有用於圖解說明本發明之目 的之兩個囊封晶片位置之圖2Q的封裝係單個化成草一接 近晶片大小封裝（CSP)，其比VFQFP-N型封裝多，如圖21 中所”、’貝示。-單個化式部分圖案化之引線框架封裝之一俯 視圖係顯示在圖22a中，其中顯示引線⑴3,)彼此隔離且連 接至晶片（130，）之下側上之焊料球（135ι)。圖22b顯示晶片 與連接至可提供於—卡或—板（1 5G1)上之-外部觸點（145，） 的引線中之-者之間的封裝之一拐角之一放大視圖。預鑛 覆表面（120')已經製備以連結至下一級觸點，如同一圖中 所顯示。引呆留或移除預鑛覆層或遮罩層，此視為此時的 適當或所需方式。亦可在該製程中酌情針對個別情況在其 他時間移除預鍍覆層或遮罩層。而且，將引線（113,)之下 側（114')曝露至周圍環境’因而提供增強的冷卻。在某些 情形中’可將一塗層施加至下側（114)以減小板安裝期間可 月色短路之機會，尤其對於細小間距應用而言。 可使用與以前所揭示之技術相同之技術來防止囊封物與 FCL之表面的分層，即，藉由併入網式引線框架之凹入區 域U15')及（117’）之垂直壁上之圖13a至13f的不規則形狀之 空腔。此等表面增強之形成可輕易地併入至自前側之部分 蝕刻中。此對於自背側進行蝕刻而言將沒有必要，此乃因 153285.doc •41 · 201232673 模製材料僅囊封自前側而部分形成之表面。 圖23將本實施例之方法概述為以自前側部分圖案化引線 框架（20〇|)至一金屬條帶中開始，並以形成期望晶片接收 區域及周圍引線之此一方式背面圖案化（24〇，）同一金屬條 帶結束。FC放置（210’）、FC晶片連結（220')及囊封（230，）之 中間步驟係全部在機械及熱穩定FCL中完成，此乃因引線 仍透過金屬膜中的經部分蝕刻網狀結構而連接。注意到以 下亦很重要，僅在已將封裝之所有組件固定在囊封物中之 後才透過背面圖案蝕刻（24〇|)來選擇性地移除引線之網部 分，而且使引線彼此分離以進行適當隔離。因此，不需要 在單個化（250，）成單個接近晶片大小封裝期間切穿任何金 屬。 本發明之方法可用以形成各種封裝，諸如一陣列類型之 部分圖案化引線框架，其中谭料凸塊之—區域陣列可同時 晶片連結至上方使晶片翻轉之引線框架，類似於本文所揭 示之具有-周邊焊料凸塊集之方法。而且，可同時形成部 分圖案化之引線框架本身之—陣列，且然後亦同時連社 FC’後輸亥陣列單個化成多個分離的VFQFp__封裝。 而且，每一所得的csp可因此在用於連結至下—級封裝上 的陣列類型之封裝下面具有焊料凸塊、墊或其他電連接以 形成具有著陸點栅格陣列之一經钮刻之引線框架封裝，或 圖24a及24b中所顯示之ELGA型封裝。圖24a中顯示一叫視 圖’其中在引線⑽·)上方形成晶片墊⑽,）。在背面圖案 化之後，引線（145，）係彼此電隔離以連結至下一級封裝。 I53285.doc -42· 201232673 可透過沈浸錫浸潰或無電鑛錄鎮覆藉助任一數目個可焊材 料閃光π成（145)之曝露的底部表面。el(Ja封裝之底部表 面⑴1’)係顯示在圖24b中，其中_陣列圖案用於電連接件 (145')。 焊料凸塊之形式可係一金屬凸塊（諸如一銅柱凸塊）， 其中每-凸塊係由具有約75微米高度的一cu軸組成，該軸 具有详料（或無Pb)蓋以造成約⑽微米之—總高度。當使 用CU柱凸塊時，「焊料凸塊」將係「焊料蓋」。使用Cu柱 在晶片表面UBM與板接觸點之間給出大於5〇微米之一凸出 物，且使塑膠囊封物能自&地流動且覆蓋覆晶下面的裂 縫。 由於形成ELP、ELPF或ELGA封裝中之任一者的部分蝕 刻方法在各個製造步驟期間提供強固性，因此其他形式的 電子封裝亦可行。-種此類形$包括纟發明之引線框架封 裝之線接合至下一級封裝。超聲波接合技術由於引線本身 之脆弱性而無法用於習用引線框架上，除非將其附接至一 實心基底以提供穩定性及強度。相比而言，部分經蝕刻之 引線框架由於其網式結構而係穩定的。部分圖案化之引線 框架之未經蝕刻及經預鍍覆底部表面（12〇，）提供實心接合 區域或柱狀物，以有效地將超聲波能量應用於接合在ELp 或ELPF之區塊或條帶上的鋁線楔形物。根據本發明之另 一態樣’因此鋁線（121)係以超聲波方式附接至部分經钮刻 之引線框架之一區塊或條帶之底部表面，如圖25a中所顯 示。線直徑範圍係在約0.001英吋至0.020英忖之間，後者 153285.doc -43- 201232673 直徑代表帶狀物而非線。然後對該等條帶進行囊封、背面 圖案化及單個化以形成個別接近CSP。需要超聲波接合， 此乃因其避免曝露至藉由球柵格陣列型封裝所經歷之球接 合溫度，並因此獲得經改良之可靠性。亦可應用銅線球接 合，如圖25b中所顯示。將理解圖25a及25b中所顯示之csp 可係ELP及ELPF中之任一者。 本發明在用於電子封裝之製造製程中促進若干個額外優 點。舉例而言，在背面蝕刻之後且在單個化之前，在封裝 係仍配置於封裝之一區塊中之同時，該區塊將内在地準備 用於條帶測試。與將封裝處理為個別單元相比，此提供一 重大優點。在將封裝配置於一區塊中之同時對其進行條帶 測試會改良測試之可靠性。 本發明亦使一製造商能夠生產具有兩列或三列交錯引線 之封裝，該等引線可使一給定封裝之I/C)能力倍增。引線 框架之扁平連續底部表面使得能夠使用通用組裝設備，其 不需要針對每一應用而改裝，且其對於自動化係完全靈活 的舉例而s ’ 2x2到12x12個封裝區塊之間的處理不需要 任一機械變化。另外，本發明輕易地促進構造具有用於每 腳之一「凸出物」之封裝（例如在腳之表面處的模製體 之底部之間的2密耳處）。當晶片封裝欲連接至下一級封裝 (諸如一板）時，該凸出物提供額外優點。 圖26a及26b圖解說明本發明之一態樣之一實施例，其中 兩個曰曰片（505、510)晶粒堆疊於一引線框架（5〇〇)之一晶片 塾（515)上。下晶片（5〇5)(即黏附至晶片墊接收區域卩15)之 153285.doc 201232673 B曰片）電連接至晶片.墊區域（515)周圍之内部電引線集 (520)。上晶片（51〇)(即黏附至下晶片（5〇5)之頂部之晶片） 電連接至晶片墊區域（515)周圍之最外部引線集（525)β藉 助保護晶片及線免受損壞之一囊封物（53〇)來囊封晶片。雖 然圖26a及26b _之晶片（5〇5、5 1〇)係符合本發明之線接合 晶片，但該等晶片中之一者或多者亦可係覆晶。下晶粒堆 疊晶片（505)在大小方面係大於上晶片（51〇)。雖然在某些 實施例之說明中下晶片及上晶片並未彼此電連接，但此等 晶片可（例如）藉由自一個晶片至另一晶片的線而電連接。 可藉由將各個晶片之端子連接至自引線框架延伸之電引線 之端部分來完成形成電連接之步驟。 圖27a至27c圖解說明本發明之一實施例，其中晶片墊區 域（550)係凹入的以允許經改良之晶粒堆疊及封裝高度之減 小。在圖27a至27c中，三個晶片（555、56〇、565)經晶粒堆 疊以形成一晶片封裝。如可在圖27a中看出，已移除晶片 墊區域（550)之内部以便僅存在一正方形外環。將一晶片 (5 55)放入於此晶片墊區域中並將其附接至該晶片墊區域。 雖然圖27a至27c中顯示符合本發明之三個晶粒堆疊式晶片 (555、560、565)，但可存在任一數目個晶粒堆疊式晶片。 在圖27a中，凹入的晶片墊區域（55〇)之内部係顯示為引線 框架之頂部表面。即，僅該晶片塾區域之外正方形環（575) 已沈積於引線框架之頂部上，且該晶片墊區域的整個内部 (550)並未沈積或自引線框架得以移除β在本發明之替代性 實施例中’將一薄材料層沈積於該晶片墊區域之内部，或 153285.doc -45- 201232673 移除曰曰片塾内部區域之一部分。在此等實施例中，該晶片 墊區域之内部將高於引線框架背面，但仍低於該晶片墊區 域之外部分’從而為-晶片之附接提供凹入的晶片墊區 域。 雖然在圖27a至27c中，最大晶片（555)定位於晶粒堆疊之 底°卩上，而最小晶片（565)定位於頂部上，但可定位該等晶 片以使最大晶片在頂部上而最小晶片在底部上。最高晶片 (565)係顯示為連接至中間晶片（56〇)及引線框架（57〇)上之 電引線（580、585)。中間晶片（56〇)係顯示為連接至最高晶 片（565)及引線框架上之電引線。覆蓋晶粒堆疊式晶片 (555、560、565)之囊封物（59〇)防止晶片封裝之線在操作 或安裝期間遭到損壞。使用一黏合劑（諸如一導電或一非 導電環氧樹脂）或使用一絕緣材料將各個晶片附接至引線 框架（550)或將其彼此附接。 圖28a及28b係具體化本發明之若干個態樣之引線框架之 透視圖。圖28a顯示在將晶片附接至引線框架之前具有四 個晶片墊區域（605、610、615、620)之一引線框架（6〇〇)。 圖28b顯示在已將晶片（625、630、635、640)附接至晶片墊 區域（605、610、615、620)並將其電連接至引線框架之後 的同一引線框架（600)。 圖28a將引線框架（6 00)顯示為具有用於線接合晶片之三 個晶片墊區域（610、615、620)以及用於一覆晶之一個晶片 塾區域（605)。用於線接合晶片之三個晶片墊區域中之兩者 (61 5、620)並非係凹入的而剩餘晶片墊區域（61 〇)係凹入 153285.doc -46 · 201232673 的。此等晶片墊區域(61〇、615、620)包括形式為晶片塾區 域之=周長上形狀為-「τ」之鎖定區域之變更（645)。此 等鎖定特徵為欲黏著之一囊封物（650)提供額外的表面積， 且提供用以保留囊封物而無囊封物之橫向移動之構件。 在圖28b中，並非凹入的晶片墊區域（615、620)各自支 標經由至引線框架的電引線所連接之—單晶片（635、 640)。藉由一層電引線形成用於覆晶（625)之晶片墊區域 (605)，且將一覆晶（625)放置於此等引線之頂部上以形成 電連接。與線接合晶片（63〇、635、64〇)相比，覆晶（6h) 從而節省引線框架（600)上之空間。雖然為澄清起見僅將單 晶片顯示為附接至引線框架上的兩個非凹入晶片墊區域 (615、620)，但在本發明之其他實施例中，可在此等線接 合晶片或覆晶之頂部上放置一個或多個晶片。 在圖28b中，引線框架上的凹入晶片墊區域（61〇)支撐複 數個晶粒堆疊式線接合晶片（統稱為630)。此等晶片係使用 一黏合劑（諸如一導電或非導電黏合劑，例如環氧樹脂）或 使用、、邑，·彖層附接至晶片塾區域（610)。凹入晶片墊區域 (610)之外周邊包括形式為形狀為一「τ」的鎖定區域之變 更（645) 〇 圖28a及28b中之引線框架（6〇〇)亦具有定位於覆晶晶片墊 區域（6〇5)與凹入晶片墊區域（610)之間的電引線（通常為 655) ’其還可用於除電腦晶片以外的其他元件。舉例而 °此專電引線可係諸如半導體元件、無源組件、電阻器 及電谷盗或其他非晶片組件[通常顯示為（66〇)]之元件，其 153285.doc -47· 201232673 用以補充晶片封裝中的晶片之功能。在圖28b中，電容器 或電阻器附接至此等電引線。 可以將晶片逐一地晶粒堆疊於晶片墊區域上且然後在晶 粒堆疊且電連接下一晶片之前將其電連接至引線框架。另 一選擇為，可晶粒堆疊所有晶片且然後可將整個晶粒堆疊 晶片集電連接至引線框架。在另一實施例中，可與晶片塾 區域分離地晶粒堆疊該等晶片，且然後整個晶粒堆疊晶片 集可附接並電連接至引線框架。雖然其將方便將晶片及無 源組件附接至引線框架，且然後後跟線接合（或形成電連 接之其他方法），但可以任一次序形成晶粒堆疊及電連 接。 圖29a至29c顯示可應用於晶片墊區域之各種類型之變更 的實施例。在圖29a中，變更（705)在晶片墊區域（72〇)之外 部邊緣上採取一「τ」形狀切口之形式。在圖29b中，變更 (710)之形式為沿晶片墊區域（725)之外周長定位之空腔或 穿孔。圖29c圖解說明形式為沿晶片墊區域（73〇)之外周長 之切口的變更(715)。此等變更給經囊封之晶片封裝提供增 加的強度及一經改良之穩定性。 雖然圖29a至29c中的變更或鎖定特徵（7〇5、71〇、715) 定位於各別晶片墊區域（72()、725、73G)之周邊上但該 變更亦可放置於晶片塾區域之其他部分上。舉例而言了 等變更可在將並非藉由一晶片覆蓋之晶片墊區域之内部 分上且因此可用一囊封物加以填充。 在圖29a至29c令，已將該等變更顯示為係定位於晶^ 153285.doc •48· 201232673 區域上。在本發明之額外實施例（諸如圖30a至32f中所圖解 說明之彼等實施例）中，該等變更可定位於定位在引線框 架上之電引線上，且該等晶片可電連接至該引線框架。該 等變更亦可同時放置於晶片墊區域及引線上。 圖30a至31b顯示具有變更之電引線之若干個實施例之俯 視圖及側視圖。圖30a至30d圖解說明各種類型之引線 (73 5、740、745、750)及此等引線中之某些之剖面。圖3〇b 顯示一變更可具有定位於引線（740)之一内表面（755)中之 一可接合材料。圖31a及3 lb顯示引線（760、765)之表面 (7 7 0、7 7 5 )可經粗糖化以達成一囊封物之經改良之保持 力。 圖32a至32f圖解說明圖30a至3 lb之實施例之透視圖並例 證具有變更之電引線之若干個實施例。圖32a圖解說明具 有一晶片墊區域（805)之一引線框架（8〇〇)。該圖之晝圓圈 部分（810)圖解說明具有變更之電引線（815)。圖32b至32f 例證此等類型之引線。圖32b至32d顯示引線（820、825、 830)之實施例’其通常類似於圖30a、30c及30d中所圖解 說明之彼等實施例。圖32e圖解說明一引線（835)，其通常 類似於圖30b中所顯示之引線。圖32[圖解說明一引線 (840) ’其具有形式為沿該引線之周邊之水平切口的表面粗 糙化’從而給予該引線一階梯式外觀。一化學或另一類型 之製程可用以獲得圖32f中所顯示之表面粗糙化。可結合 引線及晶片墊變更來應用此表面粗链化。 圖33a至33b圖解說明本發明之一另外實施例之一態樣的 153285.doc •49- 201232673 剖視圖，其中使用一夾子（925)來替代線接合以給晶片尺寸 封裝（935)&供電力並從而改良其功率容量。圖33a圖解說 明使用線接合晶片（905及910)之此實施例，且圖33b圖解說 明用於覆晶（顯示為一單晶片907)之實施例。該夾子提供與 線接合相比大致更大量之電力且因此允許所得的晶片封裝 (935)之一經改良之可靠性。該夾子亦協助自該等晶片散 熱 Μ使用e亥失子時’最南晶片[例如圖33a中的（910)]將 含有用以將電信號發射至印刷電路板之引線。 在圖33a中，線接合晶片（9〇5及910)係放置於晶片墊區域 (900)上且經由線（920)電連接至引線（915)。雖然電連接之 數目及類型將取決於具體實施例，但複數個線（92〇)係用以 將晶片（910)連接至複數列電引線（915)。在圖331)中，一覆 晶（907)係放置於自一引線框架突出之電引線（諸如915) 上。雖然實際上可存在形成晶片尺寸封裝（93 5)之覆晶與線 接合晶片之任何組合，但為便於圖解說明起見，圖33b中 僅圖解說明一單覆晶（907)。 最上部晶片（907及910)之頂部表面係藉由一夾子（925)電 連接引線框架（900)上的一個或多個電引線（917) 〇在已將 晶片附接至引線框架之後，將夾子（925)接合至晶片之頂 部。可使用任何方便構件來將夾子接合至晶片。在圖33a 至33b中所圖解說明之實例中，一導電膏或焊料（93〇)係用 以將夾子（925)黏附至晶片（907及910)。夾子（925)可係由任 何導電物質（諸如一金屬或一金屬合金）製造。適當的導電 物質之實例包含銅及銀。端視於具體實施例，個別夾子可 153285.doc -50- 201232673 黏附至特定晶片’或可使用一成群方法使一整個導電條帶 或面板黏附至複數個晶片。在此後者實施例中，單個化之 動作切穿導電條帶或面板以有效地獲得個別晶片封裝。 隨後藉由一囊封物覆蓋堆疊式晶片且在單個化之後產生 根據本發明之晶片尺寸封裝（935)。 曝露的晶粒墊係通常用以提供一晶片尺寸封裝與一印刷 電路板（PCB)之間的一熱及電分離。然而，在某些例項 中，曝露的晶粒墊或晶片墊區域對一晶片或晶片尺寸封裝 之適當功能有害。舉例而言，某些印刷電路板設計在晶片 尺寸封裝下面具有主動電路，且此等電路在封裝具有一曝 露的晶片墊之情形下可出現故障。雖然在此等情形下使用 一 QFN(四方扁平無引線）封裝可呈現一可行性解決方案， 但經設計以使用QFN封裝之引線框架具有數個相關聯之組 裝困難。舉例而言，難以或不可能使用現有技術生產用於 無墊引線框架之QFN封裝，該等技術即，（a)藉助膠帶，其 中引線框架通常以map(模製陣列製程）格式，或（b)不藉助 膠帶，其中引線框架係以矩陣格式。 為克服此等困難，使用者將（a)使引線框架自底部得以半 蝕刻以便可在模製期間嵌入該墊，或（b)使晶粒墊顛倒。然 而，對於膠帶式map引線框架而言，存在執行線接合的問 題，此乃因膠帶將防止加熱器區塊（用於在將一半導體線 接合至引線框架之前對引線框架進行預加熱）與該墊接 觸。在線接合之後所執行之膠帶方法對生產良率具有負面 衫響。對於矩陣引線框架而言，可藉助一底座來設計加熱 153285.doc -51- 201232673 器區塊以在線接合期間支撐晶片墊區域。然而，此引線框 架設計具有一較低生產力，並因此將影響每小時單位生產 量並增加生產成本。 在此等情況下，一無墊ELP可提供經改良之功能性及減 小的故障機會。無墊ELP可維持一高密度設計且提供一更 強固的組裝製程。無墊ELP實施例具有—通常類似於ELp 晶片墊實施例之構造，但底部上沒有蝕刻保護。因此，無 墊ELP實施例並不需要對製造線進行重大改變。 無墊引線框架具有無一底部蝕刻遮罩或鍍覆層之一半蝕 刻晶粒接收區域。晶粒接收區域能夠比其他引線框架裝納 一更大晶粒大小，並可解決需要將晶粒完全隔離之裝置。 由於晶粒接收區域係凹入的，因此所得的晶片尺寸封裝將 具有一極低的輪廓，從而最小化其安裝所需要的高度。晶 粒附接材料（或黏合劑）因此將係非導電性的以防止電短 路，並將通常具有與模製化合物相同的顏色以提供一均勻 外觀。另外，晶粒附接材料或黏合劑應在背面蝕刻期間穩 定以防止損壞晶片尺寸封裝。晶粒附接材料可係此項技術 中習知之任何物質，諸如一可固化環氧樹脂或一膠帶（諸 如聚醢亞胺黏著膠帶 圖34a至34f圖解說明一部分圖案化之引線框架之一實施 例，其中缺少一晶片墊區域或一晶片接收區域，且將晶片 直接黏附至將形成引線框架之經㈣膜之底部。在晶粒附 接、囊封及背面圖案化之後，使晶片之底部曝露於晶片尺 寸封裝中》如圖34a中所顯示，部分經蝕刻之膜並沒有用 153285.doc •52- 201232673 以接收一半導體晶片之一隆起的晶片墊區域。 圖34a顯示已在前側上經部分钮刻之一金屬膜（刪）。可 藉助將促進稱後處理（諸如線接合）之一物質在一個或兩側 上預鍍覆該膜（1〇〇〇)。舉例而言，可採用一可線接合物質 (諸如NiPdAu或銀（Ag)，諸如沈浸Ag)來預鍍覆該膜之頂 部，且該膜之底部可係裸露的或藉助相同或另一可線接合 物質加以預鍍覆。在其他實施例中，一有機材料可用作蝕 刻遮罩。 在其前表面上蝕刻該膜（1000)以製備電引線部分 (1005) ’ 一積體電路晶片稍後將附接至該等電引線部分。 該膜具有使引線框架之部分分離的街道形區域（1〇35)，且 將透過此等街道形區（1035)單個化經囊封之引線框架以獲 得個別晶片尺寸封裝。將晶片安裝區域（1 〇 1 〇)蝕刻至該膜 之前表面中。此等晶片安裝區域（101 〇)之高度比引線低。 換言之，該膜（1000)係在引線（1005)之區域中蝕刻最少並 將在引線框架之其他部分中蝕刻最多。 在已製備並適合地蝕刻該膜（1000)之後，將一半導體或 積體電路晶片（1020)晶粒附接至該膜，如圖34b中所圖解說 明。可使用任何方便物質、晶粒附接材料或黏合劑 (1015)(其通常將係非導電的以避免電信號之傳播）來附接 該晶片（1020)。 在一個實施例中，可使用一非導電壤氧樹脂（1 〇 15)來附 接晶片（1020)。該黏合劑可應用為一流體或黏性液體’其 然後硬化或形成内部交聯以形成一牢固、耐久接合。該黏 153285.doc • 53- 201232673 合劑或晶粒附接材料（1015)將係可見的並曝露在所得的曰 片尺寸封裝（1040)之底部上且因此將需要具有長期熱及2 械穩定性》在其他實施例中，該黏合劑可形式為一膠帶 (諸如聚醯亞胺黏著膠帶）的。該膠帶通常由兩側上用二黏 著物質（諸如一熱塑性聚合物）塗佈之一基底膜組成，且該 膠帶可係黏的或不黏的。在另外的實施例中，該黏合劑係 一固體塑膠物質，其在適當位置固化或凝固以提供晶片與 引線框架之間的牢固附接。各種種類之黏合劑、膠帶及= 他晶粒附接材料係習知的且可商用。 在一個實施例中，黏合劑（1〇15)及周圍囊封物（1〇3〇)皆 為黑色，從而向完成的晶片尺寸封裝（丨〇4〇)呈現一均勻著 色。在其他實施例中，該黏合劑及囊封物係不同顏色。在 另外的實施例中，—製造商可教為該黏合劑&囊封物選 擇具體互補或對比顏色（例如）以提供一特定商業包裝。 雖然該黏合劑⑽5)之厚度將必須足夠厚以具有機械穩 疋性並承爻引線框架之背面蝕刻，但該厚度並不重要。該 黏合劑（1015)通常將覆蓋積體電路晶片（1〇2〇)之整個底部 表面以避免在後續的背面蝕刻或背面圖案化步驟期間以化 學或機械方式損壞晶片》 一旦已將晶片（1020)晶粒附接至膜（1〇〇〇)，就（例如）使用 引線線（1025)將該晶片連接至電引線（1〇〇5)，如圖34〇辛所 圖解說明。使用一囊封物0030)密封（圖34d)該晶片（1020) 及線引線（1025)。如上文所論述，囊封物（1〇3〇)可係此項 技術中習知之任何物質。行業中所使用之通用囊封物之一 J53285.doc •54- 201232673 非限制性清單包含矽石微粒填充式環氧樹脂及液體環氧樹 脂。通常將該囊封物作為一液體或黏性液體施加至安裝於 引線框架上或黏附至該引線框架之各種元件。固化該囊封 物會產生一強硬、耐久塗層，其保護晶片尺寸封裝中之下 伏元件免受損壞。 在已固化囊封物（1〇3〇)之後，然後背面蝕刻引線框架 (1000)以隔離電引線（1〇〇5)，如圖34e中所圖解說明。在背 面蝕刻期間大致或完全移除下伏於晶片（1〇2〇)之引線框架 (1000)之部分（即，原始晶片安裝區域）直至晶片黏合劑 (1015)。 然後沿街道形部分（1035)單個化引線框架以產生適合於 後續應用（諸如附接至電腦電路板）之個別囊封之晶片尺寸 封裝（1040)。一製造商可針對識別目的而選擇在完成的晶 片尺寸封裝上印刷或網版印刷一商標、批號或其他種類之 標記。 圖35及36a分別圖解說明經由圖34a至34f中所顯示之序 列加以製備的晶片尺寸封裝（1040)之仰視圖及剖視圖。在 圖35中，固化的黏合劑（1015)係顯示在晶片尺寸封裝 (1040)之中心中作為較亮顏色的不規則正方形。以一較暗 顏色顯示之囊封物（1030)圍繞固化的黏著性物質（1〇15)。 囊封物（1030)覆蓋並包絡積體電路晶片（1〇2〇)、線（1〇25)、 引線（1005)以及可黏附至引線框架或安裝於其上之任何其 他組件。 圖3 6b圖解說明本發明之另一實施例，其中複數個積體 153285.doc -55· 201232673 電路晶片（1020、1050)係晶粒堆疊在一完成的無塾晶片尺 寸封裝（1070)中。雖然圖26b及36b兩者皆顯示具有晶粒堆 疊式晶片的本發明之實施例’但圖26b中之實施例具有一 晶片墊（5 15)而圖36b中之實施例運用無墊技術。圖2讣與 36b之比較顯示，缺少晶片墊會減小所得的晶片尺寸封裝 之尚度，從而允許製備具有一較低輪廓之晶片尺寸封裝。 可使用所揭示之發明方法來製備圖36b中所圖解說明之 實施例。簡而言之，首先，將下晶片（1〇2〇)放置於並沒有 一 aa片塾之一部分圖案化之引線框架（此圖中未圖解說明） 上，且使用一晶粒附接材料（1 〇 1 5)(諸如—黏合劑或環氧樹 脂）將晶片（1 020)黏附至該引線框架。然後使用一黏著物質 (1045)(諸如一導電或非導電環氧樹脂或一絕緣材料）將上 晶片（1050)放置於下晶片（102〇)之頂部上並使其黏附至該 下s曰片。使用線接合將晶片（1 〇 2 〇、1 〇 5 〇)電連接至引線框 架。 可在將母一晶片放置於引線框架上之後按順序進行電連 接（1025)。即，可將第一晶片（1〇2〇)放置於引線框架上並 電連接至s玄引線框架，且然後可將第二晶片（丨〇5〇)放置於 第一晶片（1020)上並電連接至該引線框架。在其他實施例 中’首先在適當位置中晶粒堆疊晶片（1〇2〇、1〇50)，且然 後進行電連接（1025)。此等堆疊及電連接步驟之各種組合 係可行的且在本發明之範缚内。 在晶片（1020、1050)晶粒堆疊並電連接（1〇25)至引線框 架之後’然後用一囊封物（1 〇3 〇)來囊封引線框架以將晶片 153285.doc -56- 201232673 及電線永久地安裝至引線框架，然後背面圖案化、蝕刻並 酌情完成引線框架之背面以隔離電引線（1005)。在此背面 圖案化製程期間，完全移除晶粒堆疊式晶片下面的引線框 架之部分，且僅引線（1005)自完成的晶片尺寸封裝「突 出」。一般而言，在背面圖案化之後將保留之原始引線框 架之部分僅係電引線（1 〇〇5)。最後，在街道形區中單個化 晶片尺寸封裝以產生用於後續應用之個別晶片尺寸封裝 (1070)。 根據本發明之另一態樣，可在晶粒附接之前部分圖案化 或部分蝕刻引線框架之頂部及底部兩者。如圖37a中所圖 解說明’可在組裝晶片尺寸封裝之前在兩側上#刻引線框 架（1100)。引線框架之兩側上的蝕刻可具有均勻深度。另 一選擇為，蝕刻可係不均勻的且一個側可比另一側圖案化 得深。舉例而言，頂部（例如區域1160)可比底部（例如區域 1165)圖案化得深。 雙側蝕刻准許減小用於將最終被移除之引線框架之膜之 部分的厚度。因此，蝕刻將進行得較快並從而增加生產速 度且減小成本。部分圖案化可將該膜之經蝕刻部分的厚度 減小任一方便的量。舉例而言，引線框架之部分圖案化片 段可移除蝕刻區域中的原始膜厚度的25%至9〇%。 可用一抗蝕劑材料預圖案化引線框架材料。該抗蝕劑可 係一金屬或一非金屬（諸如一有機抗蝕劑），並可烤爐固化 或UV固化。此預圖案化製程在此項技術中習知。 替代用-金屬預鍍覆引線框架，可用一可印刷油墨(諸 153285.doc •57· 201232673 如環氧油墨或一模板油墨）或一有機材料（諸如聚醯亞胺樹 脂，其作為背面蝕刻之前的一蝕刻遮罩）來印刷引線框 架。此技術有利地允許成本減小及流線製造。從材料觀點 看，將可印刷油墨或一有機物質用作一#刻遮罩允許該製 造商從許多製造商獲得引線框架來源，此乃因並非所有供 應商均可在兩側上預錄覆引線框架。在此一例項中，引線 框架供應商將僅在頂部上蝕刻並鍍覆引線框架，從而使底 部未完成。舉例而言’引線框架之底部可係裸金屬（諸如 銅）。用一可印刷油墨或一有機物質遮蔽的成本通常比用 一貴金屬（諸如鈀、金、鉑、鍺、銀或釕或其合金，其為 已用以預鍍覆引線框架之物質的實例）遮蔽的成本少。另 外，在蝕刻之後移除油墨通常比移除貴金屬容易。 亦可在蝕刻之前預鍍覆引線框架。在引線框架之頂部及 底部表面上’預鑛覆材料可相同或不同。適合的預鎪覆材 料之實例包含可線接合材料（諸如試鍍型Ni/Pd/Au及銀 (Ag))，及可焊材料（諸如Sn/Pb、無鉛焊料、沈浸錫無電鍍 鎳或試鍍型Au(金））《在本發明之一實施例中，用一可接 合材料預鍍覆前表面且用一可焊材料預鍍覆背表面。在另 一實施例中，可用一可線接合材料預鍍覆前表面，且用一 抗蝕劑預鍍覆且覆蓋背表面。在另外的實施例中，可將一 有機材料印刷或施加至引線框架上以用作一光阻劑。 圖36a顯示一膜（11〇〇)，其已被蝕刻以形成一晶片墊 (1110)及複數個電引線（1105)〇該膜之頂部已被蝕刻至比 該膜之底部[如⑴6S)所例證]一更大程度[如（116〇)所例 153285.doc •58· 201232673 證]。圖36b顯示經由線接合（1125)電連接至圖36a中所顯示 之引線框架的一晶片（1120)。在圖36b中，已使用一黏合劑 (1115)將一積體電路晶片（112〇)黏附至引線框架（u 〇〇)，且 已用環氧樹脂囊封物（1130)覆蓋晶片封裝。街道形區 (1135)分離電連接及囊封之晶片（1120)。 在已將晶片（1120)黏附至引線框架之晶片塾（i i丨〇)並囊 封之後，引線框架之背表面可經背面圖案化及蝕刻以隔離 電引線（1105)與晶片墊（1110)，或以其他方式電分離引線 框采之各個部分以建立期望特徵。由於已經部分钮刻背表 面，因此此背面蝕刻製程將更迅速地繼續並從而有利地改 良每小時單位（UPH)生產力並降低成本。 先則引線框架之底部晶粒墊通常係平坦的。圖37b中圖 解說明具有一平坦底部晶粒墊之一引線框架之一實例。然 而在某些例項中，此等平坦晶粒塾係傾向於當將晶片尺 寸封裝安裝至印刷電路板時導致谭料空隙問題。在不受理 論束缚之情形下，據信烊料空隙係主要由㈣㈣ 引起的ί見象。雖然焊料空隙會減小電觸點之效率並因此 可引起第二級可靠性問題，但通常僅可藉由X射線顯微鏡 或破壞性微切片來债測焊料空隙。 根據本發明之另一態樣’一引線框架可具有一已劃影線 之底知粒塾。圓38中顯示此—晶粒墊之__實施例。影線 ()可形成橫跨晶粒墊(121〇)之一通道並減小晶粒墊與 :刷表面板之間的接觸表面積，從而有利地減少焊料空隙 置影線或通道（1255)充當通氣口以便在回谭期間不存在 153285.doc .59· 201232673 捕獲空氣。 藉由在引線樞架之底部側上的墊下面製作小鍍覆遮罩陣 列來獲得已劃影線之底部墊（1210)。在蝕刻期間，此鍍覆 遮罩陣列將建立橫跨尨部晶粒墊之半蝕刻通道。該遮罩將 在刻製程期間用作一抗姓劑。 該蝕刻遮罩可係鎳/鈀/金合成物（NiPdAu) '銀（Ag)、銻 (Sn)、鎳（Ni)或其混合物，或任何非金屬或有機材料或可 施加或印刷至引線框架上之油墨。可酌情烤爐或uv固化 該钱刻遮罩。其他適合的遮罩及光阻劑物質已為熟習此項 技術者所熟知。可如先前所論述來執行遮蔽及蝕刻之製 程。 圖38顯示具有一已劃影線之底部晶粒墊（121〇)之一晶片 尺寸封裝（1240)，複數個積體電路晶片（122〇、125〇)係安 裝至s玄墊。下晶片（1220)係經由一黏合劑（1215)黏附至已 劃影線之晶粒墊，且上晶片（125〇)係經由一黏合劑（1245) 黏附至下晶片（1220)。晶片（122〇、125〇)係經由線接合 (1225)電連接至電引線（12〇5)，雖然在其他具體實施例 中，晶片(1220、1250)亦可彼此電連接。用可係環氧樹脂 或另一物質之一囊封物（1230)來囊封該等晶片。 雖然圖38顯示包括兩個晶粒堆疊式積體電路晶片之一晶 片尺寸封[但*本發明之其他*施例中，料在一單晶 片，而在另外的實施例中，可存在三個或多個晶粒堆疊= 晶片》所有此等實施例係在本發明之範相。亦可存在黏 附至引線框架上的各個晶片墊之不同數目個晶片。舉例而 153285.doc -60· 201232673 言，一引線框架之一個晶片墊可具有一單晶粒安裝晶片， 而同一引線框架上的另一晶片墊可具有三個晶粒安裝晶 片。因此，本發明可用以在一單個引線框架上製備數個不 同及非相同晶片。 圖39a及3 9b圖鮮說明根據本發明之另一態樣之—晶片尺 寸封裝（1340)之兩個實施例，其中電著陸點具有不同結 構。圖39a圖解說明一晶片尺寸封裝（134〇)，其中所有的電 著陸點（1305)係正方形且配置成晶片（132〇)周圍的兩個同 心列以維持每一著陸點分開充足的距離。圓39b圖解說明 一晶片尺寸封裝（1340)，其中電著陸點（13〇5)之形式為引 入引線（1309)。線（1325)形成圖39a及39b中晶片（mo)與電 著陸點（1305)之間的電連接。可在蝕刻期間製備引入引 線’或可使用習用技術（諸如網版印刷）將該等引入引線施 加至引線框架上。在替代性實施例中’引線框架上之著陸 點中之任一者可具有任一形狀，諸如橢圓形 '矩形或圓 形。引線框架上任一處之此等替代性著陸點形狀係在本發 明之範疇内。 圖39a中將晶片（1320)連接至電著陸點之線（1325)比圖 39b中將晶片（1320)連接至引入引線之線（1325)長。雖然圖 39a中之實施例提供優於先前技術引線框架之一明顯改良 且高度有效，但有時有必要注意避免致使該等線觸碰或以 其他方式變得太靠近。偶爾使用專門的迴路技術來使該等 線保持分離。雖然此等技術有時可減缓線接合製程，但其 係有用的。相比而言，在圖39b中，引入引線（1309)之端相 153285.doc -61 - 201232673 當罪近IC晶片（13 2 0)之用这七通*山7 之周邊上之電端子且因此形成電連接 所需之線量甚短。由於此等線(1325)照例係由金形成，因 此用於線接合之線之較短長度准許所使用之金量減小且因 此降低生產成本。 雖然將圖39a中之電著陸點（13〇9)圖解說明為符合本發明 之引入引線’但該等著陸點中之某些可形式為引入引線而 其他著：點具有另-形式’諸如習用正方形引線。舉例而 言，最靠近晶片之電著陸點可形式為正方形、圓形或擴圓 形著陸•點，而_晶片較遠之電著陸點可具有引入引線。 此等組合係在本發明之範嘴内。 圆40a圖解說明根據本發明之另一態樣之一晶片尺寸封 裝（1340)之-實施例之—剖視圖，其中心日日片係、具有在該 晶片之周邊關配置之焊料點（138〇)之一覆日曰曰，且該晶片 電連接至在該晶片下面延伸之引入引線（1期）。圖働圖解 說明-晶片尺寸封裝(1340)之另一實施例，其中晶片 (1320)係具有在該晶片之底部上配置成一陣列之焊料點 (138〇)m該等烊料點f連接至在該晶片下面延伸 之引入引線（1309)。如圖39及40中所圖解說明，可在線接 合及覆晶實施例兩者中可藉助本發明有效使用引入引線。 圖41圖解說明使用引入引線及一無墊選項製備一ELp引 線框架之一實施例。用於製備引線框架之技術通常將與上 文針對習用著陸點先前所闡述之彼技術可媲美。在步驟i 中，一金屬框架（1300)將係用於變換之起始材料。在步驟2 中，部分蝕刻該金屬框架以得到具有網式部分（13〇5)及晶 I53285.doc -62· 201232673 片附接區域（1310)之部分經姓刻之弓！線框架之一區塊。金 屬框架（1300)可係由任一方便材料製作，諸如銅或一銅合 金。該部分姓刻步驟圖解說明自弓i線框架〇3〇〇)之中心移 除材料以便在區域（1310)周圍給出_無塾引線框架。即， • 晶片或晶粒（1320)之中心將不正位於所得的晶片尺寸封裝 • 中之一晶粒塾上。 在v驟3中，在部分蝕刻之後，用一可線接合材料（諸如 Ag、Ni/Au或NiPdAu)選擇性地鍍覆引線框架（丨3 〇〇)以形成 電著陸點（1307)，該等電著陸點在所圖解說明之實施例中 形式為引入引線。電引線部分（1307)與晶片附接區域電分 離以防止非預期的電接觸，且引線框架藉由街道形部分 (未圖解說明）彼此分離。 雖然在圖41中，在符合本發明地選擇性鍍覆（步驟3)之 前完成部分蝕刻（步驟2)，但可以任一方便次序完成此等步 驟，且可在部分蝕刻（步驟2)之前進行選擇性鍍覆（步驟 3 )。步驟序列將取決於眼前的具體實施例。引線框架之頂 部（1360)通常將係具有選擇性鍍覆之表面，且底部鍍覆係 可選性的《若鍍覆該引線框架之底部表面（1365)，則鍍層 可用作一蝕刻抗蝕劑或用於板安裝。 在步驟4中，在鍍覆之後，使用一黏合劑（1315)將一晶 片或晶粒（1320)附接至引線框架之晶片附接區域（131〇)。 然後使用線接合技術在晶片（1320)之端子與對應引線框架 之電引線部分（1307)之間形成電連接（步驟5)。如前文所論 述’引線部分（1307)之形式為引入引線，將晶片或晶粒附 153285.doc •63· 201232673 接至該晶片附接區域之步驟可視需要包括將該晶片放置於 將在缺少一晶片墊之情形下支撐該晶片之主動引線（或而 是將在最終晶片尺寸封裝中係主動之引線）之頂部上（在圖 47b中進一步圖解說明）。在此一實施例中，可使用一非導 電黏合劑（諸如一非導電環氧樹脂）或一晶粒附接膜黏合劑 將a亥晶片黏附至該晶片附接區域。在此實施例中，將在該 等主動引線與該積體電路晶片之間形成電連接。 在圖4〗中，晶片（1320)係一線接合晶片，雖然該晶片可 替代性地係一覆晶。在此一例項中，將用此項技術中習知 之一焊接步驟替代線接合步驟。 在步驟6中’在使用線接合（1325)將晶片（1320)電連接至 引線框架之電引線部分之後，藉由將一囊封物（133〇)施加 於引線框架及使該等引線框架分離之街道形部分來囊封該 引線框架。然後背面圖案化或背面蝕刻該引線框架之底部 表面（1365)以移除網式部分以及街道形部分。在此蝕刻步 驟中，可在蝕刻之前將一有機蝕刻抗蝕劑（1361)或另一適 合的抗蝕劑施加至引線框架之底部之選擇性部分以便蝕刻 製程可移除金屬框架之剩餘的不需要部分（步驟7中所顯 示）。 在步驟8中，然後使用一鋸或其他適合的技術來單個化 引線框架以形成個別晶片尺寸封裝（1340)(步驟8)。可視需 要用一非導電塗層（1375)(諸如油墨或一焊料抗蝕劑材料） 塗佈引線框架或晶片尺寸封裝之底部以保護該晶片尺寸封 裝之底部在安裝至一印刷電路板或其他裝置時免於短路。 153285.doc -64- 201232673 亦可視需要將焊料球（1380)黏附至電著陸點以促進晶片尺 寸封裝（1340)隨後附接至預期的有用位置。另外，可將一 可焊材料視需要施加至電著陸點以促進後續電連接。雖然 可在單個化之前或之後施加此等可選特徵中之任—，曰 在單個化之前施加此等特徵通常將更方便。 圖42圖解說明將一 EMI(電磁干擾）屏蔽施加至本發明之 發明性ELP引線框架之一製備製程。在圖42中，電著陸點 (1309)之形式為引入引線，且在單個化之前用一電磁干擾 (EMI)屏蔽材料（1385)塗佈引線框架。圖41及42中之步 至6共同於兩個製程，以一金屬框架（13〇〇)開始且通向步驟 6中製備經囊封引線框架，且因此將不對此做進一步論 述。 在圖42之步驟7中，在街道形區（1335)中部分切割經囊 封引線框架以曝露金屬引線框架（1300)以用於emi屏蔽 (1385)之接地。然後將EMI屏蔽（1385)施加於經囊封引線框 架及街道形區上方。可以此項技術中習知之任一方便事件 來施加EMI屏蔽。舉例而言，可藉由此項技術中習知 電鍍覆、電解鍍覆、浸潰、噴射、一網版印刷製程或任一 其他適合的技術來施加屏蔽（1385)。可在後續的背面蝕刻 製程之前視需要將一塗層抗蝕劑施加至EMI屏蔽（步驟9中 所顯示）°該塗層抗蝕劑將防止蝕刻化學劑可能附接^^^屏 蔽。 在步驟9中’背面圖案化或背面蝕刻引線框架之底部 (1365)以移除網式部分及術道形部分。可使用一有機蝕刻 153285.doc •65- 201232673 抗飯劑（1361)或另一適合的抗蝕劑來保護金屬框架（13〇〇) 之選擇性部分在蝕刻期間免被移除。通常將在製備最終封 裝之前移除此抗蝕劑。在蝕刻製程期間形成電著陸點以提 供至晶片的電連接。若將一塗層抗钱劑施加至Emi屏蔽， 則其將與在蝕刻時所使用之任一剩餘的抗蝕劑一起被移 除。 在步驟10中，然後使用一鋸或其他適合的技術（未圖解 說明）在街道形區中單個化引線框架以形成具有一 emi屏蔽 (1385)之個別晶片尺寸封裝（134〇)。類似於圖41之實施 例，可視需要用一非導電塗層（1375)(諸如油墨或一焊料抗 蝕劑材料）塗佈引線框架或晶片尺寸封裝之底部（1365)以保 護晶片尺寸封裝之底部在安裝至一印刷電路板或其他裝置 時免於短路。亦可視需要用一可焊材料視需要將焊料球 (1 3 80)或其他連接構件黏附至電著陸點以促進隨後該晶片 尺寸封裝附接至預期的有用位置。引線框架可具有一晶粒 塾’或可使用如圖42中所圖解說明之一無墊選項。 晶片尺寸封裝中之EMI屏蔽（13 85)減小經囊封之晶片 (1320)所見之周圍干擾或雜訊的量，從而改良該晶片之效 能。所得的晶片尺寸封裝適用於電路及電子設備中之許多 應用。 圖43a至43c圖解說明使用引線框架之一區塊模製選項製 備EMI屏蔽式晶片尺寸封裝中之步驟。在此實施例中，使 用一大模具在一單個區塊中用一囊封物（1330)覆蓋引線框 架之整個陣列（圖43a)。在固化該囊封物之後’移除該模 153285.doc -66 - 201232673 具，從而留下稍後被單個化之一單元陣列（134〇)。然後在 圖43b中在街道形區（1335)中切割囊封物（133〇)下至金屬框 架（1300)。有必要注意避免過分切割至金屬框架中及弱化 引線框架。在引線框架中進行部分切割之後，如圖43c中 所顯示施加EMI屏蔽（1385)，且隨後單個化該等引線框架 以獲得個別晶片尺寸封裝（1340)。 圖43d至43e圖解說明使用一個別袋式模製選項製備EM][ 屏蔽式晶片尺寸封裝中之步驟。在圖43d之實施例中，引 線框架之母一單元（1340)具有一囊封模具其自己的空腔， 從而得到用一囊封物（1330)覆蓋之個別經模製單元。如圖 43e中所顯示，然後將EMI屏蔽（1385)施加至該引線框架， 且猶後在街道形區（1335)中單個化所得的引線框架。可使 用錄覆或其他技術來施加框架之電引線部分（丨3〇7)。 可使用具有袋之習用引線框架模具’雖然膠帶協助式模 製可幫助防止模具閃光（過度囊封物附接至引線框架）。有 利地’由於個別模具袋並不塗佈街道形區（1335)且因此並 不需要藉由切割而曝露，因此用來屏蔽連接之引線已經曝 露’如關於圖49進一步論述。使用袋式模製亦消除對部分 鋸切引線框架以曝露金屬膜（1300)之需要，從而縮短循環 時間且使該製程更具成本效益。對層壓製品之個別模製亦 可行。 已參考在單個化之前將EMI屏蔽施加於經囊封引線框架 上論述了圖43a至43e。圖44a至44c圖解說明一替代性實施 例中之步驟，其中在施加屏蔽（1385)之前首先單個化單元 153285.doc -67· 201232673 (1340)。可如圆44a巾所顯示首先將經㈣及經單個化（但 並非顧屏蔽式）單元（134〇)放置於—銀模（⑽）上或如 圖44b中所圖解說明將其放置於—銀帶或承載帶⑴91)上， 或放置於其他方便構件上以促進引線㈣移動至錄 (1392)。在單個化之後’可在經單個化單元⑴叫仍在模 或帶上時經由嗔塗、網版印刷或其他手段將麵屏蔽材料 (1385)施加至該等單元。在施加屏蔽材料之後，可個別地 收拾完成的晶片尺寸封裝並將其放置於裝運托盤、管、 包、罐或其他包裝箱中以供最後交貨給一客戶。 圖45a至45b圖解說明在部分蝕刻具有一 emi屏蔽（1365) 之一引線框架之底部中之步驟。在圖45a中，先前已用一 預鑛覆遮罩或㈣抗㈣（1361)覆蓋了引線框架之底部 (1365)，且然後選擇性地飯刻了該底部以形成期望的表面 特徵。然後將一焊料抗蝕劑（1375)施加至引線框架之底 部，後跟一可焊材料（1362)以形成電著陸點（圖45b)。焊料 抗蝕劑（1375)可係習用或專門針對特定引線框架而製備’ 這取決於眼前的具體要求。可焊材料（1362)可包括銀 (Ag)、錫（Sn)、錫-金合金（SnAu)、無電鍍鎳無電鍍鈀沉浸 金（ENEPIG)或可黏附至引線框架之任一其他導電材料。可 藉由浸潰、無電鍍、網版印刷或其他方便技術來施加可焊 材料。可使用焊料膏或球滴（未顯示）來增加用於稍後的電 附接之著陸點之大小。在完全製備EMI屏蔽式引線框架之 後，可在街道形區（1335)中將其單個化以形成個別晶片尺 寸封裝。 153285.doc •68· 201232673 在圖45c中所圖解說明之一替代性實施例中，可溢流式 蝕刻一 EMI屏蔽式引線框架之未經遮蔽底部（1365)以曝露 底部表面之特徵。在溢流式蝕刻步驟中，不施加一選擇性 鍍層或遮罩。該溢流式蝕刻不造成任何突出的著陸點，雖 然已蝕刻掉網狀特徵以使引線與墊隔離。在已蝕刻了底部 之後，可將一焊料抗蝕劑施加至經模製區塊之相對平坦的 底部部分，且可使用一可焊材料施加電特徵（1362乂圖 45d) ^通常將定位任何期望墊及可焊材料以便促進安 裝可在街道开々區（1335)中單個化所得的引線框架以得到 具有一EMI屏蔽（1385)之ELp晶片尺寸封裝。 圖46a至46e圖解說明根據本發明而製造之晶片尺寸封裝 (1340)之實例性實施例之俯視及又射線視圖，其中電著陸 點（1305)具有引入引線（13〇9)且使用線接合連接至一晶片 (1320)。X射線視圖顯示透過囊封物（133〇)而觀察之晶片尺 寸封裝（1340)之電路。 在圖46a令，外部引線（！3〇5)集係在一晶片塾⑴⑺)周圍 而選路’而在圖顿中，内部及外部引線⑽5)兩者皆經選 路為引入引線(1309)。通常將用一焊料抗钱劑或保護性油 墨來覆蓋晶片尺寸封裝之底部以防止引線本身曝露。因 此在實際的aa片尺寸封裝中，僅著陸點⑴將係可見 的而選路不可見。 圖後圖解說明-晶片尺寸封裝（134〇)，其中具有一小的 大小之晶片（1320)使用導電環氧樹脂而放置於一墊上。引 線⑽5)之外部列經選路’且引線〇3〇5)之内部列未經選 153285.doc •69. 201232673 路且係以一正方形形狀。由於選路外部引線，所使用之線 量小於在未曾選路任何引線之情形下原本所需之線量。 圖46d圆解說明一晶片尺寸封裝，其中具有一小的大小 之晶片（1320)使用一導電環氧樹脂而放置於一墊上，且該 晶片正牵引已被選路之内部及外部引線（1305)。用於圖46d 中之線接合之金線量小於用於圖46c中之量。 圖46e圖解說明一晶片尺寸封裝，其中具有一大的大小 之晶片（1320)放置於經路由引線（1309)本身上，且該晶片 使用一非導電環氧樹脂或一晶粒附接膜而黏附至下面的晶 粒塑*。所需要之金線量小於在未曾選路任何電引線（1305) 之情形下原本將所需之金線量。 圖47a至47d圖解說明使用根據本發明之有塾及無塾實施 例而製造的晶片尺寸封裝（1340)之仰視圖，其中電著陸點 (1305)之形式為引入引線（1309)。 圖47a顯示一晶片尺寸封裝（134〇)，其中一單列經選路 線（1309)圍繞一晶粒墊（1310)。可使用一導電環氧樹脂 晶片附接至晶粒墊以達成電目的且達成較佳熱效能。 圖47b顯示根據一無墊選項具有一單列經選路引 (1309)之一晶片尺寸封裝（1340)。引線框架仍將在周圍 中具有一晶片附接區域（1310)e _IC晶片可放置於在缺 一晶片墊之情形下將支撐該晶片之主動引線之頂部上。 使用一非導電黏合劑（諸如一非導電環氧樹脂）或—晶粒 接膜黏合劑將該晶片黏附至引線框架，且可在引線與曰 之間形成電連接。 ' Μ 153285.doc •70· 201232673 圖47c顯示-晶片尺寸封裝（134〇)，其中晶粒塾⑽〇)之 形式為部分金屬通孔，且引線(13〇5/13〇9)以兩列之形式圍 繞該塾。内部引線列（1309)經選路，且外部列（13〇5)未經 選路且不具有引人引線。在圖47d中，晶粒墊n3lQ)係實心 且著陸點（1305/1309)在晶粒墊周圍配置成兩列。外部引線 列（1305)未經選路，且内部引線列使用引入引線（13〇9)而 被選路。 圖48a至48b圖解說明根據本發明之晶片尺寸封裝（ι 34〇) 之實施例之剖視圖，其中晶粒墊係實心或含有部分金屬通 孔’諸如熱通孔。 圖49a及49b分別圖解說明根據本發明之一經囊封ELp引 線框架之俯視圖及剖視圖且顯示用於EMI屏蔽之電接地連 接。 圖49a圖解說明一引線框架之四個經囊封晶片（132〇)之一 俯視X射線視圖，且晶片電連接至引入引線（丨3 〇9) ^雖然 為便於圖解說明起見顯示四個晶片（132〇)，但引線框架可 係任一方便的大小且可具有任一數目個單元。該引線框架 已被囊封（圖49b中之1330)且被一 EMI屏蔽（圖49b中之1385) 覆蓋，但還未被單個化以形成個別晶片尺寸封裝。EMI屏 蔽式塗層（1385)與拐角電著陸點（1308)中之每一者電接 觸。為了形成個別封裝’將沿代表引線框架之街道形區之 虚線（1335)單個化引線框架。 圖49b顯示在單個化之後圖49a之單元中之每一者之一剖 視圖。晶片（1320)已被囊封（1330)且被一 EMI屏蔽（1385)塗 153285.doc •71· 201232673Sn/Pb, lead-free solder, immersion tin electroless nickel, silver (Ag), and test-plated Au (gold). The lead frame can also be selectively shielded using any convenient or custom masking material such as a printable ink, a stencil oil, an epoxy ink or an organic material. The pre-plated material or masking material can be removed from the bottom of the lead frame at any suitable time, such as after backside patterning. The lead frame can be formed from any suitable material known in the art. For example, &' the lead frame may comprise copper or a copper alloy or a film of another metal or metal alloy. An integrated circuit wafer is attached to the wafer mounting area of the leadframe as set forth above. The wafer can be attached using one of the adhesives or other contact or fixative materials known in the art. For example, the adhesive may be a resin, an epoxy resin, a solder paste or a tape. 153285.doc 21 201232673 Stamping or embossing can be used to form a lead frame by chemical etching (eg, by chemical etching into a lead frame. The wafer can be electrically connected to the lead frame using suitable electrical connection means, such as by wire bonding). In a further embodiment, the method of the present invention permits stacking of a plurality of wafers at a wafer mounting area. For example, the method can include stacking one or more second wafers to an integrated circuit adhered to the leadframe. The first s-chip such as the top of the wafer may be electrically connected to the lead frame or to the integrated circuit wafer adhered to the lead frame or both. Combinations of such connection methods are possible. The second wafers may also be electrically connected to each other. Another aspect of the present invention provides a lead frame for fabricating a partially patterned electronic package. The partially patterned lead frame may be composed of a film having a top surface and a bottom surface. The film may have a top surface. It has (4) a portion of the pattern patterned from the top surface but not completely through the film to the bottom surface, and (b) no patterning from the top surface portion The second region may form a plurality of electrical leads for supporting one of the integrated circuit (IC) wafer pads, and a plurality of electrical leads for providing electrical connections to the 1C wafer. The electrical leads may be connected via the first region, but not through the top surface. The bottom surface of the film may also be partially patterned from the bottom surface but not completely through the film to the top surface. The top and bottom surfaces of the lead frame are patterned in a specific manner. For example, the top and bottom tables 153285.doc • 22· 201232673 faces can be patterned in a complementary pattern such that the two surfaces are on either side of the lead frame It has substantially the same features. The bottom surface of the lead frame can be patterned with hatching, channels, or both. Such hatching or channels advantageously permit side vents and side venting, so there is no trapped air during reflow. Another aspect of another aspect of the invention provides a method for forming a wafer size package. The method includes providing a portion of a patterned lead frame (a) partially patterning one of the first regions from the bottom surface but not completely through the lead frame to the bottom surface, and (b) not patterning one of the second regions from the top surface portion. The second region is formed (a a pad for supporting one of the integrated circuit (1C) wafers, and (b) for providing a plurality of electrical leads to the electrical connection of the wafer. The wafer pad region and the plurality of electrical leads are Connecting via the first region, but not through the top surface. An integrated circuit wafer is then attached to the wafer pad region of the first region of the leadframe. Then one or more terminals and leads on the wafer An electrical connection is formed between one or more of the electrical lead portions of the frame. The lead frame is then encapsulated by applying an encapsulating material over the lead frame and the street shaped portion. The bottom surface of the lead frame is then f-faced. Patterning to remove the mesh portion and the street portion. A small portion of the bottom surface of the wafer pad region is also removed to form one or more channels through the wafer pad region. These passages advantageously permit side venting σ and side venting so that no trapped air is present during reflow. The money singulates the encapsulating material disposed above the street-shaped portion of the lead frame to form an individual wafer size seal ready for subsequent use. 153285.doc -23- 201232673 The channel of the wafer pad region extends across the length of the entire wafer pad region, Or it may extend across a portion of the wafer pad area. These channels may take the form of hatching or other similar structures. Another aspect of the present invention provides a lead frame for fabricating a partially patterned electronic package. The lead frame includes a ruthenium film having a top surface and a bottom surface that is partially patterned from the top surface but not completely through the film to the bottom surface. The film is also partially patterned from the bottom surface but not completely through the film to the top surface. The patterning on the top surface is deeper than the patterning on the bottom surface. The resulting lead frame is patterned on its top side deeper than on its bottom. The two sides (four) permit a portion of the lead frame that will eventually be removed to have a reduced thickness and thereby streamline the processing and fabrication of the resulting electronic package. Another aspect of the present invention provides a wafer size package having one of the bottom surfaces of the channel, the wafer size package including one or more encapsulated computer wafers, and the channels are used as vents to reduce or eliminate Capture air during reflow. Features of the present invention provide significant advantages over existing technologies. The present invention provides features such as system level packaging and provides electrical performance, thermal performance, and I/O with increased package size. The flexibility of the present invention allows for innovative ELP type packages to accommodate increasingly complex requirements. While the embodiments of the invention discussed above provide wafer size packages that are of great utility and superior to the prior art, additional features may provide advantages in specific examples. For example, one embodiment of another aspect of the present invention provides a method of forming an electronic package using the lead 153285.doc • 24-201232673 lead. These lead-in leads allow the electrical landing site to be placed closer to the wafer attachment area or even under the wafer, and allow for a simpler electrical connection. These lead-in leads typically have a larger surface area than a typical electrical landing site, and thus allow for greater flexibility in terms of in-line or flip-chip attachment. These lead wires also allow for the use of fewer wires for wire bonding. Since the wire is typically a gold wire of Amber, reducing the amount of this wire provides significant cost savings, even if the amount of metal used for the leads or traces is slightly increased. The method includes forming a portion of a partially etched leadframe having selectively pre-plated top and bottom planes, the leadframe comprising a mesh portion, a wafer attachment region, and a form of lead-through Electric land point ^ knife. The electrical lead portions are electrically separated from the wafer attachment regions, and the lead frames are separated from each other by a street-shaped portion. These lead wires can be used with ink or any other material in conjunction with solder resists that are considered necessary or desirable for the proper function of the leadframe or resulting wafer size package. Attaching the s-day piece to one of the lead frame corresponding to the wafer attachment area, and forming one or more wires between the one or more terminals of the wafer t and one or more of the electrical lead portions of the corresponding lead frame The connection 'and then encloses the lead frame by applying an encapsulating material over the lead frame and the street shaped portion to thereby detach the lead frame. The step of attaching the wafer to the wafer attachment region may optionally include placing the wafer in an active lead that will support the wafer in the absence of a wafer defect (or will instead be active in the final wafer size package) On top of the lead), and using a non-conductive adhesive 153285.doc • 25· 201232673 (such as - non-conductive epoxy) or a die attach film adhesive to adhere the wafer. In this embodiment, an electrical connection will be made between the active leads and the integrated circuit wafer. Then, the back surface of the bottom surface of the bow line frame is patterned into a portion and a street-shaped portion, and the lead frames are singulated by the (4) ϋ placement on the street-shaped portion I square encapsulation material to form individual crystal-mounted 0 leads. The wafer attachment area of the frame (also referred to as a wafer receiving area or a wafer mounting area) can have any particular structure for receiving a computer chip. For example, the wafer attachment area can be a wafer area or a padless portion of the lead frame. The lead-in lead of embodiment t of the present invention can be configured to be in a convenient or convenient manner for the respective wafer attachment area to be closed or adjacent, for example, the lead-in lead can be configured as a single column around a wafer, or A plurality of columns disposed around the respective wafer attachment regions of the lead frame. The electrical leads can also be combined with any type of lead. By way of example, the leads may all be introduced into the leads, or the leads may be combined with one of the lead wires and one of the electrical landing points. The backside patterning step can be performed using any method or practical method. For example, partial etching or fl〇〇d etching can be used for backside patterning. Similarly, any convenient means (such as by block molding or individual unit molding) can be used. Encapsulation step. The wafer attachment of the lead frame can have any convenient structure. For example, the wafer attachment area can be solid (such as a solid wafer pad area), or 153285.doc • 26· 201232673 The wafer attachment area (or any portion of the lead frame) can include a hot pass Hole (a vertical electrical connection between different conductor layers in a printed circuit board design). After singulation, a solderable material, such as a solder ball or solder finish, can be attached to the wafer size seal before or after singulation. < - One or more electric landing sites. The solderable material facilitates wafer size packaging to be connected to a circuit board or other type of electronic software. The solderable material can have any novel or customary composition such as tin, copper, silver, silk, indium, zinc and/or antimony. The ic wafer attached to the lead frame can have any suitable or customary structure. Different types of wafers can also be bonded to different wafer attachment areas on the same lead frame. For example, wire bonding wafers and flip chip can be used, and some lead frames can support multiple types of wafers as well as die stacks. The wafers can be attached to the wafer attachment area using any suitable component. Examples of suitable techniques include the use of a conductive epoxy, a non-conductive epoxy or a die attach film adhesive. Similarly, any suitable type of technology can be used to complete the electrical connection. For example, wire bonding techniques, flip chip techniques, or a combination of both can be used to form the electrical connections. The step of forming an electrical connection can be accomplished by attaching the terminals on the wafer to the end portions of the electrical lead portions extending from the lead frame, and the lead portions can be plated or unplated. The particular technique used to electrically connect the wafer to the leadframe will depend on the particular configuration at the time of manufacture and embodiments of the present invention. The method of the present invention can further include applying a non-conductive coating to the bottom surface of the lead frame after patterning the back side. This non-conductive coating can be used to protect the leadframe from mechanical abrasion or wear and thus increase the durability of the resulting wafer-sized package. This coating is intended to protect the active lead wires from short circuits during PCB installation. The intended location of the electric landing or pad will remain open and uncovered to provide the necessary electrical connections. In a further embodiment of the invention, the method of the invention may further comprise applying an electromagnetic interference (EMI) shield to the wafer size package before or after singulation. The electromagnetic interference shield eliminates or at least significantly reduces the coupling of undesirable radiated electromagnetic energy that can occur in the electrical device. Fabrication of Prior Art Wafer Size Packages typically require partial dicing of the leadframe substrate or lamination to expose the desired metal layer for connecting the EMI shield to a ground. Since the thickness of the metal trace of the organic substrate is usually 5 to 18 μm, process control is important. In contrast, the ELP platform of the present invention is particularly suitable for applying an EMI shield because of its wider process control than other types of lead frames due to the use of thicker frames. In addition, the ELp platform of the present invention also has the option of using a pocket molding during encapsulation to avoid partial cutting into a lead frame. In this embodiment, the 'pocket molding process does not encapsulate the entire lead frame, but rather maintains one portion of the metal of the lead frame exposed and can be connected to EMI shielding for grounding. The EMI shield can be applied using any convenient process, such as by electroless recording, electrolytic clock coating, spray coating, dipping, spray deposition or a screen printing process. The invention has been discussed in terms of a single wafer having been attached to the wafer attachment region of the -lead frame. In an additional embodiment of this aspect of the invention, the method can include stacking a plurality of wafers prior to encapsulating the leadframe. For example, 1532S5.doc -28- 201232673 and δ, one wafer can be adhered to a wafer attachment area, and a second wafer can be adhered to the top of the first wafer. β can stack any number of wafers to form the wafer of the present invention. Size package. Each wafer will be electrically connected to the lead frame, another wafer in the stack, or both. The wafers can be connected using wire bonding techniques, overlay techniques, or both, and any other technique in the art, and such configurations will depend on the particular embodiment and configuration during manufacture, and any such The embodiments are combined onto a single lead frame. [Embodiment] The present invention will now be described with reference to the drawings, wherein like numerals refer to the same elements. Figures 4 through 15b and Figures 16 through 24b show different embodiments of forming a partially patterned lead frame package having a number of leads comparable to the number of leads of a near wafer size package (CSP). The method of the present invention improves the automation of the manufacturing line and the quality and reliability of the package from which it is made. This is accomplished by performing a major portion of the fabrication process step in which a portion of the patterned metal film is formed into one of the mesh lead frames on one side. In contrast to the conventional punch-through die-shaped lead frame, the lead frame used in the present invention is partially patterned on one side and solid and flat on the other side. This structure is improved by both mechanical and thermal means and exhibits no distortion or distortion during wafer attachment, wire bonding, and encapsulation processes. The bottom surface can be masked or otherwise marked to depict areas that will eventually be removed by backside etching. After the wafer attaching and wire bonding process steps are completed and the wafer and wire bonds are adhered and hermetically sealed in a molding material, the region is not shielded by the selective pre-plating layer of the bottom surface. The bottom surface of the film is partially engraved to isolate the lead contacts from the wafer pads and to isolate each other. Subsequently, 153285.doc •29-201232673 singulated the resulting encapsulated package without having to cut it into any additional metal. More specifically, Figures 4 through 15b illustrate the formation of a portion of a patterned lead frame for use in a wire bond wafer and a method for forming an ELp type electronic package. On the other hand, Figs. 16 through 22 show a method for forming a portion of a patterned lead frame and using it for forming an ELPF type electronic package. One method of forming an ELGA type electronic package using a transient partially patterned lead frame is also described in conjunction with Figures 24a and 24b. Figure 4 is a cross-sectional view of a film (preferably a metal foil, and preferably copper). The film is formed not only in a lead frame, but also during the process steps of forming a lead frame. A stable carrier. The thickness of the metal strip is equal to or greater than about 〇_05 mm. In another embodiment, the thickness may range between about 〇.〇5 to 〇·5 mm. Forming a lead frame typically involves cutting through a strip of metal, like cutting a stencil, and then operating with very small finger leads. A vacuum chuck can be used to hold this delicate structure in place. However, conventional vacuum chucks are generally not adapted to provide suction for such delicate devices and must typically apply pressure to the lead frame on the periphery. Any rigging used for this purpose must be retrofitted from lead frames of all types and sizes. However, the present invention alleviates this modification step. Since the bottom surface of the partially patterned lead frame is solid and continuous, a conventional vacuum chuck can easily hold the lead frame in place during processing. In addition, metal strips of a size 153285.doc -30- 201232673 that can accommodate a variety of industrial lead frames are commonly used in manufacturing lead frames. Subsequent processing steps for wafer attachment and wire bonding can be accomplished by very small stresses and strains on the leadframe to be formed. It is easy to manufacture a lead frame having a small geometric shape because the mesh is held in the lead frame by the mesh structure until the final step is divided into a plurality of ways. Various patterns are formed on the rifling frame. One method is to stamp/emboss the pattern to a metal towel. Other methods may include chemical or electrochemical polishing and discharge plus imprinting). On the other hand, photolithographic patterning is preferred, which is the primary means of semiconductor fabrication. In the present invention, the metal strip (1 〇〇) shown in Fig. 4 is pre-plated on both the front (or top) side and the back (or bottom) side before photolithography. Any or both of the front surface and the back surface may be pre-clocked by means of a material that achieves bonding and solderability. In one embodiment, the front surface is pre-plated by means of a bondable material such as a trial-plated Ni/Pd/Au or Ag. In another embodiment, the back surface is pre-plated by means of a solderable material such as Sn/Pb, lead-free solder, immersion tin electroless nickel or trial-plated Au. In another embodiment, the material is pre-mineralized by the same material as the top side, which material can then act as a resist during backside patterning. This resist-based plating layer can be peeled off later before final completion. Pre-plating can be performed in a later step, if desired. In the next step, the photolithography pattern pre-plats the front side (11 turns) to form regions corresponding to the wafer turns (1) 5) and the electrical contacts (113) around the wafer pad region. An electrical contact (113) may be characterized by an end portion of a lead that is connected to the i-pad region 153285.doc-31-201232673 (115) through a first region that forms an intermediate recessed portion of the mesh structure t. When the metal film (1〇〇) is etched from the back side, the intermediate recessed mesh portions are removed at a later time so that the end portions and the wafer pad portions are isolated from each other, including a wafer pad (U5) and surrounding contacts. The area of points (1) 3) is sometimes referred to as the wafer position. A plurality of wafer positions can be formed on a continuous copper foil roll in a sprocket manner to one of the reels to easily automate the formation of the lead frame including one or more wafer locations. Figure 5 illustrates two wafer locations that will be formed into two corresponding leadframes, which in turn will be part of the two packages from which they will be formed. The pattern shown for the two wafer positions illustrated in Figure 5 is then transferred by transfer to the film strip (1 inch). As shown in Figure 6, one of the main features of the present invention is to perform etching only partially through the thickness of the metal, which is referred to herein as partial patterning. Partial patterning is performed in a first region of the film to form a mesh structure (130) that connects the wafer pads (1) 5) of the lead contacts (1) 3) of each lead frame. The first region also connects the lead frames to each other in the street-shaped portion (136) of the film. As shown in Figures 6a to 6c, a matrix or such leadframe can be formed in a block/window film (138) (e.g., '16. The map shows that the first-region contains a mesh structure (139). 'Connecting the wafer pads and lead contacts of each lead frame. The first region also connects a plurality of lead frames to each other in the street-shaped portion (136) of the film. In one embodiment, partial patterning It can vary from 90% of the thickness of the film. However, 'partial patterning can be actually any percentage of the thickness of the film: and some of the defects can be determined by considering the factors that affect the manufacturability parameters. The amount of chemical, "money contains Wei, rigid to ^ 153285.doc -32 - 201232673 thermal thickness (or thermal conductivity P can be based on a given wafer size and wire bonding or other connecting medium (which can be used in a given package or under The degree of miniaturization required between the layers of the package in the first level package or the level of the inter-layer connection to determine the lateral dimensions of the lead contact area (113) and the wafer pad area (115). In particular, due to the finger leads Mesh structure, small to the lead frame Manufacturing concerns of dimensional stability are now less important. As shown in Figure 7, the BB sheet (14 inch) is next attached to the wafer pad area using any convenient member such as epoxy (150). According to the invention, the joint between the attached wafer and the wafer pad is shown to comprise epoxy or solder. The epoxy resin (150) may be filled with conductive particles to enhance the cooling of the wafer. In an alternative, solder paste may also be used ( 15〇_) instead of epoxy (15〇) to provide a tighter bond between the wafer and the wafer pad, and a more efficient cooling path to the surrounding environment. The epoxy is cured, and Figure 8 As shown in the figure, after the wafer is attached, the wire (160) is bonded to the terminal (145) and the corresponding lead contact 〇 13) using well-known wire bonding techniques, as shown in Figure 8. Since formed in accordance with the present invention The lead frame has a solid, continuous back side that is securely seated and held on a flat surface, such as by a vacuum chuck (not shown), so that the mesh structure of the leads does not vibrate or jump during wire bonding This results in an excellent joint' which improves the reliability of the final product. Even if the back side is solid and consistent, it can have an indicator of where the back side etching will occur. For example, the back side can have cracks or Other indicators, which may be part of the surface of the film, or may be masked with a pre-recording material (120) to depict the desired area to be engraved by the back. For example, may be under area (113) The pre-plated material (120) is masked to indicate that the corresponding portion of the lead 153285.doc • 33· 201232673 frame will remain during a later etch and will remove areas under the regions (130) and (136). After joining the wafer and corresponding contacts, all of the components on the front side of the metal film are then hermetically encapsulated in a molding material, for example, by a resin. An encapsulant (丨7〇) is formed over the film and all exposed surfaces, the exposed surface comprising the leadframe and its associated wires (16 turns), wafers (140) and contacts (113), and mesh structure (13〇) and the street-shaped part (136). When lifting the resulting molded package, the clean back side is now available for further processing. The problems typically encountered with molded flashes to the footprint on the underside of the package are eliminated by the method disclosed herein. The clean back side may have been previously plated by means of a substance that will facilitate subsequent processing or etching. As shown in FIG. 10, both the lead contact (113) and the wafer pad (115) can now be easily isolated from each other to form their own by etching the mesh structure U35 of the first region through the back side of the package. Island. At this moment, the back side is also engraved with a street-shaped part (136). Pre-mineral coatings (12G) using materials such as - printable inks or "organic materials" can be used as __mask or anti-(four) to form the desired bottom features (123, 125) beta. An organic material replaces the metal or solderable material as a rice mask. The organic material can be printed or applied to the lead frame (4) in any convenient step prior to the back button engraving to achieve the molding material. The money engraving method for the back side (four) genus can be different from the residual silver engraving time for the front side, which can be viewed from the front side for the front side (10) engraving time...so ^(4) degree and different side b 'W5 sub-etching today|line The beginning of the frame) 532S5.doc -34- 201232673 Forms manufacturing requirements that can be customized to suit the automation, quality, reliability and functionality of the final package. The pre-plated layer (120) on the bottom of the chemical resistance (four) can be peeled off to expose the metal strip (1 〇〇). To protect the material and to be easily mounted to a printed circuit board, an enamel material such as electroless Ni/immersion Au, immersion Sn or other such material can be plated to the metal strip (100). Any pre-plated layer can be retained or stripped, which is considered suitable for a particular situation. As a final step, the encapsulant (170) above the track-shaped portion (136) between the lead frames is singulated to form two individual packages, as shown in Figure η. This is done in several ways, including sawing, water jet cutting, laser cutting, or combinations thereof, or other techniques that are especially useful for cutting plastics. In other words, there are no other metals that need to be cut through and therefore there are no other problems associated with delamination and the combination of cutting plastic and metal. Comparing this package with a conventional package, it is necessary to bridge the metal between the (4) cut streets in a singulated package. Many times when both metal and plastic are cut at the same time, some of the metal crystal months can short the wires and contacts, causing undesirable and unpredictable wear on the saw blade. As shown in the figure, this method can also be used to produce a large number of packages from a lead frame matrix. A top view of a top view through a singulated ELP encapsulation is shown in Figure 12a. Figure I2b shows a magnified view of one of the corners of the package between the wafer and one of the contacts, the contacts comprising the original metal strip ((10)), pre-mineralized to form the bondable layer (1) 3) - top The surface, and the pre-mineral coating, forms a portion of the bottom surface of the tantalum layer (10). In Figure 12{) <=»" is displayed on both the contacts and the corners of the wafer. Contact (11 3) 1532S5. Doc-35-201232673 and wafer (140) are shown as being isolated from each other on their own islands, but connected to each other only through wires (160) that have been wire bonded. The solderable pre-plated surface (120) on the underside of the package can now be used for several purposes without being stripped. First, direct external access to the backside (125) of the wafer pad (14) provides an additional thermal path for cooling. Second, proximity to the contacts (123) within the footprint of the chip-scale package (CSP) makes it possible to install closely spaced packages in the next package and thus increase the performance of the same region. Another aspect of the invention provides a means for reducing the likelihood of delamination between the molding material and the surface to which the molding material should adhere. This is accomplished by half etching the wafer pad and the edges around the contact area to form a lap or a "lip j" (such as referenced by number (105) in Figure 12b). It is also possible to form Figure 12c. The irregularly shaped cavity (1〇7) is shown to enhance the interlocking mechanism of the surface in contact with the molding material. Figure 13 & to 13 also shows an enlarged view of each of the other cavities, and such surface enhancement The formation can be easily incorporated into the portion from the front side. This will not be necessary for the (4) from the back side. This is because the molding material only encapsulates the surface formed from the front side portion. Figure 14 shows the invention. The method is generally characterized by etching a lead frame (200) from the front side portion to a metal strip towel, and inducing (25()) the same metal with the back pattern of forming the desired wafer and the peripheral contact. The end step of strip attachment (21〇), epoxy curing (220), wire bonding (230) and —G), all in the mechanical and thermal stability lead frame. The wire is still transmitted through a portion of the metal film through a mesh or mesh structure The concave intermediate portion of the first region and connected to 153,285 noted. Doc •36-201232673 is also important to remove the first zone of the intermediate recessed portion by the backside pattern etch (250) only after all components of the package have been secured in a package, and to make the perimeter touch The dots and wafer pads are separated from each other for proper isolation. A strip of pre-plated layer (12 turns) and a solderable material may be applied prior to the final step. Therefore, there is no need to cut through any metal during singulation (26 〇) into a single near wafer size package. The method of the present invention can be used to form various packages, such as one of the array types for one of an electronic package. A top view of an array package (4 turns) is shown in Figure 15b as adjacent to the standard perimeter package (300) shown in Figure 15a, although the number (3〇5) refers to one of the peripheral locations of the wafer terminals. But number (405) refers to an array type configuration that can be configured as an inline or interleaved terminal. Both packages are formed using the disclosed knife patterning invention as indicated by reference numerals (31〇) and (41〇). In the array type ELp, the inner lead (440) and the outer lead (445) are displayed. Both packages are encapsulated in molding material (320) or (420). The backside pattern etch is indicated by (330) and (430) to isolate the contacts from the wafer. The number (45〇) shows a grounding loop feature that is etched to the same level as the mold. No. (Array type input/output configuration on the bottom view of 46 〇W^ELp. The second embodiment shown in Figures 16 to 24b discloses a method of forming a partially patterned VFQFP-N type lead frame, which It is especially suitable for mass production of FC electronic packages. Lead frames fabricated to accommodate flip chip will be referred to hereinafter as FCL to distinguish them from conventional lead frames. This is because, unlike conventional lead frames, FCL is more robust and more adaptable. For automated manufacturing lines, as explained below. 153285. Doc •37- 201232673 FCI^^ is a mesh structure compared to the conventional universal punch-through template lead frame. The front side of a mesh KFCL has a concave section (including partially patterned guide wires), while the back side is solid and flat. This provides mechanical rigidity to behave without distortion or deformation during the manufacturing process. After the wafer attachment and encapsulation are completed, the back side is etched to isolate the lead contacts from each other. The removal of the pre-plated layer or the re-plating with other solderable materials can be accomplished by electroless plating or immersion processes. The resulting encapsulated package is then singulated without having to cut it into any additional metal. Therefore, it should be understood that 2FCL having a small geometry (such as having a VFQFP_N package) can be easily fabricated because the leads are held together by a mesh or mesh structure until the final singulation step is completely separated from each other. Like the partially patterned lead frame of the first embodiment disclosed, the FCL of the second embodiment is also formed of a metal foil (preferably a copper film as shown in FIG. 4) in which pre-plating is performed. Both the front surface and the back surface' or as previously stated, the plating may be delayed to a later step. (It should be noted that since the process steps for the two embodiments are similar, the reference numbers have been kept the same as appropriate, except for the reference numbers indicating the second embodiment with the nickname. The same reference number (100) has been Consistent for the metal film used in the two examples). Then, the pre-plated front side (110,) is patterned by photolithography to form a wafer receiving region (115,), a lead portion (113') surrounding the wafer receiving region, and other intermediate regions (in). In one of the subsequent processing steps disclosed below, one end portion of the lead is connected to the terminal ' of one PC and the other end portion is connected to the next-stage package. The area including a wafer receiving area and surrounding leads is sometimes referred to as a wafer position, 153285. Doc • 38 - 201232673 Similar to the wafer position with wire bonded wafers. A plurality of lead frames including a plurality of wafer positions can be formed on the i% continuous copper foil roll continuously continuous to the reel in a sprocket manner to easily automate the formation of the lead frame including one or more wafer positions. Figure 16 illustrates two wafer locations which will be formed into 13⁄4 corresponding leadframes. These leadframes will in turn be part of the two packages from which they will be formed. The pattern displayed for the two day slice positions of the month illustrated in Fig. 16 is then transferred to the metal film ((10)) by patterning through the portion A of the button. The partial patterning shown in the figure can be at most half the thickness of the metal strip, one of the four/knife, or any ratio for this purpose, and can be considered to affect flexibility, rigidity and thermal thickness (or thermal conductivity). Rate) the various factors of the manufacturing of the constituents; Lead contacts can be determined based on the degree of miniaturization required for a given wafer location and lead including wafer size that can be used for inter-level or inter-level connections between packages in a given package or in a lower package The lateral dimension of the region (113') and the wafer region (115,). In particular, it should be noted that due to the mesh structure of the finger leads, the manufacturing attention to the fine features and dimensional stability of the lead frame is now less important. The flip chip (FC) (130') is then flipped so that the terminal (丨35,) on the front side of the wafer is on one end portion of the lead as shown in FIG. In a later step, the opposite ends of the leads will be formed into the electrical contacts for connection to the next level of package (such as a card or a board). However, first, the wafer assembled on the mesh lead frame structure shown in Fig. 18 is transmitted through a wafer bonding furnace as practiced in the art. The solder balls are backed up to limit reflow to form solder pillars. Due to the lead frame formed in accordance with the present invention 153285. Doc •39· 201232673 The frame has a stable seat and is held on one of the solid, continuous back sides of a flat surface so that the mesh of the leads does not vibrate or jump around the wafer bonding furnace to produce an excellent wafer bond. Therefore, the disclosed method improves the reliability of the final product, i.e., the reliability of the VFQFP-Ν package. After the wafer is bonded, the wafer is then encapsulated in a molding material along with a partially patterned lead on the front side of the original metal film, for example, by a resin, as shown. The encapsulant (14〇,) is formed around all exposed surfaces of the surface including the leads (113·), around the solder balls (135,), under the wafer, along the recessed wafer receiving area (1) 5. The vertical wall of the vertical wall and the vertical wall of the recessed area (1) 7,) is firmly held to the unscratched, solid and flat back side of the metal strip (1 〇〇) on a flat surface. When the resulting (4) package is lifted, the clean (4) can now be used for further processing. The problems typically encountered with molded flashes to the footprint on the underside of the package are also eliminated in this embodiment. The leads (113,) can now be easily separated (4) by patterning at the beginning of the process by patterning the back side of the package aligned with the portion of the front side. The back button will continue until the molding material is reached. This shows that the mesh portion of the lead frame is removed (ie, region (1) n =) = slice region (1) 5. The method of disconnecting from each other and causing the lead (10) to be metallized may or may not be used for 'd. The p-division etching method is the same. Moreover, the eclipse time from the back side can be viewed from the front side.  (4) When the button is engraved, the degree of the part of the front side of the (4) time is different from the automation, quality, reliability and function of the final package that can be customized to suit the initial formation of the most etched lead frame. Doc 201232673 Manufacturing requirements for sex. The pre-mineral coating (120) on the bottom of the chemical anti-surname agent can be peeled off to expose the metal strip (10). To protect the material and facilitate mounting to a printed circuit board, a tantalum material such as an electroless Ni/immersion Au, immersion Sn or other material can be plated to the metal strip (1〇〇). As a final step, the package of Figure 2Q, which has two encapsulated wafer locations for purposes of illustrating the present invention, is singulated into a wafer-to-wafer size package (CSP), which is more than a VFQFP-N package. As shown in Fig. 21, 'Bei'. A top view of a singulated partially patterned lead frame package is shown in Fig. 22a, in which the leads (1) 3 are shown isolated from each other and connected to the wafer (130,). a solder ball on the side (135 ι). Figure 22b shows one of the packages between the wafer and the leads connected to the external contacts (145,) that can be provided on the card or board (1 5G1). An enlarged view of one of the corners. The pre-mineralized surface (120') has been prepared to join to the next level of contact, as shown in the same figure. Leaving or removing the pre-mineral coating or mask layer, this is considered Appropriate or required mode of time. The pre-plated layer or mask layer may also be removed at other times as appropriate for the individual case during the process. Moreover, the lower side (114') of the lead (113,) is exposed to the surroundings. The environment 'provides enhanced cooling. In some cases 'can be one A coating is applied to the underside (114) to reduce the chance of a moonlight short during board mounting, especially for fine pitch applications. The same techniques as previously disclosed can be used to prevent encapsulation and FCL surfaces. Layering, that is, by forming the irregularly shaped cavities of Figures 13a to 13f on the vertical walls of the recessed areas U15') and (117') of the mesh lead frame. It is easily incorporated into the partial etch from the front side. This will not be necessary for etching from the back side, which is due to 153285. Doc •41 · 201232673 The molding material only encapsulates the partially formed surface from the front side. Figure 23 illustrates the method of the present embodiment as beginning with patterning the leadframe (20〇|) from the front side portion into a metal strip and patterning the back side in such a manner as to form the desired wafer receiving area and surrounding leads (24). 〇,) The end of the same metal strip. The intermediate steps of the FC placement (210'), the FC wafer connection (220'), and the encapsulation (230,) are all done in the mechanical and thermally stable FCL because the leads are still permeable to the partially etched mesh in the metal film. Structure and connection. It is also important to note that the mesh portions of the leads are selectively removed by backside pattern etching (24〇|) only after all of the components of the package have been secured in the encapsulant, and the leads are separated from each other for proceeding. Properly isolated. Therefore, there is no need to cut through any metal during singulation (250,) into a single near wafer size package. The method of the present invention can be used to form various packages, such as a partially patterned lead frame of an array type, wherein the array of tan bumps can be simultaneously bonded to the lead frame above which flips the wafer, similar to that disclosed herein. - A method of surrounding solder bumps. Moreover, an array of partially patterned lead frames can be formed at the same time, and then simultaneously connected to a plurality of separate VFQFp__ packages. Moreover, each resulting csp can thus have solder bumps, pads or other electrical connections under the array type package for bonding to the lower level package to form a lead frame with one of the landing point grid arrays. Package, or ELGA type package shown in Figures 24a and 24b. A pictorial view is shown in Fig. 24a in which a wafer pad (10) is formed over the leads (10). After patterning on the back side, the leads (145,) are electrically isolated from each other to bond to the next level of package. I53285. Doc -42· 201232673 Can be immersed in a tin-impregnated or electroless mineral-coated town with any number of weldable materials flashing π (145) exposed bottom surface. The el (the bottom surface of the Ja package (1) 1') is shown in Figure 24b, where the _array pattern is used for the electrical connector (145'). The solder bumps may be in the form of a metal bump (such as a copper stud bump), wherein each bump is comprised of a cu axis having a height of about 75 microns, the shaft having a detail (or no Pb) cover Causes a total height of about (10) microns. When using CU pillar bumps, the "solder bumps" will be "solder caps". Using a Cu column, a protrusion of more than 5 Å micrometer is provided between the UBM and the plate contact point on the wafer surface, and the plastic capsule seal can flow from the ground and cover the crack below the flip chip. Since the partial etching method of forming any of the ELP, ELPF or ELGA packages provides robustness during various manufacturing steps, other forms of electronic packaging are also possible. - This type of shape includes the wire of the lead frame package of the invention joined to the next level of package. Ultrasonic bonding techniques cannot be used on conventional lead frames due to the fragility of the leads themselves unless they are attached to a solid substrate to provide stability and strength. In contrast, partially etched lead frames are stable due to their mesh structure. The unetched and pre-plated bottom surface of the partially patterned leadframe provides a solid bond area or pillar to effectively apply ultrasonic energy to the block or strip bonded to the ELp or ELPF Aluminum wire wedge on the top. According to another aspect of the invention, the aluminum wire (121) is ultrasonically attached to the bottom surface of a portion or strip of a portion of the buttoned lead frame, as shown in Figure 25a. The line diameter range is about 0. 001 inches to 0. Between 020 miles, the latter 153285. Doc -43- 201232673 Diameter represents a ribbon rather than a line. The strips are then encapsulated, back patterned, and singulated to form individual proximity CSPs. Ultrasonic bonding is required because it avoids exposure to ball bonding temperatures experienced by ball grid array packages and thus results in improved reliability. A copper ball joint can also be applied, as shown in Figure 25b. It will be understood that the csp shown in Figures 25a and 25b can be any of ELP and ELPF. The present invention facilitates several additional advantages in the fabrication process for electronic packaging. For example, after backside etching and prior to singulation, while the package is still disposed in one of the packages, the block will be inherently ready for strip testing. This provides a significant advantage over processing the package as an individual unit. Strip testing of the package while it is placed in a block improves the reliability of the test. The present invention also enables a manufacturer to produce packages having two or three columns of staggered leads that can multiply the I/C capability of a given package. The flat continuous bottom surface of the lead frame enables the use of a universal assembly device that does not need to be retrofitted for each application, and which is completely flexible for the automation system, and does not require processing between 2x2 and 12x12 package blocks. A mechanical change. Additionally, the present invention readily facilitates the construction of a package having a "projection" for each foot (e.g., 2 mils between the bottoms of the molded body at the surface of the foot). This projection provides an additional advantage when the wafer package is to be connected to a next level package, such as a board. Figures 26a and 26b illustrate an embodiment of one aspect of the invention in which two dies (505, 510) are stacked on a wafer raft (515) of a lead frame (5 Å). Lower wafer (5〇5) (ie adhered to the wafer pad receiving area 卩15) 153285. Doc 201232673 B ) film) electrically connected to the wafer. An internal electrical lead set (520) around the pad area (515). The upper wafer (51 turns) (ie, the wafer adhered to the top of the lower wafer (5〇5)) is electrically connected to the outermost lead set (525) around the wafer pad region (515) by protecting the wafer and the wire from damage. A capsule (53 〇) is used to encapsulate the wafer. Although the wafers (5〇5, 5 1〇) of Figs. 26a and 26b are in accordance with the wire bonding wafer of the present invention, one or more of the wafers may be flipped. The lower die stack wafer (505) is larger in size than the upper wafer (51 turns). Although the lower and upper wafers are not electrically connected to each other in the description of some embodiments, the wafers can be electrically connected, for example, by wires from one wafer to another. The step of forming an electrical connection can be accomplished by attaching the terminals of the individual wafers to the end portions of the electrical leads extending from the leadframe. Figures 27a through 27c illustrate an embodiment of the invention in which the wafer pad region (550) is recessed to allow for improved die stacking and package height reduction. In Figures 27a through 27c, three wafers (555, 56A, 565) are stacked via a die to form a wafer package. As can be seen in Figure 27a, the interior of the wafer pad region (550) has been removed so that only a square outer ring is present. A wafer (5 55) is placed in the wafer pad area and attached to the wafer pad area. Although three die-stacked wafers (555, 560, 565) in accordance with the present invention are shown in Figures 27a through 27c, any number of die-stacked wafers may be present. In Figure 27a, the interior of the recessed wafer pad region (55〇) is shown as the top surface of the leadframe. That is, only the square ring (575) outside the wafer area has been deposited on top of the lead frame, and the entire interior (550) of the wafer pad area is not deposited or removed from the lead frame. In the embodiment, a thin material layer is deposited inside the wafer pad region, or 153285. Doc -45- 201232673 Remove one of the inner areas of the picture. In such embodiments, the interior of the wafer pad region will be higher than the back of the leadframe, but still below the portion of the wafer pad region to provide a recessed wafer pad region for the attachment of the wafer. Although in FIGS. 27a-27c, the largest wafer (555) is positioned on the bottom of the die stack and the smallest wafer (565) is positioned on the top, the wafers can be positioned such that the largest wafer is on top and minimized. The wafer is on the bottom. The highest wafer (565) is shown as being connected to the intermediate wafer (56 turns) and the electrical leads (580, 585) on the lead frame (57 turns). The intermediate wafer (56 inch) is shown as being connected to the highest wafer (565) and the electrical leads on the leadframe. The encapsulation (59〇) covering the die-stacked wafers (555, 560, 565) prevents the wafer package wires from being damaged during operation or installation. Each of the wafers is attached to the lead frame (550) or attached to each other using an adhesive such as a conductive or non-conductive epoxy or using an insulating material. Figures 28a and 28b are perspective views of a lead frame embodying aspects of the present invention. Figure 28a shows one of the four wafer pad regions (605, 610, 615, 620) lead frames (6 turns) prior to attaching the wafer to the leadframe. Figure 28b shows the same leadframe (600) after the wafer (625, 630, 635, 640) has been attached to the wafer pad region (605, 610, 615, 620) and electrically connected to the leadframe. Figure 28a shows the leadframe (600) as having three wafer pad regions (610, 615, 620) for wire bonding wafers and a wafer germanium region (605) for a flip chip. Two of the three wafer pad regions for wire bonding wafers (61 5, 620) are not recessed and the remaining wafer pad regions (61 〇) are recessed 153285. Doc -46 · 201232673. These wafer pad regions (61, 615, 620) include a change (645) in the form of a wafer defect region = a lock region having a shape of - "τ" on the circumference. These locking features provide additional surface area for adhering one of the encapsulants (650) and provide means for retaining the encapsulant without lateral movement of the encapsulation. In Fig. 28b, the respective pads of the recessed wafer pad regions (615, 620) are connected via a single lead (635, 640) via electrical leads to the leadframe. A wafer pad region (605) for flip chip (625) is formed by a layer of electrical leads, and a flip chip (625) is placed on top of the leads to form an electrical connection. The flip chip (6h) saves space on the lead frame (600) compared to wire bond wafers (63〇, 635, 64〇). Although only a single wafer is shown as being attached to two non-recessed wafer pad regions (615, 620) on the leadframe for clarity, in other embodiments of the invention, the wafers may be bonded or otherwise One or more wafers are placed on top of the flip chip. In Figure 28b, the recessed wafer pad region (61A) on the leadframe supports a plurality of die-stacked wire bond wafers (collectively 630). These wafers are attached to the wafer cassette region (610) using an adhesive such as a conductive or non-conductive adhesive such as an epoxy or a layer of 邑, 彖. The periphery of the recessed wafer pad region (610) includes a change in the shape of the lock region in the form of a "τ" (645). The lead frame (6〇〇) in FIGS. 28a and 28b also has a pad on the flip chip. Electrical leads (typically 655) between the region (6〇5) and the recessed wafer pad region (610)' can also be used for components other than computer chips. For example, the dedicated electrical lead may be a component such as a semiconductor component, a passive component, a resistor, and an electric snail or other non-wafer component [generally shown as (66 〇)], 153285. Doc -47· 201232673 is used to supplement the function of the wafer in the chip package. In Figure 28b, a capacitor or resistor is attached to the electrical leads. The wafers may be stacked one by one on the wafer pad region and then electrically connected to the lead frame before the crystal grains are stacked and electrically connected to the next wafer. Alternatively, all of the wafers can be stacked in a die and then the entire die-stacked wafer can be collectively connected to the leadframe. In another embodiment, the wafers may be stacked separately from the wafer germane regions, and then the entire die stack wafer stack may be attached and electrically connected to the leadframe. While it will facilitate the attachment of the wafer and the passive component to the leadframe, and then the heel wire bonding (or other method of forming electrical connections), the die stacking and electrical connections can be formed in either order. Figures 29a through 29c show embodiments of various types of variations that can be applied to the wafer pad area. In Fig. 29a, the change (705) takes the form of a "τ" shaped slit on the outer edge of the wafer pad region (72〇). In Figure 29b, the change (710) is in the form of a cavity or perforation positioned along the perimeter of the wafer pad region (725). Figure 29c illustrates a modification (715) in the form of a slit along the perimeter of the wafer pad region (73〇). These changes provide increased strength and improved stability to the encapsulated wafer package. Although the alteration or locking features (7〇5, 71〇, 715) in Figures 29a to 29c are located on the periphery of the respective wafer pad regions (72(), 725, 73G), the changes can also be placed in the wafer defect region. On the other part. For example, the changes can be made to be internal to the area of the wafer pad that is not covered by a wafer and thus can be filled with a seal. In Figures 29a to 29c, the changes have been shown to be located in the crystal 153285. Doc •48· 201232673 on the area. In additional embodiments of the invention, such as the embodiments illustrated in Figures 30a through 32f, the changes may be located on electrical leads positioned on the leadframe and the wafers may be electrically connected to the Lead frame. These changes can also be placed on the wafer pad area and leads simultaneously. Figures 30a through 31b show top and side views of several embodiments with modified electrical leads. Figures 30a through 30d illustrate various types of leads (73 5, 740, 745, 750) and sections of some of these leads. Figure 3B shows a change that can have a bondable material positioned in an inner surface (755) of one of the leads (740). Figures 31a and 3b show that the surface (770, 765) of the leads (760, 765) can be coarsely saccharified to achieve improved retention of an encapsulant. Figures 32a through 32f illustrate perspective views of the embodiment of Figures 30a through 3b and illustrate several embodiments of modified electrical leads. Figure 32a illustrates a lead frame (8〇〇) having a wafer pad region (805). The circled portion (810) of the figure illustrates the electrical lead (815) with variations. Figures 32b through 32f illustrate these types of leads. Figures 32b through 32d show an embodiment of a lead (820, 825, 830) which is generally similar to the embodiments illustrated in Figures 30a, 30c and 30d. Figure 32e illustrates a lead (835) that is generally similar to the lead shown in Figure 30b. Figure 32 [illustrates a lead (840)' having a surface roughened in the form of a horizontal slit along the periphery of the lead to give the lead a stepped appearance. A chemical or another type of process can be used to achieve surface roughening as shown in Figure 32f. This surface thickening can be applied in conjunction with lead and wafer pad changes. Figures 33a to 33b illustrate one aspect of another embodiment of the present invention 153285. Doc • 49- 201232673 A cross-sectional view in which a clip (925) is used in place of the wire bond to power the wafer size package (935) & and thereby improve its power capacity. Figure 33a illustrates this embodiment using wire bond wafers (905 and 910), and Figure 33b illustrates an embodiment for flip chip (shown as a single wafer 907). The clip provides substantially more power than wire bonding and thus allows for improved reliability of one of the resulting wafer packages (935). The clip also assists in dissipating heat from the wafers. The southernmost wafer [e.g., (910) in Figure 33a] will contain leads for transmitting electrical signals to the printed circuit board. In Fig. 33a, wire bond wafers (9〇5 and 910) are placed on the wafer pad region (900) and electrically connected to leads (915) via wires (920). While the number and type of electrical connections will depend on the particular embodiment, a plurality of wires (92 turns) are used to connect the wafer (910) to the plurality of electrical leads (915). In Figure 331), a flip chip (907) is placed over an electrical lead (such as 915) that protrudes from a leadframe. While virtually any combination of flip chip and wire bond wafers forming a wafer size package (93 5) may be present, only one flip chip (907) is illustrated in Figure 33b for ease of illustration. The top surface of the uppermost wafers (907 and 910) is electrically connected to one or more electrical leads (917) on the leadframe (900) by a clip (925). After the wafer has been attached to the leadframe, A clip (925) is bonded to the top of the wafer. Any convenient member can be used to bond the clip to the wafer. In the examples illustrated in Figures 33a through 33b, a conductive paste or solder (93 turns) is used to adhere the clips (925) to the wafers (907 and 910). The clip (925) can be made of any conductive material such as a metal or a metal alloy. Examples of suitable conductive materials include copper and silver. Depending on the specific embodiment, the individual clips can be 153285. Doc -50- 201232673 Adhesive to a specific wafer' or a group of methods can be used to adhere an entire conductive strip or panel to a plurality of wafers. In this latter embodiment, the singulation action cuts through the conductive strips or panels to effectively obtain individual wafer packages. The stacked wafer is then covered by an encapsulant and after singulation, a wafer size package (935) in accordance with the present invention is produced. The exposed die pad is typically used to provide a thermal and electrical separation between a wafer size package and a printed circuit board (PCB). However, in some instances, the exposed die pad or wafer pad area is detrimental to the proper functioning of a wafer or wafer size package. For example, some printed circuit board designs have active circuitry under the wafer size package, and such circuits can fail if the package has an exposed wafer pad. While the use of a QFN (quad flat no-lead) package presents a viable solution in such situations, lead frames designed to use QFN packages have several associated assembly difficulties. For example, it is difficult or impossible to produce QFN packages for padless lead frames using prior art techniques, ie, (a) by means of tape, where the lead frames are typically in a map (molded array process) format, or (b) ) without the use of tape, where the lead frame is in a matrix format. To overcome these difficulties, the user will (a) have the lead frame half etched from the bottom so that the pad can be embedded during molding, or (b) reverse the die pad. However, for a tape-type map lead frame, there is a problem of performing wire bonding because the tape will prevent the heater block (for preheating the lead frame before bonding a semiconductor wire to the lead frame) and Pad contact. The tape method performed after the wire bonding has a negative impact on the production yield. For the matrix lead frame, the heating can be designed with a base 153285. The doc -51- 201232673 block supports the wafer pad area during wire bonding. However, this lead frame design has a lower productivity and therefore will affect unit throughput per hour and increase production costs. In such cases, a padless ELP provides improved functionality and reduced chances of failure. The padless ELP maintains a high density design and provides a more robust assembly process. The padless ELP embodiment has a configuration that is generally similar to the ELp wafer pad embodiment, but without etch protection on the bottom. Therefore, the matte ELP embodiment does not require major changes to the manufacturing line. The padless leadframe has a semi-etched die receiving area without a bottom etch mask or plating layer. The die receiving area can accommodate a larger die size than other lead frames and can address devices that require complete isolation of the die. Since the die receiving area is recessed, the resulting wafer size package will have an extremely low profile, thereby minimizing the height required for its mounting. The grain attachment material (or binder) will therefore be non-conductive to prevent electrical shorting and will typically have the same color as the molding compound to provide a uniform appearance. Additionally, the die attach material or adhesive should be stable during backside etching to prevent damage to the wafer size package. The die attach material can be any of the materials known in the art, such as a curable epoxy or a tape (such as a polyimide tape). Figures 34a through 34f illustrate one embodiment of a partially patterned lead frame. In the absence of a wafer pad region or a wafer receiving region, and directly bonding the wafer to the bottom of the (4) film that will form the lead frame. After the die attach, encapsulation, and backside patterning, the bottom of the wafer is exposed to In the wafer size package, as shown in Figure 34a, the partially etched film does not use 153285. Doc • 52- 201232673 to receive a raised wafer pad area of one of the semiconductor wafers. Fig. 34a shows that a metal film (deleted) has been partially engraved on the front side. The film (1〇〇〇) may be pre-plated on one or both sides by means of a substance which promotes post-treatment (such as wire bonding). For example, a wire bondable material such as NiPdAu or silver (Ag), such as immersed Ag, may be used to pre-plate the top of the film, and the bottom of the film may be bare or by the same or another wire. The bonding material is pre-plated. In other embodiments, an organic material can be used as an etch mask. The film (1000) is etched on its front surface to prepare an electrical lead portion (1005)'. An integrated circuit wafer will be attached to the electrical lead portions later. The film has a street-shaped region (1〇35) that separates portions of the leadframe, and the encapsulated leadframe will be singulated through the street-shaped regions (1035) to obtain individual wafer-sized packages. The wafer mounting area (1 〇 1 〇) is etched into the front surface of the film. These wafer mounting areas (101 〇) are lower in height than the leads. In other words, the film (1000) is etched minimally in the area of the leads (1005) and will be etched the most in other portions of the lead frame. After the film (1000) has been prepared and suitably etched, a semiconductor or integrated circuit wafer (1020) die is attached to the film, as illustrated in Figure 34b. The wafer (1020) can be attached using any convenient substance, die attach material or adhesive (1015) which will typically be non-conductive to avoid propagation of electrical signals. In one embodiment, a non-conductive earth oxide resin (1 〇 15) can be used to attach the wafer (1020). The adhesive can be applied as a fluid or viscous liquid which then hardens or forms internal crosslinks to form a strong, durable bond. The sticky 153285. Doc • 53- 201232673 Mix or die attach material (1015) will be visible and exposed on the bottom of the resulting wafer size package (1040) and will therefore require long-term heat and mechanical stability. In one example, the adhesive can be in the form of a tape (such as a polyimide tape). The tape is typically composed of a base film coated with two adhesive materials (such as a thermoplastic polymer) on both sides, and the tape may be tacky or non-tacky. In other embodiments, the adhesive is a solid plastic material that cures or solidifies in place to provide a secure attachment between the wafer and the leadframe. Various types of adhesives, tapes, and other die attach materials are conventional and commercially available. In one embodiment, the adhesive (1〇15) and the surrounding encapsulant (1〇3〇) are all black, presenting a uniform color to the finished wafer size package (丨〇4〇). In other embodiments, the adhesive and encapsulant are of different colors. In other embodiments, the manufacturer may teach to select a particular complementary or contrasting color (e.g., for the binder & encapsulant to provide a particular commercial package. Although the thickness of the adhesive (10) 5) will have to be thick enough to be mechanically stable and etched backside of the lead frame, this thickness is not critical. The adhesive (1015) will typically cover the entire bottom surface of the integrated circuit wafer (1〇2〇) to avoid chemical or mechanical damage to the wafer during subsequent backside etching or backside patterning steps. Once the wafer has been transferred (1020) The die is attached to the film (1〇〇〇), which is connected to the electrical leads (1〇〇5), for example, using a wire (1025), as illustrated in Figure 34. The wafer (1020) and the wire lead (1025) are sealed (Fig. 34d) using an encapsulant 0030). As discussed above, the encapsulate (1〇3〇) can be any of the materials well known in the art. One of the universal encapsulations used in the industry J53285. Doc •54- 201232673 A non-limiting list of vermiculite particulate filled epoxy resins and liquid epoxy resins. The encapsulant is typically applied as a liquid or viscous liquid to various components mounted to or attached to the leadframe. Curing the encapsulant produces a tough, durable coating that protects the underlying components of the wafer size package from damage. After the cured encapsulant (1〇3〇), the leadframe (1000) is then back etched to isolate the electrical leads (1〇〇5), as illustrated in Figure 34e. The portion of the lead frame (1000) underlying the wafer (i.e., the original wafer mounting region) is substantially or completely removed during the back etching until the wafer adhesive (1015). The leadframe is then singulated along the street shaped portion (1035) to produce an individually encapsulated wafer size package (1040) suitable for subsequent applications, such as attachment to a computer circuit board. A manufacturer may choose to print or screen a trademark, lot number or other type of mark on a finished wafer size package for identification purposes. Figures 35 and 36a illustrate bottom and cross-sectional views, respectively, of a wafer size package (1040) prepared via the sequence shown in Figures 34a through 34f. In Figure 35, the cured adhesive (1015) is shown as an irregular square of brighter color in the center of the wafer size package (1040). The encapsulate (1030), shown in a darker color, surrounds the cured adhesive material (1〇15). The encapsulant (1030) covers and envelops the integrated circuit wafer (1〇2〇), the wires (1〇25), the leads (1005), and any other components that can be attached to the lead frame or mounted thereon. Figure 3 6b illustrates another embodiment of the invention in which a plurality of integrated bodies 153285. Doc -55· 201232673 Circuit wafers (1020, 1050) are stacked in a completed silicon-free wafer size package (1070). Although both Figures 26b and 36b show an embodiment of the invention having a die-stacked wafer, the embodiment of Figure 26b has a wafer pad (5 15) and the embodiment of Figure 36b utilizes a padless technique. A comparison of Figures 2A and 36b shows that the lack of a wafer pad reduces the resulting wafer size package, allowing for the fabrication of a wafer package having a lower profile. The disclosed embodiment of the invention can be used to prepare the embodiment illustrated in Figure 36b. In short, first, the lower wafer (1〇2〇) is placed on a lead frame (not illustrated in this figure) which is not partially patterned by one aa film, and a die attach material is used ( 1 〇 1 5) (such as - adhesive or epoxy) adheres the wafer (1 020) to the lead frame. The upper wafer (1050) is then placed on top of the lower wafer (102〇) using an adhesive material (1045) such as a conductive or non-conductive epoxy or an insulating material and adhered to the lower s wafer. . The wafer (1 〇 2 〇, 1 〇 5 〇) is electrically connected to the lead frame using wire bonding. Electrical connections (1025) may be made in sequence after placing the mother wafer on the lead frame. That is, the first wafer (1〇2〇) can be placed on the lead frame and electrically connected to the s-sinus lead frame, and then the second wafer (丨〇5〇) can be placed on the first wafer (1020) and Electrically connected to the lead frame. In other embodiments, the wafers are first stacked in a suitable position (1〇2〇, 1〇50), and then electrically connected (1025). Various combinations of such stacking and electrical joining steps are possible and within the scope of the invention. After the wafers (1020, 1050) are stacked and electrically connected (1〇25) to the lead frame, then a capping material (1 〇3 〇) is used to encapsulate the lead frame to wafer 153285. Doc -56- 201232673 and the wires are permanently mounted to the lead frame, then the back side is patterned, etched and the back side of the lead frame is completed as appropriate to isolate the electrical leads (1005). During this backside patterning process, portions of the leadframe underneath the die-stacked wafer are completely removed, and only the leads (1005) are "bumped" from the completed wafer size package. In general, the portion of the original lead frame that will remain after the backside patterning is only the electrical leads (1 〇〇 5). Finally, the wafer size package is singulated in the street region to create an individual wafer size package (1070) for subsequent applications. In accordance with another aspect of the invention, both the top and bottom of the leadframe may be partially patterned or partially etched prior to die attach. As illustrated in Figure 37a, the lead frame (1100) can be etched on both sides prior to assembly of the wafer size package. The etching on both sides of the lead frame may have a uniform depth. Alternatively, the etch may be non-uniform and one side may be patterned deeper than the other side. For example, the top (e.g., region 1160) can be patterned deeper than the bottom (e.g., region 1165). Double sided etching permits a reduction in the thickness of the portion of the film used for the lead frame that will ultimately be removed. Therefore, the etching will proceed faster and thereby increase the production speed and reduce the cost. Partial patterning can reduce the thickness of the etched portion of the film by any convenient amount. For example, a portion of the patterned segments of the leadframe can remove 25% to 9% of the original film thickness in the etched regions. The leadframe material can be pre-patterned with a resist material. The resist may be a metal or a non-metal such as an organic resist and may be oven cured or UV cured. This pre-patterning process is well known in the art. Alternative - metal pre-plated lead frame, available with a printable ink (153283. Doc • 57· 201232673 such as epoxy ink or a stencil ink) or an organic material (such as polyimine resin, which serves as an etch mask before backside etching) to print the lead frame. This technique advantageously allows for cost reduction and streamline manufacturing. From a material point of view, the use of printable inks or an organic material as a mask allows the manufacturer to obtain leadframe sources from many manufacturers, as not all suppliers can pre-record leads on both sides. frame. In this example, the leadframe supplier will only etch and plate the leadframe on top, leaving the bottom unfinished. For example, the bottom of the lead frame can be bare metal (such as copper). The cost of masking with a printable ink or an organic material is typically masked by the use of a precious metal such as palladium, gold, platinum, rhodium, silver or iridium or an alloy thereof which is an example of a material that has been used to pre-plate the leadframe. The cost is small. In addition, it is generally easier to remove the ink after etching than to remove the precious metal. The lead frame can also be pre-plated prior to etching. The pre-mineral coating materials may be the same or different on the top and bottom surfaces of the lead frame. Examples of suitable pre-coating materials include wire bondable materials (such as test-coated Ni/Pd/Au and silver (Ag)), and solderable materials (such as Sn/Pb, lead-free solder, immersion tin electroless nickel or test) Plating type Au (gold)" In one embodiment of the invention, the front surface is pre-plated with a bondable material and the back surface is pre-plated with a solderable material. In another embodiment, the front surface may be pre-plated with a wire bond material and pre-plated with a resist and overlying the back surface. In other embodiments, an organic material can be printed or applied to the leadframe for use as a photoresist. Figure 36a shows a film (11 inch) that has been etched to form a wafer pad (1110) and a plurality of electrical leads (1105). The top of the film has been etched to the bottom of the film [e.g. (1) 6S). Illustration] a greater degree [eg (116〇) example 153285. Doc •58· 201232673 Certificate]. Figure 36b shows a wafer (1120) electrically connected to the leadframe shown in Figure 36a via wire bonds (1125). In Fig. 36b, an integrated circuit wafer (112 〇) has been adhered to the lead frame (u 〇〇) using a bonding agent (1115), and the wafer package has been covered with the epoxy capsular (1130). The street shaped area (1135) separates the electrically connected and encapsulated wafer (1120). After the wafer (1120) has been adhered to the wafer package (ii) of the lead frame and encapsulated, the back surface of the lead frame can be patterned and etched through the back surface to isolate the electrical leads (1105) from the wafer pads (1110). Or electrically separate the various portions of the leadframe to create the desired features. Since the back surface has been partially stamped, this backside etching process will continue more quickly and thereby advantageously improve hourly unit (UPH) productivity and reduce cost. The bottom die pad of the lead frame is usually flat. An example of a lead frame having a flat bottom die pad is illustrated in Figure 37b. However, in some instances, such flat grain lanthanum tends to cause tantalum void problems when mounting a wafer size package to a printed circuit board. In the case of non-acceptance, it is believed that the gaps in the material are mainly caused by (4) (4). While solder voids can reduce the efficiency of electrical contacts and can therefore cause second-level reliability issues, solder voids can typically only be tested by X-ray microscopy or destructive micro-slices. According to another aspect of the invention, a lead frame can have a bottom line of creped lines. This embodiment of the die pad is shown in circle 38. The hatch () can form a channel across one of the die pads (121〇) and reduce the contact surface area between the die pad and the brush face plate, thereby advantageously reducing the solder void shadow line or channel (1255) acting Vents so that there is no 153285 during the return to the Tan. Doc . 59· 201232673 Capture air. The bottom pad (1210) of the hatched line is obtained by making a small plated mask array under the pad on the bottom side of the lead pivot. During the etch, this array of plated masks will establish a half-etched via across the dome die pad. This mask will be used as a primary anti-soul agent during the engraving process. The etch mask can be nickel/palladium/gold composite (NiPdAu) 'silver (Ag), strontium (Sn), nickel (Ni) or mixtures thereof, or any non-metallic or organic material or can be applied or printed to the lead frame The ink on it. At the discretion of the oven or uv curing the money engraved. Other suitable masking and photoresist materials are well known to those skilled in the art. The masking and etching process can be performed as previously discussed. Figure 38 shows a wafer size package (1240) having a bottomed die pad (121〇) with a hatched line, and a plurality of integrated circuit chips (122〇, 125〇) mounted to the s-cushion. The lower wafer (1220) is adhered to the patterned die pad via a bonding agent (1215), and the upper wafer (125〇) is adhered to the lower wafer (1220) via an adhesive (1245). The wafers (122〇, 125〇) are electrically connected to the electrical leads (12〇5) via wire bonds (1225), although in other embodiments, the wafers (1220, 1250) may also be electrically connected to each other. The wafers are encapsulated with an epoxy resin or one of the other materials (1230). Although FIG. 38 shows one wafer size package including two die-stack integrated circuit chips [but * other embodiments of the present invention, in one single wafer, and in other embodiments, there may be three Or multiple die stacks = wafers. All such embodiments are within the scope of the present invention. There may also be a different number of wafers attached to the individual wafer pads on the leadframe. For example, 153285. Doc-60·201232673 stated that one wafer pad of a lead frame can have a single die mounted wafer, while another wafer pad on the same lead frame can have three die mounted wafers. Thus, the present invention can be used to prepare a plurality of different and non-identical wafers on a single lead frame. Figures 39a and 3b illustrate two embodiments of a wafer size package (1340) in accordance with another aspect of the present invention in which the electrical landing sites have different configurations. Figure 39a illustrates a wafer size package (134〇) in which all of the electrical landing points (1305) are square and are arranged in two concentric columns around the wafer (132〇) to maintain a sufficient distance for each landing point. Circle 39b illustrates a wafer size package (1340) in which the electrical landing point (13〇5) is in the form of an lead (1309). Line (1325) forms the electrical connection between the wafer (mo) and the electrical landing point (1305) in Figures 39a and 39b. The lead wires can be prepared during etching or can be applied to the lead frame using conventional techniques such as screen printing. In alternative embodiments, any of the landing points on the lead frame can have any shape, such as an elliptical 'rectangular or circular shape. These alternative landing point shapes anywhere on the lead frame are within the scope of the present invention. The line connecting the wafer (1320) to the electrolanding point (1325) in Fig. 39a is longer than the line (1325) connecting the wafer (1320) to the lead in Fig. 39b. While the embodiment of Figure 39a provides a significant improvement over the prior art leadframe and is highly effective, it is sometimes necessary to take care to avoid causing the lines to touch or otherwise become too close. Occasionally special circuit techniques are used to keep the lines separate. While these techniques can sometimes slow down the wire bonding process, they are useful. In contrast, in Figure 39b, the end phase of the lead (1309) is introduced 153285. Doc -61 - 201232673 The amount of wire required for the electrical terminals on the periphery of the seven-way* mountain 7 and thus the electrical connection is very short for IC chips (13 2 0). Since these lines (1325) are typically formed of gold, the shorter length of the wire for wire bonding permits a reduction in the amount of gold used and thus lowers production costs. Although the electrical landing point (13〇9) in Figure 39a is illustrated as conforming to the lead of the present invention, some of the landing points may be in the form of lead-in leads and others: the dots have another-form such as conventional Square lead. For example, the electrical landing point closest to the wafer may be in the form of a square, circular or rounded landing point, and the electrical landing site that is further away from the wafer may have lead-in leads. These combinations are within the scope of the invention. Circle 40a illustrates a cross-sectional view of an embodiment of a wafer size package (1340) according to another aspect of the present invention, the center day wafer system having solder dots (138 〇) disposed off the periphery of the wafer. One of the wafers is electrically connected, and the wafer is electrically connected to an lead-in lead (stage 1) extending under the wafer. Figure Illustrated - another embodiment of a wafer size package (1340) in which the wafer (1320) has solder dots (138 〇) disposed on the bottom of the wafer as an array of m points connected to A lead wire (1309) extends below the wafer. As illustrated in Figures 39 and 40, the lead-in can be effectively utilized by both the in-line and flip-chip embodiments. Figure 41 illustrates an embodiment of an ELp lead frame fabricated using lead-in leads and a padless option. The techniques used to fabricate the leadframe will generally be comparable to the techniques previously described above for the conventional landing site. In step i, a metal frame (1300) will be used to transform the starting material. In step 2, the metal frame is partially etched to obtain a mesh portion (13〇5) and a crystal I53285. Doc -62· 201232673 Part of the attached area (1310) is carved by the surname! One of the line frames. The metal frame (1300) can be made of any convenient material, such as copper or a copper alloy. The portion of the surname step illustrates the removal of material from the center of the bow i-frame 以便3〇〇) to give a _no-lead lead frame around the region (1310). That is, • the center of the wafer or die (1320) will not be located on one of the resulting wafer size packages. In step 3, after partial etching, the lead frame (丨3 〇〇) is selectively plated with a wire bonding material such as Ag, Ni/Au or NiPdAu to form an electric landing site (1307), which The isoelectric landing point is in the form of an introduction lead in the illustrated embodiment. The electrical lead portions (1307) are electrically separated from the wafer attachment regions to prevent unintended electrical contact, and the lead frames are separated from each other by a street-shaped portion (not illustrated). Although in FIG. 41, partial etching (step 2) is completed prior to selective plating (step 3) in accordance with the present invention, these steps may be performed in any convenient order and may be performed prior to partial etching (step 2) Selective plating (step 3). The sequence of steps will depend on the particular embodiment in front of you. The top of the lead frame (1360) will typically have a selectively plated surface, and the bottom plating is optional. If the bottom surface of the lead frame is plated (1365), the coating can be used as an etch resist. Or for board mounting. In step 4, after plating, a wafer or die (1320) is attached to the wafer attachment area (131A) of the lead frame using an adhesive (1315). Electrical bonding is then formed between the terminals of the wafer (1320) and the electrical lead portions (1307) of the corresponding leadframe using wire bonding techniques (step 5). As previously discussed, the lead portion (1307) is in the form of a lead-in lead, and the wafer or die is attached to 153285. Doc • 63· 201232673 The step of attaching to the wafer attachment area may optionally include placing the wafer on an active lead that will support the wafer in the absence of a wafer pad (or will be active in the final wafer size package) On top of the lead) (illustrated further in Figure 47b). In this embodiment, a non-conductive adhesive (such as a non-conductive epoxy) or a die attach film adhesive can be used to adhere the a-wafer to the wafer attachment area. In this embodiment, an electrical connection is made between the active leads and the integrated circuit die. In Fig. 4, the wafer (1320) is a one-wire bonded wafer, although the wafer may alternatively be a flip chip. In this example, a wire bonding step will be replaced with one of the soldering steps known in the art. After the wafer (1320) is electrically connected to the electrical lead portion of the lead frame using wire bonding (1325) in step 6, by applying a capping material (133〇) to the lead frame and separating the lead frames A street shaped portion encloses the lead frame. The bottom surface of the lead frame is then patterned or back etched (1365) to remove the mesh portion and the street portion. In this etching step, an organic etch resist (1361) or another suitable resist may be applied to the selective portion of the bottom of the lead frame prior to etching to etch the remaining portion of the process removable metal frame. The required part (shown in step 7). In step 8, the lead frame is then singulated using a saw or other suitable technique to form an individual wafer size package (1340) (step 8). The bottom of the lead frame or wafer size package may be coated with a non-conductive coating (1375), such as an ink or a solder resist material, to protect the bottom of the wafer-sized package from mounting to a printed circuit board or other device. Free from short circuits. 153285. Doc -64- 201232673 The solder ball (1380) can also be adhered to the electro-landing point as needed to facilitate subsequent attachment of the wafer size package (1340) to the intended useful location. Alternatively, a solderable material can be applied to the electrical landing site as needed to facilitate subsequent electrical connections. While any of these optional features can be applied before or after singulation, it would generally be more convenient to apply such features prior to singulation. Figure 42 illustrates a process for preparing an EMI (electromagnetic interference) shield to one of the inventive ELP lead frames of the present invention. In Fig. 42, the electric landing site (1309) is in the form of a lead-in lead and the lead frame is coated with an electromagnetic interference (EMI) shielding material (1385) prior to singulation. Steps 6 through 42 of Figures 41 and 42 are common to both processes, starting with a metal frame (13 turns) and leading to the preparation of the encapsulated lead frame in step 6, and will therefore not be discussed further. In step 7 of Figure 42, the encapsulated leadframe is partially cut in the street shaped area (1335) to expose the metal leadframe (1300) for grounding of the emi shield (1385). An EMI shield (1385) is then applied over the encapsulated leadframe and the street shaped area. EMI shielding can be applied to any convenient event known in the art. For example, the shield (1385) can be applied by electroplating, electrolytic plating, dipping, spraying, a screen printing process, or any other suitable technique known in the art. A coating resist can be applied to the EMI shield (shown in step 9) as needed prior to the subsequent backside etch process. The coating resist will prevent the etch chemistry from attaching to the shield. The bottom portion (1365) of the lead frame is 'back patterned or back etched in step 9 to remove the mesh portion and the stalk portion. An organic etching can be used 153285. Doc • 65- 201232673 Anti-rice (1361) or another suitable resist to protect the selective portion of the metal frame (13〇〇) from being removed during etching. This resist will typically be removed prior to preparation of the final package. An electrical landing site is formed during the etching process to provide an electrical connection to the wafer. If a coating anti-money agent is applied to the Emi shield, it will be removed along with any remaining resist used during etching. In step 10, the leadframe is then singulated in a street shaped area using a saw or other suitable technique (not illustrated) to form an individual wafer size package (134A) having an emi shield (1385). Similar to the embodiment of Figure 41, the bottom of the leadframe or wafer size package (1365) may be coated with a non-conductive coating (1375) such as ink or a solder resist material to protect the bottom of the wafer size package. Avoid short circuits when mounted to a printed circuit board or other device. Solder balls (1 3 80) or other connecting members may also be adhered to the landing land as needed using a solderable material to facilitate subsequent attachment of the wafer size package to the intended useful location. The lead frame can have a die 塾' or a padless option as illustrated in Figure 42 can be used. The EMI shield (13 85) in the wafer size package reduces the amount of ambient interference or noise seen by the encapsulated wafer (1320), thereby improving the effectiveness of the wafer. The resulting wafer size package is suitable for many applications in circuits and electronic devices. Figures 43a through 43c illustrate the steps in the fabrication of an EMI shielded wafer size package using one of the block molding options of the leadframe. In this embodiment, a large mold is used to cover the entire array of lead frames (Fig. 43a) with a seal (1330) in a single block. After curing the encapsulant, the mold 153285 is removed. Doc -66 - 201232673 with, thus leaving a single array of cells (134〇) to be singulated later. The encapsulation (133〇) is then cut down to the metal frame (1300) in the street-shaped area (1335) in Figure 43b. Care must be taken to avoid excessive cutting into the metal frame and to weaken the lead frame. After partial dicing in the leadframe, EMI shields (1385) are applied as shown in Figure 43c, and the leadframes are then singulated to obtain individual wafer size packages (1340). Figures 43d through 43e illustrate the steps in preparing an EM] [shielded wafer size package using a pocket molding option. In the embodiment of Figure 43d, the parent unit (1340) of the lead frame has a cavity that encloses the mold itself, resulting in an individual molded unit covered with a seal (1330). As shown in Figure 43e, an EMI shield (1385) is then applied to the leadframe and the resulting leadframe is then singulated in a street shaped area (1335). The recording or other technique can be used to apply the electrical lead portion of the frame (丨3〇7). A conventional lead frame mold with a pouch can be used, although tape assisted molding can help prevent the mold from flashing (the excess encapsulation is attached to the lead frame). Advantageously, since the individual mold pockets do not coat the street shaped area (1335) and therefore do not need to be exposed by dicing, the leads used to shield the connections have been exposed' as discussed further with respect to Figure 49. The use of bag molding also eliminates the need to partially saw the lead frame to expose the metal film (1300), thereby reducing cycle time and making the process more cost effective. Individual molding of laminates is also possible. Figures 43a through 43e are discussed with reference to the application of EMI shielding to the encapsulated lead frame prior to singulation. Figures 44a through 44c illustrate the steps in an alternative embodiment in which the unit 153285 is first singulated prior to application of the shield (1385). Doc -67· 201232673 (1340). The unit (134) and the singulated (but not shielded) unit (134〇) may be placed on the silver mold ((10)) as shown in the circle 44a, or placed in the silver as illustrated in Figure 44b. The belt or carrier tape (1) 91) is placed on other convenient components to facilitate movement of the lead (4) to the recording (1392). After singulation, the face shield material (1385) may be applied to the cells via smear, screen printing or other means while the singulation unit (1) is still on the die or tape. After application of the shielding material, the completed wafer size package can be individually packed and placed in a shipping tray, tube, pack, can or other package for final delivery to a customer. Figures 45a through 45b illustrate the steps in partially etching the bottom of one of the lead frames having an emi shield (1365). In Fig. 45a, the bottom of the lead frame (1365) has been previously covered with a pre-mineral mask or (iv) anti-(4) (1361), and then the bottom is selectively engraved to form the desired surface features. A solder resist (1375) is then applied to the bottom of the leadframe followed by a solderable material (1362) to form an electrical landing site (Fig. 45b). Solder resist (1375) can be prepared conventionally or specifically for a particular leadframe' depending on the specific requirements at hand. The solderable material (1362) may comprise silver (Ag), tin (Sn), tin-gold alloy (SnAu), electroless nickel electroless palladium immersion gold (ENEPIG) or any other electrically conductive material that may be adhered to the leadframe. The solderable material can be applied by dipping, electroless plating, screen printing or other convenient techniques. Solder paste or ball drops (not shown) may be used to increase the size of the landing point for later electrical attachment. After the EMI shielded leadframe is fully fabricated, it can be singulated in a street shaped area (1335) to form an individual wafer size package. 153285. Doc • 68· 201232673 In an alternative embodiment illustrated in Figure 45c, the unshielded bottom (1365) of an EMI shielded lead frame may be overflow etched to expose features of the bottom surface. In the overflow etching step, no selective plating or mask is applied. The overflow etch does not cause any outstanding landing points, although the mesh features have been etched away to isolate the leads from the pads. After the bottom has been etched, a solder resist can be applied to the relatively flat bottom portion of the molded block, and an electrical feature can be applied using a solderable material (1362 Figure 45d) ^ typically any desired position will be located Pads and solderable materials to facilitate mounting The resulting leadframe can be singulated in a street open area (1335) to provide an ELp die size package with an EMI shield (1385). Figures 46a through 46e illustrate top and rear ray views of an exemplary embodiment of a wafer size package (1340) fabricated in accordance with the present invention, wherein the electrical landing (1305) has lead-in leads (13〇9) and is connected using wire bonds To a wafer (1320). The X-ray view shows the circuitry of the wafer size package (1340) viewed through the encapsulant (133〇). In Fig. 46a, the outer leads (!3〇5) are arranged around a wafer 塾(1)(7)) and in the case of Tudor, both the inner and outer leads (10)5) are routed as lead-in leads (1309). . A solder resist or protective ink will typically be used to cover the bottom of the wafer size package to prevent exposure of the leads themselves. Therefore, in the actual aa chip size package, only the landing point (1) will be visible and the routing will not be visible. The figure is illustrated below - a wafer size package (134 inch) in which a wafer (1320) having a small size is placed on a pad using a conductive epoxy. The external column of the lead (10) 5) is selected by the routing 'and the lead 〇3〇5) is not selected 153285. Doc •69.  201232673 The road is in the shape of a square. Since the external leads are routed, the amount of wire used is less than the amount of wire originally required in the case where any of the leads have not been routed. Figure 46d illustrates a wafer size package in which a wafer (1320) having a small size is placed on a pad using a conductive epoxy and the wafer is pulling the internal and external leads (1305) that have been routed. . The amount of gold wire used for wire bonding in Figure 46d is less than that used in Figure 46c. Figure 46e illustrates a wafer size package in which a wafer (1320) having a large size is placed on the routed lead (1309) itself and the wafer is adhered using a non-conductive epoxy or a die attach film. To the following grain plastic*. The amount of gold wire required is less than the amount of gold wire that would otherwise be required if no electrical leads (1305) were selected. Figures 47a through 47d illustrate bottom views of a wafer size package (1340) fabricated using a germanium and germanium-free embodiment in accordance with the present invention, wherein the electrical landing point (1305) is in the form of a lead-in lead (1309). Figure 47a shows a wafer size package (134 inch) in which a single column of selected routing lines (1309) surrounds a die pad (1310). A conductive epoxy wafer can be attached to the die pad for electrical purposes and achieves superior thermal performance. Figure 47b shows a wafer size package (1340) having a single column of selected traces (1309) according to a padless option. The leadframe will still have a wafer attachment area (1310) in the periphery. The e-IC wafer can be placed on top of the active leads that will support the wafer in the absence of a wafer pad. The wafer is adhered to the lead frame using a non-conductive adhesive such as a non-conductive epoxy or a die attach adhesive, and an electrical connection can be made between the leads and the turns. ' Μ 153285. Doc •70· 201232673 Figure 47c shows a wafer size package (134〇) in which the grain 塾(10)〇) is in the form of a partial metal via and the leads (13〇5/13〇9) are surrounded by two columns. private school. The inner lead row (1309) is routed and the outer column (13〇5) is unrouted and does not have an attractive lead. In Fig. 47d, the die pad n3lQ) is solid and the landing points (1305/1309) are arranged in two columns around the die pad. The outer lead column (1305) is unrouted and the inner lead row is routed using lead-in leads (13〇9). Figures 48a through 48b illustrate cross-sectional views of an embodiment of a wafer size package (104) in accordance with the present invention in which the die pad is solid or contains portions of metal vias such as thermal vias. Figures 49a and 49b illustrate top and cross-sectional views, respectively, of an encapsulated ELp lead frame in accordance with the present invention and showing electrical ground connections for EMI shielding. Figure 49a illustrates a top view X-ray view of one of the four encapsulated wafers (132 turns) of a lead frame, and the wafer is electrically connected to the lead-in leads (丨3 〇 9) ^ although four wafers are shown for ease of illustration (132〇), but the lead frame can be of any convenient size and can have any number of units. The leadframe has been encapsulated (1330 in Figure 49b) and covered by an EMI shield (1385 in Figure 49b), but has not been singulated to form individual wafer size packages. The EMI shielded coating (1385) is in electrical contact with each of the corner electrical landing sites (1308). To form an individual package, the lead frame will be singulated along a dashed line (1335) representing the street-shaped region of the lead frame. Figure 49b shows a cross-sectional view of each of the cells of Figure 49a after singulation. The wafer (1320) has been encapsulated (1330) and coated by an EMI shield (1385). Doc •71· 201232673

顯示用作用以屏蔽連接之 且該等引線之形式為引入 佈。 圖49a與49b之間的箭頭 接地之電引線（1308)之對應物， 引線（13G9)且在晶片（132G)T面延伸。可藉由使其他引線 橫跨封裝線而延伸至街道形區中而使該線用於至接地 的電磁屏蔽式層連接以便此等引線可連接至 (I385)。該等封裝亦在引線上具有可烊材料⑴叫以用於 連接至一電路板或其他裝置，且具有封裝（134〇)之底部上 的一非導電塗層（1365)。 本發明之各種所闡述之實施例並非相互排斥且可視需要 地進行組合以製備所揭示之引線框架之變型。舉例而言， 圖37&中所圖冑說明之不均勻㈣之引線框架@晶粒塾之 底部可進行交又影線並用以製備圖38中所圖解說明之具有 底部通道之晶片尺寸封裝。類似地’可將圖42中所顯示之 EMI屏蔽施加至圖27b之晶片尺寸封裝以獲得具有£]^1屏蔽 之多BB片封裝。其他變型係可行的且在本發明之範疇内。 儘管已參考特定具體實施例顯示並闡述了本發明，但熟 習此項技術者將瞭解可在不背離本發明之精神及範疇之情 形下進行各種形式及細節上的改變。 【圖式簡單說明】 圖1 a係根據先前技術，具有引線及一晶片墊區域之一習 用引線框架之一圖式。 圖lb係根據先前技術，顯示將一晶片附接至晶片墊且將 該晶片上之端子線接合至引線之圖la的習用引線框架之一 圖式。 153285.doc -72- 201232673 圖2a係根據先前技術，顯示藉助引線連接至下一級封裝 之一線接合及引線式（具有引線）近晶片尺寸封裝（CSP)之一 剖視圖。 圖2b係根據先前技術，顯示藉助焊料凸塊或球連接至下 一級封裝之一線接合及無引線式（沒有任何引線）接近CSP 之一剖視圖。 圖2c係根據先前技術，顯示藉助引線連接至下一級封裝 之一覆晶及引線式接近CSP之一剖視圖。 圖2d係根據先前技術，顯示藉助焊料球連接至下一級封 裝之一覆晶及無引線式接近CSP之一剖視圖。 圖3 a係根據先前技術，顯示一背面接合晶片線接合連接 至引線框架之引線的一模板狀引線框架之一俯視圖。 圖3 b係根據先前技術，顯示透過一焊料回焊製程一覆晶The display is used to shield the connections and the leads are in the form of an incoming cloth. The arrow between Figures 49a and 49b corresponds to the grounded electrical lead (1308), the lead (13G9) and extends on the T-plane of the wafer (132G). The wires can be used to connect to the grounded electromagnetic shield layer by extending the other leads across the package line into the street shaped regions so that the leads can be connected to (I385). The packages also have an electrically conductive material (1) on the leads for connection to a circuit board or other device and have a non-conductive coating (1365) on the bottom of the package (134〇). The various illustrated embodiments of the invention are not mutually exclusive and can be combined as needed to prepare variations of the disclosed leadframe. For example, the bottom of the lead frame @die塾 illustrated in Figures 37 & (4) can be cross-hatched and used to prepare a wafer-scale package having a bottom channel as illustrated in Figure 38. The EMI shield shown in Figure 42 can be similarly applied to the wafer size package of Figure 27b to obtain a multi-BB chip package with a shield. Other variations are possible and are within the scope of the invention. Although the present invention has been shown and described with reference to the specific embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1a is a diagram of a conventional lead frame having a lead and a wafer pad area according to the prior art. Figure lb is a diagram showing one of the conventional lead frames of Figure la, which attaches a wafer to a wafer pad and bonds the terminal wires on the wafer to the leads, in accordance with the prior art. 153285.doc -72- 201232673 Figure 2a is a cross-sectional view showing one of a wire bond and a leaded (with lead) near wafer size package (CSP) connected to the next package by wire bonding according to the prior art. Figure 2b is a cross-sectional view showing the proximity of the CSP by wire bonding and leadless (without any leads) connected to the next level of the package by solder bumps or balls according to the prior art. Figure 2c shows a cross-sectional view of one of the flip chip and leaded proximity CSPs connected to the next level of the package by means of a lead according to the prior art. Figure 2d shows a cross-sectional view of one of the flip chip and leadless proximity CSPs connected to the next stage of the package by solder balls in accordance with the prior art. Figure 3a is a top plan view of a stencil-like leadframe showing a backside bonded wafer wire bonded to a lead of a leadframe in accordance with the prior art. Figure 3b shows a flip chip through a solder reflow process according to the prior art.

直，其中每一位置包含一 圖1 2 3係根據本發明， 膜之一剖視圖。 膜之一 已部分經圖案化之圊4的經鍍覆金屬 之部分經圖案化之引線框架之一 圖6a係顯示根據本發明 矩陣之一俯視圖。 I53285.doc -73· 1 的一金屬膜之一剖視圖，其中僅 2 已經圖案化以對應於兩個晶片位 3 -晶片墊及圍繞每一晶片墊之引線 201232673 圖6b及6c顯示圖心中所顯示之矩陣—之引線框架之逐漸 放大俯視圖。 圖7a係根據本發明之圖6的部分經圖案化之金屬膜之一 剖視圖，其中已將一晶片附接至兩個晶片位置中之每一者 上之晶片塾。 圖7b係根據本發明顯示包括環氧樹脂或焊料之附接的晶 片與晶片墊之間的連結部之一放大視圖。 圖8係根據本發明之圖7asil7b的晶片附接金屬膜之一剖 視圊’其甲已將每-晶片上之端子線接合至如此形成於每 一晶片位置上之引線框架之引線部分。 圖9係根據本發明之圖8的線接合引線框架之一剖視圖， 其中已在一囊封物中密封包含晶片及線接合之金属膜的頂 部表面。 圖10係據本發明之圖9之經密封封裝之一剖視圖，已自 背側飯刻該封裝以移除該膜中之每一引線框架及街道形區 之第一區。 圖11係兩個接近晶片大小的部分經圖案化之封裝之一剖 視圖，其中已根據本發明在街道形區中單個化囊封物以形 成兩個分離封裝。可藉助鋁線、銅線球接合技術或藉助任 何其他方便的接合技術超聲波接合此等封裝。 圖12a係根據本發明顯示晶片、觸點以及將晶片端子連 接至引線觸點之線之圖丨丨的單個化封裝中之一者之一俯視 圖，以及具有一線接合之觸點中之一者之一放大截面。 圖12b係根據本發明在晶片墊與觸點中之一者之間的區 153285.doc •74· 201232673 域之-剖視圖，其顯示使用與模製材料接觸之垂直表面上 之一「唇狀物」以提供錨定並防止分層。 圖12c係根據本發明在晶片墊與觸點中之一者之間的區 域之-剖視圖，其顯示使用與模製材料接觸之垂直表面上 的之不同形狀之空腔以提供錨定並防止分層。 圖13aj_13f係各種空腔之圖式’可根據本發明使用該等 空腔以為圖12b及12c所顯示之垂直表面上之模製材料提供 錯定構件。 圖14係根據本發明之—流簡，其概述形成—部分經圖 案化之封裝的各種製程步驟。 圖15a係根據本發明顯示具有一周邊1/〇組態之一封裝之 俯視、側視及仰視圖之一圖式。 圖15b係根據本發明顯示具有1/〇塾之一陣列組態之一封 裝之俯視、側視及仰視圖之圖式。 圖16係根據本發明之圖4的—金相之—職圖，其中 僅頂。P表面上之預鍍覆已經圖案化以對應於兩個覆晶位 置，其中每-位置包含一晶片附接區域及圍繞每一晶片附 接區域之引線。 圖17係根據本發明，已部分經圖案化以形成—網狀引線 框架（即，網式結構）之圖16的經鍍覆金屬膜之一剖視圖。 ㈣係根據本發明，顯示覆晶（FC)連結之—晶片連結式 引線框架（FCL)之一剖視圖。 圖19係根據本發明之圖18的似之—剖視圖，其中已在 一囊封物中密封包含晶片之金屬膜之頂部表面。 I53285.doc •75· 201232673 之一剖視圖，已 線之間以及凹入 圖20係根據本發明之圖19之經密封封裝 自背側蝕刻該封裝以選擇性地移除個別弓丨 的晶片附接區域之間的網式部分。 圖21係根據本發明已自圖2〇之封裝單個化之兩個接近晶 片大小的部分經圖案化之封裝之一剖視圖。 圖22a係根據本發明之圖2 1的單個化封裝中之一者之一 俯視圖’其顯^晶Μ及將3料連接至引線之端部分 之引線，該等端部分又連接至下一級封裝。 圖2 2 b係根據本發明在覆晶與顯示一引線之兩個端連接 之下一級封裝的連接之間的區域之一放大剖視圖。 圖23係根據本發明之一流程圖，其概述形成支撐一覆晶 之一部分經圖案化之封裝的各個製程步驟。 圖24a及24b顯示根據本發明已被單個化且然後具備用於 連接至下一級封裝以形成一 ELGA型封裝之著陸點柵格陣 列連接器之兩個接近晶片大小的部分經圖案化之封裝之一 剖視圖及一仰視圖。 圖25a及25b顯示本發明之另一可選實施例，其包括將本 發明之引線框架封裝線接合至下—級封裝。此等圖圖解說 明藉助铭線（圖2 5 a中所顯示）或藉助銅線球接合技術（圖2 5 b 中所顯不）超聲波接合圖24a及24b之封裝。可使用銅線球 接合技術將覆晶封裝連接至引線框架。 圖26a及26b係本發明之一實施例之透視圖及剖視圖，其 中晶粒堆疊複數個晶片以形成一半導體封裝。 圖27a至27c係本發明之一實施例之透視圖及剖視圖，其 153285.doc -76- 201232673 中晶片墊凹入以允許經改良之晶粒堆疊及封裝高度之一減 小 〇 圖28a及28b顯示根據本發明之一實施例具有一凹入式晶 片墊區域及晶粒堆疊晶片之引線框架之透視圖。 圖29a至29c顯示根據本發明之一態樣具有之形式為晶片 墊鎖定特徵之變更的引線框架之透視圖。 圖30a至30d圖解說明根據本發明之一態樣之若干個實施 例具有變更之若干種類型之電引線之俯視圖及側視圖。 圖31a至31b圖解說明根據本發明之另一實施例之電引線之 俯視圖及側視圖，其中已粗糙化引線框架或引線之表面。 圖32a至32e圖解說明根據本發明之另一態樣提供於電引 線上之若干種類型之變更之透視圖。圖32f圖解說明根據 本發明之另一態樣之一實施例之一電引線之俯視圖及側視 圖，其中已粗縫化引線框架之表面以提供一囊封物之經改 良之黏著。可結合本發明中所呈現之變更來完成此表面粗 縫化。 圖33a至別圖解說明本發明之實施例之—態樣，其中使 用夾子來替代線接合以改良晶片之功率容量。 圖34a至34f圖解說明—部分經㈣化之引線框架之一實 施例’其中不存在一晶片接收區域，且將晶片直接放置於 引線框架上。在後續的晶粒附接、線接合、囊封以及 圖案㈣完成步驟之後，移除晶片下面之引線框架之部 为。此元成步驟將曝露用以將晶片黏附至引線框架之 電黏合劑（諸如一環氧材科或一膠帶）。 153285.doc -77- 201232673 圖35圓解說明經由圖34a至34f所顯示之序列而製備之晶 片尺寸封裝之一仰視圖。 圖36a提供圖34f_所顯示之晶片尺寸封裝之一剖視圖。 圖36b提供本發明之另一實施例之一剖視圖，其中該晶片 尺寸封裝包括複數個晶粒堆疊之線接合晶片。 圖37a圖解說明一引線框架，其中在將任何晶片附接至 引線框架之前已部分圖案化頂部及底部表面兩者。圖371? 圖解說明圖37a之引線框架，一晶片已與該引線框架電連 接’且在背面圖案化及單個化之前已囊封該引線框架。 圖38圖解說明包括複數個晶粒堆疊之線接合晶片之一晶 片尺寸封裝，其中已給晶粒塾之底部劃影線以提供空氣通 風0 圖39a圖解說明根據本發明之一態樣之一晶片尺寸封裝 之一實施例之一俯視圖，其中電著陸點之形狀皆為正方形 且在晶片周圍配置成兩個同心圓列，且線將該晶片連接至 。亥等電著陸點。如稍後將論述，在替代性實施例中，該等 著陸點可具有任何形狀，諸如（但不限於）橢圓形、矩形或 圓形。 圖39b圖解說明圖39a之實施例之一變形之一俯視圖，其 中電著陸點之形式為引入引線且在晶片周圍配置成兩列。 線將該晶片連接至非常接近該晶片之引入引線之端子部 分。 圖40a圖解說明根據本發明之另一態樣之一晶片尺寸封 裝之一實施例之一剖視圖，其中該晶片係具有在該晶片之 153285.doc •78- 201232673Straight, each of which contains a Figure 1 2 3 is a cross-sectional view of a film in accordance with the present invention. One of the films has been partially patterned with one of the plated metal portions of the patterned metal frame. Figure 6a shows a top view of a matrix in accordance with the present invention. I53285.doc -73. A cross-sectional view of a metal film in which only 2 has been patterned to correspond to two wafer levels 3 - wafer pads and leads around each wafer pad 201232673. Figures 6b and 6c are shown in the figure. Matrix - the progressive enlargement of the lead frame. Figure 7a is a cross-sectional view of a portion of the patterned metal film of Figure 6 in accordance with the present invention in which a wafer has been attached to the wafer cassette on each of the two wafer locations. Figure 7b is an enlarged view showing one of the joints between the wafer including the epoxy or solder attached and the wafer pad in accordance with the present invention. Figure 8 is a cross-sectional view of one of the wafer attaching metal films of Figure 7asil7b in accordance with the present invention. The armor has bonded the terminal wires on each of the wafers to the lead portions of the lead frames thus formed at each of the wafer locations. Figure 9 is a cross-sectional view of the wire bond lead frame of Figure 8 in accordance with the present invention in which the top surface of the metal film comprising the wafer and the wire bond has been sealed in a package. Figure 10 is a cross-sectional view of the hermetic package of Figure 9 in accordance with the present invention, the package having been engraved from the back side to remove each of the lead frames and the first region of the street region of the film. Figure 11 is a cross-sectional view of a portion of a partially patterned package near wafer size in which the encapsulation has been singulated in a street shaped region to form two separate packages in accordance with the present invention. The packages can be ultrasonically bonded by means of aluminum wire, copper ball bonding techniques or by any other convenient joining technique. Figure 12a is a top plan view of one of the singulated packages showing wafers, contacts, and wires connecting the wafer terminals to the lead contacts, and one of the contacts having a wire bond, in accordance with the present invention. An enlarged section. Figure 12b is a cross-sectional view of a region 153285.doc • 74· 201232673 between one of the wafer pads and the contacts in accordance with the present invention, showing one of the "lips" on the vertical surface in contact with the molding material. To provide anchoring and prevent delamination. Figure 12c is a cross-sectional view of a region between one of a wafer pad and a contact in accordance with the present invention showing a cavity of a different shape on a vertical surface in contact with the molding material to provide anchoring and to prevent separation Floor. Figures 13aj_13f are diagrams of various cavities' that can be used in accordance with the present invention to provide a staggered member for the molding material on the vertical surfaces shown in Figures 12b and 12c. Figure 14 is a flow diagram showing the various process steps for forming a partially patterned package in accordance with the present invention. Figure 15a is a diagram showing a top, side and bottom view of a package having a perimeter 1/〇 configuration in accordance with the present invention. Figure 15b is a diagram showing a top, side and bottom view of a package having an array configuration of 1/〇塾 in accordance with the present invention. Figure 16 is a view of the metallographic view of Figure 4 in accordance with the present invention, with only the top. The pre-plating on the P surface has been patterned to correspond to two flip-chip locations, where each position includes a wafer attachment area and leads surrounding each wafer attachment area. Figure 17 is a cross-sectional view of the plated metal film of Figure 16 partially patterned to form a mesh lead frame (i.e., a mesh structure) in accordance with the present invention. (4) A cross-sectional view showing a flip chip bonded (FC) bonded wafer-connected lead frame (FCL) according to the present invention. Figure 19 is a cross-sectional view similar to Figure 18 of the present invention in which the top surface of the metal film comprising the wafer has been sealed in a seal. I53285.doc • 75· 201232673 A cross-sectional view, between lines and recessed FIG. 20 is a sealed package of FIG. 19 in accordance with the present invention etched from the back side to selectively remove individual bow wafer attachments The mesh portion between the regions. Figure 21 is a cross-sectional view of a portion of a patterned wafer package having been singulated from the package of Figure 2 in accordance with the present invention. Figure 22a is a top plan view of one of the singulated packages of Figure 21 in accordance with the present invention, the leads of which are connected to the end portions of the leads, which are in turn connected to the next level of package . Figure 2 2b is an enlarged cross-sectional view of a region between a flip chip and a connection showing a lower level package of the two ends of a lead according to the present invention. Figure 23 is a flow diagram showing the various process steps for forming a portion of a patterned package that supports a flip chip in accordance with one embodiment of the present invention. Figures 24a and 24b show two near-wafer-sized partially patterned packages that have been singulated according to the present invention and then provided with a landing point grid array connector for connection to the next level package to form an ELGA type package. A cross-sectional view and a bottom view. Figures 25a and 25b illustrate another alternative embodiment of the present invention that includes bonding a leadframe package wire of the present invention to a lower level package. These figures illustrate the ultrasonic bonding of the packages of Figures 24a and 24b by means of a Ming wire (shown in Figure 25a) or by means of a copper ball bonding technique (not shown in Figure 2 5b). The flip chip package can be attached to the lead frame using copper ball bonding techniques. Figures 26a and 26b are perspective and cross-sectional views of an embodiment of the invention in which a plurality of wafers are stacked to form a semiconductor package. 27a through 27c are perspective and cross-sectional views of an embodiment of the present invention in which the wafer pad is recessed to allow for improved die stacking and package height reduction in Figures 153a and 28b. A perspective view of a lead frame having a recessed wafer pad region and a die stacked wafer in accordance with an embodiment of the present invention is shown. Figures 29a through 29c show perspective views of a lead frame in the form of a wafer pad locking feature in accordance with one aspect of the present invention. Figures 30a through 30d illustrate top and side views of several types of electrical leads with variations in accordance with an embodiment of the present invention. Figures 31a through 31b illustrate top and side views of an electrical lead in accordance with another embodiment of the present invention in which the surface of the leadframe or lead has been roughened. Figures 32a through 32e illustrate perspective views of several types of variations provided on an electrical lead in accordance with another aspect of the present invention. Figure 32f illustrates a top and side elevational view of an electrical lead in accordance with an embodiment of another aspect of the present invention in which the surface of the lead frame has been roughened to provide a modified adhesion of an encapsulant. This surface roughening can be accomplished in conjunction with the variations presented in the present invention. Figure 33a illustrates, in other aspects, an embodiment of the invention in which a clip is used in place of wire bonding to improve the power capacity of the wafer. Figures 34a through 34f illustrate one embodiment of a partially planarized leadframe wherein there is no wafer receiving area and the wafer is placed directly on the leadframe. After the subsequent die attach, wire bond, encapsulation, and pattern (4) steps are completed, portions of the leadframe under the wafer are removed. This elementary step exposes an electrical adhesive (such as an epoxy or a tape) used to adhere the wafer to the leadframe. 153285.doc -77- 201232673 Figure 35 illustrates a bottom view of a wafer size package prepared via the sequences shown in Figures 34a through 34f. Figure 36a provides a cross-sectional view of the wafer size package shown in Figure 34f. Figure 36b provides a cross-sectional view of another embodiment of the present invention in which the wafer size package includes a plurality of die-bonded wire bond wafers. Figure 37a illustrates a leadframe in which both the top and bottom surfaces have been partially patterned prior to attaching any wafer to the leadframe. Figure 371 illustrates the lead frame of Figure 37a, a wafer has been electrically connected to the lead frame and has been encapsulated prior to patterning and singulation of the back side. Figure 38 illustrates one of the wafer-bonded wafers including a plurality of die-stacked wafers in which the bottom of the die has been hatched to provide air venting. Figure 39a illustrates one of the wafers in accordance with one aspect of the present invention. A top view of one of the embodiments of the size package wherein the electrical landing sites are all square in shape and are arranged in two concentric rows around the wafer and the wires connect the wafer. Hai and other electric landing sites. As will be discussed later, in alternative embodiments, the landing points can have any shape such as, but not limited to, elliptical, rectangular or circular. Figure 39b illustrates a top view of one variation of the embodiment of Figure 39a, wherein the electrical landing sites are in the form of lead-in leads and are arranged in two rows around the wafer. The wire connects the wafer to the terminal portion of the lead-in lead that is very close to the wafer. Figure 40a illustrates a cross-sectional view of one embodiment of a wafer size package in accordance with another aspect of the present invention, wherein the wafer has 153285.doc •78-201232673 on the wafer.

周邊周圍配置之焊料點> mB 杆村點之—覆晶，且該晶片電連接至在該 晶片下面延伸之？1線框架上之弓丨入引線。 圖杨圖解說明圖杨中之實施例之一變形之一剖視圓， 其中5亥晶片係具有配置成一陣列圖案之焊料點之一覆晶， 且該晶片連接至在該晶片下面延伸之電引入著陸點。 圖41圖解說明用於使用—無墊引線框架選項製備根據本 發明之-晶片尺寸封裝之步驟，且其中該引線框架上之電 著陸點之形式為引入引線。 圖42圖解說明用於劁+ 一 肝兄月用於氟備具有一電磁干擾（EMI)屏蔽材料 之一晶片尺寸封裝之步驟，其令該引線框架上之電著陸點 之形式為引入引線。 圖43a至解說明❹―區塊模製選項製備麵屏蔽 式晶片尺寸封裝之剖視圖，其令已將一單元陣列囊封於一 單個區塊中。 圖43d至43e圖解說明❹—個別袋式模製選項製備麵 屏蔽式晶片尺寸封裝之剖視圖，其中將每—單元模製於一 模具其自己的空腔中。 圖44a至44c圖解說明製備職屏蔽式晶片尺寸封裝之步 驟之剖視圖，其中在施加屏蔽材料之前首先已單個^該等 單元。 〆 圖45a至45b圖解說明部分敍刻一引線框架之底部以及後 續的將-焊料抗㈣|及電特徵施加至料框架之 視圖。 -叫 < 幻 圖45c至45d圖解說明溢流式钱刻一引線框架之底部以及 153285.doc •79· 201232673 後續的將一焊料抗蝕劑及電特徵施加至引線框架之底部之 剖視圖。 圖46a至46e圖解說明根據本發明而製造之晶片尺寸封裂 之實施例之透視俯視及X射線視圖’其中電著陸點之形式 為引入引線且使用線接合連接至一晶片。 圖47a至47d圖解說明根據本發明使用有墊及無墊實施例 而製造之晶片尺寸封裝之透視俯視圖，其中電著陸點之形 式為引入引線。 圖48a至48b圖解說明根據本發明之晶片尺寸封裝之實施 例之剖視圖’其中晶粒墊係實心的或含有部分金屬通孔。 圖49a及49b分別圖解說明根據本發明之—經囊封ELp引 線框架之俯視圖及剖視圖，且顯示用於所得的屏蔽EMI封 裝之EMI屏蔽之電接地連接。 【主要元件符號說明】 100 金屬條帶 105 搭接物或唇狀物 107 空腔 110 前側 11Γ 底部表面/網狀部分 113 電觸點 113' 引線部分 114， 下侧 115 晶片塾 115， 晶片接收區域 153285.doc . g〇. 201232673 117' 凹入區域 119' 網狀部分 120 預鍍覆層 120' 預鍍覆表面 121 鋁線 123 可焊層/底部特徵 125 底部特徵 130 網式結構 130’ 覆晶 135 網式結構 135' 端子 136 街道形部分 138 區塊/視窗膜 139 網式結構 140 晶片 140' 囊封物 145 端子 145' 外部觸點 150 環氧樹脂 150， 焊料膏 160 線 170 囊封物 300 周邊型封裝 305 周邊配置 -81 · I53285.doc 201232673 320 模製材料 330 背面圖案蝕刻 400 陣列型封裝 405 陣列型配置 410 部分圖案化發明 420 模製材料 430 背面圖案蝕刻 440 内部引線 445 外部引線 450 接地環特徵 460 陣列型輸入/輸出組態 500 引線框架 505 晶片 510 晶片 515 晶片塾 520 内部電引線集 525 最外部引線集 530 囊封物 550 晶片塾區域 555 晶片 560 晶片 565 晶片 570 引線框架 575 外正方形環 153285.doc ,82· 201232673 580 電引線 585 電引線 590 囊封物 600 引線框架 605 晶片塾區域 610 晶片塾區域 615 晶片塾區域 620 晶片塾區域 625 晶片 630 晶片 635 晶片 640 晶片 645 變更 650 囊封物 655 電引線 660 非晶片組件 705 變更 710 變更 715 變更 720 晶片塾區域 725 晶片塾區域 730 晶片塾區域 735 引線 740 引線 I53285.doc -83· 201232673 745 引線 750 引線 755 内表面 760 引線 765 引線 770 表面 775 表面 800 引線框架 805 晶片塾區域 810 畫圓圈部分 815 電引線 820 引線 825 引線 830 引線 835 引線 840 引線 900 晶片塾區域 905 線接合晶片 907 覆晶 910 線接合晶片 915 電引線 917 電引線 920 線 925 史子 153285.doc -84- 930 201232673 935 1000 1005 1010 1015 1020 1025 1030 1035 1040 1045 1050 1070 1100 1105 1110 1115 1120 1125 1130 1135 1205 導電膏或焊料 晶片尺寸封裝 金屬膜 電引線部分 晶片安裝區域 晶粒附接材料或黏合劑 晶片 引線線 囊封物 街道形部分 晶片尺寸封裝 黏著物質 上晶片 晶片尺寸封裝 引線框架 電引線 晶片塾 黏合劑 積體電路晶片 線接合 環氧樹脂囊封物 街道形區 電引線 底部晶粒塾 153285.doc -85- 1210 201232673 1215 黏合劑 1220 下晶片 1225 線接合 1230 囊封物 1240 晶片尺寸封裝 1245 黏合劑 1250 晶片 1255 影線 1300 金屬框架 1305 電著陸點 1307 電著陸點 1308 拐角電著陸點 1309 引入引線 1310 晶片附接區域 1315 黏合劑 1320 晶片 1325 線接合 1330 囊封物 1335 街道形區 1340 晶片尺寸封裝 1360 頂部 1361 有機蚀刻抗敍劑 1362 可焊材料 1365 底部 153285.doc -86- 1375 201232673 1380 1385 1390 1391 1392 非導電塗層 焊料點 電磁干擾（EMI)屏蔽材料 鋸模 鋸帶或承載帶 鋸 153285.doc 87-A solder dot disposed around the periphery > mB pole-top-chip, and the wafer is electrically connected to extend under the wafer? The bow on the 1-line frame breaks into the lead. Figure YANG illustrates a cross-sectional view of one of the variants of the embodiment of Figure YANG, wherein the 5 ray wafer has a flip chip of one of the solder dots arranged in an array pattern, and the wafer is connected to an electric lead-in landing point extending under the wafer . Figure 41 illustrates the steps for fabricating a wafer size package in accordance with the present invention using a padless leadframe option, and wherein the electrical landing point on the leadframe is in the form of an incoming lead. Figure 42 illustrates the steps of a wafer size package for a fluorometer having an electromagnetic interference (EMI) shielding material in the form of a lead-on having an electrical landing point on the lead frame in the form of an incoming lead. Figure 43a illustrates a cross-sectional view of a ❹-block molding option fabrication face shield wafer size package that has encapsulated a cell array in a single block. Figures 43d through 43e illustrate cross-sectional views of a 屏蔽-individual bag molding option preparation face shielded wafer size package in which each cell is molded into its own cavity. Figures 44a through 44c illustrate cross-sectional views of the steps of preparing a shielded wafer size package in which the cells are first individually applied prior to application of the shielding material. 〆 Figures 45a through 45b illustrate a partial view of the bottom of a lead frame and subsequent application of the solder resist (tetra)| and electrical features to the frit. - Illustrated < Magic Figures 45c to 45d illustrate the bottom of the overflow frame engraved with a lead frame and 153285.doc • 79· 201232673 Subsequent cross-sectional view of applying a solder resist and electrical features to the bottom of the lead frame. Figures 46a through 46e illustrate a perspective top view and an X-ray view of an embodiment of wafer size cracking fabricated in accordance with the present invention wherein the electrical landing land is in the form of a lead wire and is connected to a wafer using wire bonding. Figures 47a through 47d illustrate perspective top views of a wafer size package fabricated using a padded and padless embodiment in accordance with the present invention, wherein the electrical landing point is in the form of an incoming lead. Figures 48a through 48b illustrate cross-sectional views of an embodiment of a wafer size package in accordance with the present invention wherein the die pad is solid or contains portions of metal vias. Figures 49a and 49b illustrate top and cross-sectional views, respectively, of an encapsulated ELp lead frame in accordance with the present invention, and showing electrical ground connections for the resulting EMI shielded EMI shield. [Main component symbol description] 100 metal strip 105 lap or lip 107 cavity 110 front side 11 Γ bottom surface / mesh portion 113 electrical contact 113' lead portion 114, lower side 115 wafer 塾 115, wafer receiving area 201232673 117' recessed area 119' mesh portion 120 pre-plated layer 120' pre-plated surface 121 aluminum wire 123 solderable layer / bottom feature 125 bottom feature 130 mesh structure 130' flip chip 135 Mesh Structure 135' Terminal 136 Street Shaped Section 138 Block/Window Film 139 Mesh Structure 140 Wafer 140' Encapsulant 145 Terminal 145' External Contact 150 Epoxy 150, Solder Paste 160 Line 170 Encapsulation 300 Peripheral Package 305 Peripheral Configuration -81 · I53285.doc 201232673 320 Molding Material 330 Back Pattern Etching 400 Array Type Package 405 Array Type Configuration 410 Partial Patterning Invention 420 Molding Material 430 Back Pattern Etching 440 Inner Lead 445 External Lead 450 Ground Ring Feature 460 Array Type Input/Output Configuration 500 Lead Frame 505 Wafer 510 Wafer 515 Wafer 塾 5 20 Internal Electrical Lead Set 525 External External Lead Set 530 Encapsulant 550 Wafer Area 555 Wafer 560 Wafer 565 Wafer 570 Lead Frame 575 Outer Square Ring 153285.doc , 82· 201232673 580 Electrical Lead 585 Electrical Lead 590 Encapsulant 600 Lead Frame 605 Wafer Area 610 Wafer Area 615 Wafer Area 620 Wafer Area 625 Wafer 630 Wafer 635 Wafer 640 Wafer 645 Change 650 Encapsulant 655 Electrical Lead 660 Non-wafer Assembly 705 Change 710 Change 715 Change 720 Wafer Area 725 Wafer塾 Area 730 Wafer 塾 Area 735 Lead 740 Lead I53285.doc -83· 201232673 745 Lead 750 Lead 755 Inner Surface 760 Lead 765 Lead 770 Surface 775 Surface 800 Lead Frame 805 Wafer 塾 Area 810 Circled Section 815 Electrical Lead 820 Lead 825 Lead 830 lead 835 lead 840 lead 900 wafer 塾 area 905 wire bond wafer 907 flip chip 910 wire bond wafer 915 electrical lead 917 electrical lead 920 line 925 history 153285.doc -84- 930 201232673 935 1000 1005 1010 1015 1020 10 25 1030 1035 1040 1045 1050 1070 1100 1105 1110 1115 1120 1125 1130 1135 1205 Conductive paste or solder wafer size package metal film electrical lead part wafer mounting area die attach material or adhesive wafer lead wire encapsulation street-shaped part wafer size Package Adhesive Material Wafer Chip Size Package Lead Frame Electrical Lead Wafer 塾 Adhesive Integrated Circuit Wafer Junction Epoxy Encapsulation Street Shape Electric Lead Bottom Grain 塾153285.doc -85- 1210 201232673 1215 Adhesive 1220 Wafer 1225 Wire Bonding 1230 Encapsulant 1240 Wafer Size Package 1245 Adhesive 1250 Wafer 1255 Hatching 1300 Metal Frame 1305 Electrical Landing Point 1307 Electrical Landing Point 1308 Corner Electrical Landing Point 1309 Leading Lead 1310 Wafer Attachment Area 1315 Adhesive 1320 Wafer 1325 Wire Bonding 1330 Encapsulant 1335 Street Shape 1340 Wafer Size Package 1360 Top 1361 Organic Etch Anti-Symbolizer 1362 Solderable Material 1365 Bottom 153285.doc -86- 1375 201232673 1380 1385 1390 1391 1392 Non-conductive Coating Solder Spot Electromagnetic Interference ( EMI) screen Saw band saw or a molding saw band carrier material 153285.doc 87-

Claims (1)

201232673 七、申請專利範園·· .-種形成電子封裝之方法，該方法包括以下步驟： 形成具有經選擇性地預鑛覆之頂部及底部表面 經㈣引線框架之-區塊，該等引線框架包括網：； 乂、晶片附接區域及引入引線形式之電引線部分，其： 该等電引線部分與該等晶片附接區域電分離，且該等 線框架藉由街道形部分彼此分離； =曰曰片附接至一引線框架之—對應晶片附接區域； 在該晶片之一個或多個端子與該對應引線框架之―個 或多個電引線部分之間形成一個或多個電連接； 藉由將-囊封材料施加於該等51線框架及將該等弓I線 框架分離之該等街道形部分上方而囊封該等引線框架；、 者面圖案化該等引線框架之該底部表面以移除該等網 式部分及該等街道形部分；及 早個化女置於該等街道形部分上方之該囊封材料以形 成個別晶片尺寸封裝。 2. 如項1之方法，其中該晶片附接區域係該引線框架 之曰曰片墊區域或一無墊部分。 3. ^晴求項1之方法，其中該將該晶片附接至該晶片附接 品域之步驟包括將該晶片放置於在缺少一晶片墊之情形 I支撐該晶片之主動引線之頂部上，且使用一非導電黏 合劑或—晶粒附接膜黏合劑黏附該晶片。 Θ求項1之方法’其中該等引入引線在該等引線框架 各別片附接區域周圍配置成一單個列或多個列。 153285.doc 201232673 5. 如請求項丨之方法，其 今/線。 、 步匕括非5丨入引線形式之電 6. 如請求項丨之方法，其 進行該背安 、中使用刀蝕刻或溢流式蝕刻來 仃茨淥面圖案化步驟。 其中藉由區塊模製或個別單元模製 7. 如請求項1之方法 來進行該囊封步驟 其中該晶片墊係實心的或包括 個 8. 如請求項1之方法 或多個熱通孔。 將焊：：1之方法’其進-步包括在單個化之前或之後 二衣、焊料面層或可焊材料黏附至該等晶片尺寸封 裝之一個或多個電著陸點。 兩者^1之方法’其中使用線接合技術、覆晶技術或 組合來完成該形成電連接之步驟。 11.如喷求項1之方法，其中藉由將該晶片上之該等端子連 接至自該引線框架延伸之該等電引線部分之端部分來完 成形成電連接之該步驟。 12 · t °、月求項1之方法’其中藉由一焊料遮罩塗佈引線部 刀、引線框架之該區塊之底部或兩者。 13.如：求们之方法，其進一步包括在單個化之前或之後 將一電磁干擾屏蔽施加至該等晶片尺寸封裝。 14·如請求項13之方法，其中藉由無電鑛覆、電解鍵覆、喷 塗、浸潰、噴濺沈積或一網版印刷製程來施加該電磁干 擾屏蔽。 15·如請求項1之方法’其十使用-導電環氧樹脂、非導電 153285.doc 201232673 環氧樹脂或晶粒附接膜黏合劑來將該等晶片附接至該等 晶片附接區域。 16·如請求項1之方法，其進一 之前將一個或多個第_ 之頂部上。 步包括在囊封料引線框架 晶粒堆叠於-個或多個晶片 153285.doc201232673 VII. Application for a patent garden ··· A method of forming an electronic package, the method comprising the steps of: forming a block having a top and bottom surface selectively pre-mineralized via a (four) lead frame, the leads The frame includes a mesh: a die attach region and an electrical lead portion in the form of a lead wire, wherein: the electrical lead portions are electrically separated from the die attach regions, and the wire frames are separated from each other by a street shaped portion; The cymbal is attached to a lead frame - a corresponding wafer attachment area; one or more electrical connections are formed between one or more terminals of the wafer and one or more electrical lead portions of the corresponding lead frame Encapsulating the lead frames by applying an encapsulating material over the 51-line frames and separating the street-shaped portions of the bow-line frames; and patterning the lead frames A bottom surface to remove the mesh portions and the street shaped portions; and the encapsulating material placed over the street shaped portions to form an individual wafer size package. 2. The method of item 1, wherein the wafer attachment area is a pad area or a padless portion of the lead frame. 3. The method of claim 1, wherein the step of attaching the wafer to the wafer attachment field comprises placing the wafer on top of an active lead supporting the wafer in the absence of a wafer pad, The wafer is adhered using a non-conductive adhesive or a die attach film adhesive. The method of claim 1 wherein the lead wires are arranged in a single column or columns around the attachment regions of the lead frames. 153285.doc 201232673 5. If requested, the current line. Steps include the non-intrusion of the lead wire. 6. If the method of claim 丨 is used, it performs the back-and-forth, using a knife etch or an overflow etch to perform the 图案 渌 face patterning step. Wherein the encapsulation step is performed by block molding or individual unit 7. The method of claim 1 wherein the wafer pad is solid or comprises 8. The method of claim 1 or a plurality of thermal vias . The method of soldering: 1 includes the step of attaching a second coat, a solder finish or a solderable material to one or more electrical landing sites of the wafer size package before or after singulation. The method of both ^' wherein the step of forming an electrical connection is accomplished using a wire bonding technique, a flip chip technique, or a combination. 11. The method of claim 1, wherein the step of forming an electrical connection is accomplished by attaching the terminals on the wafer to end portions of the electrical lead portions extending from the lead frame. 12 t °, method of the first item 1 wherein the lead portion of the lead frame, the bottom portion of the lead frame, or both are coated by a solder mask. 13. The method of claim, further comprising applying an electromagnetic interference shield to the wafer size packages before or after singulation. The method of claim 13, wherein the electromagnetic interference shield is applied by electroless ore coating, electrolytic bonding, spray coating, dipping, sputter deposition or a screen printing process. 15. The method of claim 1 wherein the wafer is attached to the wafer attachment regions by a conductive epoxy, non-conductive 153285.doc 201232673 epoxy or die attach film adhesive. 16. The method of claim 1, which precedes one or more of the tops of the _. The steps are included in the encapsulation lead frame. The die is stacked on one or more wafers. 153285.doc
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