CN102386106A - Partially patterned lead frames and methods of making and using the same in semiconductor packaging - Google Patents

Partially patterned lead frames and methods of making and using the same in semiconductor packaging Download PDF

Info

Publication number
CN102386106A
CN102386106A CN2011102570720A CN201110257072A CN102386106A CN 102386106 A CN102386106 A CN 102386106A CN 2011102570720 A CN2011102570720 A CN 2011102570720A CN 201110257072 A CN201110257072 A CN 201110257072A CN 102386106 A CN102386106 A CN 102386106A
Authority
CN
China
Prior art keywords
chip
lead frame
lead
wire
encapsulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011102570720A
Other languages
Chinese (zh)
Other versions
CN102386106B (en
Inventor
R·S·S·安东尼奥
M·H·麦凯瑞根
A·苏巴吉奥
A·C·托里阿戈
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Interconnect Technology Ltd
Unisem (Mauritius) Holdings Ltd
Original Assignee
Advanced Interconnect Technology Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/875,248 external-priority patent/US20110057298A1/en
Priority claimed from US13/009,362 external-priority patent/US8236612B2/en
Application filed by Advanced Interconnect Technology Ltd filed Critical Advanced Interconnect Technology Ltd
Publication of CN102386106A publication Critical patent/CN102386106A/en
Application granted granted Critical
Publication of CN102386106B publication Critical patent/CN102386106B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

The invention discloses partially patterned lead frames and methods of making and using the same in semiconductor packaging, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Description

Partially patterned lead frame and the method for in semiconductor packages, making and use it
The application is the U.S. Patent application S/N.12/875 that submitted on September 3rd, 2010,248 part continuation application, and U.S. Patent application S/N.12/875,248 is the U.S. Patent application S/N.11/877 that submitted on October 24th, 2007; 732, be US7,790,500 continuation application, U.S. Patent application S/N.11/877 at present; 732 is the U.S. Patent application S/N.11/553 that submitted on October 27th, 2006,664, be US7 at present, and 799,611 part continuation application; U.S. Patent application S/N.11/553,664 is the U.S. Patent application S/N.11/197 that submitted on August 4th, 2005,944, be US7,622 at present; 322 part continuation application, and U.S. Patent application S/N.11/197,944 is the U.S. Patent application S/N.10/916 that submitted on August 10th, 2004,093, be US 7 at present; 129,116 continuation application, and U.S. Patent application S/N.10/916,093 is again the U.S. Patent application S/N.10/134 that submitted on April 29th, 2002; 882, be US 6,812,552 continuation application at present.All these applications completely by reference are incorporated into this.
Technical field
The present invention relates generally to Electronic Packaging, the method that relates in particular to partially patterned lead frame and be used to make and use it.It is firmer and more stable that partially patterned lead frame is compared conventional lead frame.The robustness of partially patterned lead frame has been improved the technology of making leadframe package and the total reliability that strengthens final products.Lead frame also is integrated the functional of high degree of flexibility and increase that provide of device.
Background of invention
In making the Electronic Packaging of using lead frame, there are some processing steps that make lead frame stand machinery and thermal stress.The integrated level of the finer geometry of current lead frame and the further increase of semiconductor core on-chip circuit has caused on lead frame, applying even the processing of bigger stress.The usually similar very exquisite needlework of the lead frame of meticulous configuration, the stencil-like metal structure of perhaps tending to easy bending, break, damage or being out of shape.(referring to Fig. 1 a and 1b).These conventional lead frames comprise the various Chip Packaging that wire-bonded and flip-chip (FC) encapsulate in order to establishment in industry.(referring to Fig. 2 a-2d and 3a-3b).
Conventional lead frame lacks the rigidity of structure usually.The finger type of lead frame part can be very fragile and be difficult to remain on original position.This causes handling defective, damage and distortion in the wire-bonded situation of integrated technique and complicacy.Thereby the lead frame that splice parameters has to be optimized to compensate during joint technology bounces.Splice parameters can't be optimized and relatively poor joint viscosity can be caused with the mechanical instability of compensating lead wire frame, and thereby relatively poor bond quality and reliability.
Usually the big metal plate sections of lead frame is extended from the center that is called the chip housing region, is also referred to as chip bonding pad.Chip is attached to housing region usually, and dorsal part down and the front side be placed with and face up, and terminal peripherally places on the periphery of chip or with array format and places on the surface of chip.Housing region has the size of about 5mm x 5mm usually, and has the thick typical sizes of about 10mm wide x0.2mm of long x 1mm from the outward extending lead-in wire of chip-pad area.Lead frame is compressed by vacuum chuck and mechanical clamp usually.Chuck must be reequiped for the lead frame of different sizes and shape with anchor clamps.The invention solves this problem.
The still not shown any lead frame that tolerates the stress that in current semiconductor packaging process, runs into and can cost-effective mode make of prior art.The present invention realizes this purpose through partially patterned lead frame is provided, and this partially patterned lead frame has not only improved the manufacturability of lead frame self, and improves from the integrated level and the reliability of the Electronic Packaging of its formation.The present invention also solves the device complexity demand that continues to increase that can not provide for conventional lead frame, such as the flexibility in high I/O number, the design of multicore sheet, system in package and the wiring.
The size of computer chip is also dwindled continuing.For the lead frame with specific dimensions, the use of the chip that size continues to diminish makes chip terminal and the wire-bonded that is electrically connected between the dish elongated.Can make to the needs of longer wiring and to shake during being routed in processing, and might make the wafer-level package of particular type be easy to short-circuit.
The length of arrangement wire that increases progressively also influences unit cost.Usually, gold thread is used for computer chip is connected to terminal pad.In fact price of gold has turned over three times in 5 years in the past, and along with die size reduces, the amount of gold thread increases, thereby causes the remarkable price pressure to Chip Packaging manufacturer.Although applying line is the alternative of gold thread, its your 2-3 doubly.
The layout of lead-in wire on lead frame can be regulated sometimes, but the ability of the layout of modification lead-in wire depends on the configuration of lead frame and the production capacity of manufacturer.Fixing lead-in wire position might need the technology in special formation loop when engaging wiring, thereby makes that engaging process is slack-off and do not eliminate the possibility of short-circuit fully.
Some computer encapsulation need radio shielding (RF shielding), disturb it correctly to bring into play function to prevent electromagnetic field when the encapsulation work.The lamination device has this RF shielding usually, but this is very expensive characteristic.There is the electronic device standard (" moisture sensitivity rank ") that can be exposed to the industry acceptance of the time quantum under the indoor conditions to the moisture sensitivity device.The nominal level of many laminate is MSL 3.At MSL 3, assembly must be installed in 168 hours and reflux after from damp proof bag, taking out.
Sawing is usually used in making the lead frame singualtion, thereby forms each wafer-level package, and partly cuts lead frame and expect metal level to expose, thereby is connected to special characteristic, such as EMI (electromagnetic interference) curtain coating.Yet carrying out many wheels with a saw can influence productivity and product recovery rate.When the metal surface that is exposed is generally 5-18 μ m when thick, the high level control of sawing technology is to guaranteeing that correct saw blade height is important.
Summary of the invention
Lead frame is made up of the film with end face and bottom surface.But the first area of film is arrived the bottom surface from end face by the partially patterned film that not exclusively passes.The chip housing region and a plurality of that the second area of film (not from the end face patterning) is formed for supporting integrated circuit (IC) chip is used to be provided to the lead contact of the electrical connection of IC chip.The first area forms groove in film, and produces interconnection not from the web shape structure of the second area of summit portion patterning.The invention still further relates to a kind of method and the Electronic Packaging that adopts these lead frames of lead frame of fabrication portion patterning.Lead frame of the present invention is because its web shape or the web shape architecture advances rigidity of structure.
According to the present invention, photoetching technique or the similar techniques patterning that at first uses standard by its form lead frame metal film end face with draw with the profile of chip housing region with the corresponding zone of lead-in wire.At next step, be etched in drawing in the first area outside the contour area of film and carry out, the thickness that passes lower membrane from the end face of film is to produce the lead frame pattern film.After partially patterned, form second area from the remaining area of end face patterning, it will be as the chip housing region and along the lead-in wire of end face.Recessed web shape zone under the end face of first area formation film.The web shape structure of first area interconnects lead portion and is connected to the chip housing region.Thereby partially patterned film looks and webfoot (webbed foot) is similar and keep its rigidity and intensity, so it can tolerate the stress of follow-up manufacturing technology steps.Especially, partially patterned lead frame can tolerate the stress that during wire-bonded and packaging technology, meets with.In certain embodiments, chip housing region and electrical lead can form (for example, at electrical lead supporting integrated chip and provide under the situation about being electrically connected with it) from the same section of second area.
The present invention also provides a kind of peculiar methods of using partially patterned lead frame to make a plurality of Electronic Packaging.This method relates to the film with end face and bottom surface.In the first area, film is from the summit portion patterning but be not to pass completely through to arrive the bottom.Do not form a plurality of partially patterned lead frames on the film from the residue second area of summit portion patterning.So having a chip housing region that is used to support integrated circuit (IC) chip and a plurality of separately, lead frame is used to provide the electrical lead that is electrically connected with the IC chip.
The first area of film forms the web shape structure of the electrical lead interconnection that makes chip housing region and each lead frame.The first area also interconnects a plurality of lead frames in street (street) part of film.
Be provided with a plurality of chips, each chip has a plurality of electric terminals that are used to be attached to respective leadframe.Each chip is attached to the chip housing region on the respective leadframe and is connected electrically between one of at least one terminal of each chip and electrical lead of lead frame and forms.In addition, the encapsulant street that is applied to lead frame and film is partly gone up the top with complete coverlay.In case encapsulant is dried up, the back Patternized technique is just carried out to remove the street part of web shape structure and film from the bottom surface of film in the first area.Be arranged on the street part of film encapsulant then by singualtion to form each encapsulation.
In a preferred embodiment, this method comprises lead frame is formed the film in the matrix in frame/pattern of windows, and relates to the production of wafer-level package.
Some advantages produce from partially patterned lead frame of the present invention.Smooth and the solid not etched bottom surface of lead frame during wire bonding technique as outstanding heat sink.This provides uniform heat transfer for better with more consistent bond quality.In addition, solid construction provides continuous surface for the universal vacuum chuck compresses lead frame, thereby makes that chip attach technology is more stablized and gone between safer during subsequent process steps.The clumsiness of the outer rim of lead frame clamps to be eliminated to allow array matrix leadframe design and processing and need not to change.Because the bottom side of partially patterned lead frame is smooth continuous surface, the universal vacuum chuck can be used to compress the frame of many different sizes.The complexity of having to reequip vacuum chuck when this removes the lead frame that at every turn in packaging technology, adopts different size.In addition, not to the further demand of clamp.The staggered leads that the use of universal vacuum chuck and the elimination of clamping allow on second area, to construct two row or triplex row is to obtain the lead-in wire of higher number.
The present invention relates to not only to hold the wire-bonded chip but also hold the partially patterned lead frame that welds protruding flip-chip.In addition; Teaching of the present invention a kind of for etched lead frame encapsulation (ELP) that make to use wire-bonded, have the ELP (ELPF) of flip-chip and have the method that bank grid array (LGA) pad uses partially patterned lead frame with the ELP that forms etching bank grid array (ELGA) encapsulation or ELPF, as further said in the various embodiments of the present invention.
Flip-chip (FC) technology is to another step that is attached to next stage encapsulation fully automatically with the electric terminal on the chip, and this next stage encapsulation is pottery or plastic base, or is attached to the chip microcarrier (microcarrier) of substrate after a while.Microcarrier (it only is a bit larger tham chip itself) is called wafer-level package (CSP) now.The FC technology is from being with automation to engage (TAB) development, and TAB develops from wire-bonded (WB).Although be placed on its back side and the terminal that is positioned at around the periphery on its end face be electrically connected in WB and TAB chips, yet be inverted in the orientation of FC technology chips.Chip placed with facing down and the dorsal part of chip up.This flip chip orientation has remarkable advantage, because it concentrates the electric work ability at the downside of chip, stays the top side and when developing the design of heat transfer efficiently, freely uses.
In FC technology, chip terminal or bond pad are with the lip-deep dissimilar projection sealing of chip, and wherein pattern can be arranged to area array, peripheral pattern or other pattern.Chip can be attached to next stage by following mode: a) FC is attached to lead frame; B) FC of layer/substrate attached (being called insert) is used on lead frame again route and connects the space; C) FC is attached to the preparatory attached insert on the lead frame; Perhaps d) uses and comprise that the routine techniques FC of chip remelting method is attached to printed circuit board (PCB).
The chip attach of use routine techniques becomes especially difficult when in the process of making QFN encapsulation and the growth such as VFQPF-N thereof, being applied to QFN (quad flat no-lead (QFN) encapsulation) lead frame.This is because conventional lead frame lacks the rigidity of structure usually.The finger type of lead frame part can be quite fragile and be difficult to remain on an exact position.This causes handling defective, damage and distortion in the chip join situation of packaging technology and complicacy.The PC combined process needs protruding solder heads to aim at fragile the accurate of lead end with the suspension of lead frame.In addition, the scolder end of getting wet must remain on their position after through solder reflow technology.Therefore, the lead frame spring during the remelting parameter must be optimised and combine with compensation chips, this (proper if be untreated) can cause the binding site of difference, thereby and causes the poor quality and the relatively poor reliability of final products.
General custom is to wear pattern through photoresist on pattern metal bar or the metal film and etching to form to go between from the outward extending finger type of chip housing region and form conventional stencil-type lead frame.Also " shunt bar " between the custom use finger (tie-bar) separates so that finger is held during each processing step, shown in Fig. 3 a and 3b.The present invention is through forming web shape, partially patterned lead frame but not the stencil-type lead frame solves the problem that the rigidity of structure of lead frame lacks.
According to a kind of method of the present invention, all main technique steps that form semiconductor packages are carried out from a side that will become lead frame of film.Opposite side (being the bottom side) keeps smooth and does not touch on the surface such as the surface of vacuum chuck.This comprise encapsulation and hermetically the part of sealed package form the step of front side.In case encapsulation is accomplished, just making goes between interconnects and is connected to the web shape part of chip housing region optionally to remove by the back etching in the bottom surface.Therein chip by flip-chip bonded to the chip housing region chip bonding pad and carry out under the ELP situation that is electrically connected with chip terminal through wire-bonded, web shapes part is cut off through etching and makes the moulding material in the front of lead contact through centering on chip, lead-in wire and wire-bonded contact region of chip bonding pad and wire-bonded end isolate each other in the middle of all.Yet, under the situation of ELFP encapsulation, the interconnective web shape of lead-in wire is partly cut off through etching, provide with next stage encapsulates and be electrically connected because be connected to the lead-in wire of chip solder head projection itself.
The removal that embeds the metal of the thick or street of saw in the web shape part has some advantages, comprises the sawing force that elimination is propagated in whole lead frame structure, and therefore, prevents the layering on the metallo-plastic interface.In addition, through the etched electric insulation in back extension test can or be carried out at extension test before any sawing or the singualtion before any further processing step.After the patterning of back, reservation on the bottom surface and exposing metal part can use the weldable material of any number to carry out burr finishing (flash finish) through wicking immersion plating or chemical nickel plating.Yet the PC of ELPF encapsulation is used in the ELGA encapsulation, and the LGA pad is used to be connected to the next stage encapsulation.
For any separation the between other assembly that prevents moulding material and encapsulation during manufacture; The present invention also teaching how on the exposure vertical wall of the recessed web shape part of partially-etched lead frame (such as on the sidewall of lead-in wire) form Lock Part, these parts will contact with the moulding material such as resin.As replacement, also teaching forms " antelabium " on the edge of chip bonding pad and lead contact, so that catch the moulding material under each antelabium, thus make that moulding material is difficult to separate with match surface.
From above obviously visible, partially-etched lead frame provides the consistency of structure and the rigidity of following and intensity to come when making Electronic Packaging, to tolerate well the stress and strain of various manufacturing process.This is because these unique mechanical properties cause, and makes partially-etched leadframe package also can tolerate and be used to be connected to the tight ultrasonic joint that routes to package bottom that next stage encapsulates that this is impossible for conventional Plastic Package up to now.
One aspect of the present invention provides a kind of method that is used to form Electronic Packaging.This method comprises forming to have the partially-etched lead frame that selectivity is electroplated end face and bottom surface in advance.This lead frame comprises web shape part and partly is separated from each other through street.
The first core assembly sheet is attached to the chip-pad area on the lead frame.For simplicity; The zone of supporting integrated chip (IC) or the IC die attach lead frame on it will be called as chip-pad area or chip housing region, no matter this zone is used for wire-bonded chip, flip-chip, or any other type known in the art.These chips of first group can use adhesive, resin, other perhaps compatible with these two assemblies material flip-chip bonded to arrive the chip housing region.For example, flip-chip bonded can use epoxy resin, non-conductive epoxy resin, band or soldering paste to accomplish.Other suitable material is well known in the art.
Second core assembly sheet tube core then is stacked on the top of the corresponding first core assembly sheet.The second core assembly sheet is stacked on the top of the first core assembly sheet by tube core after; One or more other chipsets can be stacked on the top of the second core assembly sheet by tube core, comprise two, three or the encapsulation of more a plurality of chips that is stacked in top of each other thereby provide.In certain embodiments of the present invention, not that all chips in the first core assembly sheet can have the chip that tube core is stacked in their tops.In these embodiment, lead frame will have one or more single (non-closed assembly) chips and one or more groups tube core closed assembly chip.
Each the electrical lead portion of terminal and respective leadframe that is connected electrically in first chip forms between dividing.Electrical lead part and chip-pad area electric insulation.Also form and second or being electrically connected of additional chips group.A plurality of electrical connections can be formed after the tube core closed assembly is to lead frame at chip simultaneously.Alternatively, the first core assembly sheet is attachable and be electrically connected to lead frame, and subsequently second or additional core assembly sheet can be by the tube core closed assembly to the top of the first core assembly sheet and be electrically connected to lead frame.
By the tube core closed assembly to lead frame and after being electrically connected to lead frame, lead frame encapsulates through on lead frame and the street part of separating lead frame, applying encapsulant then at chip.After encapsulation, the bottom rear of lead frame by the back patterning to remove web shape part and street part.The back patterning can be carried out through any facilitated method, such as through etching.
If preparatory plated material is applied to the bottom of lead frame for example as photoresist, then this preparatory plated material can be removed after the patterning of back.
Isolating pattern can form the bottom at lead frame after the patterning of back.These are isolated pattern and can electroplated or apply to protect its surface with material.Suitably the example of material comprise Electroless Plating Ni/soak Au,, soak Sn, organic surface-protective agent (OSP) and other weldable material.This polishing or plating step are convenient to the back side of Chip Packaging additional stability is provided, and tolerable and computer plate, socket or Chip Packaging other position of placing through improved connectivity.
Place encapsulant on the street part by singualtion to form single wafer-level package for the various application that are used for semicon industry.Singualtion can be used any any convenient means completion that can be used for separating each Chip Packaging.In one embodiment, singualtion can be carried out through using saw or abrasion water spray cutting sealing material.
But another aspect of the present invention provides and comprises chip-pad area and lead-in wire and have the alternately lead frame of variant (alternation).Alternately but variant can be regarded as the element on the structure member that is positioned at lead frame, but its with do not have the surface area that increase is provided when alternately the lead frame of variant is compared.But these replace variant and are convenient to be coated on before being retained in singualtion the encapsulant on the lead frame.But these replace variant can be any type of, such as the recess on the electrical lead of lead frame.
Each of the second core assembly sheet can be identical or different with corresponding first die size.In addition, the first core assembly sheet that is attached to lead frame needs not be all identical, thereby these first core assembly sheets can comprise greater or lesser chip.Usually, maximum chip will be attached to the top that chip-pad area and more and more littler chip will be stacked in this chip by tube core.In alternative embodiment, maximum chip will not be attached to chip-pad area, but will be at the centre or the top of tube core closed assembly chip.The big I of tube core closed assembly chip is all identical.
Second group of chip with additional group can use any convenient means closed assembly known in the art and join corresponding first chip to.For example, chip can use non-conductive epoxy resin or the insulating material closed assembly such as band with prevent between the chip or within interference or electromigration moving.In another embodiment, the second core assembly sheet can use band, electroconductive binder or conductive epoxy resin to be attached to corresponding first chip.
The first core assembly sheet uses known technology to be electrically connected to lead frame.For example, chip can use the wire-bonded technology or use flip chip technology (fct) to be connected to lead frame.
The first core assembly sheet can be electrically connected to lead frame before the second core assembly sheet tube core is stacked in first chip.Alternatively, the first core assembly sheet can be connected to lead frame after second group or additional core assembly sheet tube core closed assembly are to the corresponding first core assembly sheet.Forming the step that is electrically connected can realize through the end that each terminal on the chip is connected to the electrical lead that extends to chip area.Electrical connection can use any facility or proper technology to form.For example, be the wire-bonded chip like fruit chip, then connect the wire-bonded technology that can use such as heat sound engages (thermasonic bonding) and form.Flip-chip will use flip chip technology (fct) to be electrically connected to lead frame usually.The combination of wire-bonded and flip chip technology (fct) also within the scope of the invention.When flip-chip directly was attached to lead frame, corresponding lead-in wire can be electroplated or do not electroplated.
The second core assembly sheet received power is calculated or other function to carry out.This second core assembly sheet can be electrically connected to corresponding first chip, lead frame or they both.The join dependency of between each chip and lead frame, setting up is in the contiguous concrete condition and the particular electronic package of formation.
Chip type used in this invention also will depend on concrete environment.For example, chip can be wire-bonded chip, flip-chip, or be applicable to the chip of any other type of electronic chip encapsulation.In one embodiment, the first core assembly sheet comprise flip-chip or wire-bonded chip or they both, and second group and any sheet of core assembly subsequently comprise the wire-bonded chip.What one in the chip also can comprise semiconductor device.
The Electronic Packaging that forms through tube core closed assembly chip according to the present invention will have certain height after encapsulation and singualtion.In order to reduce the height of Electronic Packaging, chip-pad area can be recessed into to reduce the height of the encapsulation that obtained.That is, the chip bonding pad on the lead frame can form to have and reduce innerly, has the chip that reduces height so that make chip can pack in this zone and therefore provide.
The Electronic Packaging that forms according to disclosed method is firm and stable.For the further reliability during being encapsulated in stress state and making is provided, but alternately variant can be used to increase the reservation of encapsulant.Alternately but variant can be along chip bonding pad, lead-in wire or their both periphery settings.
The selectivity of bottom lead frame is electroplated the bottom part that can be used to limit lead frame in advance.The preparatory plating of this selectivity can provide similar pattern in the end face and the lower surface of lead frame.The preparatory plating of selectivity can use any convenient material to accomplish.In one embodiment, NiPdAu or silver alloy are used to preparatory electroplate lead wire frame.
After encapsulation, tube core closed assembly chip will by the sealed solid material around with prevent between chip and the lead frame be electrically connected move or weaken.The closed assembly chip of whole group can be covered by encapsulant.Alternatively, the part of the top layer chip such as the back side or end face can keep exposure after encapsulation.For example, the surperficial penetrable encapsulant of top layer chip and the remainder that embeds the chip in the encapsulant expose.In this way, the amount of encapsulant can be reduced and can acutely not influence the stability of final packaging.In addition, if the end face or the back side of top layer chip comprise identification information, then encapsulation can form this information is not covered by encapsulant and can by user easier check.
As discussed previously, chip and tube core closed assembly chip electricity are attached to lead frame so that to chip electric power is provided.Except the chip such as flip-chip or wire-bonded chip, other element also can be connected to lead frame.These additional elements can be to encapsulation the supporting of increase or the structural detail of stability to be provided.Additional element can also be the electric device of the function of supporting chip or Chip Packaging.The example of these add ons is passive blocks, isolates pad, power ring, ground loop and select wiring.Any of in the Chip Packaging these and other structure or electric device is combined within the scope of the present invention.
Encapsulating material can be the material of any kind, and it can be coated to tube core closed assembly chip or solidify to form curable solid.In one embodiment, encapsulant can be around chip and harden to obtain the liquid resin of chip.The example of encapsulant is an epoxy resin.Encapsulant jumps to another to prevent the signal of telecommunication in the encapsulant from a chip with normally non-conductive material.
When additional element comprised electric device, these elements can be directly to be electrically connected or to be electrically connected to indirectly lead frame.These additional elements also can be electrically connected to the one or more chips in the encapsulation, and these embodiment can be dependent on formed concrete wafer-level package.
Lead frame also can use production technology known in the art to form.For example, lead frame can use chemical etching, punching press or stamping technique to form.
Lead frame can use the film of the material such as electric conducting material to apply or part applies.This film can provide the electricity that increase is provided between lead frame and the chip that is attached to lead frame through amount (comparing with the lead frame that does not have such film).In one embodiment, film is formed by copper or copper alloy.The thickness of film is not crucial usually, and is enough thick in to have mechanical stability although film will be had to.In one embodiment, the thickness of film is more than or equal to about 0.05mm.
Another aspect of the present invention provides the lead frame that comprises chip-pad area and lead-in wire.But the alternately variant that the increase that lead frame has provides the encapsulant that covers lead frame keeps.Chip will be attached to chip-pad area usually and be electrically connected to lead-in wire.
Alternately but variant can be by structural design and is configured to be provided for keeping the increase surface area of encapsulant.Alternately but variant can adopt the form of any kind of the increase reservation that encapsulant is provided.For example, but alternately variant can be the shape of hole, depression or recess, its be positioned on the lead frame or the part of lead frame on.Alternately but variant also can appear on the lead-in wire that is electrically connected that forms with chip.
Alternately but variant can be on any part of lead frame.For example, but alternately variant can be in the periphery of chip-pad area or lead-in wire or they on both.Alternately but variant can also be the form of roughening chip-pad area, lead-in wire or their both peripheries.
But replace the variant except the improvement for encapsulant keeps to provide, the surface of lead frame can be by roughening to provide the surface area of increase.The surface that encapsulant is adhered to lead frame will be convenient in surface through roughening.
Wire clamp can preferably be used for replacing wire-bonded to increase electric power flowing and thereby improve the performance of chip to chip.
In another embodiment of the present invention, a kind of method that is used to form the Electronic Packaging with ultrasonic joint wiring is provided.Form a partially-etched lead frame, have continuous bottom surface comprising web shape part and through the lead frame that street partly is separated from each other.Chip is attached to the chip housing region on the lead frame.The terminal of each chip be electrically connected between the electrical lead portion of respective leadframe is divided.Wiring is joined to the bottom surface of lead frame ultrasonically.Lead frame comprises that through on lead frame the street of isolating lead frame partly upward applies encapsulant and encapsulates.The back patterning of then carrying out the bottom surface removes web shape part and street part.Lead frame through encapsulation is had the wafer-level package that ultrasonic joint connects up by singualtion to form then on the bottom surface on the street part.
One embodiment of the invention provide a kind of method that forms wafer-level package.This method comprises partially-etched lead frame of formation, and this lead frame comprises web shape part, chip installation area territory, a plurality of electrical lead part and street part.IC chip is attached to the chip installation area territory of the first area of film.Be electrically connected then and between the one or more electrical lead portion on one or more terminals on the chip and the lead frame are divided, form.Lead frame is then through applying the encapsulant encapsulation on lead frame and street part.The bottom surface of lead frame then by the back etching removing web shape part, street part and chip mounting portion, thereby the lead frame of the whole or considerable part below IC chip is removed.Place on the street part of film encapsulant then by singualtion to form each wafer-level package.Any number of dies of any kind is attached to partially patterned lead frame.
Lead frame can optionally be electroplated with preparatory plated material in advance, and perhaps they can sheltered on top side, bottom side or the two of mask material at them before the encapsulation.If lead frame is masked, then can there be regulation to the opening on the solder mask of the expectation terminal pad that is used to be connected to printed circuit board (PCB) (PCB).
Lead frame can optionally be electroplated with any facility or conventional substances in advance.The example of these materials comprise the Ni/Pd/Au-strike,, Sn/Pb, lead-free solder, wicking chemical nickel plating, silver (Ag) and Au (gold) strike.
Also available any facility of lead frame or conventional mask material are sheltered, but such as printer's ink, tusche, epoxy resin China ink or organic substance.
Plated material or mask material can be removed such as the bottom from lead frame after the patterning of back at any appropriate time in advance.
Lead frame can be formed by any suitable material known in the art.For example, lead frame can comprise the film of copper or copper alloy or the film of another metal or metal alloy.
As discussed previously, IC chip is attached to the chip installation area territory of lead frame.Chip useful binders or other ability stereognosis known in the art or fixed substance adhere to.For example, adhesive can be resin, epoxy resin, soldering paste, perhaps be with.
Lead frame for example can use the common process through chemical etching, impression or pressure-sizing and so on to form.
Chip can use such as the suitable electrical connection means through wire-bonded and be connected to lead frame.
In a further embodiment, method of the present invention allows in the chip installation area territory a plurality of chips of tube core closed assembly.For example, this method can comprise one or more second chip-die closed assemblies to the top of the IC chip that is attached to lead frame.These second chips can be electrically connected to lead frame, perhaps are attached to the IC chip of lead frame, perhaps they both.The combination of these methods of attachment is possible.Second chip can also be electrically connected each other.
Another aspect of the present invention provides partially patterned lead frame to be used to make Electronic Packaging.
Partially patterned lead frame can be made up of the film with end face and bottom surface.This film can have end face, and it has (a) from the summit portion patterning but not exclusively through the first area of bottom surface, and (b) not from the second area of summit portion patterning.A plurality of electrical leads of chip-pad area that second area can be formed for supporting integrated circuit (IC) chip and the electrical connection that is used to be provided to the IC chip.Chip-pad area can be connected via the first area with a plurality of electrical leads, but does not connect via end face.The bottom surface of film also can be from the bottom surface portions patterning, but not exclusively passes through end face.
The end face of lead frame and bottom surface can any ad hoc fashion patternings.For example, end face and bottom surface can replenish the pattern patterning, so that two surfaces have the characteristic of basically identical on the both sides of lead frame.
The bottom surface of lead frame can be patterned as opening, passage or they both.These openings or passage advantageously allow lateral ventilation hole and lateral ventilation, so during remelting, there is not entrapped air.
The further embodiment of another aspect of the present invention provides a kind of method that is used to form wafer-level package.This method comprises providing to have (a) from the summit portion patterning but not exclusively through the first area of bottom surface and (b) not from the second area of summit portion patterning.Second area forms (a) and is used to support the chip-pad area of integrated circuit (IC) chip and (b) is used to be provided to a plurality of electrical leads of the electrical connection of IC chip.Chip-pad area can be connected via the first area with a plurality of electrical leads, but does not connect through end face.
IC chip is attached to the chip-pad area of the first area of lead frame then.Be electrically connected then and between the one or more electrical lead portion on one or more terminals on the chip and the lead frame are divided, form.Lead frame encapsulates through on lead frame and street part, applying encapsulant then.The bottom surface of lead frame then by the back patterning to remove web shape part and street part.The fraction of the bottom surface of chip-pad area also is removed to form the one or more passages through chip-pad area.These passages advantageously allow lateral ventilation hole and lateral ventilation, so during remelting, there is not entrapped air.Place on the street part of lead frame encapsulant then by singualtion to form each wafer-level package, it is got ready for follow-up use.
The passage of chip-pad area extends on the length of entire chip welding disking area, and perhaps they can extend on the part of chip-pad area.These passages can be the forms of opening (hatching) or other similar structures.
Another aspect of the present invention is provided at the partially patterned lead frame that uses in the manufacturing of Electronic Packaging.Lead frame is made up of the film with end face and bottom surface.This film is from the summit portion patterning, still imperfectly through the bottom.Film is also from the bottom surface portions patterning but be not fully through end face.Patterning on the end face is darker than the patterning on the bottom surface.The gained lead frame has at its top compares the darker patterning in its bottom.Two-sided etching allows the each several part of lead frame to have reduction thickness, and these parts will finally be removed and thereby the processing and the manufacturing of streaming gained Electronic Packaging.
Another aspect of the present invention provides a kind of wafer-level package with the bottom surface that has passage.Wafer-level package comprises the computer chip of one or more warp encapsulation and is used as pore during remelting, to reduce or eliminate the passage of entrapped air.
Characteristic of the present invention provides the remarkable advantage that is superior to prior art.The present invention provides the characteristic such as system in the encapsulation, and increases along with package dimension reduces electricity, heat and I/O.Flexibility of the present invention makes the ELP type encapsulation of novelty can adapt to the requirement that becomes increasingly complex.
Although above-mentioned all embodiment of the present invention provide the improved wafer-level package that has remarkable practicality and be superior to prior art, supplementary features can provide advantage in instantiation.
For example, an embodiment of another aspect of the present invention provides a kind of use to introduce the method that lead-in wire (pull-in lead) forms Electronic Packaging.These introduce lead-in wire make the electrical connection dish can be more near the chip attach zone or even below chip, place, and allow to be electrically connected more easily.
Introduce lead-in wire and has usually than the big surface area of electrical connection dish commonly used, therefore permission has greater flexibility when wire-bonded or upside-down mounting are attached.Introduce lead-in wire and also allow in wire-bonded, to use wiring still less.Because the gold thread that wiring is normally expensive, so suitable cost has been practiced thrift in the minimizing of the amount of these lines, the amount that promptly is used in the metal of lead-in wire or trace slightly increases.
This method comprises: formation has the preparatory end face of electroplating of selectivity and the partially-etched lead frame piece of bottom surface, and these lead frames comprise the electrical connection disc portion of web shape part, chip attach zone and introducing lead-in wire form.Electrical lead part and chip attach zone electrical separation, and lead frame is separated from each other through compartment.The introducing lead-in wire can combine solder resist, China ink or be regarded as essential or desirable any other material of the correct function of lead frame or gained wafer-level package is used.
Chip is attached to the respective chip attachment levels of lead frame, and one or more terminals of chip with form one or more the electrical connection between one or more electrical lead portion of respective leadframe are divided.Come package leadframe through on the compartment of lead frame and separate leadframes, applying the encapsulants material then.The step in chip attach to chip attach zone can randomly be comprised: place active lead-in wire (or opposite chip; Will be in final wafer-level package active lead-in wire) on; Active lead-in wire will be when lacking chip bonding pad supporting chip, and use non-conductive adhesive (such as non-conductive epoxy resin) or attached die film adhesive to paste chip.In this embodiment, electrical connection will form between active lead-in wire and IC chip.
The bottom surface of lead frame then by back side patterning to remove web shape part and compartment; And lead frame places the encapsulants material on the compartment to come singualtion through cutting, to form each wafer-level package.
The chip attach zone of lead frame (be also referred to as chip and hold district or chip installation area) can have any ad hoc structure that is used to hold computer chip.For example, the chip attach zone can be the landless part of chip bonding pad district or lead frame.
Introducing lead-in wire among all embodiment of the present invention can be around the relevant chip attachment levels or near with arbitrarily easily mode arrange.For example, introduce lead-in wire and can around chip, be arranged in single file, perhaps they can be arranged in multirow around the respective chip attachment levels of lead frame.
Electrical lead can also be the combination in any of dissimilar lead-in wires.For example, lead-in wire can be to introduce lead-in wire arbitrarily, and perhaps lead-in wire can be the combination of introducing lead-in wire and electrical connection dish.
The back patterning step can use any convenience or practical method to carry out.For example, the back patterning can use partially-etched or the overflow etching is carried out.Similarly, encapsulation step can use any means easily to carry out, such as molded or individual unit is molded through the piece material.
The chip attach zone of lead frame can have any structure easily.For example, chip attach zone (or arbitrary part of lead frame) can comprise one or more heat through-holes (vertical electrical in the PCB design between the different conductor layer connects).
After singualtion, can before or after singualtion, be adhered to one or more electrical connection dishes of wafer-level package such as the solderable material of soldered ball or weldering lacquer.The solderable material is convenient to being connected of electronic hardware of wafer-level package and circuit board or other type.The solderable material can have any novelty or conventional formation, such as tin, copper, silver, bismuth, indium, zinc and/or antimony.
The IC chip that is attached to lead frame can have any suitable or conventional structure.Dissimilar chips also can be engaged to the different chip attach zone on the identical lead frame.For example, can use wire-bonded chip and flip-chip, and particular leadframe instance can be supported polytype chip and die stacks.Chip can use any suitable means to be attached to the chip attach zone.The example of proper technology comprises uses conductive epoxy resin, non-conductive epoxy resin or attached die film adhesive.
Equally, can use the technology of any suitable type to realize being electrically connected.For example, electrical connection can be used wire-bonded technology, flip chip technology (fct) or its to make up to form.Forming the step that is electrically connected can accomplish through the terminal on the chip being connected to from the electrical lead end partly that lead frame extends, and lead portion can be electroplated or not electroplate.The particular technology that is used for chip is electrically connected to lead frame will depend on the present invention concrete configuration and embodiment during fabrication.
The inventive method applies non-conductive coating to the bottom surface of lead frame after can further being included in the back patterning.This non-conductive coating can be used to protect lead frame not by mechanical wear or consume, therefore can strengthen the durability of gained wafer-level package.The intention of coating is between the PCB installation period, to make active introducing lead-in wire to avoid short circuit.The desired location of electrical connection dish or pad will keep open or expose, so that necessary electrical connection is provided.
In other embodiments of the invention, the inventive method applies the electromagnetic interference (EMI) shielding to wafer-level package before or after can further being included in singualtion.This electromagnetic interference shield is eliminated or the coupling of the non-expectation electromagnetic radiation energy that remarkable at least in part minimizing may occur in electric device.The preparation of prior art wafer-level package generally needs the part cutting of leadframe substrate or lamination to expose the expectation metal level, for the EMI shielding is connected to ground connection.Because the thickness of the metal trace of organic substrate is 5-18 μ m normally, so technology controlling and process is crucial.On the contrary, ELP platform of the present invention is specially adapted to apply the EMI shielding, because it has the technology controlling and process more wide in range than other types of leads frame owing to used thicker lead frame.In addition, ELP platform of the present invention also can be chosen in and use that bag mould is molded avoids partly cutting lead frame during the encapsulation.In this embodiment, the bag mould molding process does not encapsulate whole lead frame, but make a part of lead frame metal exposed and can be used for being connected to EMI shielding so that ground connection.
Electromagnetic interference shield can use any common process to apply, such as chemical plating, metallide, injection, dipping, sputtering sedimentation or silk-screen printing technique.
With reference to the single chip in the chip attach zone that pastes lead frame the present invention has been discussed.In other embodiment in this respect of the present invention, method can be included in the package leadframe a plurality of chips of tube core closed assembly before.For example, a chip can be adhered to the chip attach zone, and second chip can be adhered to the top of first chip.The chip of overlappable any amount is to form wafer-level package of the present invention.Each chip will be electrically connected to another chip or both in lead frame, the lamination.These chips can use that any other technology connects in wire-bonded technology, flip chip technology (fct) or both and this area; And this arrangement will be depended on specific embodiment and configuration during the manufacturing, and any this embodiment can be incorporated on the single lead frame.
The accompanying drawing summary
Fig. 1 a is the diagrammatic sketch according to the conventional lead frame with lead-in wire and chip-pad area of prior art.
Fig. 1 b is the diagrammatic sketch according to the conventional lead frame of Fig. 1 a of prior art, shows terminal and the wire-bonded of lead-in wire on the attached and chip of chip and chip bonding pad.
Fig. 2 a is the sectional view through the approximate wafer-level package (CSP) of wire-bonded and leaded (having lead-in wire) according to prior art, shows through lead-in wire to be connected with next stage encapsulates.
Fig. 2 b be according to prior art through the sectional view of wire-bonded with the approximate CSP that does not have lead-in wire (not having lead-in wire), show through solder projection or soldered ball and be connected with next stage encapsulates.
Fig. 2 c is the sectional view through flip-chip and leaded approximate CSP according to prior art, illustrates through lead-in wire to be connected with next stage encapsulates.
Fig. 2 d be according to prior art through the sectional view of flip-chip with the approximate CSP that does not have lead-in wire, show through soldered ball and be connected with next stage encapsulates.
Fig. 3 a is the vertical view according to the stencil-type lead frame of prior art, shows the flip-chip bonded chip and is connected with the wire-bonded of lead frame lead-in wire.
Fig. 3 b is the vertical view according to the stencil-type lead frame of prior art, shows through the flip-chip bonded chip of solder reflow technology and being connected of lead frame lead-in wire.
But Fig. 4 is the sectional view according to the preparatory electroplated metal film of usefulness grafting material of the present invention uniform thickness on both sides.
Fig. 5 is the sectional view according to the metal film of Fig. 4 of the present invention, and wherein only the preparatory electrodeposited coating on the end face is patterned corresponding to two chip positions, and each position comprises chip bonding pad and around the lead contact of each chip bonding pad.
Fig. 6 is by the sectional view of the electroplating metal film of partially patterned Fig. 4 according to of the present invention.
Fig. 6 a is the vertical view that illustrates according to the matrix of partially patterned lead frame of the present invention.
Fig. 6 b and 6c illustrate the progressively amplification plan view of the lead frame in the matrix shown in the 6a.
Fig. 7 a is the sectional view according to the partially patterned metal film of Fig. 6 of the present invention, and its chips has been attached to the chip bonding pad on each of two chip positions.
Fig. 7 b is according to the chip of the attached thing that comprises epoxy resin or scolder and the enlarged drawing of the junction between the chip bonding pad of illustrating of the present invention.
Fig. 8 is the sectional view according to the chip attach metal film of Fig. 7 a of the present invention or 7b, and wherein the terminal on each chip is by the lead portion of wire-bonded to formed lead frame on each chip position.
Fig. 9 is the sectional view according to the wire-bonded lead frame of Fig. 8 of the present invention, is sealed in the encapsulant comprising the end face and the wire-bonded of the metal film of chip with being sealed.
Figure 10 is the sectional view according to the encapsulation of the airtight sealing of Fig. 9 of the present invention, and this encapsulation is from first area and street film the zone of back side etch to remove each lead frame.
Figure 11 is the sectional view according to the partially patterned encapsulation of two approximate die size of two individual packages of formation of the present invention, wherein encapsulant in the street zone by singualtion.These encapsulation can use aluminum steel, copper cash soldered ball joining technique, or use any other easily joining technique come ultrasonic joint.
Figure 12 a is the vertical view according to one of the singualtion of Figure 11 of the present invention encapsulation, the amplification cross section that it illustrates chip, chip terminal is connected to the contact and the wiring of lead contact and has one of the contact of wire-bonded.
Figure 12 b is the sectional view according to the zone between one of chip bonding pad of the present invention and contact, its illustrate use with vertical surface that moulding material contacts on " antelabium " so that grappling is provided and prevents layering.
Figure 12 c is the sectional view according to the zone between one of chip bonding pad of the present invention and contact, its illustrate use with vertical surface that moulding material contacts on the difformity hole so that grappling is provided and prevents layering.
Figure 13 a-13f is the diagrammatic sketch that can be used to provide for the moulding material on the vertical surface shown in Figure 12 b and the 12c the various holes of grappling means according to of the present invention.
Figure 14 is the flow chart that conclusion according to the present invention forms the various processing steps of partially patterned encapsulation.
Figure 15 a is the diagrammatic sketch that vertical view, end view and upward view with peripheral I/O package configured is shown according to of the present invention.
Figure 15 b is the diagrammatic sketch that vertical view, end view and the upward view of the encapsulation of the array configurations with I/O pad is shown according to of the present invention.
Figure 16 is the sectional view according to the metal film of Fig. 4 of the present invention, and wherein only the preparatory electrodeposited coating on the end face is patterned corresponding to two chip positions, and each position comprises the chip attach zone and around the lead-in wire in each chip attach zone.
Figure 17 is by the sectional view of partially patterned electroplating metal film with Figure 16 of forming web shape lead frame (being web shape structure) according to of the present invention.
Figure 18 is the sectional view that the chips incorporate lead frame (FCL) of flip-chip (FC) combination is shown according to of the present invention.
Figure 19 is the sectional view according to the FCL of Figure 18 of the present invention, is sealed in the encapsulant comprising the end face of the metal film of chip with being sealed.
Figure 20 is the sectional view according to the encapsulation of the airtight sealing of Figure 19 of the present invention, this encapsulation from back side etch optionally to remove between each lead-in wire and web shape part between each recessed chip attach zone.
Figure 21 is from the sectional view of the partially patterned encapsulation of two approximate die size of the encapsulation singualtion of Figure 20 according to of the present invention.
Figure 22 a is the vertical view of one of singualtion encapsulation according to Figure 21 of the present invention, and it illustrates the end that chip and lead-in wire and chip terminal are connected to lead-in wire, and the end of lead-in wire is connected to the encapsulation of next stage again.
Figure 22 b be flip-chip according to the present invention with being connected of next stage encapsulation between the amplification sectional view in zone, show two ends of lead-in wire.
Figure 23 is the flow chart that forms each processing step of the partially patterned encapsulation of supporting flip-chip according to conclusion of the present invention.
Figure 24 a and 24b illustrate according to the sectional view of the partially patterned encapsulation of two approximate die size of the present invention and upward view, and this encapsulation is by singualtion and be provided with then and be used to be connected to the next stage encapsulation to form the bank grid array connector of ELGA type encapsulation.
Figure 25 a and 25b illustrate further optional embodiment of the present invention, and it comprises the wire-bonded of leadframe package of the present invention and next stage encapsulation.These accompanying drawings illustrate the encapsulation of Figure 24 a and 24b and use aluminum steel (shown in Figure 25 a) or use the ultrasonic joint of copper cash soldered ball joining technique (shown in Figure 25 b).Copper cash soldered ball joining technique can be used to Flip-Chip Using is connected to lead frame.
Figure 26 a and 26b are the stereogram and the sectional views of the embodiment of the invention, and wherein a plurality of chip-die closed assemblies are to form semiconductor packages.
Figure 27 a-27c is the stereogram and the sectional view of the embodiment of the invention, and wherein chip bonding pad is recessed to allow the reduction through improved tube core closed assembly and packaging height.
Figure 28 a and 28b illustrate the stereogram according to the lead frame of recessed chip-pad area of having of the embodiment of the invention and tube core closed assembly chip.
But Figure 29 a-29c illustrates the alternately stereogram of the lead frame of variant of the chip bonding pad Lock Part form that has according to an aspect of the present invention.
But Figure 30 a-30d illustrates vertical view and the end view with some types of electrical leads that replace variant of some embodiment according to an aspect of the present invention.Figure 31 a and 31b illustrate the vertical view and the end view of electrical lead according to another embodiment of the present invention, and wherein the surface of lead frame or lead-in wire is by roughening.
But Figure 32 a-32e illustrates the some types of stereograms that replace variant on the electrical lead that are arranged on according to a further aspect in the invention.Figure 32 f illustrates the vertical view and the end view of electrical lead according to a further aspect in the invention, and wherein the surface of lead frame is improved adhesiveness by roughening with the warp that encapsulant is provided.But this surface roughening can be combined into row with the given alternately variant of the present invention.
Figure 33 a-33b illustrates the one side of embodiments of the invention, and wherein wire clamp is used to replace wire-bonded to improve the power capability of chip.
Figure 34 a-34f illustrates the embodiment of partially patterned lead frame, do not exist at this lead frame chips housing region, and chip directly is placed on the lead frame.After, wire-bonded attached in subsequent die, encapsulation and back patterning and the pre-shaping step, the part of lead frame below chip is removed.This pre-shaping step is used for exposure with the non-conductive adhesive (such as epoxide resin material or band) of die attach in lead frame.
Figure 35 illustrates the upward view via the wafer-level package of the preparation of the operation shown in Figure 34 a-34f.
Figure 36 a provides the sectional view of the wafer-level package shown in Figure 34 f.Figure 36 b provides the sectional view of another embodiment of the present invention, and wherein wafer-level package comprises the wire-bonded chip of a plurality of tube core closed assemblies.
Figure 37 a illustrated wherein before any chip is attached to lead frame end face and bottom surface by partially patterned lead frame.Figure 37 b illustrates the lead frame of Figure 37 a that chip is electrically connected with it, and this lead frame is packed before patterning and the singualtion at the back.
Figure 38 illustrates the wafer-level package of the wire-bonded chip that comprises a plurality of tube core closed assemblies, wherein the bottom of pipe core welding disc by opening so that ventilation to be provided.
Figure 39 a illustrates the vertical view of an embodiment of wafer-level package according to an aspect of the present invention, and wherein the electrical connection dish all is square, and around chip, is arranged in two concentric row, and wiring is connected to the electrical connection dish with chip.To describe ground as following, in alternate embodiment, terminal pad can have Any shape, such as but be not limited to ellipse, rectangle or circle.
Figure 39 b illustrates the vertical view of the variant of Figure 39 a embodiment, and wherein the electrical connection dish is the form of introducing lead-in wire, and around chip, is arranged in two row.Wiring is connected to chip the end near chip of introducing lead-in wire.
Figure 40 a illustrates the sectional view of an embodiment of wafer-level package according to a further aspect of the invention, and its chips is that solder joint is arranged in its peripheral flip-chip, and the introducing that extends below at chip that chip is electrically connected on the lead frame goes between.
Figure 40 b illustrates the sectional view of the variant of Figure 40 a embodiment, and its chips is the flip-chip that solder joint is arranged in array pattern, and chip is connected to the electricity introducing terminal pad that extends below at chip.
Figure 41 illustrates and is used to use the linerless lead frame to select the step of preparation according to wafer-level package of the present invention, and wherein the electrical connection dish on the lead frame for introducing the form of lead-in wire.
Figure 42 illustrates the step that is used to prepare the wafer-level package with electromagnetic interference (EMI) shielding material, and wherein the electrical connection dish on the lead frame for introducing the form of lead-in wire.
Figure 43 a-43c illustrates the sectional view that uses the molded selection of piece material to prepare EMI shielding wafer-level package, and wherein cell array is encapsulated in single.
Figure 43 d-43e illustrates the sectional view that uses the molded selection of single bag mould to prepare EMI shielding wafer-level package, and wherein each unit is molded in its oneself die cavity.
Figure 44 a-44c illustrates the sectional view of the step of preparation EMI shielding wafer-level package, wherein each unit singualtion at first before applying shielding material.
Figure 45 a-45b illustrates partially-etched lead frame bottom and with solder resist and the follow-up sectional view that is applied to the lead frame bottom of electrical feature.
Figure 45 c-45d illustrates and floods etched lead frame bottom and with solder resist and the follow-up sectional view that is applied to the lead frame bottom of electrical feature.
Figure 46 a-46e illustrates perspective bottom view and the X ray picture of each embodiment of wafer-level package constructed in accordance, and wherein the electrical connection dish is to introduce the form of lead-in wire and use wire-bonded to be connected to chip.
Figure 47 a-47d illustrates use according to the perspective bottom view that the wafer-level package of liner and linerless embodiment manufacturing is arranged of the present invention, and wherein the electrical connection dish is a form of introducing lead-in wire.
Figure 48 a-48b illustrates the sectional view according to each embodiment of wafer-level package of the present invention, and wherein die pad is solid or comprises the part metals through hole.
Figure 49 a and 49b illustrate vertical view and the sectional view according to encapsulation ELP lead frame of the present invention respectively, and the connection electrical ground of the EMI shielding that is used for the encapsulation of gained EMI shielded is shown.
Describe in detail
Referring now to accompanying drawing the present invention is described, wherein identical Reference numeral indication components identical.Fig. 4-15b illustrates the different embodiment that form the number of leads partially patterned leadframe package suitable with approximate wafer-level package (CSP) with Figure 16-24b.The q&r of the automation of method improvement production line of the present invention and the encapsulation of therefrom making.This major part and partially patterned metal film through carrying out manufacturing technology steps forms netted lead frame in a side and realizes.With the stencil-like lead frame contrast of conventional break-through, lead frame used in this invention in a side by partially patterned and be solid and smooth on opposite side.This structure improves through machinery and thermodynamics means, and during chip attach, wire-bonded and packaging technology, does not have distortion or shifting ground to carry out.Lower surface can by mask in addition or otherwise mark to draw the most at last the profile in the zone of removing through the back etching.Chip attach and the completion of wire bonding technique step and chip and wire-bonded is attached and be encapsulated in the moulding material hermetically after; Lower surface is worn film by etching partly in the zone of not sheltered by the preparatory electrodeposited coating of the selectivity of lower surface, so that lead contact is isolated with chip bonding pad and isolation each other.Subsequently, gained need not to cut any additional metal through the encapsulation of encapsulation by singualtion.
More specifically, Fig. 4-15b illustrates the formation of the partially patterned lead frame that is used for the wire-bonded chip and uses it to form the method for ELP type Electronic Packaging.On the other hand, Figure 16-22 illustrates with the formation of the partially patterned lead frame of flip-chip and uses it to form the method for ELPF type Electronic Packaging.The method that the partially patterned lead frame of a kind of the present invention of use forms ELGA type Electronic Packaging also combines Figure 24 a and 24b to describe.
Fig. 4 is the sectional view that is preferably the film of metal (being preferably copper) sheet, and this film not only forms lead frame, and during guaranteeing to form the processing step of lead frame as stable carrier.The thickness of bonding jumper is equal to or greater than about 0.05mm.In another embodiment, this thickness can be about 0.05 in the scope of 0.5mm.
Form lead frame and be usually directed to cut and wear bonding jumper, similar cutting board, and then the finger type lead-in wire of very thin is worked.Put in place for very thin like this structure is compressed, can use vacuum chuck.Yet conventional vacuum chuck is inappropriate for usually to very thin like this device provides suction and lead frame and must clamps in the periphery usually.Any rigging that is used for this purpose must be reequiped to another kind from a kind of lead frame of type and size.Yet the present invention has eliminated this repacking step.Because the lower surface of partially patterned lead frame is solid and continuous, so conventional vacuum chuck can easily keep this lead frame to put in place during processing.The bonding jumper that in addition, can adapt to a kind of size of various industrial lead frames can generally be used for the manufacturing of lead frame.The subsequent process steps of chip attach and wire-bonded can be accomplished under the situation that has much little stress and strain to form on the lead frame.Lead frame with much very thin geometry can easily be made, because lead-in wire is bonded to together through web shape structure and does not separate up to final step each other.
On lead frame, forming various patterns can accomplish in every way.A kind of method can be with pattern impression/pressure-sizing to metal.Other method can comprise chemistry or electrochemical milling and edm (EDM).On the other hand, preferred lithographic patterning, it is the pillar that semiconductor is made.In the present invention, the bonding jumper shown in Fig. 4 (100) is electroplated in preceding (or on) side and the back of the body (or down) side before the lithographic patterning in advance.One of front and back or both can use the material that can engage and can weld to electroplate in advance respectively.In one embodiment, but the front use such as the Ni/Pd/Au strike or silver grafting material electroplate in advance.In another embodiment, the back side is used and is electroplated in advance such as Sn/Pb, lead-free solder, wicking chemical nickel plating or au base plate coating.In another embodiment, the back side is used with the top side identical materials and is electroplated in advance, and it can play the etchant resist effect then during the patterning of back.This etchant resist class electrodeposited coating can be peelled off before final finishing after a while.Plating can carried out (if desired like this) after a while in the step in advance.
At next step, the front side (110) of electroplating in advance by lithographic patterning to form corresponding to chip bonding pad (115) with around the zone of the electric contact (113) of chip-pad area.Electric contact (113) can be characterized by the end of lead-in wire, and lead-in wire is connected to chip-pad area (115) through the first area of the middle recessed portion of formation web shape structure.The etched time after a while is removed web shape part recessed in the middle of these from the back at metal film (100), so that end and chip bonding pad part are isolated each other.Comprise chip bonding pad (115) and on every side the zone of contact (113) be sometimes referred to as chip position (chip site).A plurality of chip positions can be on the continuous volume copper sheet to bobbin, forming, so that comprise the formation automation easily of the lead frame of one or more chip positions.Fig. 5 illustrates two chip positions, and it will form two corresponding lead frames, and these lead frames will be again the parts with two encapsulation that formed by it.
For the pattern shown in two chip positions shown in Fig. 5 arrives film bar (100) through etch transfer then.As shown in Figure 6, principal character of the present invention is the only partly thickness of penetrating metal execution of etching, and this is called partially patterned at this.The partially patterned web shape structure (130) that the chip bonding pad (115) of the lead contact (113) of each lead frame is connected with formation of in the first area of film, carrying out.This first area also makes lead frame interconnect in the street part (street portion) (136) of film.
Shown in Fig. 6 a-c, matrix or these lead frames (for example, 16x 16) can form in frame/window film (138).Fig. 6 b and 6c illustrate the web shape structure (139) that the first area comprises that the chip bonding pad that makes each lead frame is connected with lead contact.The first area also interconnects a plurality of lead frames in the street part (136) of film.
In one embodiment, partially patternedly can change to 90% from 25% of film thickness.Yet in fact partially patterned can be the film thickness of any percentage, and partially-etched amount can confirm that these factors comprise flexibility, rigidity and hot thickness (or thermal conductivity) through considering the various factors that influences manufacturability parameters.The lateral dimension of lead contact zone (113) and chip-pad area (115) can be connected the degree decision of the required miniaturization of medium based on given die size with wire-bonded or other, connection in inter-stage between wire-bonded or other encapsulation that connection medium can be used in the given encapsulation or next stage encapsulates or the level.Especially it should be noted that and rely on the web shape structure that refers to the type lead-in wire to become more inessential now the very thin parts of lead frame and the manufacturability factor of dimensional stability.
As shown in Figure 7, chip (140) then uses any convenient means such as epoxy resin (150) to be attached to chip-pad area.Chip and the junction basis that illustrates between the attached chip bonding pad the present invention includes epoxy resin or scolder.Epoxy resin (150) can be filled with conductive particle to strengthen the cooling of chip.As replacement, replace the soldering paste (150 ') of epoxy resin (150) also to can be used to provide firmer between chip and the chip bonding pad to engage and to the more effective cooling path of surrounding environment.Epoxy resin is cured and is as shown in Figure 8, and after chip attach, line (160) uses known wire-bonded technology to join terminal (145) and corresponding lead contact (113) to, and is as shown in Figure 8.Because lead frame formed according to the present invention has firm fixing and such as solid, the continuous dorsal part that is compressed by the vacuum chuck (not shown) in the plane, so swing or the spring during wire-bonded of the web shape structure of lead-in wire.This causes outstanding joint, and this improves the reliability of final products.Though dorsal part is solid and continuous, it still can have the designator that will where carry out about the back etching.For example, dorsal part can have other designator of a part on the surface that maybe can be film of breaking, and perhaps dorsal part can use preparatory plated material (120) to shelter to draw by the profile of the etched presumptive area in back.For example, in advance plated material (120) can will be retained during the etching after a while and zone under zone (130) and (136) will be removed in masked appropriate section with the indication lead frame under the zone (113).
In Fig. 9, after making chip and corresponding contacts is connected, all component on the front side of metal film for example is sealed through resin then and is encapsulated in the moulding material.Encapsulant (170) partly forms on all exposed surfaces of (136) with comprising line (160) that lead frame is associated with them, chip (140) and contact (113) and web shape structure (130) and street at film.When the gained molded package was picked up, clean dorsal part can supply further processing now.What run into usually uses this disclosed method to eliminate to molded burr (mold flashing) problem that encapsulates the overlay area on the downside.Clean dorsal part can be electroplated with being convenient to following process or etched material in advance.
Shown in figure 10, lead contact (113) and chip bonding pad (115) can penetrate the encapsulation dorsal part through the web shape structure (135) of etching first area now easily to isolate the island that forms them each other.At this moment, street part (136) is also by the back etching.But the preparatory electrodeposited coating (120) of the material use such as printer's ink or the organic material can be used as mask or etchant resist to form required bottom part (123,125).In other embodiments, organic material can be used to replace metal or weldable material as etching mask.Organic material can be printed or be coated on the lead frame in any convenient step before the etching at the back.
The back etching continues up to arriving moulding material.Be used for the back etching metal engraving method can be used for the different of front side.According to the partially-etched degree of carrying out from the front side, be used for dorsal part etching period can be used for the different of front side.Thereby the initial formation of partially-etched lead frame can be automation, quality, reliability and functional manufacturing demand with suitable final packaging of customization.Playing the preparatory electrodeposited coating (120) of the bottom of chemical etchant resist effect can be peelled off with exposing metal bar (100).
For protective material and be convenient to be installed to printed circuit board (PCB), can be electroplated onto bonding jumper (100) such as Electroless Plating Ni/soak Au, the weldable material or other the such material that soak the Sn.Think that any preparatory electrodeposited coating can keep or peel off when being fit to specific environment.
As final step, the encapsulant (170) on street between the lead frame part (136) by singualtion to form two encapsulation separately shown in figure 11.This realizes by multiple mode, comprises sawing sheet, water spray cutting, laser cutting or its combination, other technology that perhaps is specially adapted to cut plastics.In other words, the layering or the other problem that no longer cut metal and therefore be not associated with the combination of cutting plastics and metal.This and wherein the bridge joint metal between the street must make comparisons in the routine encapsulation that encapsulation be cut in by singualtion.Repeatedly, when while cutting metal and plastics, the part in the metal chip can be short circuit line and contact, thereby causes non-expectation and unpredictable loss on the saw blade.Shown in Fig. 6 a, the method also can be applicable to by a large amount of encapsulation of leadframe matrix manufacturing.
See through sectional top view that the encapsulant of singualtion ELP overlooks shown in Figure 12 a.Figure 12 b shows the enlarged drawing in the corner between one of chip and contact of encapsulation, said corner comprise original metal bar (100) but a part, in advance electroplate to form knitting layer (113) but end face and electroplate bottom surface in advance with formation layer (123).In Figure 12 b, " antelabium " illustrates on the corner of contact and chip.Contact (113) and chip (140) are shown on their island each other isolates, but only interconnects through the line of wire-bonded (160).
Welding preparatory plate surface (120) and then can be used for some purposes now on the downside of encapsulation as unstripped.The first, for cooling additional hot path is provided to the direct external path at the back (125) of chip bonding pad (140).The second, the contact (123) in the area coverage of approximate wafer-level package (CSP) makes the encapsulation that possibly in the next stage encapsulation, tight spacing is installed, and therefore promotes the performance of the same area.
Another aspect of the present invention provides a kind of method that reduces the possibility of the layering between moulding material and its attached surface.This accomplishes such as flange or " antelabium " of the Reference numeral among Figure 12 b (105) indication to form through etching partially chip bonding pad and contact region edge on every side.Also possibly form erose hole (107) shown in Figure 12 to strengthen the interlocking mechanism on the surface that contacts with moulding material.The enlarged drawing in various other holes also illustrates at Figure 13 a-13f, and the formation that strengthen of these surfaces can be readily incorporated partially-etched from the front side.This is for dispensable from back side etch, because moulding material only encapsulates the surface that forms from front part ground.
Figure 14 reduces method of the present invention with lead frame and is etched into that (200) bonding jumper begins and forms required chip bonding pad and the same bonding jumper end of mode back pattern etched (250) of contact on every side to use from front part.The intermediate steps of chip attach (210), epoxy resin cure (220), wire-bonded (230) and encapsulation (240) all mechanically with on the thermodynamics realizes on the stable lead frame because lead-in wire still through the partially-etched web shape in the metal film or web shape structural in the middle of the first area of recessed portion connect.Also importantly should be noted that; Only after all component of encapsulation had been protected in the encapsulant, the first area of middle recessed portion was removed through back pattern etching (250) and makes peripheral contact and chip bonding pad be separated from each other for suitable isolation.Before final step, can carry out and peel off preparatory electrodeposited coating (120) and apply weldable material.Therefore, need, singualtion (260) not cut any metal during becoming single approximate wafer-level package.
Method of the present invention can be used for forming various encapsulation, such as the array type lead frame that is used for Electronic Packaging.The vertical view of array type encapsulation (400) is regarded as adjacent with the standard peripheral type package (300) shown in Figure 15 a in Figure 15 b.Though Reference numeral (305) refers to the chip terminal of peripheral arrangement, Reference numeral (405) refers to the terminal of array type arrangement that can be coaxial or interconnected.The disclosed partially patterned invention of using as being indicated by Reference numeral (310) and (410) forms this two kinds of encapsulation.In array type ELP, lead (440) and outer lead (445) are illustrated.These two kinds of encapsulation are encapsulated in moulding material (320) or (420).The back pattern etched is indicated by (330) and (430) with spacing contact and chip.Reference numeral (450) is described the ground loop parts, and it is etched to the level identical with mould.Reference numeral (460) refers to the array type I/O configuration on the vertical view of ELP.
Second embodiment shown in the accompanying drawing 16-24b discloses a kind of method that forms partially patterned VFQFP-N type lead frame, and this method is particularly useful for the FC Electronic Packaging of large-scale production.Make the lead frame that holds flip-chip and will be called as FCL hereinafter so that it and conventional lead frame are differentiated.This is because different with conventional lead frame, FCL is firmer and be more suitable for automatic production line, like the following stated.
FCL also is a web shape structure, and break-through, the stencil-type lead frame general with routine are opposite.The front side of web shape FCL has the recessed portion that comprises partially patterned lead-in wire, and dorsal part is solid and smooth.This provides mechanical stiffness to come not distortion or shifting ground to carry out during manufacturing process.After the chip attach of accomplishing encapsulation and airtight sealing, dorsal part is etched so that lead contact is isolated each other.Remove preparatory electrodeposited coating, or use other weldable material to electroplate again can or to immerse technology and accomplish through chemical plating.Subsequently, gained need not to cut any additional metal through the encapsulation of encapsulation by singualtion.Thereby, can easily make such as FCL it is obvious that, because lead-in wire is maintained at together through web shape or web shape structure and not exclusively separates up to final singualtion step each other with more very thin geometry with VFQFP-N encapsulation.
The similar partially patterned lead frame that discloses first embodiment, the FCL of second embodiment are also formed by sheet metal, preferred copper film as shown in Figure 4, and wherein front and back is by plating in advance, and plating perhaps as discussed previously can be put off to step after a while.(note, because the processing step of these two embodiment is similarly, so that Reference numeral remains as required is identical, except indicate those marks of second embodiment with prime number.Identical Reference numeral (100) has been kept for the metal film of these two embodiment from consistency.Then, electroplate in advance front side (110 ') by lithographic patterning with form chip housing region (115 '), around lead portion (113 ') and other zone line (117 ') of chip housing region.In the subsequent process steps of following discloses, an end of lead-in wire will be connected to the terminal of PC, and another end will be connected to the next stage encapsulation.Similar with chip position with wire-bonded chip, comprise that chip housing region and the zone that goes between are sometimes referred to as chip position on every side.The a plurality of lead frames that comprise a plurality of chip positions can be forming around rolling up on the copper sheet continuously to one of bobbin, easily to make the formation automation of the lead frame that comprises one or more chip positions.Figure 16 illustrates two chip positions, and it will form two corresponding lead frames, and these lead frames will be again the parts with two encapsulation that formed by it.
The pattern of two chip positions shown in Figure 16 is then through via the etched partially patterned metal film (100) of transferring to.Partially patterned shown in Figure 17 can be the most nearly 1/2nd, 1/4th; Any ratio that perhaps can be up to the thickness of bonding jumper; And partially-etched amount can confirm that the execution factor comprises flexibility, rigidity and hot thickness (or thermal conductivity) through considering the various factors that influences manufacturability parameters.The lateral dimension of lead contact zone (113 ') and chip area (115 ') can confirm based on the required degree of miniaturization of given chip position, comprise die size and be used in the given encapsulation or inter-stage between the encapsulation of next stage encapsulation or level in the lead-in wire of connection.Especially it should be noted that and rely on the web shape structure of finger type lead-in wire to become more inessential now the very thin parts of lead frame and the manufacturability factor of dimensional stability.
Flip-chip (FC) (130 ') is then by upside-down mounting, so that the terminal (135 ') on the chip front side rests on the end of lead-in wire shown in figure 18.In step after a while, the end opposite of lead-in wire will be formed the electric contact of the next stage encapsulation that is used to be connected to such as card or plate.Yet at first, the chip that is assembled on the web shape lead frame structure shown in figure 18 transmits through the chips incorporate stove like practice in the art.The soldered ball remelting is so that remelting is limited by BLM, thus the formation welding column.Because lead frame formed according to the present invention has robust sealed and compresses solid, continuous dorsal part in the plane, thus not swing or the spring around the chips incorporate stove of the web shape structure of lead-in wire, thus obtain outstanding chips incorporate.As a result, disclosed method improvement the reliability of final products, i.e. the reliability of VFQFP-N type encapsulation.
After chips incorporate, chip for example is sealed through resin then with the partially patterned lead-in wire on the front side of original metal film and is encapsulated in the moulding material, and is shown in figure 19.Encapsulant (140 ') is formed on around all exposed surfaces; All exposed surfaces comprise lead-in wire (113 '), soldered ball (135 ') is on every side, below the chip, along the exposed surface of the vertical wall of recessed chip housing region (115 '); And the exposed surface of the vertical wall in recessed zone (117 '), except the firm not etching that compresses bonding jumper (100) in the plane, solid and smooth dorsal part.When the gained molded package was picked up, clean dorsal part can supply further processing now.Usually the molded Burr Problem of overlay area to the downside of encapsulation that runs into also is eliminated in this embodiment.
Lead-in wire (113 ') now can be easily through with when technology begins, aims at the dorsal part that the ground patterning passes encapsulation and comes isolation each other from the etched pattern of front part.The back etching continues up to arriving moulding material.This is shown in Figure 20, the web shape part of lead frame wherein, and promptly zone (111 ') and (119 ') is removed so that chip area (115 ') breaks off each other, and lead-in wire (113 ') disconnection each other.Be used for the engraving method of back pattern metal can or can be not be used for from the front part etching method identical.In addition, according to the partially-etched degree of carrying out from the front side, from time of back side etch can be used for the different of front side.Thereby the initial formation of partially-etched lead frame can be automation, quality, reliability and functional manufacturing demand with suitable final packaging of customization.Playing the preparatory electrodeposited coating (120) of the bottom of chemical etchant resist effect can be peelled off with exposing metal bar (100).For protective material and be convenient to be installed to printed circuit board (PCB), can be electroplated onto bonding jumper (100) such as Electroless Plating Ni/soak Au, the weldable material or other material that soak the Sn.
As final step, for the present invention is described, the encapsulation with Figure 20 of two packaged chip positions is then changed into single approximate wafer-level package (CSP) by monolithic, and they are mostly to be the encapsulation of VFQFP-N type, shown in figure 21.The vertical view of singualtion patterning leadframe package is shown in Figure 22 a, and wherein lead-in wire (113 ') is illustrated as mutual isolation and is connected to the soldered ball (135 ') on the downside of chip (130 ').Figure 22 b illustrate encapsulation at chip and be connected to the enlarged drawing in the corner between one of the lead-in wire that can be arranged on the external contact (145 ') on card or the plate (150 ').Plate surface (120 ') has been prepared into the contact that is attached to like same next stage shown in the drawings in advance.As think at this moment and be fit to or when catering to the need, electroplate in advance or mask can be held or remove.Electroplate in advance or mask also can be in technology other the time be removed, thereby be suitable for various environment.In addition, the downside (114 ') of lead-in wire (113 ') is exposed to surrounding environment, thereby the cooling of enhancing is provided.In some cases, coating can be applied to downside (114) between the plate installation period, to reduce the possibility of potential short circuit, especially for fine pitch applications.
Like the former disclosed constructed erose hole that can be used to through combination Figure 13 a-13f on the vertical wall of the recessed zone (115 ') of web shape lead frame and (117 '), prevent the skin lamination of encapsulant from FCL.Formation that these surfaces strengthen can be readily incorporated partially-etched from the front side.This will be for being unnecessary from back side etch, because moulding material only encapsulates the surface that forms from front part.
Figure 23 reduces the method for present embodiment and is etched into from front part with lead frame that (200 ') bonding jumper begins and form required chip housing region and the same bonding jumper of mode back patterning (the 240 ') end of lead-in wire on every side to use.The intermediate steps that FC places (210 '), FC chips incorporate (220 ') and encapsulation (230 ') all mechanically with thermodynamics on stable FCL go up and realize because lead-in wire still connects through the partially-etched web shape structure in the metal film.Only it is noted that importantly also that after all component of encapsulation has been protected in the encapsulant the web shape of lead-in wire is partly optionally removed and made to go between through back pattern etched (240 ') and is separated from each other for suitable isolation.Therefore, need, singualtion (250 ') not cut any metal during becoming single approximate wafer-level package.
Be similar to the method for the peripheral group of disclosed in this article use solder projection; Method of the present invention can be used to form various encapsulation; Such as a plurality of partially patterned lead frame of array type, wherein the area array of solder projection simultaneously chips incorporate to the lead frame that flip-chip is arranged.In addition, the array of partially patterned lead frame itself can form simultaneously, and FC combination simultaneously then, and array is changed into the VFQFP-N type encapsulation of a plurality of separation by monolithic subsequently.In addition, each gained CSP can be provided with then and under encapsulation, be used for solder projection, pad or other electricity that array type is attached to next stage encapsulation and connect to form etched lead frame encapsulation with bank grid array or the encapsulation of ELGA type shown in Figure 24 a and 24b.At Figure 24 a, chip bonding pad (135 ') is shown goes up the viewgraph of cross-section that forms at lead-in wire (145 ').After the patterning of back, lead-in wire (145 ') electricity is each other isolated to be attached to the next stage encapsulation.The bottom surface (145 ') that is exposed can be electroplated the weldable material that uses any number through wicking dipping or chemical nickel plating and come the burr finishing.The bottom surface (111 ') of ELGA encapsulation with the array pattern (145 ') that is used to be electrically connected is shown in Figure 24 b.
Solder projection can be the form of the metal column projection such as copper post projection, and wherein each projection is by about 75 microns high, and has scolder (or unleaded) cap and cause the Cu shaft of about 100 microns total heights to constitute.When using copper post projection, " solder projection " can be " solder caps ".The use of copper post gives between chip surface UBM and the plate contact gap greater than 50 microns, and the plastic seal material is freely flowed and covers the crack below the flip-chip.
Any one partially-etched method provides robustness in ELP, ELPF or the ELGA encapsulation during each manufacturing step because form, so other form electronic encapsulation also is possible.A kind of such form comprises the wire-bonded of leadframe package of the present invention to the next stage encapsulation.Because the ultrasonic joining technique of the fragility of lead-in wire itself can not be used for conventional lead frame, only if they are attached to solid substrate so that stability and intensity to be provided.On the contrary, partially-etched their web shape structure of lead frame dependence is stable.The not etching of partially patterned lead frame with electroplate in advance bottom surface (120 ') solid engaging zones or post be provided, effectively ultrasonic energy is used for the piece of ELP or ELPF or the aluminum steel wedge joint on the bar closes.Therefore, according to a further aspect in the invention, aluminum steel (121) is the ultrasonic bottom surface that is attached to one or the partially-etched lead frame of bar shown in Figure 25 a.The linear diameter scope is between about 0.001 inch to 0.020 inch, and back one diameter is represented band (ribbon) but not line.Bar is packed then, back patterning and singualtion to be to form each approximate CSP.Ultrasonic joint is desirable, because it avoids being exposed to the ball bonding junction temperature by solder ball grid array type encapsulation experience, therefore improved reliability is arranged.Shown in Figure 25 b, also can use the copper cash ball bonding and engage.To understand, the CSP shown in Figure 25 a and the 25b can be any one among ELP and the ELPF.
The present invention facilitates a plurality of attendant advantages in the Electronic Packaging manufacturing process.For example, after the etching of back and before the singualtion, package blocks will be inherently extension test and get ready and encapsulate and still be arranged in piece.This with encapsulation process is become each unit compare remarkable advantage is provided.The reliability of their retrofit testings of extension test when encapsulation is arranged in piece.
The present invention can also make manufacturer produce the encapsulation of two or triplex row staggered leads of the I/O capacity with the given encapsulation of can doubling.The smooth continuous bottom surface of lead frame can be used general mounting equipment, and it need not use repacking to each, and it is fully flexibly to automation.For example, in the processing of 2x2 between the 12x12 package blocks without any need for mechanically variation.In addition, the present invention easily promotes each pin is had the structure (between the bottom of the surperficial molding of pin, being 2 mils for example) of the encapsulation in " gap ".When Chip Packaging was connected to the next stage encapsulation such as plate, this gap provided additional advantage.
Figure 26 a and 26b illustrate the embodiment of one side of the present invention, and wherein two chips (505,510) tube core is stacked on the chip bonding pad (515) of lead frame (500).Following chip (505) (promptly being attached to the chip of chip bonding pad housing region (515)) is electrically connected to interior group of (520) electrical lead around chip-pad area (515).Last chip (510) (promptly being attached to down the chip at the top of chip (505)) is electrically connected to outermost group (525) lead-in wire around chip bonding pad area (515).Chip is with encapsulant (530) encapsulation, and its protection chip and line are with antisitic defect.Though the chip among Figure 26 a and the 26b (505,510) is the wire-bonded chip, and is consistent with the present invention, one or more in the chip can also be flip-chips.Following tube core closed assembly chip (505) is dimensionally greater than last chip (510).Though following chip and last chip are not electrically connected in diagram each other, in certain embodiments, these chips can for example be electrically connected through the line from a chip to another.Forming the step that is electrically connected can be connected to through the terminal with various chips from the end realization of the electrical lead of lead frame extension.
Figure 27 a-27c illustrates embodiments of the invention, and wherein chip-pad area (550) is recessed to allow the reduction of improved tube core closed assembly and packaging height.In Figure 27 a-27c, three chips (555,560,565) tube core closed assembly is to form Chip Packaging.As can be from Figure 27 a finding, the inside of chip-pad area (550) has been removed and has made to have only foursquare outer shroud.Chip (555) is placed into and is attached to this chip-pad area.Though three tube core closed assembly chips (555,560,565) have been shown in Figure 27 a-27c, consistent with the present invention, the tube core closed assembly chip of any number can be arranged.In Figure 27 a, the inside of recessed chip-pad area (550) is illustrated as the end face of lead frame.That is, only the outer square loop (575) of chip-pad area has been deposited over the top of lead frame, and the whole inside (550) of chip-pad area is not deposited or removes from lead frame.In an alternate embodiment of the invention, thin-material layers is deposited over the inside of chip-pad area or the part of chip bonding pad interior zone is removed.In these embodiment, the inside of chip-pad area will be higher than leadframe pad, but still be lower than the outside of chip-pad area, thereby recessed chip-pad area will be provided for chip attached.
Though in Figure 27 a-27c, maximum chip (555) is positioned at the bottom of die stacks, and minimum chip (565) is positioned at the top, chip can be placed to make maximum at the top and minimum in the bottom.The chip (565) of top layer is illustrated as and is connected to intermediate chip (560), and is connected to the electrical lead (580,585) on the lead frame (570).Intermediate chip (560) is illustrated as the chip (565) that is connected to top layer, and is connected to the electrical lead on the lead frame.The encapsulant (590) that covers tube core closed assembly chip (555,560,565) prevents that the line of Chip Packaging is damaged between operation or installation period.Various chips use the adhesive such as conduction or non-conductive epoxy resin or use insulating material to be attached to lead frame (550) or attached each other.
Figure 28 a and 28b are the stereograms of specializing the lead frame of some aspects of the present invention.Figure 28 a is illustrated in chip and is attached to the lead frame lead frame (600) with four chip-pad area (605,610,615,620) before.Figure 28 b is illustrated in chip (625,630,635,640) and has been attached to chip-pad area (605,610,615,620) and has been electrically connected to lead frame same lead frame (600) afterwards.
Figure 28 a is shown lead frame (600) to have three chip-pad area (610,615,620) that are used for the wire-bonded chip and a chip-pad area (605) that is used for flip-chip.Two (615,620) being used for three chip-pad area of wire-bonded chip do not have recessed and remaining chip-pad area (610) to be recessed into.These chip-pad area (610,615,620) on the neighboring of chip-pad area, comprise be shaped as " T " but the alternately variant (645) of ' locked ' zone form.These Lock Parts are that encapsulant (650) adhesion provides additional surfaces long-pending, and a kind of method that is used to keep encapsulant and encapsulant is displaced sideways is provided.
In Figure 28 b, there is not each supporting of recessed chip-pad area (615,620) to be connected to the single chip (635,640) of lead frame via electrical lead.The chip-pad area (605) that is used for flip-chip (625) forms through the electrical lead bed, and the top that flip-chip (625) is placed on these lead-in wires is to form electrical connection.Compare with wire-bonded chip (630,635,640), flip-chip (625) thus go up to save the space at lead frame (600).Though for clarity sake; Only single chip is illustrated as two of being attached on the lead frame does not have recessed chip-pad area (615,620); But in other embodiments of the invention, can there be one or more chips to be placed on the top of these wire-bonded chips or flip-chip.
In Figure 28 b, the wire-bonded chip (being generically and collectively referred to as 630) of a plurality of tube core closed assemblies of recessed chip-pad area (610) supporting on the lead frame.These chips use the adhesive such as conduction or non-conductive adhesive (for example epoxy resin) or use insulating barrier to be attached to chip-pad area (610).The periphery of recessed chip-pad area (610) comprise be shaped as " T " but the alternately variant (645) of ' locked ' zone form.
Lead frame among Figure 28 a and the 28b (600) also has the electrical lead (common 655) that is positioned between flip-chip welding disking area (605) and the recessed chip-pad area (610), and it also can be used for other element except computer chip.For example, these electrical leads can be the elements such as semiconductor element, passive block, resistor and capacitor, and perhaps other is used for replenishing the non-chip assembly (generally being shown (660)) of Chip Packaging chips function.In Figure 28 b, capacitor or resistor are attached to these electrical leads.
Chip one by one tube core closed assembly is electrically connected to lead frame at next chip by the tube core closed assembly and before being electrically connected on chip-pad area and then.Alternatively, all chips can be electrically connected to lead frame by the chip of tube core closed assembly and whole then tube core closed assembly group.In another embodiment, chip can with chip-pad area tube core closed assembly discretely, and the chip of whole then tube core closed assembly group can be attached and be electrically connected to lead frame.The tube core closed assembly can form by any order with being electrically connected, and is easily although chip and passive block are attached to lead frame, carries out wire-bonded (or form other method of the electrical connection) then.
But Figure 29 a-29c illustrates various types of alternately each embodiment of variant that can be applicable to chip-pad area.In Figure 29 a, but replace variant (705) adopts " T " shape recess on the outer ledge of chip-pad area (720) form.In Figure 29 b, but alternately variant (710) is to be positioned at along the hole of the neighboring of chip-pad area (725) or the form of perforation.Figure 29 c illustrate along chip-pad area (730) but the alternately variant (715) of form of recess of neighboring.But replacing variant, these increased intensity and improved stability are provided for the Chip Packaging that encapsulates.
But though the periphery that alternately variant among Figure 29 a-29c or Lock Part are positioned at respective chip welding disking area (720,725,730), but replace other part that variant also can be placed in chip-pad area.For example, but alternately variant can be in the inside of chip-pad area, and the inside of this chip-pad area will not covered by chip and therefore available encapsulant is filled.
In Figure 29 a-29c, but alternately variant has been illustrated as and has been positioned on the chip-pad area.In additional embodiment of the present invention, such as at shown in Figure 30 a-32f those, but alternately variant can be positioned on the lead frame and chip can with electrical lead that it is electrically connected on.On alternately but variant also can be placed on chip-pad area simultaneously and be gone between.
But illustrating, Figure 30 a-31b has alternately top view and the end view of some embodiment of the electrical lead of variant.Figure 30 a-30d illustrates the cross section of the part in various types of lead-in wires (735,740,745,750) and these lead-in wires.Grafting material but Figure 30 b illustrates that variant alternately can have the inner surface (755) that is arranged in lead-in wire (740).The surface (770,775) that Figure 31 a and 31b illustrate lead-in wire (760,765) can be kept by the improvement of roughening for encapsulant.
Figure 32 a-32f illustrates the stereogram of each embodiment of Figure 30 a-31b, but these stereogram illustrations have alternately some embodiment of the electrical lead of variant.Figure 32 a illustrates the have chip-pad area lead frame (800) of (805).The circle of accompanying drawing part (810) but illustrate and have the alternately electrical lead (815) of variant.The lead-in wire of these types of Figure 32 b-32f illustration.Figure 32 b-32d illustrates the embodiment with those the roughly similar lead-in wires (820,825,830) shown in Figure 30 a, 30c and the 30d.Figure 32 e illustrates and the roughly similar lead-in wire (835) shown in Figure 30 b.Figure 32 f illustrates the lead-in wire (840) that has along the surface roughening of the peripheral horizontal recess form of lead-in wire, thus the outward appearance of the step that goes between.The technology of chemistry or other type can be used to obtain the surface roughening shown in Figure 32 f.But this surface roughening can with lead-in wire and chip and pad variant Combination application alternately.
Figure 33 a-33b illustrates the sectional view of the one side of further embodiment of the present invention, wherein wire clamp (925) be used to replace wire-bonded with to wafer-level package (935) thus power supply and improve its power capability.Figure 33 a illustrates the embodiment that uses wire-bonded chip (905 and 910), and Figure 33 b illustrates the embodiment that is used for flip-chip (being shown single chip 907).Wire clamp is compared wire-bonded significantly a large amount of electric power is provided, and the result makes gained Chip Packaging (935) that improved reliability can be arranged.Wire clamp also helps from chip cooling.When using wire clamp, the chip of top layer will comprise the lead-in wire that is used for the signal of telecommunication is transferred to printed circuit board (PCB).
In Figure 33 a, wire-bonded chip (905 and 910) is placed on chip-pad area (900) and upward and via line (920) is electrically connected to lead-in wire (915).A plurality of lines (920) are used to chip (910) is connected to multirow electrical lead (915), though the number and the type that are electrically connected will depend on specific embodiment.In Figure 33 b, flip-chip (907) is placed on from the electrical lead (such as 915) of lead frame protrusion.For ease of explanation, only single flip-chip (907) is shown in Figure 33 b, though any combination of the flip-chip and the wire-bonded chip of formation wafer-level package (935) in fact can be arranged.
The end face of the highest chip (907 and 910) is electrically connected to the one or more electrical leads (917) on the lead frame (900) through wire clamp (925).After chip was attached to lead frame, wire clamp (925) joined the top of chip to.Any means easily can be used to join wire clamp to chip.In the example shown in Figure 33 a-33b, conducting resinl or scolder (930) are used to wire clamp (925) is attached to chip (907 and 910).Wire clamp (925) can be by the conductive materials manufacturing such as metal or metal alloy.Suitably the example of conductive materials comprises copper and silver.According to specific embodiment, each wire clamp can be attached to certain chip, and perhaps whole bus or plate can use combined method to be attached to a plurality of chips.In one embodiment of back, the action incision bus of singualtion or plate are to obtain each Chip Packaging effectively.
According to the present invention, the closed assembly chip is covered and after singualtion, obtains wafer-level package (935) by encapsulant subsequently.
The pipe core welding disc that exposes is commonly used to provide the electricity between wafer-level package and the printed circuit board (PCB) (PCB) to isolate.Yet in some example, the pipe core welding disc of exposure or chip-pad area are unfavorable for the suitable function of chip or wafer-level package.For example, some PCB design have the active circuit below wafer-level package, and if chip bonding pad then these circuit of encapsulation with exposure can break down.Though the use of QFN in these situation (quad flat no-lead (QFN) encapsulation) encapsulation can provide possible solution, be designed so that to have a plurality of assembling difficult points that are associated with the lead frame of QFN encapsulation.For example, be difficult to or can not use prior art production to be used for the QFN encapsulation of landless lead frame, these methods promptly are that (a) uses and be with, lead frame map (mode array technology) form normally wherein, or (b) need not be with, wherein lead frame is a matrix form.
In order to overcome these difficulties, user (a) has the lead frame that etches partially from the bottom has upset so that pad can be embedded into perhaps (b) during molded at pipe core welding disc.Yet, for band map lead frame is arranged, there is the problem of carrying out wire-bonded, (being used for before semiconductor leads being joined to lead frame, preheating lead frame) contact with pad because band will prevent heater block.After wire-bonded, carry out to paste to be with the rate of manufacturing a finished product is had negative effect.For the matrix lead frame, heater block can be designed to have pedestal with supports chip welding disking area during wire-bonded.Yet this leadframe design has low capacity, and therefore per hour will influence specific yield and increase production cost.
In these cases, landless ELP can provide the possibility of the improved functional and fault that reduces.Landless ELP can keep high density designs and the more packaging technology of robust is provided.Landless ELP embodiment has the similar structure roughly with ELP chip bonding pad embodiment, but need not the etching of bottom protection.Therefore, landless ELP embodiment need acutely not change production line.
The landless lead frame has the tube core housing region that etches partially and need not bottom etching mask or electrodeposited coating.The tube core housing region is compared other lead frame can hold bigger die size, and can provide the device that needs tube core to isolate fully.Because the tube core housing region is recessed into,, required height is installed thereby minimize it so the gained wafer-level package can have low-down profile.Therefore die-attach material (or adhesive) will be nonconducting preventing short circuit, and will be that same color is to provide consistent outward appearance with mold compound usually.In addition, die-attach material or adhesive should be stable during the etching of back, so that prevent the damage to wafer-level package.Die-attach material can be any material known in the art, such as curable epoxy or the band such as the polyimides adhesive tape.
Figure 34 a-34f illustrates the embodiment of partially patterned lead frame, and wherein chip-pad area or chip housing region do not exist and chip directly is attached to the bottom with the etching-film that forms lead frame.After attached die, encapsulation and back patterning, the bottom of chip is exposed in the wafer-level package.Shown in Figure 34 a, the not lobed chip-pad area of partially-etched film is with the holding semiconductor chip.
Figure 34 a illustrates in the front side by partially-etched metal film (1000).This film (1000) can use the substances processed after a while that will be convenient to such as wire-bonded to electroplate in advance one or both sides.For example, the top of film can with such as NiPdAu or the silver such as soaking Ag (Ag) but and so on the lead-in wire mating substance electroplate in advance, but and the bottom of film can be expose and use identical or another lead-in wire mating substance is electroplated in advance.In other embodiments, organic material can be used as etching mask.
Film (1000) will be etched in its front with the preparation IC chip attached with it after a while electrical lead part (1005).Film has the street zone (1035) of the each several part of isolating lead frame, and will be through these street zone (1035) singualtion to obtain each wafer-level package through the lead frame of encapsulation.Chip installation area territory (1010) is etched to the front of film.These chip installation area territories (1010) are in height low than lead-in wire.In other words, film (1000) is etched minimumly in the zone (1005) of lead-in wire, and will be etched at most in other part of lead frame.
Prepared and suitably after the etching, semiconductor or IC chip (1020) will be by attached die to films, shown in Figure 34 b at film (1000).Any convenient material of the available die-attach material of chip (1020) or adhesive (1015) and so on is attached, and these materials will be normally nonconducting to avoid the propagation of the signal of telecommunication.
In one embodiment, the available nonconducting epoxy resin of chip (1020) (1015) is attached.This adhesive is applicable as fluid or viscous liquid, and it will harden or form internal crosslinking then to form firm, durable joint.Adhesive or die-attach material (1015) will be visible and be exposed to the bottom of gained wafer-level package (1040), and therefore needs had long-term thermodynamics and mechanical stability.In other embodiments, adhesive can be the form of the band such as the polyimides adhesive tape.Band is made up of the base band film that on both sides, is coated with the adhesion substance such as the thermoplastic polymer usually, and band can be viscosity or tack-free.In a further embodiment, adhesive is the solid plastics material, and it solidifies in position or solidifies so that firm attached between chip and the lead frame to be provided.Various types of adhesives, band and other die-attach material are known and can buy.
In one embodiment, adhesive (1015) and the encapsulant (1030) that centers on all are black, therefore entire chip level encapsulation (1040) are demonstrated the painted of unanimity.In other embodiments, adhesive and encapsulant are different colours.In a further embodiment, manufacturer for example can hope the color for adhesive and encapsulant selection particular complementary or contrast, thereby special trade dress is provided.
The thickness of adhesive (1015) is not crucial, though it will have to enough thick with have mechanical stability and the tolerance lead frame the back etching.The whole bottom surface that adhesive (1015) will cover IC chip (1020) usually is to avoid during subsequently back etching or back patterning process chemistry or the mechanical damage to chip.
In case chip (1020) is arrived film (1000) by attached die, chip just for example uses lead-in wire (1025) to be connected to electrical lead (1005), shown in Figure 34 c.Chip (1020) and lead-in wire (1025) use the airtight sealing of encapsulant (1030) (Figure 34 d).Like above discussion ground, encapsulant (1030) can be any material known in the art.The unrestricted tabulation of the common encapsulant that uses in the industry comprises tripoli particulate filling epoxy resin and liquid epoxies.Encapsulant is coated to the various elements that are installed in or are attached to lead frame as liquid or viscous liquid usually.Solidify encapsulant and obtain hard, curable coating, the following element in its protection wafer-level package is not damaged.
After encapsulant (1030) has solidified, lead frame (1000) then by the back etching to isolate electrical lead (1005), shown in Figure 34 e.The each several part below chip (1020) of lead frame (1000) (being the original chip installation region) during the etching of back by basic or complete removal, till die attach adhesives (1015).
Lead frame then along street part (1035) by the wafer-level package (1040) of singualtion, such as being used to be attached to computer circuit board with each encapsulation of obtaining to be suitable for subsequent applications.The mark that manufacturer can be chosen in printing on the wafer-level package of completion or silk screen printing sign, lot number or other type is used for recognition purpose.
Figure 35 and 36a illustrate vertical view and the cross sectional view via the wafer-level package (1040) of the preparation of the operation shown in Figure 34 a-34f respectively.Figure 35 person, cure adhesive (1015) is shown the irregular square than light colour at the center of wafer-level package (1040).Around solidifying adhesion substance (1015) is encapsulant (1030), as than shown in the dark colour.Encapsulant (1030) covers also encapsulated integrated circuit chip (1020), wiring (1025), goes between (1005) and can be attached to or be installed to any other assembly on the lead frame.
Figure 36 b illustrates another embodiment of the present invention, and wherein a plurality of IC chips (1020,1050) are stacked in the wafer-level package of landless of finishing (1070) by tube core.Though Figure 26 b and 36b illustrate the various embodiments of the present invention with tube core closed assembly chip, the embodiment that the embodiment among Figure 26 b has among chip bonding pad (515) and Figure 36 b adopts the landless technology.The height that does not have reduction gained wafer-level package of the comparison display chip pad of Figure 26 b and 36b, thus making to prepare has the wafer-level package of hanging down profile.
Embodiment shown in Figure 36 b can use method preparation disclosed by the invention.In brief; The first, down chip (1020) is placed on (not shown in this accompanying drawing) on the partially patterned lead frame with chip bonding pad, and this chip (1020) uses the die-attach material (1015) such as adhesive or epoxy resin to be attached to lead frame.Last chip (1050) uses the adhesion substance such as conduction or nonconducting epoxy resin or insulating material to be placed on down the top of chip (1020) and to be attached to this time chip then.Chip (1020,1050) uses wire-bonded to be electrically connected to lead frame.
Being electrically connected (1025) can sequentially carry out after each chip is placed on the lead frame.That is, first chip (1020) can be placed on the lead frame and be electrically connected to this lead frame, and second chip (1050) can be placed on first chip (1020) and be electrically connected to lead frame then.In other embodiments, chip (1020,1050) is at first in position by the tube core closed assembly, and is electrically connected (1025) then.These closed assemblies and the various combinations that are electrically connected step are possible and within scope of the present invention.
Chip (1020,1050) by tube core closed assembly and electrical connection (1025) after lead frame, lead frame uses encapsulant (1030) encapsulation for good and all chip and electric wire are installed on the lead frame then.Back patterning, etching and finishing are carried out then as required to isolate electrical lead (1005) in the back of lead frame.During this back Patternized technique, the part of lead frame below tube core closed assembly chip is by complete removal, and only go between (1005) are from through the wafer-level package of finishing " protrusion ".Generally speaking, the original lead frame that after the patterning of back, keeps part is only arranged is electrical lead (1005).At last, wafer-level package is used for subsequent applications by singualtion to obtain each wafer-level package (1070) in the street zone.
According to a further aspect in the invention, the end face of lead frame and bottom surface can be by partially patterned or partially-etched before attached die.Shown in Figure 37 a, lead frame (1100) can be etched on both sides before the encapsulation of assembling chip level.Etching on the both sides of lead frame can be the consistent degree of depth.Alternatively, etching can be uneven, and a side is compared opposite side and can be patterned deeplyer.For example, (for example, zone 1165) can be patterned deeplyer bottom top (for example, zone 1160) compared.
The bilateral etching allows that the each several part of the film of final removed lead frame is had the thickness that reduces.Thereby etching will be carried out sooner, and thereby increase speed of production and reduce cost.The partially patterned thickness that can reduce the etching part of film reaches any convenient quantity.For example, the partially patterned segmentation of lead frame can be removed the original membrane thickness of 25-90% in etching area.
Lead frame material can carry out preparatory patterning with the etchant resist material.Etchant resist can be a metal such as organic etchant resist or nonmetal, but and baking-curing or UV solidify.These preparatory Patternized techniques are well known in the art.
Replace to use the preparatory electroplate lead wire frame of metal, but lead frame can use printer's ink printing such as epoxy resin China ink or tusche, or the organic material such as polyimide resin as the etching mask printing before the etching of back.This technology advantageously makes into the instinct reduction and can streamlinedly make.See from the material angle, but make manufacturer obtain lead frame there as etching mask printer's ink or organic substance from many manufacturers because not every supplier can be on both sides electroplate lead wire frame in advance.In this example, lead frame supplier is etching and electroplate lead wire frame at the top only, and it is undressed to stay the bottom.For example, the bottom of lead frame can be the naked metal such as copper.But the noble metal such as palladium, gold, platinum, rhodium, silver or ruthenium or its alloy that uses printer's ink or organic substance to shelter to compare usually use to be used for preparatory electroplate lead wire frame is sheltered more cheap.In addition, the removal China ink is easier than removing noble metal usually after etching.
Lead frame can also be electroplated before etching in advance.In advance plated material can be identical or different on the end face of lead frame and bottom surface.The example of suitable preparatory plated material comprise such as Ni/Pd/Au strike and silver (Ag) but wire-bonded material and the weldable material such as Sn/Pb, lead-free solder, wicking chemical nickel plating or Au (gold) strike.In an embodiment of the present invention, but the front uses grafting material to electroplate in advance, and the back side uses weldable material to electroplate in advance.In another embodiment, but the front can use the wire-bonded material to electroplate in advance, and the back side can electroplate and cover with etchant resist in advance.In a further embodiment, organic material can be printed or be coated on the lead frame with for use as photoresist.
Figure 36 a illustrates and is etched to form the film (1100) of chip bonding pad (1110) and a plurality of electrical lead (1105).The bottom that film is compared at the top of film has been etched to bigger degree.Figure 36 b illustrates the chip (1120) that is electrically connected to the lead frame shown in Figure 36 a via wire-bonded (1125).In Figure 36 b, IC chip (1120) has used adhesive (1115) to be attached to lead frame (1100), and Chip Packaging has used epoxy sealing material (1130) to cover.Street zone (1135) makes and is electrically connected and packed chip (1120) isolation.
Chip (1120) be attached to lead frame chip bonding pad (1110) and packed after; The back side of lead frame can be by back patterning and etching to isolate electrical lead (1105) and chip bonding pad (1110), and perhaps the electricity each several part of isolating lead frame is expected parts to produce.Because the back side is by partially-etched, so this back etch process will carry out more quickly and thereby per hour advantageously improve unit (UPH) capacity and reduce cost.
The bottom die pad of previous lead frame is the plane normally.The example of lead frame of bottom die pad with plane is shown in Figure 37 b.Yet in some example, the pipe core welding disc on these planes tends to when wafer-level package is installed to printed circuit board (PCB), cause scolder space problem.Do not accept the opinion constraint, should believe that the scolder space mainly is the phenomenon that is caused by the degasification that encapsulates solvent.Though the scolder space reduce the efficient electrically contact and thereby can cause the secondary integrity problem, detection can only be cut by X-ray microscope method or destructive differential usually in the scolder space.
According to a further aspect in the invention, lead frame can have the bottom die pad of opening.The embodiment of such pipe core welding disc is shown in Figure 38.Opening (1255) can go up form passage at pipe core welding disc (1210), and reduces the surface area that contacts between pipe core welding disc and the print surface plate, thereby advantageously reduces the amount in scolder space.Opening or passage (1255) play pore, so that during remelting, there is not entrapped air.
The bottom land of opening (1210) is made little array below the pad on the bottom side of lead frame plating mask obtains.During etching, this array of electroplating mask will produce on the bottom die pad and etch partially passage.Mask will play the etchant resist effect during etch process.
Etching mask can be nickel/palladium/golden synthetic (NiPdAu), silver (Ag), antimony (Sn), nickel (Ni) or its mixture, perhaps any nonmetal or organic material or China ink that applies or be printed onto on the lead frame.Etching mask can be solidified by baking or UV as required.Mask that other is suitable and photoresist material are known to those skilled in the art.Shelter with etched technology and can carry out like previous discussion ground.
Figure 38 illustrates to have a plurality of IC chips (1220,1250) is installed to the wafer-level package (1240) of the open bottom pipe core welding disc (1210) on it.Following chip (1220) is attached to the opening pipe core welding disc via adhesive (1215), is attached to down chip (1220) and go up chip (1250) via adhesive (1245).Chip (1220,1250) is electrically connected to electrical lead (1205) via wire-bonded (1225), although chip (1220,1250) also can be electrically connected each other in other embodiments.Use can be encapsulant (1230) packaged chip of epoxy resin or another material.
Though Figure 38 illustrates the wafer-level package of the IC chip that comprises two tube core closed assemblies, in other embodiments of the invention single chip can only be arranged, and further among the embodiment three or more a plurality of tube core closed assembly chip can arranged.All these embodiment are within scope of the present invention.The different number chips that the different chip bonding pads that are attached on the lead frame can also be arranged.For example, a chip bonding pad of lead frame can have singulated dies chip is installed, yet another chip bonding pad on the same lead frame can be three tube cores chip is installed.Therefore, the present invention can be used to a plurality of differences of preparation and different chip on single lead frame.
Figure 39 a and 39b illustrate two embodiment of wafer-level package (1340) according to a further aspect of the invention, and wherein the electrical connection dish has different structure.Figure 39 a illustrates all electrical connection dishes (1305) wherein for square and be arranged in two concentric row on every side so that each terminal pad keeps separating the wafer-level package (1340) of enough distances at chip (1320).Figure 39 b illustrates wherein, and electrical connection dish (1305) is the wafer-level package (1340) of introducing lead-in wire (1309) form.Wiring (1325) forms the chip (1320) and the electrical connection that is electrically connected between the dish (1305) among Figure 39 a and the 39b.Introducing lead-in wire can prepare in etch device, and perhaps they can use the routine techniques such as silk screen printing to be applied on the lead frame.In alternate embodiment, the arbitrary terminal pad on the lead frame can have such as ellipse, rectangle or circular Any shape.On the lead frame Anywhere this optional terminal pad shape within the scope of the invention.
The wiring (1325) that among Figure 39 a chip (1320) is connected to the electrical connection dish is than among Figure 39 b chip (1320) being connected to wiring (1325) length of introducing lead-in wire.Although the embodiment among Figure 39 a provides the difference that is superior to the prior art lead frame to improve and is efficiently, take every caution against error sometimes and avoid the wiring contact, otherwise just become too approaching.Once in a while, use the technology in special formation loop to make wiring keep separating.This technology is useful, although they can make that wire bonding technique is slack-off sometimes.On the contrary, in Figure 39 b, the end of introducing lead-in wire (1309) therefore forms the amount much shorter that is electrically connected necessary wiring quite near the electric terminal on IC chip (1320) periphery.Because these wirings (1325) are formed by the gold customization, the short amount of the gold that uses that allows of length that therefore is used for the wiring of wire-bonded reduces, and has therefore reduced production cost.
Although the electrical connection dish (1309) among Figure 39 a all is illustrated as the corresponding to introducing lead-in wire with the present invention, some terminal pads can be the forms of introducing lead-in wire, and other terminal pad has another form, such as the square lead-in wire of routine.For example, the electrical connection dish near chip can be the form of square, circular or oval terminal pad, and can have the lead-in wire of introducing away from the electrical connection dish of chip.This combination within the scope of the invention.
Figure 40 a illustrates the sectional view of an embodiment of wafer-level package (1340) according to a further aspect of the invention; Wherein the IC chip is to have the flip-chip that is arranged near the solder joint (1380) of chip periphery, and chip is electrically connected to the introducing lead-in wire (1309) that extends below at chip.Figure 40 b illustrates another embodiment of wafer-level package (1340), and its chips (1320) is to have the flip-chip that is arranged in the solder joint (1380) of array in chip bottom.Solder joint is electrically connected to the introducing lead-in wire (1309) that extends below at chip.Shown in Figure 39 and 40, in wire-bonded and flip-chip embodiment, introduce lead-in wire and can use with the present invention effectively.
Figure 41 illustrates the preparation of an embodiment who uses the ELP lead frame of introducing lead-in wire and landless selection.Be used to prepare general and above-mentioned the quite technological of conventional terminal pad that be used for of technology of lead frame.In step 1, metal frame (1300) will be that raw material are used in conversion.In step 2, metal frame is by the partially-etched partially-etched lead frame piece that has web shape part (1305) and chip attach zone (1310) with generation.Metal frame (1300) can be by making things convenient for material to process arbitrarily, such as copper or copper alloy.Partially-etched step illustrates material and removes from lead frame (1300) center, so that provide the landless lead frame on every side in zone (1310).That is, in the gained wafer-level package, the center of chip or tube core (1320) will not remain on the pipe core welding disc.
In step 3, after partially-etched, lead frame (1300) but use the wire-bonded material such as Ag, Ni/Au or NiPdAu to come selective electroplating to form electrical connection dish (1307), these electrical connection dishes are the form of introducing lead-in wire in the embodiment shown.Electrical lead part (1307) is separated with chip attach zone electricity preventing electrically contacting of non-expectation, and lead frame is separated from each other through the compartment (not shown).
Although in Figure 41, consistent with the present invention selective electroplating (accomplished partially-etched (step 2) before the step 3), these steps can any order easily be carried out, and selective electroplating (step 3) can be carried out (step 2) before partially-etched.The order of step will depend on concrete embodiment at hand.The top of lead frame (1360) is the surface of selective coating normally, and bottom coating is optional.If electroplate the bottom surface of lead frame (1365), then coating can be used as underseal or is used for the plug-in unit assembling.
In step 4, after electroplating, use adhesive (1315) chip or tube core (1320) to be attached to the chip attach zone (1310) of lead frame.Use the wire-bonded technology partly to form electrical connection (step 5) between (1307) with the electrical lead of corresponding lead frame then at the terminal of chip (1320).As previously mentioned, lead portion (1307) is to introduce the form of lead-in wire.The step in chip or attached die to chip attach district can randomly be comprised: place active lead-in wire (perhaps opposite chip; Will be in final wafer-level package active lead-in wire) on, active lead-in wire will be when not having chip bonding pad supporting chip (as among Figure 47 b further shown in).In this embodiment, chip can use non-conductive adhesive (such as non-conductive epoxy resin) or attached die film adhesive to paste the chip attach zone.In this embodiment, electrical connection will form between active lead-in wire and IC chip.
In Figure 41, chip (1320) is the wire-bonded chip, but this chip also can be a flip-chip.In such instance, as known in the art, wire-bonding step can be soldered step and substitute.
In step 6, after the electrical lead portion of using wire-bonded (1325) chip (1320) to be electrically connected to lead frame is divided, packed through lead frame on the compartment that encapsulants (1330) is coated in lead frame and separate leadframes.The bottom surface of lead frame (1365) then by back patterning or back etching to remove web shape part and compartment.In this etching step, organic underseal (1361) or another suitable resist can be applied to the selectivity part of lead frame bottom before etching, thereby etch process can be removed remaining unwanted part (shown in the step 7) in the metal frame.
In step 8, use saw or other proper technology with the lead frame singualtion then, to form single wafer-level package (1340) (step 8).The bottom of lead frame or wafer-level package can randomly scribble the conductive coating (1375) such as China ink or solder resist material, when being mounted to printed circuit board (PCB) or miscellaneous equipment, to prevent the bottom short circuit of wafer-level package.Soldered ball (1380) also can randomly affix to the electrical connection dish so that with the follow-up expectation use location that affixes to of wafer-level package (1340).In addition, the solderable material can randomly be applied to the electrical connection dish so that follow-up electrical connection.Although but any of these optional feature can be used before or after singualtion, generally speaking, it is more convenient before singualtion, using this characteristic.
Figure 42 illustrates the set-up procedure that is used for EMI (electromagnetic interference) shielding is put on ELP lead frame of the present invention.In Figure 42, electrical connection dish (1309) is a form of introducing lead-in wire, and lead frame scribbled electromagnetic interference (EMI) shielding material (1385) before singualtion.Step 1-6 among Figure 41 and 42 is identical in two processes, begins to step 6, to prepare package leadframe from metal frame (1300), therefore will not further describe.
In the step 7 of Figure 42, part is cut package leadframe with exposing metal lead frame (1300) in interval region (1335), for EMI shielding (1385) ground connection.EMI shielding (1385) is applied on package leadframe and the interval region then.The EMI screening energy applies with any convenient manner known in the art.For example, shielding (1385) can apply through chemical plating, metallide, dipping, splatter, silk screen printing or any other proper technology as known in the art.Before the etch process of follow-up back, resist coating can randomly be applied to EMI shielding (shown in the step 9).Resist coating will prevent that etching material from might adhere to the EMI shielding.
In step 9, the bottom of lead frame (1365) by back patterning or back etching to remove web shape part and compartment.Organic resist (1361) or another suitable resist can be used to during etching, prevent to remove the selectivity part of metal frame (1300).This resist generally will be removed before the preparation final packaging.The electrical connection dish forms during etch process so that the electrical connection to chip to be provided.If resist coating is applied to EMI shielding, then it will be removed with any remaining resist that uses when the etching.
In step 10, use saw or other proper technology (not shown) singualtion lead frame in interval region then, have the single wafer-level package (1340) of EMI shielding (1385) with formation.With the embodiment of Figure 41 similarly; The bottom of lead frame or wafer-level package (1365) can randomly scribble the non-conductive coating (1375) such as China ink or solder resist material, when being mounted to printed circuit board (PCB) or miscellaneous equipment, to prevent the bottom short circuit of wafer-level package.Soldered ball (1380) or other jockey also can randomly affix to electrical connection dish (can randomly use the solderable material) so that with the follow-up expectation use location that affixes to of wafer-level package.Lead frame can have pipe core welding disc, perhaps can use landless part shown in figure 42.
EMI shielding (1385) in the wafer-level package has reduced the amount of being seen environmental interference of packaged chip (1320) or noise, has improved the performance of chip thus.The wafer-level package of gained is suitable for the many purposes in circuit and the electronic equipment.
Step when Figure 43 a-43c is illustrated in the molded selection of piece material of using lead frame and prepares EMI shielding wafer-level package.In this embodiment, (Figure 43 a) to use big mould to cover the lead frame of whole array with the encapsulants (1330) of monolithic.After the cure package agent, remove mould, stay cell array (1340), then singualtion.In Figure 43 b then in interval region (1335) with encapsulants (1330) incision to metal frame (1300).Take every caution against error and avoid cutting off metal frame and weaken lead frame.In lead frame, carry out after the part cutting, shown in Figure 43 c, apply EMI and shield (1385), and subsequently with the lead frame singualtion to obtain single wafer-level package (1340).
Figure 43 d-43e is illustrated in the step when using the molded selection of single bag mould to prepare EMI shielding wafer-level package.In the embodiment of Figure 43 d, each unit (1340) of lead frame has its encapsulation die cavity, generates the independent moulding unit that is coated with encapsulants (1330) thus.Shown in Figure 43 e, then EMI shielding (1385) is applied to lead frame, the gained lead frame is singualtion in interval region (1335) afterwards.The electrical lead part (1307) of this frame can use plating or other technology to apply.
Can use conventional lead frame mould, although band is assisted the molded mold flashing (being pasted to the excessive encapsulants of lead frame) that can help to prevent with bag mould.Advantageously, the lead-in wire that expectation is used to shield connection is exposed, because single mould bag does not cover interval region (1335), therefore need not expose through cutting, and further discusses about Figure 49 as following.Use the molded needs of part sawing lead frame of also having eliminated of bag mould, shortened cycle time thus and made this technology have higher cost efficiency with exposing metal film (1300).The independent molded of lamination also is possible.
With reference to before the EMI shielding being applied to Figure 43 a-43e has been discussed on the package leadframe in singualtion.Figure 44 a-44c shows a plurality of steps in the alternate embodiment, is wherein applying shielding (1385) at first singualtion unit (1340) before.Unit (1340) through encapsulation and singualtion (but not EMI shielding) can at first place on the saw cramp (1390) shown in Figure 44 a; Perhaps shown in Figure 44 b, place on saw band or the band conveyor (1391); Perhaps place other to make things convenient on the device, so that lead frame moving to saw (1392).After singualtion, EMI shielding material (1385) can through the unit (1340) of singualtion still at clip or be with last time to be applied to these unit through splash, silk screen printing or other means.After applying shielding material, transfer dish, pipe, bag, jar or other packing container can picked up and inserted to the wafer-level package of completion respectively for finally sending to the client.
Step when Figure 45 a-45b illustrates the bottom (1365) of lead frame of the partially-etched EMI of having shielding (1385).In Figure 45 a, before with electroplating in advance the bottom (1365) that mask or resist (1361) cover lead frame, then optionally this bottom of etching to form required surface characteristics.Then solder resist (1375) is applied to the bottom of lead frame, applies solderable material (1362) then to form electrical connection dish (Figure 45 b).Solder resist (1375) can depend on that particular requirement at hand is the convenient or preparation particularly of particular leadframe instance.Solderable material (1362) can comprise that silver (Ag), tin (Sn), tin-billon (SnAu), chemical nickel plating palladium soak gold (ENEPIG) or any other can affix to the electric conducting material of lead frame.The solderable material can through dipping, chemical plating, silk screen printing or other easily technology apply.Soldering paste or soldered ball drip size that (not shown) can be used to increase terminal pad so that afterwards electric attached.After having prepared EMI shielded lead frame fully, can be at this lead frame of interval region (1335) singualtion to form single wafer-level package.
In alternate embodiment, shown in Figure 45 c, not the adding mask bottom (1365) and can be submerged etching of EMI shielded lead frame to expose the characteristic of bottom surface.In flooding etching step, do not apply selective electroplating or mask.Flood the terminal pad that etching does not produce protrusion, although etched away net-like character to isolate lead-in wire and pad.In etching after the bottom, solder resist can be applied to the relatively flat bottom of pieces, and electrical feature (1362) can use the solderable material to apply (Figure 45 d).Any required pad and solderable material generally will be oriented to be convenient to PCB and install.The lead frame of gained can singualtion have the ELP wafer-level package of EMI shielding (1385) with generation in interval region (1335).
Figure 46 a-46e illustrates the bottom view and the X ray picture of the exemplary embodiment of wafer-level package constructed in accordance (1340), and wherein electrical connection dish (1305) has the lead-in wire of introducing (1309) and uses wire-bonded to be connected to chip (1320).X ray picture illustrates the Circuits System through the wafer-level package of encapsulants (1330) (1340).
In Figure 46 a, outside lead (1305) is integrated into chip bonding pad (1310) route on every side, and in Figure 46 b, inside and outside lead-in wire (1305) all is introducing lead-in wire (1309) route.The bottom of wafer-level package will cover to prevent that lead-in wire itself from exposing with solder resist or protection China ink usually.Therefore, in the wafer-level package of reality, terminal pad (1305) but not route lines will be visible only.
Figure 46 c illustrates and wherein uses conductive epoxy resin that small size chip (1320) is placed the wafer-level package (1340) on the pad.Outside lead (1305) row is routed, and is not routed and for square and inner lead (1305) is capable.Because the route of outside lead, institute use the amount that connects up than do not have a lead by the time necessary lacking.
Figure 46 d illustrates and wherein uses conductive epoxy resin to place small size chip (1320) on the pad and the chip drawing wafer-level package of the inside and outside lead-in wire (1305) of route.The amount that is used for the gold thread of wire-bonded among Figure 46 d is lacked than the employed amount of Figure 46 c.
Figure 46 e illustrates wherein large size chip (1320) and is placed on the route lead-in wire (1309) itself, and uses non-conductive epoxy resin or attached die film that chip is pasted to the wafer-level package under the pipe core welding disc.The amount of required gold thread necessary lacking when not having electrical connection dish (a 1305) route.
Figure 47 a-47d illustrates use according to the upward view that the wafer-level package (1340) of pad and landless embodiment manufacturing is arranged of the present invention, and wherein electrical bonding pads (1305) is for introducing the form of lead-in wire (1309).
Figure 47 a illustrates and has the one way traffic that surrounds pipe core welding disc (1310) wafer-level package (1340) by lead-in wire (1309).Conductive epoxy resin can be used to chip attach to pipe core welding disc to be used for the hot property of electric purposes and Geng Jia.
Figure 47 b illustrates according to what landless was selected and has the wafer-level package (1340) of one way traffic by lead-in wire (1309).Lead frame still has the chip attach zone in the zone (1310) around.The IC chip can be placed on the active lead-in wire, these active lead-in wires will be when not having chip bonding pad supporting chip.Chip can use non-conductive adhesive (such as non-conductive epoxy resin) or attached die film adhesive to be pasted to lead frame, and is electrically connected and can between lead-in wire and chip, forms.
Figure 47 c illustrates wherein, and pipe core welding disc (1310) is the wafer-level package (1340) of part metals through-hole form and lead-in wire (1305/1309) branch two row encirclement pads.Inner lead capable (1309) is routed, and outer row (1305) is not routed and do not have the lead-in wire of introducing.In Figure 47 d, solid pipe core welding disc (1310) and terminal pad (1305-1309) divide two row to be arranged in around the pipe core welding disc.Outside lead (1305) is capable not to be routed, and inner lead is exercised with introducing lead-in wire (1309) route.
Figure 48 a-48b illustrates the sectional view according to each embodiment of wafer-level package of the present invention (1340), and wherein pipe core welding disc is solid or comprises the part metals through hole, such as heat through-hole.
Figure 49 a and 49b illustrate vertical view and the sectional view according to encapsulation ELP lead frame of the present invention respectively, and the connection electrical ground that is used for the EMI shielding is shown.
Figure 49 a illustrates the X ray vertical view of four packaged chips (1320) of lead frame, and chip is electrically connected to introducing lead-in wire (1309).Although four chips (1320) illustrate for the ease of illustration, lead frame can have any size easily and can have any amount of unit.Lead frame packed (1330 among Figure 49 b) and cover with EMI shielding (1385 among Figure 49 b), but as yet not singualtion to form each wafer-level package.EMI curtain coating (1385) is electrically connected dish (1308) and electrically contacts with each corner.In order to form each encapsulation, lead frame will be along dotted line (1335) singualtion of the interval region of representing lead frame.
Figure 49 b illustrates the sectional view of one of unit of Figure 49 a after the singualtion.Chip (1320) packed (1330) and cover with EMI screen (1385).Arrow between Figure 49 a and the 49b illustrates the correspondence that connects with the electrical lead (1308) of ground connection as shielding, and lead-in wire is for introducing the form of (1309) that goes between and extending below at chip (1320).Other lead-in wire can extend in the interval region lead-in wire so that these lead-in wires can be connected to EMI shielding (1385), as the electro-magnetic screen layer connection to ground connection through striding packaging line.Encapsulation also has the solderable material (1362) on the lead-in wire so that be connected to circuit board or miscellaneous equipment, and the non-conductive coating (1365) on the package bottom.
Various described embodiment of the present invention repels each other, and can at random make up to prepare the variant of disclosed lead frame.For example, the bottom of the pipe core welding disc of the lead frame of the uneven etching shown in Figure 37 a can intersect opening and be used for preparing the wafer-level package with foot passage shown in Figure 38.Equally, EMI shielding shown in Figure 42 can be applied to the wafer-level package of Figure 27 b to obtain the multicore sheet encapsulation with EMI shielding.Other variant also is possible and within scope of the present invention.
Though illustrate especially and describe the present invention, it should be appreciated by those skilled in the art that the various changes on the form of to do or the details and do not deviate from the spirit and scope of the present invention with reference to each specific embodiment.

Claims (16)

1. method that forms Electronic Packaging said method comprising the steps of:
Formation has the partially-etched lead frame piece that selectivity is electroplated end face and bottom surface in advance; Lead frame comprises web shape part, chip attach zone, introduces the electrical lead part of lead-in wire form; Wherein said electrical lead part is separated with chip attach zone electricity, and said lead frame partly is separated from each other through street;
With the relevant chip attachment levels of chip attach to the lead frame;
One or more terminals of said chip with form one or more the electrical connection between one or more electrical lead portion of corresponding lead frame are divided;
Encapsulate said lead frame through on said lead frame and the said street part of separating said lead frame, applying encapsulant;
The bottom surface of the said lead frame of back patterning is to remove said web shape part and said street part; And
Singualtion places said encapsulant on the said street part to form each wafer-level package.
2. the method for claim 1 is characterized in that, said chip attach zone is the chip-pad area or the landless part of said lead frame.
3. the method for claim 1; It is characterized in that; The step in chip attach to chip attach zone comprised said chip is placed on the active lead-in wire; And use non-conductive adhesive or attached die film adhesive to attach said chip, wherein said active lead-in wire is supported said chip when not having chip bonding pad.
4. the method for claim 1 is characterized in that, said introducing lead-in wire divides single file or multirow to be arranged in around the respective chip attachment levels of lead frame.
5. the method for claim 1 is characterized in that, further comprises the electrical lead that is not to introduce the lead-in wire form.
6. the method for claim 1 is characterized in that, said back patterning step is used partially-etched or flooded etching and carries out.
7. the method for claim 1 is characterized in that, said encapsulation step is molded or individual unit is molded carries out through the piece material.
8. the method for claim 1 is characterized in that, said chip bonding pad is solid or comprises one or more heat through-holes.
9. the method for claim 1 is characterized in that, also comprises the one or more electrical connection dishes that soldered ball, weldering lacquer or solderable material affixed to said wafer-level package before or after singualtion.
10. the method for claim 1 is characterized in that, forms the step that is electrically connected and uses wire-bonded technology, flip chip technology (fct) or their both combinations to accomplish.
11. the method for claim 1 is characterized in that, forms the step that is electrically connected and accomplishes through the terminal on the said chip being connected to from the electrical lead end partly that said lead frame stretches out.
12. the method for claim 1 is characterized in that, the bottom of lead portion, lead frame piece or both are soldered mask and cover.
13. the method for claim 1 is characterized in that, electromagnetic interference shield is applied to said wafer-level package before or after also being included in singualtion.
14. method as claimed in claim 13 is characterized in that, said electromagnetic interference shield applies through chemical plating, metallide, injection, dipping, sputtering sedimentation or silk-screen printing technique.
15. the method for claim 1 is characterized in that, said chip uses conductive epoxy resin, non-conductive epoxy resin or attached die film adhesive to be attached to said chip attach zone.
16. the method for claim 1 is characterized in that, also comprises:
Before one or more second chip-die closed assemblies are arrived the top of one or more chips at the said lead frame of encapsulation.
CN201110257072.0A 2010-09-03 2011-08-24 Partially patterned lead frame and manufacture and use its method in semiconductor packages Expired - Fee Related CN102386106B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/875,248 2010-09-03
US12/875,248 US20110057298A1 (en) 2002-04-29 2010-09-03 Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging
US13/009,362 US8236612B2 (en) 2002-04-29 2011-01-19 Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US13/009,362 2011-01-19

Publications (2)

Publication Number Publication Date
CN102386106A true CN102386106A (en) 2012-03-21
CN102386106B CN102386106B (en) 2015-07-29

Family

ID=45825394

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110257072.0A Expired - Fee Related CN102386106B (en) 2010-09-03 2011-08-24 Partially patterned lead frame and manufacture and use its method in semiconductor packages

Country Status (2)

Country Link
CN (1) CN102386106B (en)
TW (1) TWI397964B (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021884A (en) * 2012-12-10 2013-04-03 华天科技（西安）有限公司 Flat package part manufacturing process based on thin frame
CN103021885A (en) * 2012-12-10 2013-04-03 华天科技（西安）有限公司 Flat package part manufacturing process based on sand blasting
CN103594448A (en) * 2013-11-15 2014-02-19 杰群电子科技（东莞）有限公司 Lead frame
WO2015161731A1 (en) * 2014-04-22 2015-10-29 柯全 Encapsulation method and device for flip chip
CN107799475A (en) * 2016-08-31 2018-03-13 新光电气工业株式会社 Lead frame and electronic part apparatus
CN108807657A (en) * 2017-04-26 2018-11-13 矽品精密工业股份有限公司 Package structure and method for fabricating the same
CN109585408A (en) * 2017-09-29 2019-04-05 矽品精密工业股份有限公司 Board structure and its preparation method
CN109983591A (en) * 2016-11-11 2019-07-05 亮锐控股有限公司 The method for manufacturing lead frame
CN113823569A (en) * 2020-06-18 2021-12-21 吴江华丰电子科技有限公司 Method for manufacturing electronic device

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101366672B1 (en) * 2012-11-20 2014-02-25 주식회사 프로텍 Chip die bonding method and chip die bonding apparatus
TWI606555B (en) 2015-05-15 2017-11-21 尼克森微電子股份有限公司 Chip package structure and manufacturing method thereof
CN106340496B (en) * 2015-05-15 2019-06-04 无锡超钰微电子有限公司 Chip-packaging structure and its manufacturing method
KR101674322B1 (en) * 2015-11-18 2016-11-08 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
US10553542B2 (en) * 2017-01-12 2020-02-04 Amkor Technology, Inc. Semiconductor package with EMI shield and fabricating method thereof
CN113035721A (en) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 Packaging process for plating conductive film on side wall
CN113035722A (en) * 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 Packaging process for plating with selective molding
JP7292776B2 (en) * 2020-01-30 2023-06-19 大口マテリアル株式会社 Lead frame
JP7408885B2 (en) * 2020-01-30 2024-01-09 長華科技股▲ふん▼有限公司 Lead frame

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101601133A (en) * 2006-10-27 2009-12-09 宇芯（毛里求斯）控股有限公司 Partially patterned lead frame and the method for in semiconductor packages, making and use it

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6821821B2 (en) * 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
JP3600131B2 (en) * 2000-09-04 2004-12-08 三洋電機株式会社 Circuit device manufacturing method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101601133A (en) * 2006-10-27 2009-12-09 宇芯（毛里求斯）控股有限公司 Partially patterned lead frame and the method for in semiconductor packages, making and use it

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021884A (en) * 2012-12-10 2013-04-03 华天科技（西安）有限公司 Flat package part manufacturing process based on thin frame
CN103021885A (en) * 2012-12-10 2013-04-03 华天科技（西安）有限公司 Flat package part manufacturing process based on sand blasting
CN103594448A (en) * 2013-11-15 2014-02-19 杰群电子科技（东莞）有限公司 Lead frame
WO2015161731A1 (en) * 2014-04-22 2015-10-29 柯全 Encapsulation method and device for flip chip
CN107799475A (en) * 2016-08-31 2018-03-13 新光电气工业株式会社 Lead frame and electronic part apparatus
CN107799475B (en) * 2016-08-31 2023-04-28 新光电气工业株式会社 Lead frame and electronic component device
CN109983591A (en) * 2016-11-11 2019-07-05 亮锐控股有限公司 The method for manufacturing lead frame
CN109983591B (en) * 2016-11-11 2022-10-04 亮锐控股有限公司 Method for manufacturing lead frame
CN108807657A (en) * 2017-04-26 2018-11-13 矽品精密工业股份有限公司 Package structure and method for fabricating the same
CN108807657B (en) * 2017-04-26 2022-01-04 矽品精密工业股份有限公司 Package structure and method for fabricating the same
CN109585408A (en) * 2017-09-29 2019-04-05 矽品精密工业股份有限公司 Board structure and its preparation method
CN113823569A (en) * 2020-06-18 2021-12-21 吴江华丰电子科技有限公司 Method for manufacturing electronic device

Also Published As

Publication number Publication date
CN102386106B (en) 2015-07-29
TW201232673A (en) 2012-08-01
TWI397964B (en) 2013-06-01

Similar Documents

Publication Publication Date Title
CN101601133B (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
CN102386106B (en) Partially patterned lead frame and manufacture and use its method in semiconductor packages
US8236612B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US8487424B2 (en) Routable array metal integrated circuit package fabricated using partial etching process
US7977161B2 (en) Method of manufacturing a semiconductor package using a carrier
US8076181B1 (en) Lead plating technique for singulated IC packages
US9966326B2 (en) Lead frames with wettable flanks
CN104854695A (en) Lead carrier with print-formed terminal pads
CN101383301A (en) Method of forming flip-chip bump carrier type package
US11810842B2 (en) Side-solderable leadless package
KR20180002812A (en) A lead carrier structure, and packages formed therefrom without die attach pads
US20030006501A1 (en) Semiconductor device, method of manufacturing semiconductor device, lead frame, method of manufacturing lead frame, and method of manufacturing semiconductor device with lead frame
US9659842B2 (en) Methods of fabricating QFN semiconductor package and metal plate
KR101674537B1 (en) Leadframe, method of manufacturing the same and semiconductor package, method of manufacturing the same
US9202712B2 (en) Lead frame and a method of manufacturing thereof
US6930377B1 (en) Using adhesive materials as insulation coatings for leadless lead frame semiconductor packages
KR101036354B1 (en) Structure and manufacture method for multi-row lead frame and semiconductor package
KR20100104112A (en) Circuit board used for semiconductor package, method thereof and semiconductor package using the same
KR101047874B1 (en) Lead frame and semiconductor package and manufacturing method thereof
JP2001127227A (en) Terminal land frame, manufacturing method thereof, resin-sealed semiconductor device and manufacturing method thereof
KR20090123473A (en) Structure and manufacture method for multi-row lead frame of semiconductor package
CN101740411A (en) Manufacturing process for a chip package structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150729

Termination date: 20160824