CN109585408A - Board structure and its preparation method - Google Patents
Board structure and its preparation method Download PDFInfo
- Publication number
- CN109585408A CN109585408A CN201711006909.8A CN201711006909A CN109585408A CN 109585408 A CN109585408 A CN 109585408A CN 201711006909 A CN201711006909 A CN 201711006909A CN 109585408 A CN109585408 A CN 109585408A
- Authority
- CN
- China
- Prior art keywords
- board structure
- layer
- structure according
- preparation
- recess portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000000463 material Substances 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 3
- 239000012774 insulation material Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 abstract description 12
- 229910052751 metal Inorganic materials 0.000 abstract description 12
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 103
- 238000005530 etching Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910020776 SixNy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- XLTRGZZLGXNXGD-UHFFFAOYSA-N benzene;1h-pyrazole Chemical compound C=1C=NNC=1.C1=CC=CC=C1 XLTRGZZLGXNXGD-UHFFFAOYSA-N 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
A kind of board structure and its preparation method, it is formed with an at least recess portion in the top surface of the line layer of substrate body, for the conducting element of subsequent combination such as solder bump, so there is no need in forming convex block underlying metal layer (UBM) on the line layer, thus cost of manufacture can be effectively reduced.
Description
Technical field
The present invention is in relation to a kind of board structure, espespecially a kind of board structure for having line layer.
Background technique
The board structure (such as chip, package substrate) of general electronic packing piece be in forming solder bump on electrical contact,
And will become solder ball after reflow (reflow), for external other electronic devices.
Figure 1A to Fig. 1 D is the diagrammatic cross-section of the preparation method of existing board structure 1.As shown in Figure 1A, have at least one in one
A passivation layer 11 and one first dielectric layer 12 are sequentially formed on the semiconductor substrate 10 of electrical contact 100, re-form a line layer
13 on first dielectric layer 12, and the line layer 13 is made to be electrically connected the electrical contact 100.Then, as shown in Figure 1B, formed
One second dielectric layer 14 is on the line layer 13 and first dielectric layer 12, and to be formed at least one exposed for second dielectric layer 14
The opening 140 of 13 part of the surface of line layer.Then, as shown in Figure 1 C, a convex block underlying metal layer (Under Bump is formed
Metallurgy, abbreviation UBM) on 15 line layer 13 in the opening 140.Later, as shown in figure iD, a solder bump is formed
16 on the convex block underlying metal layer 15 to be electrically connected the line layer 13, for combining semiconductor element, package substrate or electricity
The electronic devices such as road plate.
However, in the preparation method of aforementioned existing board structure 1, because passing through the opening 140 and 15 structure of convex block underlying metal layer
At metal recesses in favor of combining the solder bump 16, therefore second dielectric layer 14 and the convex block need to be formed on the line layer 13
Underlying metal layer 15, causes cost of manufacture to be difficult to decrease.
Therefore, how to overcome above-mentioned problem of the prior art, have become want to solve the problems, such as at present in fact.
Summary of the invention
In view of the disadvantages of the above-mentioned prior art, the present invention provides a kind of board structure and its preparation method, can be effectively reduced
Cost of manufacture.
Board structure of the invention, comprising: substrate body has an at least electrical contact；Insulating layer is formed in this
In substrate body, and the electrical contact is made to expose outside the insulating layer；And line layer, it is formed on the insulating layer and electrically connects
Connect the electrical contact, wherein the top surface of the line layer is formed with an at least recess portion.
The present invention also provides a kind of preparation method of board structure, comprising: providing one has at least an electrical contact and insulating layer
Substrate body, which exposes outside the insulating layer；And line layer is formed on the insulating layer, to enable the line layer electric
Property connects the electrical contact, and the top surface of the line layer is enabled to be formed with an at least recess portion.
In board structure above-mentioned and its preparation method, which defines the pad portion and trace portion being connected, wherein this is recessed
Portion is formed in the pad portion.For example, the width in the pad portion is greater than or equal to the width in the trace portion.
In board structure above-mentioned and its preparation method, which does not run through the line layer.
In board structure above-mentioned and its preparation method, the processing procedure of the recess portion includes: to form etch stop layer in the top surface of the line layer
On, and the etch stop layer is enabled to be formed with the opening for exposing outside the line layer part of the surface；And it forms the recess portion and opens in exposing outside this
In the line layer part of the surface of mouth.For example, the etch stop layer is metal material or isolation material, such as nickel layer.Further, it should only lose
Layer is not in contact with the insulating layer.
It further include forming conducting element on the recess portion in board structure above-mentioned and its preparation method.For example, the conducting element
The side and bottom surface of the recess portion are contacted not in contact with the insulating layer or the conducting element.
From the foregoing, it will be observed that board structure and its preparation method of the invention, are mainly formed at least one by the top surface of the line layer
Recess portion, for the conducting element of subsequent combination such as solder bump, therefore compared to the prior art, preparation method of the invention is not necessarily in the line
Existing soldermask layer and existing convex block underlying metal layer are formed on the floor of road, thus cost of manufacture can be effectively reduced.
Detailed description of the invention
Figure 1A to Fig. 1 D is the diagrammatic cross-section of the preparation method of existing board structure；
Fig. 2A to Fig. 2 D is the diagrammatic cross-section of the preparation method of board structure of the invention；
Fig. 3 A is view plane schematic diagram on the part of corresponding diagram 2D；And
Fig. 3 B is view plane schematic diagram on the part of another embodiment of corresponding diagram 3A.
Symbol description:
1,2 board structure, 10 semiconductor substrate
100,200 electrical contact, 11 passivation layer
12 first dielectric layer, 13,23 line layer
14 second dielectric layers 140,240 opening
15 convex block underlying metal layer, 16 solder bump
20 substrate body, 21 first insulating layer
210 first aperture, 22 second insulating layer
220 second top surfaces aperture 23a
230 bottom surfaces recess portion 230a
231,331 pad portion, 232 trace portion
24 etch stop layer, 26 conducting element
D, h thickness R, t width
Y arrow direction.
Specific embodiment
Illustrate embodiments of the present invention below by way of particular specific embodiment, those skilled in the art can be by this explanation
The revealed content of book is understood other advantages and efficacy of the present invention easily.
It should be clear that this specification structure depicted in this specification institute accompanying drawings, ratio, size etc., only to cooperate specification to be taken off
The content shown is not intended to limit the invention enforceable qualifications for the understanding and reading of those skilled in the art, therefore
Do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size are not influencing the present invention
Under the effect of can be generated and the purpose that can reach, it should all still fall in disclosed technology contents and obtain the model that can cover
In enclosing.Meanwhile cited such as "upper" in this specification, " first ", " second " and " one " term, be merely convenient to chat
That states is illustrated, rather than to limit the scope of the invention, relativeness is altered or modified, and is changing skill without essence
It is held in art, when being also considered as the enforceable scope of the present invention.
Fig. 2A to Fig. 2 D is the diagrammatic cross-section of the preparation method of board structure 2 of the invention.
As shown in Figure 2 A, have in one and sequentially form one first insulation in at least substrate body 20 of an electrical contact 200
Layer 21 and a second insulating layer 22, re-form a line layer 23 in the second insulating layer 22.
The substrate body 20 is the semiconductor board of insulation board, metal plate or such as wafer, chip, silicon material, glass
Material.For example, the substrate body 20 be silicon intermediate plate (Through Silicon interposer, abbreviation TSI) or glass substrate,
It is such as fanned out to the molded line road (fan out) redistribution layer with silicon perforation (Through-silicon via, abbreviation TSV) and wiring layer
(redistribution layer, abbreviation RDL), the electric contact mat of the end or the wiring layer that make the silicon perforation can be used as this
Electrical contact 200；Alternatively, the substrate body 20 is package substrate, it includes tool core layer or seedless central layer (coreless)
Circuit configurations, the circuit configurations include the wiring layer such as RDL, and electric contact mat can be used as the electrical contact 200.
First insulating layer 21 is formed with the first aperture of at least one corresponding exposed 200 part of the surface of electrical contact
210, and the material for forming first insulating layer 21 may be, for example, oxide layer or nitration case, such as silica (SiO2) or silicon nitride
(SixNy), using as passivation layer.
The second insulating layer 22 is formed on first insulating layer 21 and is formed at least one corresponding first aperture
210 and exposed 200 part of the surface of electrical contact the second aperture 220, and formed the second insulating layer 22 material be dielectric
Material, such as polyimide (Polyimide, abbreviation PI), prepreg (Prepreg, abbreviation PP), benzocyclobutene
(Benezocy-clobutene, abbreviation BCB) or poly- to diazole benzene (Polybenzoxazole, abbreviation PBO).
The line layer 23 extends in second aperture 220 and is electrically connected the electricity to contact the electrical contact 200
Property contact 200.In this present embodiment, the line layer 23 be with RDL processing procedure production, material may be, for example, titanium/copper (Ti/Cu) or
Other conduction materials.
As shown in Figure 2 B, an etch stop layer 24 is formed on the line layer 23, and the etch stop layer 24 is not in contact with second insulation
Layer 22, and make the etch stop layer 24 be formed at least one exposed line layer 23 portion top surface 23a opening 240.
In this present embodiment, which is metal material (such as nickel (Ni) or other metals) or insulation material, and it is with electricity
Processing procedure or other appropriate processing procedure production are plated, and required material can be selected according to the etching solution used in subsequent etching processes.
As shown in Figure 2 C, in forming a recess portion 230 on the line layer 23 for exposing outside the opening 240.
In this present embodiment, which is made with etch process.Specifically, by etching solution along the thickness of the line layer 23
Degree direction (arrow direction Y as shown in Figure 2 B) is etched down to certain depth, makes the recess portion 230 not through the line layer
23, that is, remove the part material of the line layer 23 its thickness (as shown in Fig. 2 B and Fig. 2 C, does not etch the thickness d at place with thinning
For 9um, the thickness h after etching is 4.5um), therefore the bottom surface 230a of the recess portion 230 is the material of the line layer 23, thus this
Two insulating layers 22 will not expose outside the recess portion 230.
As shown in Figure 2 D, formed an at least conducting element 26 on the recess portion 230 of the line layer 23 to be electrically connected the line
Road floor 23, for combining the electronic devices such as semiconductor element, package substrate or circuit board.
In this present embodiment, which is soldered ball, metal coupling (such as spherical or column), and contact is bound to
The bottom surface 230a of the recess portion 230.
Furthermore as shown in Figure 3A, in an embodiment, the line layer 23 definition has the pad portion 231 and trace portion being connected
232, it is formed in the recess portion 230 in the pad portion 231, and the width R in the pad portion 231 is greater than the width t in the trace portion 232, makes
For example round or other geometries are presented in the shape in the pad portion 231；Alternatively, as shown in Figure 3B, in another embodiment, pad portion
331 width t is equal to the width t in trace portion 232, makes the pad portion 331 in stripe shape.
It therefore, is by the line layer 23 in preparation method of the invention in directly etching forms the recess portion 230 on the 23a of its top surface
For combining the conducting element 26, therefore compared to the prior art, preparation method of the invention is not necessarily in forming dielectric on the line layer 23
Layer and convex block underlying metal layer, thus cost of manufacture can be effectively reduced.
Furthermore the side of the opening 240 and the side wall and bottom surface 230a of the recess portion 230 are contacted by the conducting element 26,
The contact area of the conducting element 26 can be increased, to improve binding force, therefore the conducting element 26 is can avoid and delamination occurs.
The present invention also provides a kind of board structure 2, comprising: substrate body 20, a shape with an at least electrical contact 200
At in the substrate body 20 first and second insulating layer 21,22 and one be formed in the second insulating layer 22 and electrically
Connect the line layer 23 of the electrical contact 200.
The electrical contact 200 exposes to first and second insulating layer 21, and 22, and the top surface of the line layer 23
23a has an at least recess portion 230.
In an embodiment, which does not run through the line layer 23, and the line layer 23 definition has the pad portion being connected
231,331 with trace portion 232, be formed in the recess portion 230 in the pad portion 231,331.For example, the width in the pad portion 231,331
R, t are greater than or equal to the width t in the trace portion 232.
In an embodiment, the board structure 2 further includes an etch stop layer being formed on 23 top surface 23a of the line layer
24, there is the opening 240 of the corresponding recess portion 230.Specifically, which is metal material or isolation material, such as nickel
Layer, and the etch stop layer 24 is not in contact with first and second insulating layer 21,22.
In an embodiment, the board structure 2 further includes at least one conducting element being formed on the recess portion 230
26.Further, the conducting element 26 is not in contact with first and second insulating layer 21,22.
In conclusion board structure and its preparation method of the invention, are the recess arrangements by the line layer, can not only combine
The conducting element, and cost of manufacture can be reduced.
Above-described embodiment is only to be illustrated the principle of the present invention and its effect, and is not intended to limit the present invention.Appoint
What one of ordinary skill in the art without departing from the spirit and scope of the present invention, modifies to above-described embodiment.Therefore
The scope of the present invention, should be as listed in the claims.
Claims (22)
1. a kind of board structure, it is characterized in that, which includes:
Substrate body, and there is an at least electrical contact；
Insulating layer is formed in the substrate body, and the electrical contact is made to expose outside the insulating layer；And
Line layer is formed on the insulating layer and is electrically connected the electrical contact, wherein the top surface of the line layer be formed with to
A few recess portion.
2. board structure according to claim 1, it is characterized in that, which defines the pad portion being connected and trace
Portion, and the recess portion is formed in the pad portion.
3. board structure according to claim 2, it is characterized in that, the width in the pad portion is greater than or equal to the width in the trace portion
Degree.
4. board structure according to claim 1, it is characterized in that, which does not run through the line layer.
5. board structure according to claim 1, it is characterized in that, which further includes being formed in the line layer top surface
On etch stop layer, wherein the etch stop layer has the opening of the corresponding recess portion.
6. board structure according to claim 5, it is characterized in that, the material for forming the etch stop layer is metal material or insulation
Material.
7. board structure according to claim 5, it is characterized in that, which is nickel layer.
8. board structure according to claim 5, it is characterized in that, the etch stop layer is not in contact with the insulating layer.
9. board structure according to claim 1, it is characterized in that, which further includes being formed in leading on the recess portion
Electric device.
10. board structure according to claim 9, it is characterized in that, the conducting element is not in contact with the insulating layer.
11. board structure according to claim 9, it is characterized in that, which contacts the side and bottom surface of the recess portion.
12. a kind of preparation method of board structure, it is characterized in that, which includes:
A substrate body at least an electrical contact and insulating layer is provided, which exposes outside the insulating layer；And
Line layer is formed on the insulating layer, to enable the line layer be electrically connected the electrical contact, and in the top surface of the line layer
Form an at least recess portion.
13. the preparation method of board structure according to claim 12, it is characterized in that, which defines the pad portion being connected
With trace portion, and the recess portion is formed in the pad portion.
14. the preparation method of board structure according to claim 13, it is characterized in that, the width in the pad portion is greater than or equal to the mark
The width in line portion.
15. the preparation method of board structure according to claim 12, it is characterized in that, which does not run through the line layer.
16. the preparation method of board structure according to claim 12, it is characterized in that, the processing procedure of the recess portion includes:
Etch stop layer is formed on the top surface of the line layer, and enables the etch stop layer be formed with and exposes outside opening for the line layer part of the surface
Mouthful；And
The recess portion is formed in the line layer part of the surface for exposing outside the opening.
17. the preparation method of board structure according to claim 16, it is characterized in that, the material for forming the etch stop layer is metal material
Matter or isolation material.
18. the preparation method of board structure according to claim 16, it is characterized in that, which is nickel layer.
19. the preparation method of board structure according to claim 16, it is characterized in that, the etch stop layer is not in contact with the insulating layer.
20. the preparation method of board structure according to claim 12, it is characterized in that, the preparation method further include to be formed conducting element in
On the recess portion.
21. the preparation method of board structure according to claim 20, it is characterized in that, the conducting element is not in contact with the insulating layer.
22. the preparation method of board structure according to claim 20, it is characterized in that, which contacts the side of the recess portion
With bottom surface.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106133657 | 2017-09-29 | ||
| TW106133657A TW201916180A (en) | 2017-09-29 | 2017-09-29 | Substrate structure and the manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109585408A true CN109585408A (en) | 2019-04-05 |
Family
ID=65919490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711006909.8A Pending CN109585408A (en) | 2017-09-29 | 2017-10-25 | Board structure and its preparation method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109585408A (en) |
| TW (1) | TW201916180A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1417855A (en) * | 2001-10-31 | 2003-05-14 | 新光电气工业株式会社 | Multilayer substrate for semiconductor device |
| CN1532907A (en) * | 2003-03-20 | 2004-09-29 | 精工爱普生株式会社 | Semiconductor wafer, semiconductor device and its producing method, circuit base board and electronic machine |
| CN1547875A (en) * | 2001-11-12 | 2004-11-17 | 松下电器产业株式会社 | Audio coding and decoding |
| CN101715274A (en) * | 2008-10-07 | 2010-05-26 | 欣兴电子股份有限公司 | Circuit board and process thereof |
| CN102386106A (en) * | 2010-09-03 | 2012-03-21 | 宇芯（毛里求斯）控股有限公司 | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
| CN104347528A (en) * | 2013-08-02 | 2015-02-11 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN105762132A (en) * | 2014-12-04 | 2016-07-13 | 矽品精密工业股份有限公司 | Single-layer circuit type packaging substrate and manufacturing method thereof, single-layer circuit type packaging structure and manufacturing method thereof |
| CN105990268A (en) * | 2015-01-30 | 2016-10-05 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
-
2017
- 2017-09-29 TW TW106133657A patent/TW201916180A/en unknown
- 2017-10-25 CN CN201711006909.8A patent/CN109585408A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1417855A (en) * | 2001-10-31 | 2003-05-14 | 新光电气工业株式会社 | Multilayer substrate for semiconductor device |
| CN1547875A (en) * | 2001-11-12 | 2004-11-17 | 松下电器产业株式会社 | Audio coding and decoding |
| CN1532907A (en) * | 2003-03-20 | 2004-09-29 | 精工爱普生株式会社 | Semiconductor wafer, semiconductor device and its producing method, circuit base board and electronic machine |
| CN101715274A (en) * | 2008-10-07 | 2010-05-26 | 欣兴电子股份有限公司 | Circuit board and process thereof |
| CN102386106A (en) * | 2010-09-03 | 2012-03-21 | 宇芯（毛里求斯）控股有限公司 | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
| CN104347528A (en) * | 2013-08-02 | 2015-02-11 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN105762132A (en) * | 2014-12-04 | 2016-07-13 | 矽品精密工业股份有限公司 | Single-layer circuit type packaging substrate and manufacturing method thereof, single-layer circuit type packaging structure and manufacturing method thereof |
| CN105990268A (en) * | 2015-01-30 | 2016-10-05 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201916180A (en) | 2019-04-16 |
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Application publication date: 20190405 |