WO2015161731A1

WO2015161731A1 - Encapsulation method and device for flip chip

Info

Publication number: WO2015161731A1
Application number: PCT/CN2015/075218
Authority: WO
Inventors: 柯全
Original assignee: 柯全
Priority date: 2014-04-22
Filing date: 2015-03-27
Publication date: 2015-10-29
Also published as: CN104658929A

Abstract

An encapsulation method and device for a flip chip. The method comprises the following steps: S1, bonding a chip (100) to a substrate (101), wherein the chip (100) comprises at least two electrodes (102, 105), at least one insulating region (104) used for insulating the electric connection between the electrodes is arranged between the electrodes (102, 105), the substrate (101) comprises at least one conducting region, and after the chip (100) is bonded to the substrate (101), and the electrodes (102, 105) are electrically connected through the conducting region; and S2, separating the conducting region from a region in which the conducting region is overlapped with the insulating region (104), to form several conducting sub-regions which are insulated from each other. By arranging a conducting region on a substrate (101) and bonding same to all electrodes (102, 105) on a chip at the same time, and separating the conducting region to form conducting sub-regions which are bonded to the electrodes (102, 105) on the chip (100) in one-to-one correspondence and are insulated from each other, the problem in the encapsulation technique that the spacing between bumps on the substrate is limited and the problem that the accuracy of alignment of a substrate electrode and a chip electrode is difficult to control are solved at a lower cost.

Description

Flip chip packaging method and device

The present application claims priority from Chinese Patent Application No. CN201410163880.4, filed on Apr. 22, 2014. This application cites the entire text of the above-mentioned Chinese patent application.

Technical field

The present invention relates to a semiconductor packaging technology, and in particular to a flip chip packaging method and apparatus.

Background technique

In the art, in order to dispose the bare chip on the substrate, it can be realized by a plurality of bonding pads on the bare chip and the substrate. In the process, various chip packaging technologies such as a ball grid array (BallGrid) can be applied. Array, BGA), wire bonding, flip chip, etc. In order to ensure the miniaturization and diversification of electronic products or communication devices, semiconductor packages require small size, multi-pin connection, high speed, high power, and multi-function.

The increase in the number of input-output (I/O) pins, the increase in demand for high-performance ICs, and the increased demand for high-power LEDs have contributed to the development of flip-chip packaging technology. Flip-chip technology uses a plurality of bumps located on multiple bond pads of the chip to directly interconnect with the package medium. The chip faces the packaged medium through the shortest path. This technology can be applied not only to single-chip packages, but also to larger integrated packages of higher integration levels, as well as more sophisticated substrates that can accommodate several chips to form larger functional units. Flip-chip technology uses an area array that has the advantage of achieving the highest interconnect density with the device and lower interconnect inductance of the package.

However, conventional flip chip technology faces the challenge of bump spacing limitations on the substrate. In addition, high performance FCBGA packages are expensive due to the expensive chip carrier substrate (a typical chip carrier substrate containing 1+2+1 layer build material or more layers of build material). Due to the development of flip chip technology and the reduction of bump pitch, it is much slower than the shrinkage of the bare chip and the number of pins. Therefore, the bump between the substrates The distance is the bottleneck of the flip chip circuit diagram. Even if the shrinking of the bare chip in the future will exceed the resolution of the bump pitch of the substrate carrier. To overcome this technology gap, silicon interposer technology and through silicon via (TSV) technology are currently the only and expensive solutions. Therefore, there is a strong need in the industry for an improved flip chip packaging technology that is cost effective and addresses the bump spacing limitations on the substrate.

In addition, with the popularity of semiconductor LED lighting, the use of flip-chip packaging for semiconductor LED chips has become a trend. In addition to the common flip-chip package bonding method of eutectic, there are also newly emerging electromagnetic pulse solder bonding. The method is as described in the patent CN103094135 A (the full text of which is incorporated herein by reference); the advantage of this bonding method is that the chip electrode and the substrate electrode are atomically connected, which is very helpful for heat dissipation of the high power chip. However, in the process of development, it was found that the alignment accuracy of the chip electrode and the substrate electrode became a key factor affecting the packaging efficiency and the finished product when bonded by electromagnetic pulse welding.

Summary of the invention

The purpose of the invention is to solve the defects that the alignment precision of the chip electrode and the substrate electrode is poor, the pitch of the bump on the substrate is limited, and the cost is too high, and the alignment precision between the chip electrode and the substrate electrode is higher. And a lower cost flip chip packaging method and device.

In order to achieve the above object, the present invention adopts the following technical solutions:

A flip chip packaging method is characterized in that it comprises the following steps:

S1, bonding a chip to a substrate, wherein the chip comprises at least two electrodes, and the electrodes include at least one insulating region for isolating electrical connection between the electrodes, the substrate comprises Having at least one conductive region, after the chip and the substrate are bonded, the electrodes are electrically connected through the conductive region;

S2, separating the conductive region from the region where the conductive region overlaps the insulating region to form a plurality of electrically conductive regions that are insulated from each other.

Here, the prior art usually implants several metals on the electrodes of the chip for flip chip. The bumps are then bonded to the electrodes on the substrate by the bumped side, and the accuracy is limited by the pitch of the bumps. In the solution of the present invention, since the conductive region is disposed on the substrate, the conductive region covers the insulating region between the electrodes of the chip after the chip is bonded to the substrate, so that the precision requirement in the bonding process is greatly reduced (because the chip The point-to-point between the upper bump and the electrode of the substrate and the alignment of the chip with the insulating region on the substrate are very high in accuracy. In addition, after the bonding, since the electrodes of the chip are electrically connected through the conductive regions on the substrate, it is necessary to cut the electrical connection between the electrodes of the chip along the insulating region between the electrodes on the chip, so that the conductive region can be selected. A line segment on a region overlapping the insulating region of the chip, along which the conductive region is separated into a plurality of mutually insulated conductive segments that correspond one-to-one with the electrodes of the chip.

That is to say, since it is required to reduce the accuracy requirement of mutual alignment when the chip is bonded to the substrate, the alignment between the insulating region on the chip and the insulating region on the substrate requires high precision, and the solution of the present invention ignores the substrate. The insulating region is provided with a conductive region directly on the substrate to cover the insulating region on the chip. As a result, the accuracy requirements for bonding are greatly reduced, but the side effect is that there is an electrical connection between the electrodes of the chip, which cannot be used. In order to eliminate this side effect, it is necessary to cut off the electrical connection between the electrodes of the chip after bonding. In other words, the precision of the cutting/blocking required to cut the electrical connection between the electrodes of the chip is relative to the precision of the alignment of the insulating region on the chip with the insulating region on the substrate (it can also be understood as the alignment of the substrate electrode and the chip electrode). Accuracy) is easier to achieve.

In addition, the present invention can also be understood that after the substrate with a single electrode is bonded to the chip, the single electrode of the substrate is separated into a plurality of bonded electrodes that correspond one-to-one with the electrodes of the chip.

Preferably, the substrate is a single layer metal substrate.

Preferably, the substrate is a multilayer metal substrate.

That is to say, when a substrate made of metal is used, the entire substrate is a conductive region. Moreover, the substrate made of metal has the advantage of quick heat dissipation compared to the ceramic substrate of the prior art.

Preferably, the S2 is: cutting a region where the conductive region overlaps the insulating region by using a laser, so that the conductive region is divided to form a plurality of mutually insulated conductive regions.

Laser Beam Machining (LBM) is a high-energy beam processing that uses a laser beam with a high energy density to melt, vaporize, and evaporate the workpiece material. The laser is monochromatic light with high intensity, coherence and directionality. Through a series of optical systems, the laser beam can be focused to a spot diameter as small as a few microns, an energy density of up to 108-109 W/cm ² , and In a few seconds or even less, any meltable, indecomposable material is melted, evaporated, vaporized for processing purposes. Laser beam processing is mainly used in a series of processing processes such as forming, modifying and other materials such as punching, cutting, welding and surface treatment. In the past two decades, laser beam processing technology has developed very rapidly and has been widely used in industrial applications.

Here, laser cutting is easier to achieve a higher precision, or the cost of laser cutting to a higher precision is much lower than the cost of increasing the alignment accuracy of chip-chip bonding. The cutting forms a conductive partition that is insulated from each other in order to break the electrical connection between the electrodes of the chip.

Preferably, the S2 is:

The region where the conductive region overlaps the insulating region is cut by mechanical grinding or cutting such that the conductive region is divided to form a plurality of mutually insulated conductive regions.

Here, mechanical grinding or cutting is also possible.

Preferably, the S2 is:

A region in which the conductive region overlaps the insulating region is etched by development to expose the insulating region such that the conductive region separates to form a plurality of mutually insulated conductive regions.

Here, it is also possible to apply a corrosion-resistant layer on the substrate after bonding the substrate and the chip, such as development, and expose the position where the conductive region overlaps with the insulating region on the chip, and etch away the conductive region and the chip. After the conductors at the overlapping locations of the insulating regions, the electrical connections between the electrodes of the chip can also be broken.

Preferably, the conductive region is provided with at least one through groove for exposing the pattern recognition feature on the bonding side of the chip and the substrate.

Here, since the position of the insulating region on the chip needs to be accurately positioned when performing mechanical cutting or laser cutting of the substrate, after the through groove is provided, the side of the substrate from which the chip is not bonded can be used in the through-channel. The location identifies the graphical recognition features on the chip. E.g, When the insulating region is a thin straight line, two through grooves may be respectively disposed to expose a segment of the thin straight line for pattern recognition, or the through-groove may be used to expose the pattern identification point at other positions on the chip to indirectly position the insulating region. Positioning.

The invention further relates to a flip chip packaging device comprising a bonding device for bonding a chip to a substrate, characterized in that the flip chip packaging device uses a flip chip package as described above The method includes at least two electrodes including at least one insulating region for isolating an electrical connection between the electrodes, the substrate including at least one conductive region, and the chip and After the substrate is bonded, the electrodes are electrically connected through the conductive region;

Here, the bonding device may be a device adopting a process such as eutectic or reflow soldering, and the processes such as eutectic or reflow soldering are common means of the prior art, and are not described herein again.

The flip chip packaging apparatus further includes a separating device for separating the conductive regions from the conductive region and the insulating region to form a plurality of mutually insulated conductive regions.

Preferably, the separating device is configured to cut a region where the conductive region overlaps the insulating region using a laser, such that the conductive region is divided to form a plurality of mutually insulated conductive regions.

Preferably, the separating device is configured to cut a region where the conductive region overlaps the insulating region by mechanical grinding or cutting, so that the conductive region is divided to form a plurality of mutually insulated conductive regions.

The positive progress of the present invention is that by providing a conductive region on the substrate while bonding with all the electrodes on the chip, the conductive region is separated to form a conductive partition which is bonded and insulated from each other in one-to-one correspondence with the electrodes on the chip. The problem of the bump spacing limitation on the substrate in the packaging technology is solved at a lower cost, and the problem that the substrate electrode and the chip electrode alignment precision are difficult to control.

DRAWINGS

1 is a bottom perspective view showing a plurality of chips placed on a substrate according to Embodiment 1 of the present invention.

2 is a schematic structural view of a chip according to Embodiment 1 of the present invention.

FIG. 3 is a schematic structural view of a single chip bonded to a substrate according to Embodiment 1 of the present invention.

4 is a schematic structural view showing a state in which a corresponding position of an insulating portion between substrate extension chip electrodes is divided according to Embodiment 1 of the present invention.

FIG. 5 is a flowchart of a method for packaging a flip chip according to Embodiment 1 of the present invention.

detailed description

The invention is further illustrated by the following examples, which are not intended to limit the invention.

Example 1

FIG. 5 is a flowchart of a method for packaging a flip chip according to the embodiment. As shown in FIG. 5, the method for packaging a flip chip according to the embodiment includes the following steps:

Step 1. Bonding a chip to a substrate, wherein the chip includes at least two electrodes, and the electrodes include at least one insulating region for isolating electrical connection between the electrodes, and the substrate includes at least one conductive region. After the chip and the substrate are bonded, the electrodes are electrically connected through the conductive region;

Step 2: Cutting a region where the conductive region and the insulating region overlap by using a laser, so that the conductive region is divided to form a plurality of mutually insulated conductive regions.

Wherein, the conductive region is provided with at least one through groove for exposing the pattern recognition feature on the bonding side of the chip and the substrate.

The above-described flip chip packaging method will be further described below.

1 is a bottom perspective view of a plurality of chips placed on a substrate in the embodiment, FIG. 2 is a schematic structural view of the chip according to the embodiment, and FIG. 3 is a schematic structural view of the single chip bonded to the substrate in the embodiment; FIG. 4 is a schematic structural view showing the substrate at the corresponding position of the insulating portion between the extended chip electrodes of the embodiment.

As shown in FIGS. 1 to 4, the chip 100 has a size of 1000 μm, a width of 1000 μm, a thickness of 335 μm, a bottom electrode region, a positive electrode 102 having a size of 945×75 μm, and a negative electrode 105 having a size of 945×795. The micrometers have a separation distance between the positive electrode 102 and the negative electrode 105 of 75 micrometers.

First, a substrate is prepared. The substrate includes a plurality of 150 μm thick copper sheets 101 having a thickness of 15 μm. Each copper sheet 101 corresponds to a chip 100. The plane size of the copper sheet 101 is 2000. A square of micron x 2000 microns is described below as a unit.

The substrate is placed in a laser cutting table, and the center point of each copper piece 101 on the substrate (ie, the center point of the 2000 micrometer x 2000 micrometer unit) is confirmed, and the center point is cut to a length of 400 in the direction of the square side of the parallel unit. The through-holes 103 of micrometers and widths of 20 micrometers are parallel cut out of the same-sized through-grooves 103 at 250 micrometers apart from each other on the sides of the through-grooves 103. (It is convenient for the positioning and positioning of the chip 100 and the laser cutting electrode).

That is, the copper substrate is divided into a plurality of copper plate 101 units, and three through grooves 103 for exposing the pattern recognition features of the electrode spaces 104 of the chip 100 are laser-cutted on each of the copper sheets 101 (see FIG. 4).

The electrode surface of the chip 100 is placed on the gold-tin alloy plating layer of the copper sheet 101, the center of the chip 100 is aligned with the center of the copper sheet 101, and the electrode spacing 104 as an insulating region on the chip 100 is perpendicular to the three through grooves 103.

The substrate on which the chip is placed is placed in a eutectic furnace to achieve bonding, and since the eutectic process already has a mature process, it will not be described herein.

The chip and substrate that have been bonded are placed in a laser cutting table with the chip under and the substrate on top. Specifically, to the copper piece 101 of each unit, the laser cutting table grabs the position of the electrode spacing 104 between the positive electrode 102 and the negative electrode 105 of the chip 100 through the through groove 103 on each copper piece 101. The 101 is cut along the electrode spacing 104 such that the copper sheet 101 is split into conductive segments 111 and conductive segments 112 that are electrically connected to the positive and

negative electrodes

102, 105, respectively, of the chip 100 and are insulated from each other. Finally, the connection between the plurality of copper sheets 101 is cut to form a separate unit of the chip and the substrate package. Due to the mature process of laser cutting identification and cutting precision, it will not be repeated here.

In addition, the embodiment further relates to a flip chip packaging device including a eutectic device and a laser cutting device, and using the flip chip packaging method as described above.

Example 2

Embodiment 2 provides a flip chip packaging method and apparatus, and Embodiment 2 differs from Embodiment 1 in that:

After the substrate is bonded to the chip 100, after the electrode spacing 104 on the chip 100 is positioned according to the through-groove 103, a barrier tape is laid on each position of the copper wafer 101 corresponding to the electrode spacing 104 on the substrate, and then on the substrate. Apply a corrosion-resistant layer to it.

Thereafter, the barrier strip is uncovered, thus exposing the position where the copper sheet 101 overlaps the electrode spacing 104 on the chip 100, and after etching the conductor (ie, copper) at the exposed position, the electrodes of the chip 100 are interposed between the electrodes The electrical connection is in an open state.

While the invention has been described with respect to the embodiments of the present invention, it is understood that the scope of the invention is defined by the appended claims. A person skilled in the art can make various changes or modifications to these embodiments without departing from the principles and spirit of the invention, for example, by using a laser to cut a copper sheet, and mechanically cutting or the like to separate the substrate. The conductive region, or a substrate made of other metals/alloys or the like, or a reflow soldering process or the like without using eutectic bonding, etc., is within the scope of the present invention.

Claims

A flip chip packaging method is characterized in that it comprises the following steps:

S1, bonding a chip to a substrate, wherein the chip comprises at least two electrodes, and the electrodes include at least one insulating region for isolating electrical connection between the electrodes, the substrate comprises Having at least one conductive region, after the chip and the substrate are bonded, the electrodes are electrically connected through the conductive region;

S2, separating the conductive region from the region where the conductive region overlaps the insulating region to form a plurality of electrically conductive regions that are insulated from each other.
The method of packaging a flip chip according to claim 1, wherein the substrate is a single-layer metal substrate.
The method of packaging a flip chip according to claim 1, wherein the substrate is a multilayer metal substrate.
The method of packaging a flip chip according to at least one of claims 1 to 3, wherein the S2 is:

A region where the conductive region overlaps the insulating region is cut using a laser such that the conductive region is divided to form a plurality of mutually insulated conductive regions.
The method of packaging a flip chip according to at least one of claims 1 to 3, wherein the S2 is:

The region where the conductive region overlaps the insulating region is cut by mechanical grinding or cutting such that the conductive region is divided to form a plurality of mutually insulated conductive regions.
The method of packaging a flip chip according to at least one of claims 1 to 3, wherein the S2 is:

A region in which the conductive region overlaps the insulating region is etched by development to expose the insulating region such that the conductive region separates to form a plurality of mutually insulated conductive regions.
A method of packaging a flip chip according to at least one of claims 1 to 6, characterized in that The conductive region is provided with at least one through groove for exposing the pattern recognition feature on the bonding side of the chip and the substrate.
A flip chip packaging device comprising a bonding device for bonding a chip to a substrate, wherein the flip chip packaging device uses the device according to at least one of claims 1 to 7 a flip chip packaging method, the chip includes at least two electrodes, and the electrodes include at least one insulating region for isolating electrical connection between the electrodes, and the substrate includes at least one conductive region. After the chip and the substrate are bonded, the electrodes are electrically connected through the conductive region;

The flip chip packaging apparatus further includes a separating device for separating the conductive regions from the conductive region and the insulating region to form a plurality of mutually insulated conductive regions.
The package device of a flip chip according to claim 8, wherein the separating means is for cutting a region where the conductive region overlaps the insulating region by using a laser, so that the conductive region is divided into a plurality of sections. Conductive partitions that are insulated from each other.
A package device for flip chip according to claim 8, wherein said separating means is for cutting a region in which said conductive region overlaps said insulating region by mechanical grinding or cutting, such that said The conductive region is divided to form a plurality of electrically conductive regions that are insulated from each other.