TWI665774B - Electronic package and manufacturing method thereof - Google Patents

Abstract

An electronic package and a manufacturing method thereof are formed with a plurality of pointed portions at electrical contacts of a load-bearing structure, so that during the flip-chip manufacturing process, the pointed portions will penetrate the conductive bumps of the electronic components, so there is no need to use a flux. Effectively bonding the conductive bump and the electrical contact.

Description

Electronic package and manufacturing method thereof

The invention relates to an electronic package, in particular to a flip-chip electronic package and a method for manufacturing the same.

Known automated test equipment for semiconductor wafers, such as equipment equipped with test components, can quickly measure and produce test results, and can analyze the test results. In addition, with the development of the electronics industry, today's electronic products have been designed to be light, thin, short, and diversified in function. Semiconductor packaging technology has also developed different packaging types. Therefore, in order to meet the high integration and miniaturization requirements of semiconductor devices, in addition to the traditional wire bonding semiconductor packaging technology, the industry mainly uses flip chip semiconductor packaging technology. In order to improve the wiring density of the semiconductor package structure.

Figures 1A to 1B are schematic cross-sectional views of a conventional manufacturing method of a flip-chip package structure 1. As shown in FIG. 1A, a semiconductor wafer 11 is first bonded to the electrical contact pad 100 of a package substrate 10 through a plurality of solder bumps 13, and then the solder bump 13 is re-soldered. Next, as shown in FIG. 1B, a primer 14 is formed between the semiconductor wafer 11 and the package substrate 10 to cover the substrates. Solder bumps 13.

In the aforementioned process, before combining the solder bump 13 to the electrical contact pad 100, an oxide layer is usually formed on the outer surface of the solder bump 13; therefore, during the process of resoldering the solder bump 13, an auxiliary Flux (not shown) removes this oxide.

However, in the conventional manufacturing method of the flip-chip packaging structure 1, since a flux is required, the time for the reflow process is increased, and a part of the flux remains on the packaging structure 1, thereby generating a large soldering gap. As a result, the bonding between the solder bump 13 and the electrical contact pad 100 fails, resulting in poor reliability of the packaging structure 1.

In addition, if the diameter of the solder bump 13 is extremely small, there is a problem that part of the solder bump 13 is incompletely adhered when the flux is adhered.

On the other hand, although the oxide can be reduced by a controlled environment and then reflow soldering is performed, there is no need to use flux, but the process of this method is complicated, especially the process of mass producing the packaging structure 1 is more troublesome .

Therefore, how to overcome the problems of the above-mentioned conventional technologies has become an urgent problem to be overcome in the industry.

In view of the above-mentioned shortcomings of the conventional technologies, the present invention provides an electronic package including: a carrying structure having a plurality of electrical contacts; and an electronic component having a plurality of conductive bumps, so that the electronic component can borrow The conductive bumps are coupled to the electrical contacts of the load-bearing structure, wherein one of the electrical contacts or the conductive bumps is formed with a plurality of tips for insertion into the electrical contacts or the conductive In the other of the bumps.

The invention further provides a method for manufacturing an electronic package, which includes: providing a bearing structure having a plurality of electrical contacts and an electronic component having a plurality of conductive bumps, wherein the electrical contact or one of the conductive bumps is One is formed with a plurality of pointed portions; and the electronic component is coupled to the electrical contacts of the carrier structure through the conductive bumps, so that one of the electrical contacts or the conductive bumps The tip is inserted into the electrical contact or the other of the conductive bump.

In the aforementioned electronic package and its manufacturing method, the maximum planar width of the conductive bump is less than 25 microns.

In the aforementioned electronic package and its manufacturing method, one of the electrical contact or the conductive bump forms a rough surface, which has a plurality of the pointed portions. For example, there is a height difference between the tips, such as less than 1.5 microns.

In the aforementioned electronic package and its manufacturing method, the method further includes forming a surface treatment layer on the tip portion.

It can be known from the above that the electronic package and the manufacturing method thereof of the present invention mainly adopt a design in which a plurality of pointed portions are formed in one of the electrical contact or the conductive bump, so that when the electronic component is bonded to the supporting structure The tip can be inserted into the electrical contact or the other of the conductive bump, so the conductive bump does not need to be affixed with a flux. Therefore, compared with the conventional technology, the present invention can eliminate the need for a flux. Reducing the manufacturing process and shortening the manufacturing process time, and there is no residue of flux on the electronic package, so no coarse soldering gap is generated, and the problem of failure of the bonding between the conductive bump and the electrical contact can be avoided, In order to achieve the purpose of improving the reliability of the electronic package.

Furthermore, when the maximum planar size of the conductive bump is small (such as less than 25 Micron), after the conductive bump is re-soldered, the tip portion will be transformed into an interface alloy composite, so that the conductive bump and the electrical contact form a layer structure and complete integration, so the conductive bump can be avoided Problems with incomplete attachment.

In addition, the manufacturing method of the present invention does not need to reduce the oxide, so the manufacturing process is simple, so it is suitable for a production line for mass-producing the electronic package.

1‧‧‧ package structure

10‧‧‧ package substrate

100,200‧‧‧electric contact pad

11‧‧‧Semiconductor wafer

13‧‧‧solder bump

14‧‧‧ primer

2‧‧‧electronic package

20‧‧‧ bearing structure

20a‧‧‧first surface

20b‧‧‧Second surface

21‧‧‧Electronic components

21a‧‧‧active surface

21b‧‧‧ non-active surface

210‧‧‧ electrode pad

22‧‧‧electric contact

22a, 43a, 43b‧‧‧Rough surface

22b‧‧‧Interface alloy

220,420‧‧‧tip

23,43,43 ’‧‧‧ conductive bump

230‧‧‧Metal Department

231,431‧‧‧Soldering Department

232‧‧‧oxide

24‧‧‧ cladding

300‧‧‧Insulation protective layer

31‧‧‧Surface treatment layer

d‧‧‧width

t‧‧‧height difference

1A to 1B are schematic cross-sectional views of a conventional method for manufacturing a flip-chip package structure.

Figures 2A to 2C are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

Figure 2A 'is a partially enlarged sectional view of Figure 2A.

Figure 2B 'is a partially enlarged sectional view of Figure 2B.

Figure 2C 'is a partially enlarged sectional view of Figure 2C.

Figures 3A and 3B are partial enlarged cross-sectional views of different embodiments of the bearing structure of Figure 2A.

4A and 4B are partial enlarged cross-sectional views of different embodiments of the electronic component of FIG. 2A.

The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. Limitation Conditions, so it does not have technical significance, any structural modification, proportional relationship change, or size adjustment should still fall within the scope of the present invention without affecting the effects and goals that can be achieved by the present invention. The technical content disclosed must be within the scope. At the same time, the terms such as "first", "second", "upper", and "one" cited in the present specification are only for the convenience of description, and are not intended to limit the scope of the present invention. The change or adjustment of the relative relationship shall also be regarded as the scope in which the present invention can be implemented without substantially changing the technical content.

2A to 2C are schematic cross-sectional views of a method for manufacturing the electronic package 2 according to the present invention.

As shown in FIGS. 2A and 2A ′, an electronic component 21 and a supporting structure 20 having a plurality of electrical contacts 22 are provided, wherein a plurality of conductive bumps 23 are formed on the electronic component 21.

In this embodiment, the carrier structure 20 is, for example, a packaging substrate with a core layer and a circuit structure or a coreless circuit structure, which forms a circuit layer on a dielectric material, such as a fan-out ( fan out) redistribution layer (RDL), and has a first surface 20a and a second surface 20b opposite to each other, and the first surface 20a may be an insulating protection layer 300 (as shown in FIGS. 3A and 3B). (Shown as solder mask). Specifically, the electrical contact 22 (such as a bump) is provided on the first surface 20a and protrudes from the first surface 20a, that is, the electrical contact 22 is first made, and then the insulating protection layer 300 is formed. And the height of the insulation protection layer 300 can be designed according to requirements (as shown in the different heights in Figures 3A and 3B). It should be understood that the supporting structure 20 can also be other electronic components that can be used to support electronic components such as wafers. The carrying unit, such as a leadframe or a silicon interposer, is not limited to the above.

Furthermore, a plasma pre-treatment process is performed on the electrical contacts 22, so that the surface of the electrical contacts 22 becomes a rough surface 22a having a plurality of pointed portions 220, and each of the pointed portions 220 The heights are inconsistent, so that the highest tip 220 and the lowest tip 220 have a height difference t below 1.5 microns (um), such as between 1 and 1.5 microns. Specifically, the electrical contact 22 is pad-shaped (as shown in FIG. 2A '). Further, as shown in FIG. 3A, the electrical contact 22 is formed into a rough surface 22a by a plasma treatment process, and then a surface treatment layer 31 such as chemical nickel palladium immersion gold (ENEPIG) can be formed.

In addition, the electronic element 21 is an active element, a passive element, or a combination thereof, and the active element is, for example, a semiconductor wafer, and the passive element is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 21 is a semiconductor wafer, which has an active surface 21a and a non-active surface 21b opposite to the active surface 21a. The active surface 21a has a plurality of electrode pads 210, and conductive is formed on the electrode pads 210. Convex block 23.

In addition, as shown in FIGS. 2A and 2A ′, the conductive bump 23 has a metal portion 230 (such as a copper pillar) that is in contact with the electrode pad 210 and a solder portion 231 formed on the metal pillar 230. An oxide layer 232 is formed on the surface of the solder portion 231. The maximum planar width d of the conductive bump 23 is less than 25 microns.

As shown in FIGS. 2B and 2B ', the electronic component 21 is flip-chip bonded to the electrical contact 22 on the supporting structure 20 with the conductive bump 23.

In this embodiment, the tip portion 220 of the electrical contact 22 is inserted through the oxide layer 232 and inserted into the solder portion 231.

As shown in FIGS. 2C and 2C ′, the solder portion 231 of the conductive bump 23 is re-soldered, and then a coating layer 24 is formed on the first surface 20 a of the carrier structure 20 to cover the electrical contacts 22 and The conductive bumps 23.

In this embodiment, the coating layer 24 may be an insulating material such as a primer or a sealing gel, and is not particularly limited.

Furthermore, as shown in FIG. 2C ′, after re-soldering the solder portion 231, the pointed portions 220 and a portion of the solder portion 231 will become an inter-metallic compound (IMC) 22b, so that The tip portions 220 of the electrical contacts 22 form a layer structure due to the reaction with the solder portion 231, and have a thickness of about 1.5 micrometers or less, such as between 1 and 1.5 micrometers.

Therefore, the manufacturing method of the present invention is based on the design of the rough surface 22a of the electrical contact 22 having a plurality of pointed portions 220, so that when the electronic component 21 engages the bearing structure 20, the pointed portion 220 of the electrical contact 22 Will be inserted into the solder portion 231 of the conductive bump 23, so the conductive bump 23 does not need to be affixed with a flux. Compared with the conventional technology, the manufacturing method of the present invention can reduce the manufacturing process and shorten the processing time because no flux is required. , And a part of the flux does not remain on the electronic package 2, so no large soldering gap is generated, thereby avoiding the problem of the failure of the bonding between the conductive bump 23 and the electrical contact 22. The purpose of improving the reliability of the electronic package 2 is achieved.

Furthermore, when the maximum planar width d of the conductive bump 23 is small (for example, less than 25 microns), after re-soldering the solder portion 231, the pointed portions 220 and a portion of the solder portion 231 will become interface alloy composites 22b, make this conductive A layer structure is formed between the bumps 23 and the electrical contacts 22 for complete integration, so the problem of incomplete adhesion of the conductive bumps 23 can be avoided.

In addition, the manufacturing method of the present invention does not need to reduce the oxide layer 232, so the manufacturing process is simple, so it is suitable for being applied to a production line for mass-producing the electronic package 2.

In addition, as shown in FIGS. 4A and 4B, in another embodiment of the present invention, the electrical contacts are not formed with a rough surface, but the rough surfaces 43a, 43b are formed on the conductive bumps 43, 43 '. Specifically, as shown in FIG. 4A, the solder portion 431 of the conductive bump 43 is formed with a rough surface 43 a including a plurality of pointed portions 420; or, as shown in FIG. 4B, the conductive bump 43 ′ is made of metal only. The portion 230 is formed with a rough surface 43b including a plurality of pointed portions 420, and a solder material (an oxide layer is formed on the surface) is formed on the electrical contact 22, so that the conductive bumps 43,43 'have pointed portions. 420 is inserted into the solder material.

The present invention provides an electronic package 2 comprising: a carrying structure 20 and an electronic component 21.

The supporting structure 20 has a plurality of electrical contacts 22.

The electronic component 21 has a plurality of conductive bumps 23,43,43 ', so that the electronic component 21 is bonded to the electrical contact 22 through the conductive bumps 23,43,43'. One of the electrical contact 22 and the conductive bump 23,43,43 'has a plurality of tips 220,420 to be inserted into the other of the electrical contact 22 and the conductive bump 23,43,43' .

In one embodiment, the maximum planar width d of the conductive bumps 23,43,43 'is less than 25 microns.

In one embodiment, one of the electrical contact 22 and the conductive bump 23,43,43 'forms a rough surface 22a, 43a, 43b, which has a plurality of the tips 220,420. Specifically, there is a height difference t between the tips 220, 420. For example, the height difference t is less than 1.5 micrometers.

In one embodiment, the electronic package 2 includes a surface treatment layer 31 formed on the tip 220.

In summary, the electronic package and its manufacturing method of the present invention, by the design of the tip, makes it unnecessary to use a flux or a reduction oxide process in the manufacturing process, and can avoid the conductive bump and the electrical contact. The problem of poor joints between the two is therefore to improve the reliability of the product.

The above embodiments are used to exemplify the principle of the present invention and its effects, but not to limit the present invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

Claims (10)

An electronic package includes: a bearing structure having a plurality of electrical contacts; and an electronic component having a plurality of conductive bumps, so that the electronic component is coupled to the bearing structure through the conductive bumps. An electrical contact, wherein the maximum planar width of the conductive bump is less than 25 microns, and one of the electrical contact or the conductive bump is formed with a plurality of pointed portions for insertion into the electrical contact Or in the other of the conductive bumps. According to the electronic package of claim 1, wherein one of the electrical contact or the conductive bump is formed with a rough surface, wherein the rough surface has a plurality of the pointed portions. The electronic package according to item 1 of the scope of patent application, wherein there is a height difference between the plurality of tips. The electronic package according to item 3 of the scope of patent application, wherein the height difference is less than 1.5 micrometers. The electronic package according to item 1 of the scope of patent application, wherein a surface treatment layer is formed on the tip portion. An electronic package manufacturing method includes: providing a bearing structure having a plurality of electrical contacts and an electronic component having a plurality of conductive bumps, wherein one of the electrical contacts or the conductive bumps is formed There are a plurality of pointed portions, and the maximum plane width of the conductive bump is less than 25 micrometers; and the electronic component is combined with the electrical contact of the bearing structure through the conductive bump to make the electrical contact or the The tip of one of the conductive bumps is inserted into the electrical contact or the other of the conductive bumps. According to the method for manufacturing an electronic package as described in item 6 of the scope of the patent application, wherein one of the electrical contact or the conductive bump is formed with a rough surface, wherein the rough surface has a plurality of the pointed portions. According to the manufacturing method of the electronic package described in item 6 of the patent application scope, there is a height difference between the plurality of tips. According to the manufacturing method of the electronic package described in item 8 of the scope of the patent application, wherein the height difference is less than 1.5 micrometers. According to the method for manufacturing an electronic package described in item 6 of the scope of patent application, the method further includes forming a surface treatment layer on the tip portion.