TWI338945B - Flip chip packaging structure and manufacturing method thereof - Google Patents

Description

1338945 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a flip chip package structure and a method of fabricating the same, and a flip chip package structure for a flip chip bonded wafer on a substrate and a method of fabricating the same. [Prior Art]

After the integrated circuit is manufactured, it needs to be connected to other components, radiated, and protected by the outer casing, so it needs to be packaged. Due to the increasing integration of the Ultra Large Scale lntegrati0n (ULSI), the number of pins to be packaged has also increased. In addition, the form of packaging is diversified and the process of packaging is becoming more and more demanding. On the other hand, it is necessary to reduce wages, automation and non-welding. Furthermore, in order to be convenient to carry around, there are also a variety of light and thin packages.

In addition to the original two-row Duai In Line Package (DIP), there are also die carriers (Chip (5)), flip chip, Pin Grid Array (PGA), tape carrier. Tape Carrier, Hermetic Package, Grid Array (7)

Array; BGA), Quad Flat Package (QFp) 'Lead On Chip (LOC), Chip Scale Package (CSP), Bare Die, Tape Carrier Package (TCP), etc. In recent years, the change of the chipset in the package, from the early QFpl〇〇 and QFP208 "combination" has been simplified into a very simple two bridges of the South Bridge and the North Bridge 5 1338945

The package's package type has also been upgraded to the need to use a BGA with more than 300 feet and another BGA with up to 500 feet to meet the needs of functionality and high density. If the graphics chip is integrated in the future, In the future, the chipset needs to be packaged with a BGA of more than 600 feet. If the number of legs of the BGA is higher than 600 feet and Wire B〇nding is used as the way to connect the wires, the size of the component package is bound to face an excessive problem. If you change the BGA package of Flip Chip technology, you can solve the problem of oversize in the wire bonding.

question. Therefore, flip chip packaging technology for different product applications has arisen. These new packaging methods require the use of flip-chip technology of tin-lead bumps for their package bonding.

Most tin-lead bump processes involve three basic steps. The first step is to pre-clean and deoxidize the surface of the bump. The second step is reflow. The second step is post-cleaning. The step of reflowing is quite important. In the rejuvenation v. 'The left-handed reheated tin boat bump must be able to flow freely between the weld bead and the wire to create an airtight and strong joint. H is suitable for rejuvenation only on the surface to be joined. It can happen after the oxide of high (4). The 盥 _ 々 步骤 step can be used to remove impurities and oxidation of metal and bumps. The flux can be made from a variety of different materials in the pre-cleaning step month & the second step back to the reflow step (4) to facilitate the combination of the material and the wire 1 airtight and L©. High-acid-containing and rot-resistant preservatives are often used in the joint between the layers of the sputum to form a tight oxide layer formed on the surface of the wire. However, the pure nature of the auxiliaries is seriously stunned by the microelectronic components ^ ^ ΒΛ ^ ~ ~ 夂 札 亿 物 物 物 物 物 助 助 助 助 助 助 剂 剂 剂 剂 剂 剂 剂 剂 剂 剂 剂 剂 剂The size of the electronic components is constantly shrinking. Therefore, the pre-cleaning and deoxidation steps must be removed in the post-cleaning step. However, with the completion of the work 4_ "I want 6 1338945 the flux in the component gap is completely removed but very Difficulties. The reliability of the incomplete parts of the 7L piece of the gap towel (4) is greatly reduced. In addition, in the future, 'will make the jingle treatment and help _ sample will impact the environment step === no: = "When flux and cleaning solvent are used to make the manufacturing cost" [Explanation] Therefore, the aspect of the present invention is to provide a method for fabricating a daily packaging mechanism 2 by performing a flip chip bonding Pre-formed solder-preserving layer on the line "The surface of the coating can maintain good solderability, wherein the solder-preserving layer J disappears after the flip-chip bonding. The further aspect of the invention is to provide a kind of flip-chip package = make two = Overlay; _ pre-formed solder layer on the line: 乂 make the line layer table It can maintain good solderability, and it can withstand high temperature without disappearing after flip chip bonding. 曰,, 造 Π = Provide a flip chip package structure and its green paint to enter the body to cover the wafer And the circuit layer without using a circuit. In the example of the Japanese invention, the flip chip package structure includes at least a substrate, a corrugated sheet, a conductive portion, and a sealant. The substrate has an upper surface and a lower surface, and a plurality of blind holes are formed on the lower surface of the substrate, and the circuit layer is formed on the circuit layer of the substrate layer, wherein the circuit layer is formed with an itching-free layer to be emulsified, and the conductive portion is formed on the surface layer. In the blind via, and 7 1338945 is electrically connected to the circuit layer, the encapsulation system, coated and directly in contact with the wafer and layer. Moreover, according to an embodiment of the present invention, the method for fabricating the flip chip package structure comprises at least providing a substrate, wherein the substrate has an upper surface and a surface of τ; the wiring layer is formed on the surface of the substrate; and the blind hole is formed on the substrate. The underlying surface of the material; the solder layer is on the circuit layer; the flip chip is bonded to the circuit layer; the (4) colloid is on the germanium, the chip and the circuit layer; and the conductive portion is formed in the blind hole and electrically connected to the line Floor. Therefore, the flip chip package structure of the present invention can maintain good solderability on the surface of the wiring layer to perform flip chip bonding, and use a flux to perform a cleaning operation, thereby reducing the adverse effects of the flux. In addition, the overmolding structure of the present invention does not require the use of green lacquer for packaging, thereby simplifying the process and reducing the cost. [Embodiment] Referring to Figures 1 to 1F, a cross-sectional view showing a process of a flip chip package structure according to a first embodiment of the present invention is shown. The flip chip package structure 100 of the present embodiment includes a substrate 110, a wiring layer 120, a wafer 13A, a plurality of conductive portions 140, and a sealant 150. The lower surface of the base #11〇 is provided with a plurality of blind holes (1), the circuit layer 120 is formed on the upper surface of the substrate 110, the crystal #13 is bonded to the circuit layer 120, and the conductive portion 14 is formed in the blind The hole lu is electrically connected to the circuit layer 12G, and the (10) body 15G is coated and straight (four) touches the W 130 and the circuit layer 20, wherein the circuit layer 12 is pre-formed before the encapsulation 150 is coated. The solder layer 160 is used to avoid oxidation of the circuit layer 12 现 8 1338945. Referring to FIG. 1A, first, a substrate 110 is provided. The substrate 110 of the present embodiment is made of a "electrical material, for example: BT (Bismaleimide Triazine) thermosetting resin material, epoxy resin, ceramic or Plexiglass fiber. A conductive material layer 丨2〇 is formed on the upper surface of the substrate 11A, and is formed, for example, of a conductive material such as copper, nickel or gold. The line layer 120 is formed by referring to Fig. 1B''. The circuit layer 120 of the present embodiment is formed by patterning the conductive material layer 12, and the pattern of the conductive material layer 120 is, for example, lithography or laser etching, patterning the conductive material layer 120' into a line. The layer 12 is provided with a pad 121 and a contact 122. 4 Referring to Fig. 1C, next, a blind hole is formed on the lower surface of the substrate 丨1〇. The blind hole 111 is formed, for example, by laser drilling or mechanical drilling, wherein the blind hole 111 is disposed below the contact port 22 . Referring to FIG. 1D 'then', a solder resist layer 16 is formed on the wiring layer 12, and the material of the barrier layer 160 is, for example, an organic solder resist (1) (10) (10) (1) ^ Preservatives) 'Organic solder resist can be used in conductive materials ( For example, a metal film is formed on the surface of the compound and has a protective organic film (about 35 Å to protect the surface | 12G surface, to avoid oxidation, so that the surface of the circuit layer 120 can be kept good. Solderability. Referring to FIG. 1E, the flip chip bonding wafer 130 is on the wiring layer 12, which is heated by a Ref丨ow step to heat the solder bumps i7〇 (Bump). 5 pieces 130 of the pad 121 of the circuit layer 20. When the reflow step is performed, a high temperature (about 2 〇〇) is generated between the Ba piece 130 and the circuit layer 12 ,, so that the welding 1 9338945 layer 160 Thermal decomposition. Since the soldering layer 16 〇 can maintain the good tin-positive property of the bonding pad 121 in advance, the wafer 13 can be firmly bonded to the bonding pad 12 of the wiring layer 2 after the flip-chip bonding wafer 13 Next, the encapsulant 15 is applied to the wafer 130 and the wiring layer 120. The encapsulant 150 At least the wafer 13 〇 and the circuit layer 1200 are completely covered to achieve the encapsulation effect, and since the soldering layer 160 can be used to prevent oxidation before the encapsulant i is coated, the flip chip package structure 100 of the embodiment can be It is not necessary to use a green lacquer to cover the circuit layer. The encapsulant 50 of this embodiment can also cover the upper surface of the substrate , to increase the packaging effect. 凊 Refer to FIG. 1F, and then form a conductive portion! In the blind via 1 u, the conductive portion 140 is electrically connected to the circuit layer 12 . The conductive portion 14 is, for example, a solder ball ' and is connected to the contact 122 to serve as an external electrical connection of the wafer 13 . Therefore, the flip chip package structure of the present embodiment is completed. Since the solder resist layer 16 is formed in advance on the wiring layer 12 before the flip chip bonding of the wafer 130 to maintain good solderability, the circuit layer 12 can be prevented from occurring. Oxidation does not allow smooth flip-chip bonding, and it is possible to reduce the influence of the use of the flux without using a flux before the flip-chip bonding wafer 13 is used. Referring to FIG. 2, Illustrated in accordance with the present invention A top view of the flip chip package structure of the embodiment. In addition, a solder dam 18 〇 (Solder Dam) may be formed on the circuit layer 12 before the flip chip bonding to prevent the circuit layer 12G or solder during the flip chip bonding. The bumps 17G may flow arbitrarily due to high temperature, thereby avoiding a short circuit condition caused by the flip chip bonding of the wafers 13. The month refers to FIGS. 3A and 3B, and shows a discussion aa according to the second embodiment of the present invention. A process cross-sectional view of the package structure. The circuit layer 22 of the second embodiment is directly patterned on the upper surface of the substrate 10 110 as compared to the first and second panels of the first embodiment. At this time, the circuit layer 22 can be formed by deposition or printing to form a pattern such as m, thermal evaporation, chemical vapor deposition, reduced forging, thick film printing or parallel printing, and thus the substrate of the embodiment. The upper surface of m may not require the formation of a layer 12 of conductive material first. Referring to Figure 4, there is shown a cross-sectional view of a flip chip package structure in accordance with a third embodiment of the present invention. Compared with the first F-figure of the first embodiment, the substrate 31G of the third embodiment is a core; a layer for embedding the passive component a in the substrate 31, to form a king sigma passive component substrate, and the wafer 13 〇 The wiring layer 32 is bonded to the upper surface of the substrate 310. More than a month... Fig. 5 is a cross-sectional view showing a flip chip package structure in accordance with a fourth embodiment of the present invention. Compared with the first F-figure of the first embodiment, the material of the solder resist layer of the fourth embodiment has an organic solder resist which can withstand high temperature, and t does not thermally decompose during flip chip bonding. The solder resist 460 of the flip chip joint is integrated with the solder bump 47 , to electrically connect the wafer no and the wiring layer 12G, so that the solder resist layer of the fourth embodiment can prevent the circuit layer 丨 20 from occurring in advance. The oxidation is formed between the wafer 1 and the wiring layer 120 after the flip chip bonding. It can be seen from the above embodiments of the present invention that the flip chip package structure of the present invention is formed by preliminarily forming a floating layer on the circuit layer before the flip chip bonding, so that the surface of the line f can maintain good solderability, thereby eliminating the need for use. Flux to clean the action, reducing the adverse effects of the help (4), thereby improving the process yield. And = the invention of the flip chip package structure uses the sealant to cover the wafer and the circuit layer: no need to use green paint to cover the circuit layer. Therefore, the flip chip package of the present invention can greatly simplify the process and thereby reduce the manufacturing cost. 1338945 Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is to be understood that those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. [Simple description of the map]

The above and other objects, features, advantages and embodiments of the invention will be more apparent and understood. Detailed description of the drawings is as follows: FIGS. 1A to 1 f are diagrams showing a first embodiment according to the present invention. A process profile view of a flip chip package structure. Fig. 2 is a schematic plan view showing the flip chip package according to the first embodiment of the invention. 3A and 3B are process cross-sectional views showing a crystal package structure according to a second embodiment of the present invention. The flip chip package structure of the second embodiment Fig. 4 is a cross-sectional view showing the first embodiment of the present invention.

Figure 5 is a cross-sectional view showing a coating according to a fourth embodiment of the present invention. Crystal package structure 150: sealant 160: solder resist layer 170: solder bump 180: soldering field [main component symbol description] a: passive component 100: flip chip seal structure II 〇: substrate III: blind via 12 1338945 120 : circuit layer 220 : 120,: : conductive material layer 310 : 121 : pad 320 : 122 : contact 460 : 130 : wafer 470 : 140 : conductive portion circuit layer substrate circuit layer solder layer solder bump 13

Claims (1)

1338945 Amendment I 2010 8 [ij repairing public also Wu 1 * X. Patent application scope: 1 · A flip chip package structure, comprising at least: a substrate having an upper surface and a lower surface, wherein the lower surface is provided a plurality of blind holes; a circuit layer formed on the upper surface of the substrate, wherein the blind holes expose a portion of the circuit layer; at least one wafer, flip chip bonded to the circuit layer, wherein the circuit layer Firstly, a solder layer is formed to avoid oxidation of the circuit layer and disappear after flip-chip bonding of the wafer; a plurality of solder balls are formed in the blind vias, wherein the solder balls are directly and electrically Connected to the wiring layer; and a winning body' cladding and directly in contact with the wafer and the wiring layer. 2. The flip chip package structure of claim 2, wherein the material of the solder resist layer is a 保rganic S〇丨derabi丨ity Preservatives. 3. The flip chip package structure of claim 1, wherein the encapsulation system completely covers the upper surface of the substrate. 4. The flip chip package structure of claim 1, wherein the substrate is a dielectric material layer. 5. The flip-chip package structure according to claim 1, wherein the 14 1338945 is replaced by a core layer 6 of the replacement page substrate on August 6th, as in the patent application scope. The flip chip package structure further includes: at least one solder dam (Solder Dam) formed on the circuit layer 7. The flip chip package structure according to claim 1, wherein the blind hole system It is formed by laser drilling. 8. The flip chip sealing structure of claim 4, wherein the blind holes are formed by mechanical drilling. 9. The flip chip package structure of claim i wherein the circuit layer has a plurality of pads. The flip chip package structure according to the item (1), wherein the error is formed by the patterning step. The flip-chip structure described in the patterning step, wherein the structure described in the item of FIG. 1 is 15 2〇18月丨6曰Revised replacement page 2〇1〇August丨6 The flip chip package structure described in the above item 1 is modified, wherein the material of the circuit layer is copper as in the patent application. As claimed in the patent application, the material of the circuit layer is nickel. The flip-chip package structure of the invention, wherein the material of the circuit layer is gold. 16. A method of fabricating a flip chip package structure comprising at least: Forming a circuit layer on the upper surface of the substrate; forming a plurality of blind holes on the lower surface of the substrate, wherein the blind holes expose a portion of the circuit layer; forming a solder resist layer on the circuit layer Overmolding at least one wafer on the circuit layer; coating a gel on the wafer and the circuit layer; and forming a plurality of solder balls in the blind holes, wherein the solder balls are directly and electrically connected On the circuit layer. 17. The method of fabricating a flip chip package structure according to claim 16, wherein the solder resist layer disappears after the flip chip bonding the wafer and the wiring layer. 1338945 Aug. 6, 2010 Revision Replacement Page 18. The manufacture of the flip chip package structure as described in claim 16 of the patent application/the material of the solder resist layer is the Organic Solderability preservatives. 19. The method of manufacturing a flip chip package structure according to the above-mentioned item of the patent application, wherein the organic solder resist has high temperature resistance. 20. The method of fabricating a flip chip package structure according to claim 16, wherein the encapsulating system completely covers the upper surface of the substrate in the step of covering the wafer and the wiring layer. The method of manufacturing a flip chip package structure according to claim 16, wherein the encapsulation system directly contacts the wafer and the wiring layer in the step of covering the wafer and the wiring layer. The method of fabricating a flip chip package structure according to claim 16, wherein the substrate is a dielectric material layer. The method of manufacturing a flip chip structure according to claim 16, wherein the substrate is a core layer. The method of fabricating a flip chip package structure according to claim 16, wherein the method further comprises: forming at least one solder dam on the circuit layer. 17 丄 W8945 20th Anniversary, August 丨 6曰 Amendment to the tribute 25. The manufacturer of the flip chip package described in claim 16 is to have a plurality of pads. 26. The flip chip package method of claim 16, wherein the blind vias are formed by laser drilling. Method 2, 7. The manufacture of a flip chip package structure as described in claim 16, wherein the blind holes are formed by mechanical drilling. The method of manufacturing the flip chip package structure described in claim 16 of the method of claim 28, wherein the step of forming the circuit layer further comprises: ordering a patterning step to form the circuit layer. The method, which is to clarify the manufacture of the flip chip package structure described in the scope of the patent application, in which the patterning step is a step. Method 0: The fabrication of the flip chip package structure described in item 28 of the benefit range is made. The patterning step is a deposition-deposition step. Wherein, the material of the circuit layer is steel. Method 3, 1 甘 ^ Please request the manufacture of the flip chip package structure described in the scope of claim 32. The manufacture of the flip chip seal structure as described in claim 16 of the patent application 1338945 2010 August 16 曰 repair replacement Page method 'where the material of the circuit layer is nickel. 33. A method of fabricating a flip chip package structure according to claim 16 wherein the material of the circuit layer is gold. ^ 34 · A flip chip package structure, comprising at least: - a substrate having an upper surface and a lower surface, a plurality of blind holes; Wherein the lower surface is provided with a circuit layer formed on the upper surface of the substrate, wherein the blind holes expose a portion of the circuit layer; - a protective layer is formed on the circuit layer to avoid The circuit layer is oxidized, at least one wafer is flip-chip bonded to the circuit layer; a plurality of solder balls are formed in the blind holes, wherein the solder balls are directly and electrically connected to the circuit layer; and a colloid Covering the wafer and the wiring layer. 35. The flip chip package structure of claim 34, wherein: The material of the Xuanbao solder layer is 〇rganic s〇werabi丨ity Preservatives. 36. The flip chip package structure of claim 2, wherein the organic (4) system has high temperature resistance. 19 1338945 20|August 16th of the following year, the replacement page 37. The flip chip package structure, wherein the encapsulation system completely covers the upper surface of the substrate. 38. The flip chip sealing structure according to claim 34, wherein the substrate is a 39. A flip-chip structure as described in claim 34, wherein the substrate is a core layer. 40. The flip chip package structure according to claim 34, wherein at least The method includes: 'At least one solder dam (Solder Dam) formed on the circuit layer. 41. The flip chip package structure of claim 34, wherein the blind holes are laser drilled 42. The flip chip package structure of claim 34, wherein the blind vias are formed by mechanical drilling. 43. The flip chip seal of claim 34 The circuit layer has a plurality of soldering irons. The circuit layer described in claim 34 is formed by performing a patterning step. ', 20 1338945 August 2010 丨 6曰 Amendment Replacement Page 45. The flip-chip encapsulation mechanism is characterized in that the patterning step is an etching step. The silicon-on-chip package structure according to claim 34, wherein the material of the circuit layer is copper. 48. The flip chip package structure of claim ", wherein the material of the circuit layer is recorded. The flip chip package structure of claim 34, wherein the material of the circuit layer is gold. 50. A flip chip package structure, comprising at least: - a substrate 'having an upper surface and a lower surface, wherein the lower surface is provided with a plurality of blind holes; and the circuit layer is formed on the upper surface of the substrate The blind vias expose a portion of the wiring layer; the 'to y aa wafer includes a plurality of solder bumps and is flip-chip bonded to the wiring layer, wherein a protective layer is formed on the alpha layer to avoid the wiring layer Oxidation occurs and disappears after flip chip bonding of the wafer, the tan bumps are straight 21 1338945 A modified replacement page is bonded to the circuit layer on August 16, 2010; a plurality of solder balls are formed in the blind holes, wherein the solder balls are directly and electrically connected to the circuit layer; and a gel, a package The overlay is in direct contact with the wafer and the wiring layer. twenty two