TW201633468A - Package module and its substrate structure - Google Patents

Package module and its substrate structure Download PDF

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Publication number
TW201633468A
TW201633468A TW104107867A TW104107867A TW201633468A TW 201633468 A TW201633468 A TW 201633468A TW 104107867 A TW104107867 A TW 104107867A TW 104107867 A TW104107867 A TW 104107867A TW 201633468 A TW201633468 A TW 201633468A
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Taiwan
Prior art keywords
insulating layer
layer
conductive
circuit
circuit layer
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TW104107867A
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Chinese (zh)
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TWI559464B (en
Inventor
余俊賢
胡竹青
許詩濱
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恆勁科技股份有限公司
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Priority to TW104107867A priority Critical patent/TWI559464B/en
Publication of TW201633468A publication Critical patent/TW201633468A/en
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Publication of TWI559464B publication Critical patent/TWI559464B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device

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  • Studio Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A substrate structure is provided, including a first insulating layer; a first wiring layer connected to the first insulating layer; a plurality of first conductive pillars disposed in the first insulating layer and electrically connected to the first wiring layer; a second wiring layer disposed over the first insulating layer and electrically connected to the first conductive pillars; a plurality of second conductive pillars and a plurality of conductive bumps disposed over the second wiring layer; and a second insulating layer disposed over the first insulating layer, the second wiring layer, the second conductive pillars and the conductive bumps, wherein the second insulating layer is formed with an opening for exposing the conductive bumps therefrom and allowing a sensor to be disposed therein when applied to camera lenses to thereby reduce the overall thickness of the packing module.

Description

封裝模組及其基板結構 Package module and its substrate structure

本發明係有關一種基板結構,尤指一種用以埋設電子元件之基板結構。 The invention relates to a substrate structure, in particular to a substrate structure for embedding electronic components.

隨著電子產業的發達,現今的電子產品已趨向輕薄短小與功能多樣化的方向設計,半導體封裝技術亦隨之開發出不同的封裝型態。目前應用於感測器元件或相機鏡頭之電子元件大都仍採用打線(Wire bonding)封裝型式、或晶片直接板上封裝(Chip On Board,簡稱COB)型式。 With the development of the electronics industry, today's electronic products have been designed in a light, short, and versatile manner, and semiconductor packaging technologies have also developed different packaging types. Most of the electronic components currently used in sensor components or camera lenses are still in the wire bonding package type or the Chip On Board (COB) type.

如第1圖所示之相機模組(Camera module),係為習知打線型封裝模組1,其包括:一電路件10、一鏡片11、一封裝體12、一傳動件13、一支撐件(holder)14以及一相機鏡頭之IC電子元件18。所述之電路件10係為軟硬複合(Rigid-Flex)電路板,其具有複數電性接點100及外接排線102。所述之支撐件14係設於該電路件10上並承載該封裝體12。所述之封裝體12係封裝該電子元件18,且該封裝體12具有複數電性連接該電子元件18之線路層(圖略),該線路層之外接墊16藉由複數如金線之焊線19電性連接該電路件10之電性接點100。所述之電子元件18 之上表面係具有一外露於該封裝體12之感應區18a,以作為光感應之用。所述之傳動件13係音圈馬達(Voice Coil Motor,簡稱VCM),其設於該支撐件14上。所述之鏡片11係設於該傳動件13上並遮蓋該感應區18a。 The camera module shown in FIG. 1 is a conventional wire-type package module 1 including a circuit component 10, a lens 11, a package 12, a transmission member 13, and a support. A holder 14 and an IC electronic component 18 of a camera lens. The circuit component 10 is a Rigid-Flex circuit board having a plurality of electrical contacts 100 and an external cable 102. The support member 14 is disposed on the circuit member 10 and carries the package body 12. The package body 12 encloses the electronic component 18, and the package body 12 has a circuit layer (not shown) electrically connected to the electronic component 18. The external pad of the circuit layer is soldered by a plurality of wires such as gold wires. The wire 19 is electrically connected to the electrical contact 100 of the circuit component 10. The electronic component 18 The upper surface has a sensing region 18a exposed to the package 12 for light sensing. The transmission member 13 is a voice coil motor (VCM), which is disposed on the support member 14. The lens 11 is disposed on the transmission member 13 and covers the sensing area 18a.

如第1’圖所示之另一相機模組,係為習知打線型封裝模組1’,其包括:一封裝基板10’、一鏡片11、一透光件12’、一傳動件13、一支撐件14以及一相機鏡頭之IC電子元件18。所述之封裝基板10’係承載該電子元件18並藉由複數如金線之焊線19電性連接該電子元件18。所述之支撐件14係藉由黏膠140設於該封裝基板10’上並遮蓋該電子元件18,且該支撐件14具有一開口141。所述之電子元件18之上表面係具有一感應區18a,以作為光感應之用,且該感應區18a外露於該開口141。所述之透光件12’係例如玻璃,其設於該支撐件14之開口141之底端上並遮蓋該感應區18a。所述之傳動件13係音圈馬達(VCM),其設於該支撐件14之開口141之壁面上。所述之鏡片11係設於該傳動件13上並遮蓋該透光件12’。 Another camera module as shown in FIG. 1A is a conventional wire-type package module 1 ′, which includes: a package substrate 10 ′, a lens 11 , a light transmissive member 12 ′, and a transmission member 13 . , a support member 14 and an IC electronic component 18 of a camera lens. The package substrate 10' carries the electronic component 18 and is electrically connected to the electronic component 18 by a plurality of bonding wires 19 such as gold wires. The support member 14 is disposed on the package substrate 10' by the adhesive 140 and covers the electronic component 18, and the support member 14 has an opening 141. The upper surface of the electronic component 18 has a sensing area 18a for light sensing, and the sensing area 18a is exposed to the opening 141. The light transmissive member 12' is, for example, glass, which is disposed on the bottom end of the opening 141 of the support member 14 and covers the sensing region 18a. The transmission member 13 is a voice coil motor (VCM) which is disposed on a wall surface of the opening 141 of the support member 14. The lens 11 is disposed on the transmission member 13 and covers the light transmissive member 12'.

然而,習知打線型封裝模組1,1’之組成零部件繁多,導致成本較高,且組裝複雜度高。 However, the conventional wire-type package modules 1, 1' have a large number of components, resulting in high cost and high assembly complexity.

再者,該封裝模組1,1’之部件層數極多,導致整體模組之厚度難以減低及尺寸難以縮小。例如,該封裝模組1之傳動件13之厚度極厚,且該封裝體12與該傳動件13之間需以該支撐件14作結合,導致該封裝模組1之厚度難以降低,而該封裝體12與該傳動件13需於四邊佈設連接點 (如該外接墊16),導致模組尺寸難以縮小;或者,該封裝模組1’之支撐件14需覆蓋該電子元件18,導致其體積龐大,因而難以縮小該封裝模組1’之尺寸。 Moreover, the number of component layers of the package module 1, 1' is extremely large, which makes it difficult to reduce the thickness of the entire module and to reduce the size. For example, the thickness of the transmission member 13 of the package module 1 is extremely thick, and the support member 14 and the transmission member 13 are required to be joined by the support member 14 , which makes it difficult to reduce the thickness of the package module 1 . The package body 12 and the transmission member 13 need to be connected on four sides. (For example, the external pad 16), the module size is difficult to be reduced; or the support member 14 of the package module 1' needs to cover the electronic component 18, resulting in a large volume, so it is difficult to reduce the size of the package module 1' .

又,習知封裝模組1,1’中,該些焊線19具有一定的拉高線弧,使該支撐件14需具有一定的高度以使該傳動件13(或該透光件12’)不會碰觸該些焊線19,導致難以進一步薄化該打線型封裝模組1,1’。 Moreover, in the conventional package module 1, 1 ', the bonding wires 19 have a certain height of the arc, so that the support member 14 needs to have a certain height to make the transmission member 13 (or the transparent member 12' The solder wire 19 is not touched, which makes it difficult to further thin the wire-type package module 1, 1'.

另外,習知封裝模組1’中,該支撐件14與該封裝基板10’之間需用黏膠140連接,因而衍生對位問題與厚度增加之問題。 In addition, in the conventional package module 1', the adhesive member 14 and the package substrate 10' need to be connected by the adhesive 140, thereby causing problems of alignment problems and thickness increase.

因此,如何避免習知技術中之種種缺失,實已成為目前亟欲解決的課題。 Therefore, how to avoid all kinds of defects in the prior art has become a problem that is currently being solved.

鑑於上述習知技術之種種缺失,本發明提供一種基板結構,係包括:一第一絕緣層,係具有相對之第一表面及第二表面;一第一線路層,係嵌埋並結合於該第一絕緣層之第一表面;複數個第一導電柱體,係設於該第一絕緣層中並電性連接該第一線路層;一第二線路層,係設於該第一絕緣層之第二表面上並藉由該些第一導電柱體電性連接該第一線路層;複數個第二導電柱體與複數導電凸塊,係設於該第二線路層上;以及一第二絕緣層,係設於該第一絕緣層之第二表面上並包覆該第二線路層、該些第二導電柱體與該些導電凸塊,且該第二絕緣層上形成有至少一開口,以令該些導電凸塊外露於該開口。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a substrate structure comprising: a first insulating layer having opposite first and second surfaces; and a first circuit layer embedded in and bonded to the a first surface of the first insulating layer; a plurality of first conductive pillars are disposed in the first insulating layer and electrically connected to the first circuit layer; and a second circuit layer is disposed on the first insulating layer The first circuit layer is electrically connected to the first circuit layer by the first conductive pillars; the plurality of second conductive pillars and the plurality of conductive bumps are disposed on the second circuit layer; a second insulating layer is disposed on the second surface of the first insulating layer and covers the second circuit layer, the second conductive pillars and the conductive bumps, and the second insulating layer is formed with at least An opening is formed to expose the conductive bumps to the opening.

前述之基板結構中,該導電凸塊之表面係低於、高於或齊平該開口之底面。 In the foregoing substrate structure, the surface of the conductive bump is lower than, higher than or flush with the bottom surface of the opening.

前述之基板結構中,復包括形成於該第二絕緣層上之一第三線路層,其藉由該些第二導電柱體電性連接該第二線路層。又包括形成於該第三線路層上之複數個外接墊。亦包括形成於該第二絕緣層與該第三線路層上之一絕緣保護層。或包括形成於該第三線路層上之複數個第三導電柱體、及形成於該第二絕緣層上之一第三絕緣層,以令該第三絕緣層包覆該第三線路層與該些第三導電柱體,並包括形成於該第三絕緣層上之一第四線路層,以令該第四線路層藉由該些第三導電柱體電性連接該第三線路層。 In the foregoing substrate structure, a third circuit layer formed on the second insulating layer is electrically connected to the second circuit layer by the second conductive pillars. Also included are a plurality of external pads formed on the third circuit layer. Also included is an insulating protective layer formed on the second insulating layer and the third wiring layer. Or comprising a plurality of third conductive pillars formed on the third circuit layer, and a third insulating layer formed on the second insulating layer, so that the third insulating layer covers the third wiring layer and The third conductive pillars include a fourth wiring layer formed on the third insulating layer, so that the fourth wiring layer is electrically connected to the third wiring layer by the third conductive pillars.

前述之基板結構中,復包括一電路件,係設於該第一絕緣層之第一表面或第二表面上。 In the foregoing substrate structure, a circuit component is further disposed on the first surface or the second surface of the first insulating layer.

前述之基板結構中,復包括複數導電元件,係設於該第一絕緣層之第一表面上或該第二絕緣層上。 In the foregoing substrate structure, a plurality of conductive elements are included on the first surface of the first insulating layer or on the second insulating layer.

前述之基板結構中,若應用於相機鏡頭,本發明亦提供一種封裝模組,係包括:一前述之基板結構;以及至少一具有感應區之電子元件,係設於該開口中並電性連接至該些導電凸塊,且令該感應區外露於該開口,以降低整體模組之厚度。 In the foregoing substrate structure, if applied to a camera lens, the present invention also provides a package module comprising: a substrate structure as described above; and at least one electronic component having a sensing region disposed in the opening and electrically connected The conductive bumps are exposed to the opening to reduce the thickness of the overall module.

再者,該基板結構若應用於相機鏡頭中,因封裝體(或封裝基板)與支撐件(甚至電路件與傳動件)一併製作成該基板結構,故能有效降低該相機鏡頭之整體結構之厚度,且能大幅簡化零組件,因而能大幅降低製作成本及便 於組裝。 Furthermore, if the substrate structure is applied to a camera lens, the package body (or package substrate) and the support member (even the circuit component and the transmission component) are fabricated together to form the substrate structure, so that the overall structure of the camera lens can be effectively reduced. Thickness and greatly simplifying the components, thus significantly reducing production costs and For assembly.

又,前述之封裝模組中,復包括一遮蓋該感應區之透光件或鏡片。 Moreover, in the foregoing package module, a light transmissive member or a lens covering the sensing area is further included.

另外,前述之封裝模組中,復包括一設於該第二絕緣層上之傳動件。 In addition, the foregoing package module further includes a transmission member disposed on the second insulation layer.

1,1’,5a-5d‧‧‧封裝模組 1,1',5a-5d‧‧‧Package Module

10,28,38‧‧‧電路件 10,28,38‧‧‧circuit parts

10’‧‧‧封裝基板 10'‧‧‧Package substrate

100,280‧‧‧電性接點 100,280‧‧‧Electrical contacts

102,282‧‧‧外接排線 102,282‧‧‧External cable

11,52‧‧‧鏡片 11,52‧‧‧ lenses

12‧‧‧封裝體 12‧‧‧Package

12’,51‧‧‧透光件 12', 51‧‧‧ light transmissive parts

13,53‧‧‧傳動件 13,53‧‧‧ Transmission parts

14‧‧‧支撐件 14‧‧‧Support

140‧‧‧黏膠 140‧‧‧Viscos

141,250‧‧‧開口 141,250‧‧‧ openings

16,260,460‧‧‧外接墊 16,260,460‧‧‧External mat

18,50,50’‧‧‧電子元件 18,50,50’‧‧‧Electronic components

18a,50a‧‧‧感應區 18a, 50a‧‧ Sensing area

19,500’‧‧‧焊線 19,500’‧‧‧welding line

2,3,4,4’‧‧‧基板結構 2,3,4,4’‧‧‧substrate structure

20‧‧‧承載板 20‧‧‧Loading board

21‧‧‧第一線路層 21‧‧‧First line layer

21’‧‧‧第一導電柱體 21'‧‧‧First Conductive Cylinder

21a‧‧‧表面 21a‧‧‧Surface

21b‧‧‧端面 21b‧‧‧ end face

210‧‧‧電性連接墊 210‧‧‧Electrical connection pads

211‧‧‧導電跡線 211‧‧‧ conductive traces

22‧‧‧第二線路層 22‧‧‧Second circuit layer

22’‧‧‧第二導電柱體 22’‧‧‧Second conductive cylinder

23‧‧‧第一絕緣層 23‧‧‧First insulation

23a‧‧‧第一表面 23a‧‧‧ first surface

23b‧‧‧第二表面 23b‧‧‧ second surface

24‧‧‧導電凸塊 24‧‧‧Electrical bumps

25‧‧‧第二絕緣層 25‧‧‧Second insulation

250a‧‧‧底面 250a‧‧‧ bottom

26‧‧‧第三線路層 26‧‧‧ Third circuit layer

26’‧‧‧第三導電柱體 26'‧‧‧3rd conductive cylinder

27‧‧‧絕緣保護層 27‧‧‧Insulation protective layer

281‧‧‧功能接點 281‧‧‧ functional joints

29a,29b‧‧‧導電元件 29a, 29b‧‧‧ conductive elements

380‧‧‧開孔 380‧‧‧Opening

45‧‧‧第三絕緣層 45‧‧‧ third insulation layer

46‧‧‧第四線路層 46‧‧‧fourth circuit layer

500‧‧‧導電材料 500‧‧‧Electrical materials

第1圖係為習知封裝模組的立體局部切面示意圖;第1’圖係為習知另一封裝模組的剖面示意圖;第2A至2G圖係為本發明之基板結構之第一實施例之製法之剖視示意圖;其中,第2G’係為電路件之上視圖;第3A至3C圖係為本發明之基板結構之第二實施例之製法之剖視示意圖;第4圖係為本發明之基板結構之第三實施例之剖視示意圖;第4’圖係為本發明之基板結構之第四實施例之剖視示意圖;第5A及5A’圖係為應用本發明之基板結構之封裝模組之剖視示意圖;第5B及5B’圖係為應用本發明之基板結構之封裝模組之剖視示意圖;第5C及5C’圖係為應用本發明之基板結構之封裝模組之剖視示意圖;以及第5D及5D’圖係為應用本發明之基板結構之封裝模組之剖視示意圖。 1 is a schematic partial cross-sectional view of a conventional package module; FIG. 1A is a schematic cross-sectional view of another conventional package module; and FIGS. 2A to 2G are first embodiment of a substrate structure of the present invention; FIG. 3A to 3C are schematic cross-sectional views showing the manufacturing method of the second embodiment of the substrate structure of the present invention; FIG. 4 is a schematic cross-sectional view of the second embodiment; FIG. 4A is a cross-sectional view showing a fourth embodiment of the substrate structure of the present invention; and FIGS. 5A and 5A' are diagrams showing a substrate structure to which the present invention is applied. FIG. 5B and FIG. 5B are cross-sectional views of a package module to which the substrate structure of the present invention is applied; and FIGS. 5C and 5C' are diagrams of a package module to which the substrate structure of the present invention is applied. A schematic cross-sectional view; and a 5D and 5D' diagram are schematic cross-sectional views of a package module to which the substrate structure of the present invention is applied.

以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“下”、“第一”、“第二”、“第三”、“第四”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. At the same time, the terms "upper", "lower", "first", "second", "third", "fourth" and "one" as used in this specification are also for convenience only. It is to be understood that the scope of the invention is not limited by the scope of the invention.

第2A至2G圖係為本發明之基板結構2之第一實施例之製法之剖視示意圖。 2A to 2G are schematic cross-sectional views showing the manufacturing method of the first embodiment of the substrate structure 2 of the present invention.

如第2A圖所示,藉由圖案化製程於一承載板20上形成一第一線路層21,再於該第一線路層21上形成複數第一導電柱體21’。 As shown in FIG. 2A, a first wiring layer 21 is formed on a carrier 20 by a patterning process, and a plurality of first conductive pillars 21' are formed on the first wiring layer 21.

於本實施例中,該承載板20係為基材,例如銅箔基板或其它板體,並無特別限制。 In the present embodiment, the carrier 20 is a substrate, such as a copper foil substrate or other plate, and is not particularly limited.

再者,該第一線路層21係包含複數電性連接墊210與複數導電跡線211,且該第一導電柱體21’係為銅柱。 Furthermore, the first circuit layer 21 includes a plurality of electrical connection pads 210 and a plurality of conductive traces 211, and the first conductive pillars 21' are copper pillars.

如第2B圖所示,於該承載板20上形成一具有相對之第一表面23a及第二表面23b的第一絕緣層23,以令該第一絕緣層23包覆該第一線路層21與該些第一導電柱體21’,且該第一絕緣層23係藉其第一表面23a結合至該承載板20上。 As shown in FIG. 2B, a first insulating layer 23 having a first surface 23a and a second surface 23b opposite to each other is formed on the carrier 20 such that the first insulating layer 23 covers the first wiring layer 21. And the first conductive pillars 21', and the first insulating layer 23 is bonded to the carrier 20 by the first surface 23a thereof.

於本實施例中,該些第一導電柱體21’之一端面21b係外露於該第一絕緣層23之第二表面23b。 In this embodiment, one end surface 21b of the first conductive pillars 21' is exposed on the second surface 23b of the first insulating layer 23.

再者,該第一線路層21之表面21a係齊平該第一絕緣層23之第一表面23a。 Furthermore, the surface 21a of the first wiring layer 21 is flush with the first surface 23a of the first insulating layer 23.

又,該第一絕緣層23係以壓合或鑄模(molding)方式製作,且該第一絕緣層23係為鑄模化合物(molding compound)、介電材、如環氧樹脂(Epoxy)、聚醯亞胺(Polyimide,簡稱PI)、其它感光或非感光性材料等之有機樹脂。 Moreover, the first insulating layer 23 is formed by pressing or molding, and the first insulating layer 23 is a molding compound, a dielectric material, such as an epoxy resin (Epoxy), a polyfluorene. An organic resin such as an imide (PI) or other photosensitive or non-photosensitive material.

如第2C圖所示,於該第一絕緣層23之第二表面23b上形成一第二線路層22,以令該第二線路層22藉由該些第一導電柱體21’電性連接該第一線路層21。接著,於該第二線路層22上形成複數第二導電柱體22’與導電凸塊24,再於該第一絕緣層23之第二表面23b上形成一第二絕緣層25,以令該第二絕緣層25包覆該第二線路層22、該些第二導電柱體22’與導電凸塊24。 As shown in FIG. 2C, a second circuit layer 22 is formed on the second surface 23b of the first insulating layer 23, so that the second circuit layer 22 is electrically connected by the first conductive pillars 21'. The first circuit layer 21. Then, a plurality of second conductive pillars 22 ′ and conductive bumps 24 are formed on the second circuit layer 22 , and a second insulating layer 25 is formed on the second surface 23 b of the first insulating layer 23 to The second insulating layer 25 covers the second circuit layer 22 , the second conductive pillars 22 ′ and the conductive bumps 24 .

於本實施例中,該第二線路層22係直接連接該些第一導電柱體21’與導電凸塊24。 In the embodiment, the second circuit layer 22 directly connects the first conductive pillars 21' and the conductive bumps 24.

再者,該第二導電柱體22’係為銅柱,且該第二導電 柱體22’之一端面外露於該第二絕緣層25。 Furthermore, the second conductive pillar 22' is a copper pillar, and the second conductive One end face of the cylinder 22' is exposed to the second insulating layer 25.

又,該些導電凸塊24並未外露於該第二絕緣層25。 Moreover, the conductive bumps 24 are not exposed to the second insulating layer 25.

另外,該第二絕緣層25係以壓合或鑄模(molding)方式製作,且該第一絕緣層23係為鑄模化合物(molding compound)、介電材、如環氧樹脂(Epoxy)、聚醯亞胺(Polyimide,簡稱PI)、其它感光或非感光性材料等之有機樹脂。 In addition, the second insulating layer 25 is formed by pressing or molding, and the first insulating layer 23 is a molding compound, a dielectric material, such as an epoxy resin (Epoxy), and a polyfluorene. An organic resin such as an imide (PI) or other photosensitive or non-photosensitive material.

如第2D圖所示,於該第二絕緣層25上形成一第三線路層26,以令該第三線路層26藉由該些第二導電柱體22’電性連接該第二線路層22。接著,於該第三線路層26上形成複數外接墊260。 As shown in FIG. 2D, a third circuit layer 26 is formed on the second insulating layer 25, so that the third circuit layer 26 is electrically connected to the second circuit layer by the second conductive pillars 22'. twenty two. Next, a plurality of external pads 260 are formed on the third circuit layer 26.

如第2E圖所示,於該第二絕緣層25與該第三線路層26上形成一絕緣保護層27,且令該些外接墊260外露於該絕緣保護層27。 As shown in FIG. 2E, an insulating protective layer 27 is formed on the second insulating layer 25 and the third wiring layer 26, and the external pads 260 are exposed to the insulating protective layer 27.

於本實施例中,形成該絕緣保護層27之材質係如防焊層(solder mask)、介電材或鑄模化合物(Molding Compound)。 In the present embodiment, the material forming the insulating protective layer 27 is, for example, a solder mask, a dielectric material or a molding compound.

再者,該絕緣保護層27之表面可齊平或不齊平該些外接墊260之頂面,使該絕緣保護層27外露該些外接墊260之頂面。或者,該絕緣保護層27具有複數開孔,使該些外接墊260外露於各該開孔。 Moreover, the surface of the insulating protective layer 27 may be flush or not flush with the top surface of the external pads 260, so that the insulating protective layer 27 exposes the top surfaces of the external pads 260. Alternatively, the insulating protective layer 27 has a plurality of openings, such that the external pads 260 are exposed to the respective openings.

如第2F圖所示,自該絕緣保護層27向內延伸至該第二絕緣層25中以形成至少一開口250,令該些導電凸塊24外露於該開口250。 As shown in FIG. 2F, the insulating protective layer 27 extends inwardly into the second insulating layer 25 to form at least one opening 250, and the conductive bumps 24 are exposed to the opening 250.

於本實施例中,該開口250係以物理或化學方法製 作,包括但並不限於物理研磨、雷射燒灼、或化學蝕刻等,並非採用傳統銑刀成型方式製作,故可縮小該開口250於轉彎處之導角(如底面處、開口處)。 In the embodiment, the opening 250 is made by physical or chemical methods. The method includes, but is not limited to, physical grinding, laser ablation, or chemical etching, etc., and is not formed by a conventional milling cutter, so that the opening angle of the opening 250 at the turn (such as the bottom surface and the opening) can be reduced.

再者,該些導電凸塊24之表面係齊平、略高或略低於該開口250之底面250a。 Moreover, the surfaces of the conductive bumps 24 are flush, slightly higher or slightly lower than the bottom surface 250a of the opening 250.

如第2G圖所示,移除該承載板20,使該第一線路層21仍嵌埋於該第一絕緣層23之第一表面23a,再設置一電路件28於該第一絕緣層23之第一表面23a上。 As shown in FIG. 2G, the carrier board 20 is removed, so that the first circuit layer 21 is still embedded in the first surface 23a of the first insulating layer 23, and a circuit member 28 is disposed on the first insulating layer 23. On the first surface 23a.

於本實施例中,該電路件28係為軟硬複合(Rigid-Flex)電路板,其具有複數電性接點280、功能接點281(例如供電、散熱或接地等功能)及外接排線282,如第2G’圖所示,且該些電性接點280與功能接點281係電性連接該第一線路層21。 In this embodiment, the circuit component 28 is a Rigid-Flex circuit board having a plurality of electrical contacts 280, functional contacts 281 (such as power supply, heat dissipation or grounding) and external cables. 282, as shown in FIG. 2G', and the electrical contacts 280 and the functional contacts 281 are electrically connected to the first circuit layer 21.

再者,可形成複數導電元件29b於該第二絕緣層25上,且該些導電元件29b電性連接該些外接墊260,以藉由該些導電元件29b堆疊結合其它電子裝置(圖略)。具體地,該些導電元件29b係如焊球、焊錫凸塊、銅凸塊等。 Furthermore, a plurality of conductive elements 29b can be formed on the second insulating layer 25, and the conductive elements 29b are electrically connected to the external pads 260, so as to be combined with other electronic devices by the conductive elements 29b (not shown). . Specifically, the conductive elements 29b are such as solder balls, solder bumps, copper bumps, and the like.

第3A至3C圖係為本發明之基板結構3之第二實施例之製法之剖視示意圖。本實施例與第一實施例之差異僅在於該電路件之製程順序,其它製程大致相同,故以下僅詳述相異處。 3A to 3C are schematic cross-sectional views showing the manufacturing method of the second embodiment of the substrate structure 3 of the present invention. The difference between this embodiment and the first embodiment lies only in the process sequence of the circuit component, and the other processes are substantially the same, so only the differences will be described in detail below.

如第3A圖所示,接續第2B圖製程,設置一電路件38於該第一絕緣層23之第二表面23b上,且該電路件38形成有複數開孔380,以令該些第一導電柱體21’之端面21b 外露於該些開孔380。 As shown in FIG. 3A, following the process of FIG. 2B, a circuit member 38 is disposed on the second surface 23b of the first insulating layer 23, and the circuit member 38 is formed with a plurality of openings 380 to make the first End face 21b of the conductive cylinder 21' Exposed to the openings 380.

如第3B圖所示,係進行如第2C至2E圖所示之製程,其中,該第二線路層22係沿伸至該開孔380中以電性連接該些第一導電柱體21’。 As shown in FIG. 3B, the process shown in FIGS. 2C to 2E is performed, wherein the second circuit layer 22 extends along the opening 380 to electrically connect the first conductive pillars 21'. .

如第3C圖所示,係進行如第2F圖所示之製程,自該絕緣保護層27向內延伸至該第二絕緣層25中以形成至少一開口250,令該些導電凸塊24外露於該開口250。之後,移除該承載板20,使該第一線路層21外露於該第一絕緣層23之第一表面23a。 As shown in FIG. 3C, the process shown in FIG. 2F is performed, and the insulating protective layer 27 extends inwardly into the second insulating layer 25 to form at least one opening 250, so that the conductive bumps 24 are exposed. At the opening 250. Thereafter, the carrier board 20 is removed to expose the first circuit layer 21 to the first surface 23a of the first insulating layer 23.

第4圖係為本發明之基板結構4之第三實施例之剖視示意圖。本實施例與第一實施例之差異僅在於增層設計,其它製程大致相同,故以下僅詳述相異處。 Figure 4 is a schematic cross-sectional view showing a third embodiment of the substrate structure 4 of the present invention. The difference between this embodiment and the first embodiment is only in the layering design, and the other processes are substantially the same, so only the differences will be described in detail below.

如第4圖所示,接續第2D圖之製程,於該第三線路層26上形成複數第三導電柱體26’,且於該第二絕緣層25上形成一第三絕緣層45,以令該第三絕緣層45包覆該第三線路層26與該些第三導電柱體26’。 As shown in FIG. 4, following the process of FIG. 2D, a plurality of third conductive pillars 26' are formed on the third circuit layer 26, and a third insulating layer 45 is formed on the second insulating layer 25 to The third insulating layer 45 is wrapped around the third circuit layer 26 and the third conductive pillars 26'.

接著,於該第三絕緣層45上形成一第四線路層46,以令該第四線路層46藉由該些第三導電柱體26’電性連接該第三線路層26,再於該第四線路層46上形成複數外接墊460。 Then, a fourth circuit layer 46 is formed on the third insulating layer 45, so that the fourth circuit layer 46 is electrically connected to the third circuit layer 26 by the third conductive pillars 26'. A plurality of external pads 460 are formed on the fourth circuit layer 46.

之後,於該第三絕緣層45與該第四線路層46上形成一絕緣保護層27,且令該些外接墊460外露於該絕緣保護層27。 Then, an insulating protective layer 27 is formed on the third insulating layer 45 and the fourth wiring layer 46, and the external pads 460 are exposed to the insulating protective layer 27.

後續製程,係自該絕緣保護層27向內延伸至該第二絕 緣層25中以形成至少一開口250,令該些導電凸塊24外露於該開口250。最後,移除該承載板20,並設置該電路件28。 The subsequent process extends inward from the insulating protective layer 27 to the second The edge layer 25 is formed with at least one opening 250 to expose the conductive bumps 24 to the opening 250. Finally, the carrier 20 is removed and the circuit component 28 is placed.

因此,本發明可依需求增加線路層之層數及該開口250之深度,以提升產品之應用性。 Therefore, the present invention can increase the number of layers of the circuit layer and the depth of the opening 250 as needed to enhance the applicability of the product.

另外,第一與第三實施例中,該電路件28之下側可植設銲球或不植設銲球。 In addition, in the first and third embodiments, the solder ball or the solder ball is implanted on the lower side of the circuit member 28.

第4’圖係為本發明之基板結構4’之第四實施例之剖視示意圖。本實施例與上述各實施例之差異僅在於未設置該電路件,其它製程大致相同,故以下僅詳述相異處。 Fig. 4' is a schematic cross-sectional view showing a fourth embodiment of the substrate structure 4' of the present invention. The difference between this embodiment and the above embodiments is that the circuit component is not provided, and the other processes are substantially the same, so only the differences will be described in detail below.

如第4’圖所示,該第一絕緣層23未結合該電路件,且該第一線路層21外露於該第一絕緣層23之第一表面23a,故可形成複數導電元件29a於該第一絕緣層23之第一表面23a上,且該些導電元件29a電性連接該第一線路層21,以藉由該些導電元件29a堆疊結合其它電子裝置(圖略)。 As shown in FIG. 4', the first insulating layer 23 is not bonded to the circuit member, and the first circuit layer 21 is exposed on the first surface 23a of the first insulating layer 23, so that a plurality of conductive elements 29a can be formed thereon. The first surface 23a of the first insulating layer 23 is electrically connected to the first circuit layer 21 to be combined with other electronic devices (not shown) by the conductive elements 29a.

於本實施例中,該些導電元件29a係如焊球、焊錫凸塊、銅凸塊等。 In this embodiment, the conductive elements 29a are solder balls, solder bumps, copper bumps, and the like.

因此,本發明之基板結構2,3,4,4’係以封裝成型銅連接(Copper Connection in Molding,簡稱C2iM)技術製作,若將其應用於指紋辨識或影像感測器(Image Sensor)等產品,可一併製作電路件、封裝體(或封裝基板)與支撐件(holder)成為該基板結構2,3,4,4’,甚至可依需求一併製作音圈馬達(如第4圖所示之基板結構4),因而能獲取 較薄之結構,且能大幅簡化零組件,亦即僅需該基板結構2,3,4,4’與感測器元件進行組裝,故能大幅降低製作成本,且能輕易組裝。 Therefore, the substrate structure 2, 3, 4, 4' of the present invention is fabricated by a Copper Connection in Molding (C2iM) technology, and is applied to a fingerprint identification or an image sensor (Image Sensor). The product can be used to make a circuit component, a package (or package substrate) and a support (holder) into the substrate structure 2, 3, 4, 4', and even a voice coil motor can be produced according to requirements (such as Figure 4). The substrate structure shown 4) can thus be obtained The thinner structure and the simplification of the components are greatly simplified, that is, the substrate structure 2, 3, 4, 4' is assembled with the sensor elements, so that the manufacturing cost can be greatly reduced and the assembly can be easily performed.

再者,藉由該開口250之設計,使該感測器元件能埋設於該絕緣層中,故能降低整體封裝模組之厚度。 Moreover, the design of the opening 250 enables the sensor component to be buried in the insulating layer, thereby reducing the thickness of the overall package module.

又,由於電路件、封裝體(或封裝基板)與支撐件係一體製作,故無需用黏膠連接前述各部件,因而不會產生習知對位問題與厚度增加之問題。 Moreover, since the circuit member and the package (or the package substrate) are integrally formed with the support member, it is not necessary to connect the respective members with the adhesive, so that the problem of the conventional alignment and the increase in thickness do not occur.

另外,以下詳述各基板結構2,3,4,4’之應用,如第5A至5D’圖所示。 Further, the application of each of the substrate structures 2, 3, 4, 4' will be described in detail below, as shown in Figs. 5A to 5D'.

第5A及5A’圖係為本發明之基板結構2應用於相機鏡頭之封裝模組5a之其中一方式。 The 5A and 5A' drawings are one of the modes in which the substrate structure 2 of the present invention is applied to the package module 5a of the camera lens.

如第5A圖所示,於該開口250中設置至少一電子元件50,且該電子元件50電性連接該些導電凸塊24。接著,設置一透光件51於該開口250上,使該透光件51遮蓋該電子元件50之感應區50a,但該透光件51未接觸該電子元件50。 As shown in FIG. 5A, at least one electronic component 50 is disposed in the opening 250, and the electronic component 50 is electrically connected to the conductive bumps 24. Next, a light transmissive member 51 is disposed on the opening 250 such that the light transmissive member 51 covers the sensing region 50a of the electronic component 50, but the light transmissive member 51 does not contact the electronic component 50.

於本實施例中,該電子元件50係為感測器元件,例如半導體晶片結構,其上側具有一如光感區或指紋辨識之感應區50a,以令該感應區50a外露於該開口250。 In the embodiment, the electronic component 50 is a sensor component, such as a semiconductor wafer structure, and has an optical sensing area or a fingerprint sensing area 50a on the upper side to expose the sensing area 50a to the opening 250.

再者,該電子元件50係為覆晶封裝,其下側具有複數電極墊(圖略),其藉由印刷或點膠等之導電材料500(如焊料、凸塊或導電膠)固接並電性連接於該些導電凸塊24上。 Furthermore, the electronic component 50 is a flip chip package, and has a plurality of electrode pads (not shown) on the lower side thereof, which are fixed by a conductive material 500 (such as solder, bump or conductive paste) such as printing or dispensing. Electrically connected to the conductive bumps 24.

又,該透光件51係為濾光片或玻璃,如紅外線玻璃(infrared glass),其遮蓋該感應區50a。 Moreover, the light transmitting member 51 is a filter or glass, such as infrared glass, which covers the sensing region 50a.

另外,於其它實施例中,如第5A’圖所示,該電子元件50’亦可為打線封裝,其上側具有複數電極墊(圖略),其藉由複數焊線500’電性連接該些導電凸塊24,且該電子元件50’之下側藉由黏膠501設於該開口250之底面上,而該電子元件50下方的該第二線路層22上可不需形成該導電凸塊24。 In addition, in other embodiments, as shown in FIG. 5A', the electronic component 50' may also be a wire-bonding package having a plurality of electrode pads (not shown) on the upper side thereof, which are electrically connected by a plurality of bonding wires 500'. The conductive bumps 24, and the lower side of the electronic component 50' is disposed on the bottom surface of the opening 250 by the adhesive 501, and the conductive bumps are not required to be formed on the second circuit layer 22 under the electronic component 50. twenty four.

第5B及5B’圖係為本發明之基板結構3應用於相機鏡頭之封裝模組5b之其中一方式,其中,該透光件51可接觸該電子元件50,如第5B圖所示。 5B and 5B' are diagrams showing one embodiment of the substrate structure 3 of the present invention applied to the package module 5b of the camera lens, wherein the light transmissive member 51 can contact the electronic component 50 as shown in FIG. 5B.

第5C及5C’圖係為本發明之基板結構2,4應用於相機鏡頭之封裝模組5c之其中一方式,其中,可增設鏡片(lens)52。 The 5C and 5C' drawings are one of the modes in which the substrate structure 2, 4 of the present invention is applied to the package module 5c of the camera lens, wherein a lens 52 can be added.

如第5C圖所示,係於第4圖所示之基板結構4之開口250端處架設一鏡片52,即該鏡片52設於該絕緣保護層27上,以令該鏡片52遮蓋該感應區50a。 As shown in FIG. 5C, a lens 52 is disposed at the end of the opening 250 of the substrate structure 4 shown in FIG. 4, that is, the lens 52 is disposed on the insulating protective layer 27 so that the lens 52 covers the sensing area. 50a.

如第5C’圖所示,係於第2G圖所示之基板結構2之導電元件29b上設置一傳動件53,再將該鏡片52架設於該傳動件53上,以令該鏡片52遮蓋該感應區50a。 As shown in FIG. 5C', a transmission member 53 is disposed on the conductive member 29b of the substrate structure 2 shown in FIG. 2G, and the lens 52 is mounted on the transmission member 53 to cover the lens 52. Sensing area 50a.

第5D及5D’圖係為本發明之基板結構4’應用於相機鏡頭之封裝模組5d之其中一方式,其中,可將設於第一線路層21上之該些導電元件29a結合至一電路板(圖略)上。 The 5D and 5D' drawings are one of the modes of the package structure 5d applied to the camera lens of the substrate structure 4' of the present invention, wherein the conductive elements 29a disposed on the first circuit layer 21 can be combined into one On the circuit board (figure omitted).

於上述各封裝模組5a-5d中,可依需求形成絕緣填充 材(圖略)於該開口250中,以令該絕緣填充材包覆該電子元件50。 In each of the above package modules 5a-5d, an insulation fill can be formed according to requirements The material (not shown) is in the opening 250 such that the insulating filler covers the electronic component 50.

因此,上述各相機鏡頭係藉由將其所需之封裝體與支撐件(甚至傳動件)一併製作成該基板結構2,3,4,4’,故能減少組成零部件,因而能降低成本,且簡化組裝步驟。 Therefore, each of the above-mentioned camera lenses can be made into the substrate structure 2, 3, 4, 4' by combining the required package and the support member (or even the transmission member), so that the component parts can be reduced, thereby reducing Cost and simplify assembly steps.

再者,因相機鏡頭所需之封裝體與支撐件(甚至傳動件)係一併製作,故能控制各層之厚度,以縮小整體模組之厚度及尺寸。例如,該基板結構4之傳動件之厚度極厚,且該基板結構2,3,4,4’設依需求佈設連接點(如該電性連接墊210),以縮小該相機鏡頭之模組尺寸;或者,該基板結構2,3,4,4’之支撐件無需覆蓋該電子元件50,因而能縮小該封裝模組5a-5d之尺寸。 Furthermore, since the package required for the camera lens is made together with the support member (or even the transmission member), the thickness of each layer can be controlled to reduce the thickness and size of the overall module. For example, the thickness of the transmission member of the substrate structure 4 is extremely thick, and the substrate structure 2, 3, 4, 4' is provided with a connection point (such as the electrical connection pad 210) as needed to reduce the module of the camera lens. Alternatively, the support member of the substrate structure 2, 3, 4, 4' need not cover the electronic component 50, thereby reducing the size of the package module 5a-5d.

又,該電路件28直接貼合該第一絕緣層23,且該電子元件50設於該基板結構2,3,4,4’之開口250中,故能克服焊線之拉高線弧的問題,且若以如焊球之導電材料500結合該電子元件50,更不會產生弧度,而有利於降低整體結構之厚度,進而有效薄化該相機鏡頭。 Moreover, the circuit member 28 directly fits the first insulating layer 23, and the electronic component 50 is disposed in the opening 250 of the substrate structure 2, 3, 4, 4', so that the arc of the bonding wire can be overcome. The problem is that if the electronic component 50 is bonded by a conductive material 500 such as a solder ball, the curvature is not generated, and the thickness of the overall structure is reduced, thereby effectively thinning the camera lens.

此外,該相機鏡頭係可應用球柵陣列封裝(Ball Grid Array,簡稱BGA)或平面網格陣列封裝(Land Grid Array,簡稱LGA)。 In addition, the camera lens can be applied to a Ball Grid Array (BGA) or a Land Grid Array (LGA).

上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範 圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as follows. Listed around.

2‧‧‧基板結構 2‧‧‧Substrate structure

21‧‧‧第一線路層 21‧‧‧First line layer

21’‧‧‧第一導電柱體 21'‧‧‧First Conductive Cylinder

22‧‧‧第二線路層 22‧‧‧Second circuit layer

22’‧‧‧第二導電柱體 22’‧‧‧Second conductive cylinder

23‧‧‧第一絕緣層 23‧‧‧First insulation

23a‧‧‧第一表面 23a‧‧‧ first surface

23b‧‧‧第二表面 23b‧‧‧ second surface

24‧‧‧導電凸塊 24‧‧‧Electrical bumps

25‧‧‧第二絕緣層 25‧‧‧Second insulation

250‧‧‧開口 250‧‧‧ openings

26‧‧‧第三線路層 26‧‧‧ Third circuit layer

260‧‧‧外接墊 260‧‧‧External mat

27‧‧‧絕緣保護層 27‧‧‧Insulation protective layer

28‧‧‧電路件 28‧‧‧ Circuitry

29b‧‧‧導電元件 29b‧‧‧Conducting components

Claims (20)

一種基板結構,係包括:一第一絕緣層,係具有相對之第一表面及第二表面;一第一線路層,係嵌埋並結合於該第一絕緣層之第一表面;複數個第一導電柱體,係設於該第一絕緣層中並電性連接該第一線路層;一第二線路層,係設於該第一絕緣層之第二表面上並藉由該些第一導電柱體電性連接該第一線路層;複數個第二導電柱體與複數導電凸塊,係設於該第二線路層上;以及一第二絕緣層,係設於該第一絕緣層之第二表面上並包覆該第二線路層、該些第二導電柱體與該些導電凸塊,且該第二絕緣層形成有至少一開口,以令該些導電凸塊外露於該開口。 A substrate structure includes: a first insulating layer having opposite first and second surfaces; a first circuit layer embedded in and bonded to the first surface of the first insulating layer; a conductive pillar is disposed in the first insulating layer and electrically connected to the first circuit layer; a second circuit layer is disposed on the second surface of the first insulating layer and is formed by the first The conductive pillar is electrically connected to the first circuit layer; the plurality of second conductive pillars and the plurality of conductive bumps are disposed on the second circuit layer; and a second insulating layer is disposed on the first insulating layer And coating the second circuit layer, the second conductive pillars and the conductive bumps on the second surface, and the second insulating layer is formed with at least one opening to expose the conductive bumps to the second conductive layer Opening. 如申請專利範圍第1項所述之基板結構,其中,該導電凸塊之表面係低於、高於或齊平該開口之底面。 The substrate structure of claim 1, wherein the surface of the conductive bump is lower than, higher than or flush with the bottom surface of the opening. 如申請專利範圍第1項所述之基板結構,復包括形成於該第二絕緣層上之一第三線路層,該第三線路層並藉由該些第二導電柱體電性連接該第二線路層。 The substrate structure of claim 1, further comprising a third circuit layer formed on the second insulating layer, wherein the third circuit layer is electrically connected to the second conductive pillar Two circuit layers. 如申請專利範圍第3項所述之基板結構,復包括形成於該第三線路層上之複數個外接墊。 The substrate structure of claim 3, comprising a plurality of external pads formed on the third circuit layer. 如申請專利範圍第3項所述之基板結構,復包括形成 於該第二絕緣層與該第三線路層上之一絕緣保護層。 The substrate structure as described in claim 3 of the patent application, including the formation And protecting the protective layer from one of the second insulating layer and the third circuit layer. 如申請專利範圍第3項所述之基板結構,復包括形成於該第三線路層上之複數個第三導電柱體、及形成於該第二絕緣層上之一第三絕緣層,以令該第三絕緣層包覆該第三線路層與該些第三導電柱體。 The substrate structure of claim 3, further comprising a plurality of third conductive pillars formed on the third wiring layer, and a third insulating layer formed on the second insulating layer, so as to The third insulating layer covers the third circuit layer and the third conductive pillars. 如申請專利範圍第6項所述之基板結構,復包括形成於該第三絕緣層上之一第四線路層,以令該第四線路層藉由該些第三導電柱體電性連接該第三線路層。 The substrate structure of claim 6, further comprising a fourth circuit layer formed on the third insulating layer, so that the fourth circuit layer is electrically connected by the third conductive pillars. The third circuit layer. 如申請專利範圍第1項所述之基板結構,復包括一電路件,係設於該第一絕緣層之第一表面或第二表面上。 The substrate structure of claim 1, further comprising a circuit component disposed on the first surface or the second surface of the first insulating layer. 如申請專利範圍第1項所述之基板結構,復包括複數導電元件,係設於該第一絕緣層之第一表面上或該第二絕緣層上。 The substrate structure of claim 1, further comprising a plurality of conductive elements disposed on the first surface of the first insulating layer or on the second insulating layer. 一種封裝模組,係包括:一如申請專利範圍第1項所述之基板結構;以及至少一具有感應區之電子元件,係設於該開口中並電性連接至該些導電凸塊,且令該感應區外露於該開口。 The package module includes: a substrate structure as described in claim 1; and at least one electronic component having a sensing region disposed in the opening and electrically connected to the conductive bumps, and The sensing area is exposed to the opening. 如申請專利範圍第10項所述之封裝模組,其中,該導電凸塊之表面係低於、高於或齊平該開口之底面。 The package module of claim 10, wherein the surface of the conductive bump is lower than, higher than or flush with the bottom surface of the opening. 如申請專利範圍第10項所述之封裝模組,復包括形成於該第二絕緣層上之一第三線路層,該第三線路層並藉由該些第二導電柱體電性連接該第二線路層。 The package module of claim 10, further comprising a third circuit layer formed on the second insulating layer, the third circuit layer being electrically connected by the second conductive pillars The second circuit layer. 如申請專利範圍第12項所述之封裝模組,復包括形成 於該第三線路層上之複數外接墊。 Such as the package module described in claim 12, the complex includes formation a plurality of external pads on the third circuit layer. 如申請專利範圍第12項所述之封裝模組,復包括形成於該第二絕緣層與該第三線路層上之一絕緣保護層。 The package module of claim 12, further comprising an insulating protective layer formed on the second insulating layer and the third circuit layer. 如申請專利範圍第12項所述之封裝模組,復包括形成於該第三線路層上形成複數個第三導電柱體、及形成於該第二絕緣層上之一第三絕緣層,以令該第三絕緣層包覆該第三線路層與該些第三導電柱體。 The package module of claim 12, further comprising forming a plurality of third conductive pillars formed on the third circuit layer and a third insulating layer formed on the second insulating layer, The third insulating layer is coated with the third circuit layer and the third conductive pillars. 如申請專利範圍第15項所述之封裝模組,復包括形成於該第三絕緣層上之一第四線路層,以令該第四線路層藉由該些第三導電柱體電性連接該第三線路層。 The package module of claim 15 further comprising a fourth circuit layer formed on the third insulating layer, such that the fourth circuit layer is electrically connected by the third conductive pillars The third circuit layer. 如申請專利範圍第10項所述之封裝模組,復包括一電路件,係設於該第一絕緣層之第一表面或第二表面上。 The package module of claim 10, further comprising a circuit component disposed on the first surface or the second surface of the first insulating layer. 如申請專利範圍第10項所述之封裝模組,復包括複數導電元件,係設於該第一絕緣層之第一表面上或該第二絕緣層上。 The package module of claim 10, comprising a plurality of conductive elements disposed on the first surface of the first insulating layer or on the second insulating layer. 如申請專利範圍第10項所述之封裝模組,復包括一遮蓋該感應區之透光件或鏡片。 The package module of claim 10, further comprising a light transmissive member or a lens covering the sensing area. 如申請專利範圍第10項所述之封裝模組,復包括一設於該第二絕緣層上之傳動件。 The package module of claim 10, further comprising a transmission member disposed on the second insulation layer.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI639048B (en) 2017-05-22 2018-10-21 海華科技股份有限公司 Portable electronic device and image-capturing module thereof, and carrier assembly thereof
TWI689015B (en) * 2018-10-08 2020-03-21 開曼群島商鳳凰先驅股份有限公司 Electronic package and manufacturing method thereof
CN111003682A (en) * 2018-10-08 2020-04-14 凤凰先驱股份有限公司 Electronic package and manufacturing method thereof
TWI707191B (en) * 2019-09-26 2020-10-11 大陸商廣州立景創新科技有限公司 Optical module and manufacturing method thereof

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TWI482271B (en) * 2011-11-04 2015-04-21 King Dragon Internat Inc Image sensor package with dual substrates and the method of the same
CN103227164A (en) * 2013-03-21 2013-07-31 日月光半导体制造股份有限公司 Semiconductor package structure and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI639048B (en) 2017-05-22 2018-10-21 海華科技股份有限公司 Portable electronic device and image-capturing module thereof, and carrier assembly thereof
TWI689015B (en) * 2018-10-08 2020-03-21 開曼群島商鳳凰先驅股份有限公司 Electronic package and manufacturing method thereof
CN111003682A (en) * 2018-10-08 2020-04-14 凤凰先驱股份有限公司 Electronic package and manufacturing method thereof
TWI707191B (en) * 2019-09-26 2020-10-11 大陸商廣州立景創新科技有限公司 Optical module and manufacturing method thereof

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