TW201628152A - Electronic package structure - Google Patents

Electronic package structure Download PDF

Info

Publication number
TW201628152A
TW201628152A TW104101444A TW104101444A TW201628152A TW 201628152 A TW201628152 A TW 201628152A TW 104101444 A TW104101444 A TW 104101444A TW 104101444 A TW104101444 A TW 104101444A TW 201628152 A TW201628152 A TW 201628152A
Authority
TW
Taiwan
Prior art keywords
layer
package structure
electronic package
circuit layer
insulating
Prior art date
Application number
TW104101444A
Other languages
Chinese (zh)
Other versions
TWI611544B (en
Inventor
胡竹青
許詩濱
Original Assignee
恆勁科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 恆勁科技股份有限公司 filed Critical 恆勁科技股份有限公司
Priority to TW104101444A priority Critical patent/TWI611544B/en
Publication of TW201628152A publication Critical patent/TW201628152A/en
Application granted granted Critical
Publication of TWI611544B publication Critical patent/TWI611544B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73259Bump and HDI connectors

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

An electronic package structure is provided, including an insulating layer, an electronic element embedded in the insulating layer and having a sensing zone exposed from the insulating layer, and a first circuit layer disposed on the insulating layer and electrically connecting to the electronic element, thereby reducing the overall thickness of the electronic package structure.

Description

電子封裝結構 Electronic package structure

本發明係有關一種電子封裝結構,尤指一種能薄型化之電子封裝結構。 The invention relates to an electronic package structure, in particular to an electronic package structure which can be thinned.

隨著電子產業的發達,現今的電子產品已趨向輕薄短小與功能多樣化的方向設計,半導體封裝技術亦隨之開發出不同的封裝型態。 With the development of the electronics industry, today's electronic products have been designed in a light, short, and versatile manner, and semiconductor packaging technologies have also developed different packaging types.

目前應用於感測器元件或相機鏡頭之電子元件大都仍採用打線(Wire bonding)封裝型式、或晶片直接板上封裝(Chip On Board,簡稱COB)型式。 Most of the electronic components currently used in sensor components or camera lenses are still in the wire bonding package type or the Chip On Board (COB) type.

如第1A圖所示,習知打線型封裝結構1係包括:一基板10、一電子元件13以及一封裝膠體18。 As shown in FIG. 1A, the conventional wire-type package structure 1 includes a substrate 10, an electronic component 13, and an encapsulant 18.

所述之基板10係於上、下側設有第一線路層11與第二線路層12,且藉由形成於其中之通孔或盲孔型導電體14電性連接該第一與第二線路層11,12,並於上、下側形成第一絕緣保護層16與第二絕緣保護層17,以令部分該第一與第二線路層11,12外露於該第一與第二絕緣保護層16,17,且令複數導電元件15形成於該第二線路層12上。 The substrate 10 is provided with a first circuit layer 11 and a second circuit layer 12 on the upper and lower sides, and is electrically connected to the first and second through a via hole or a blind via type conductor 14 formed therein. The circuit layers 11, 12 are formed with a first insulating protective layer 16 and a second insulating protective layer 17 on the upper and lower sides to expose portions of the first and second circuit layers 11, 12 to the first and second insulating layers. The layers 16, 17 are protected and a plurality of conductive elements 15 are formed on the second wiring layer 12.

所述之電子元件13係為感測器元件,其形成於該基板 10上側並藉由複數金線130電性連接該第一線路層11,且該電子元件13之上表面係具有一感應區131以作為指紋辨識之用。 The electronic component 13 is a sensor component formed on the substrate The upper layer 10 is electrically connected to the first circuit layer 11 by a plurality of gold wires 130, and the upper surface of the electronic component 13 has a sensing region 131 for fingerprint identification.

所述之封裝膠體18係形成於該基板10上側並包覆該電子元件13與該些金線130。 The encapsulant 18 is formed on the upper side of the substrate 10 and covers the electronic component 13 and the gold wires 130.

於習知打線型封裝結構1中,該封裝膠體18覆蓋該感應區131上之有效感應之厚度d需極薄(否則無法感測),因而需極高的精度。 In the conventional wire-type package structure 1, the thickness d of the effective sensing of the encapsulant 18 covering the sensing region 131 needs to be extremely thin (otherwise, it cannot be sensed), and thus requires extremely high precision.

然而,該金線130具有一定的拉高線弧,且模封製程需具有足夠高度以使該封裝膠體18均勻覆蓋該電子元件13,導致難以控制該封裝膠體18之極薄厚度,以致於該打線型封裝結構1無法達到薄化之需求。 However, the gold wire 130 has a certain height of the arc, and the molding process needs to have a height sufficient to uniformly cover the electronic component 13 by the encapsulant 18, which makes it difficult to control the extremely thin thickness of the encapsulant 18, so that The wire-type package structure 1 cannot meet the demand for thinning.

第1B圖係為習知COB型封裝結構1’之剖面示意圖。如第1B圖所示,該COB型封裝結構1’係包括:一基板10’、一相機鏡頭之IC電子元件13、一透光件19以及一封裝膠體18,且該基板10’係可參考第1A圖所示之構造。 Fig. 1B is a schematic cross-sectional view showing a conventional COB type package structure 1'. As shown in FIG. 1B, the COB type package structure 1' includes: a substrate 10', an IC electronic component 13 of a camera lens, a light transmissive member 19, and an encapsulant 18, and the substrate 10' is referenced. The structure shown in Fig. 1A.

所述之電子元件13係形成於該基板10’上側並藉由複數金線130電性連接該基板10’,且該電子元件13之上表面係具有一感應區131以作為光感應之用。 The electronic component 13 is formed on the upper side of the substrate 10' and electrically connected to the substrate 10' by a plurality of gold wires 130. The upper surface of the electronic component 13 has a sensing region 131 for light sensing.

所述之透光件19係藉由複數支撐件190形成於該電子元件13之上表面並遮蓋該感應區131。 The light transmissive member 19 is formed on the upper surface of the electronic component 13 by a plurality of support members 190 and covers the sensing region 131.

所述之封裝膠體18係為非透光材,其形成於該基板10上側並包覆該透光件19、電子元件13與該些金線130,且該透光件19之上表面外露於該封裝膠體18。 The encapsulant 18 is a non-transparent material, and is formed on the upper side of the substrate 10 and covers the transparent member 19, the electronic component 13 and the gold wires 130, and the upper surface of the transparent member 19 is exposed. The encapsulant 18 is encapsulated.

於習知COB型封裝結構1’中,相機鏡頭需薄型化。惟,該電子元件13需黏貼於該基板10’上,且該透光件19需藉由該些支撐件190設於該電子元件13上,使得該COB型封裝結構1’之整體厚度不易薄型化。 In the conventional COB type package structure 1', the camera lens needs to be thinned. The electronic component 13 is to be adhered to the substrate 10 ′, and the transparent component 19 is disposed on the electronic component 13 by the support member 190 , so that the overall thickness of the COB package structure 1 ′ is not easy to be thin. Chemical.

為了解決上述問題,遂有應用半導體的矽穿孔(Through Silicon Via,簡稱TSV)技術進行封裝。如第1C圖所示,習知光感應封裝結構1”係包括:一矽基板10”以及一透光件19’。 In order to solve the above problems, there is a semiconductor silicon-on-silicon (Through Silicon Via, TSV) technology for packaging. As shown in Fig. 1C, the conventional photo-sensing package structure 1" includes a substrate 10" and a light-transmissive member 19'.

所述之矽基板10”係於上、下側設有第一線路層11與第二線路層12,且藉由形成於其中之導電矽穿孔100電性連接該第一線路層11與第二線路層12,並於上側形成感應區131,而下側形成絕緣保護層17’,以令部分該第二線路層12外露於該絕緣保護層17’,且令複數導電元件15形成於該第二線路層12之外露表面上。 The first substrate layer 11 and the second circuit layer 12 are disposed on the upper and lower sides, and the first circuit layer 11 and the second layer are electrically connected by the conductive germanium through holes 100 formed therein. The circuit layer 12 has a sensing region 131 formed on the upper side, and an insulating protective layer 17' is formed on the lower side to expose a portion of the second wiring layer 12 to the insulating protective layer 17', and the plurality of conductive elements 15 are formed in the first layer The two circuit layers 12 are exposed on the surface.

所述之透光件19’係藉由黏著層190’形成於該矽基板10”上側並遮蓋該感應區131。 The light transmissive member 19' is formed on the upper side of the crucible substrate 10" by an adhesive layer 190' and covers the sensing region 131.

惟,習知光感應封裝結構1”中,因製作導電矽穿孔100之成本昂貴、整合難度高、技術難度高,尤其是應用於感測器元件或相機鏡頭之電子元件均為高成本。 However, in the conventional light-sensing package structure 1", the cost of manufacturing the conductive perforation 100 is expensive, the integration difficulty is high, and the technical difficulty is high, especially the electronic components applied to the sensor element or the camera lens are high in cost.

因此,如何克服上述習知技術之種種問題,實已成為目前業界亟待克服之難題。 Therefore, how to overcome the various problems of the above-mentioned prior art has become a difficult problem to be overcome in the industry.

鑑於上述習知技術之種種缺失,本發明係提供一種電子封裝結構,係包括:一絕緣層,係具有相對之第一表面 與第二表面;一電子元件,係埋設於該絕緣層中,且具有外露於該絕緣層之第一表面的至少一感應區及複數電極墊;以及一第一線路層,係設於該絕緣層之第一表面上並接觸該些電極墊以電性連接該電子元件,且該第一線路層未遮蓋該感應區。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides an electronic package structure comprising: an insulating layer having a first surface opposite thereto And a second surface; an electronic component embedded in the insulating layer and having at least one sensing region and a plurality of electrode pads exposed on the first surface of the insulating layer; and a first circuit layer disposed on the insulating layer And contacting the electrode pads on the first surface of the layer to electrically connect the electronic component, and the first circuit layer does not cover the sensing region.

前述之電子封裝結構中,復包括一第二線路層,係結合於該絕緣層之第二表面並電性連接該第一線路層。又包括一絕緣保護層,係設於該絕緣層之第二表面與該第二線路層上,例如該絕緣保護層外露部分該第二線路層。或者,該第二線路層可接觸或未接觸該電子元件。 In the foregoing electronic package structure, a second circuit layer is further included on the second surface of the insulating layer and electrically connected to the first circuit layer. The method further includes an insulating protective layer disposed on the second surface of the insulating layer and the second wiring layer, for example, the insulating protective layer exposes the second wiring layer. Alternatively, the second circuit layer may or may not be in contact with the electronic component.

前述之電子封裝結構中,復包括一絕緣保護層,係設於該絕緣層之第一表面與該第一線路層上,且該絕緣保護層未遮蓋該感應區,例如該絕緣保護層外露部分該第一線路層。 The electronic package structure includes an insulating protective layer disposed on the first surface of the insulating layer and the first circuit layer, and the insulating protective layer does not cover the sensing region, for example, the exposed portion of the insulating protective layer The first circuit layer.

本發明另提供一種電子封裝結構,係包括:一絕緣層,係具有相對之第一表面與第二表面;一電子元件,係埋設於該絕緣層中,且具有外露於該絕緣層之第一表面的至少一感應區及複數電極墊;一第一線路層,係設於該絕緣層之第一表面上並接觸該些電極墊以電性連接該電子元件,且該第一線路層未遮蓋該感應區;以及一絕緣保護層,係遮蓋該感應區。 The present invention further provides an electronic package structure, comprising: an insulating layer having opposite first and second surfaces; an electronic component embedded in the insulating layer and having a first exposed surface of the insulating layer At least one sensing area and a plurality of electrode pads; a first circuit layer is disposed on the first surface of the insulating layer and is in contact with the electrode pads to electrically connect the electronic component, and the first circuit layer is uncovered The sensing area; and an insulating protective layer cover the sensing area.

前述之電子封裝結構中,復包括一第二線路層,係結合於該絕緣層之第二表面並電性連接該第一線路層。又包括另一絕緣保護層,係設於該絕緣層之第二表面與該第二 線路層上。該另一絕緣保護層外露部分該第二線路層。或者,該第二線路層可接觸或未接觸該電子元件。 In the foregoing electronic package structure, a second circuit layer is further included on the second surface of the insulating layer and electrically connected to the first circuit layer. In addition, another insulating protective layer is disposed on the second surface of the insulating layer and the second On the circuit layer. The other insulating protective layer exposes a portion of the second wiring layer. Alternatively, the second circuit layer may or may not be in contact with the electronic component.

前述之電子封裝結構中,該絕緣保護層復設於該絕緣層之第一表面與該第一線路層上,例如該絕緣保護層外露部分該第一線路層。 In the above electronic package structure, the insulating protective layer is disposed on the first surface of the insulating layer and the first circuit layer, for example, the insulating protective layer exposes the first circuit layer.

前述之兩種電子封裝結構中,復包括複數導電柱體,係埋設於該絕緣層中並電性連接該第一線路層與該第二線路層。 In the above two electronic package structures, the plurality of conductive pillars are embedded in the insulating layer and electrically connected to the first circuit layer and the second circuit layer.

前述之兩種電子封裝結構中,復包括設於該絕緣層之第二表面上之複數導電元件。 In the above two electronic package structures, a plurality of conductive elements disposed on the second surface of the insulating layer are further included.

前述之兩種電子封裝結構中,復包括一線路增層結構,係設於該絕緣層之第二表面上並電性連接該第一線路層。 The two electronic package structures include a line build-up structure disposed on the second surface of the insulating layer and electrically connected to the first circuit layer.

前述之兩種電子封裝結構中,復包括一透光件,係遮蓋於該電子元件之感應區上。 In the above two electronic package structures, a light transmissive member is included to cover the sensing area of the electronic component.

由上可知,本發明之電子封裝結構,主要藉由將該電子元件嵌埋於該絕緣層中,且該第一線路層電性連接該電子元件,故於製作時,無需考量習知打線之線弧或封裝膠體之厚度,因而容易控制該絕緣層之厚度,以達到更好均勻性及更薄的厚度。 As can be seen from the above, the electronic package structure of the present invention is mainly embedded in the insulating layer, and the first circuit layer is electrically connected to the electronic component. Therefore, it is not necessary to consider the conventional wire bonding during manufacture. The thickness of the line arc or encapsulant is such that it is easy to control the thickness of the insulating layer for better uniformity and thinner thickness.

1‧‧‧打線型封裝結構 1‧‧‧Wire type package structure

1’‧‧‧COB型封裝結構 1'‧‧‧COB type package structure

1”‧‧‧光感應封裝結構 1”‧‧‧Light-sensing package structure

10,10’‧‧‧基板 10,10’‧‧‧substrate

10”‧‧‧矽基板 10"‧‧‧矽 substrate

100‧‧‧導電矽穿孔 100‧‧‧ Conductive piercing

11,21‧‧‧第一線路層 11, 21‧‧‧ first circuit layer

12,22‧‧‧第二線路層 12,22‧‧‧second circuit layer

13,23‧‧‧電子元件 13,23‧‧‧Electronic components

130‧‧‧金線 130‧‧‧ Gold wire

131,231‧‧‧感應區 131,231‧‧‧sensing area

14‧‧‧通孔或盲孔型導電體 14‧‧‧through hole or blind via conductor

15,25‧‧‧導電元件 15,25‧‧‧ conductive elements

16,26,26’‧‧‧第一絕緣保護層 16,26,26’‧‧‧First insulation protection layer

17,27‧‧‧第二絕緣保護層 17,27‧‧‧Second insulation protection layer

17’‧‧‧絕緣保護層 17'‧‧‧Insulating protective layer

18‧‧‧封裝膠體 18‧‧‧Package colloid

19,19’,40‧‧‧透光件 19,19’,40‧‧‧Lighting parts

190‧‧‧支撐件 190‧‧‧Support

190’‧‧‧黏著層 190’‧‧‧Adhesive layer

2a-2e,3a-3c,4a-4b‧‧‧電子封裝結構 2a-2e, 3a-3c, 4a-4b‧‧‧ electronic package structure

20‧‧‧第一絕緣層 20‧‧‧First insulation

20a‧‧‧第一表面 20a‧‧‧ first surface

20b‧‧‧第二表面 20b‧‧‧second surface

200‧‧‧第二絕緣層 200‧‧‧Second insulation

23a‧‧‧作用面 23a‧‧‧Action surface

23b‧‧‧非作用面 23b‧‧‧Non-active surface

230‧‧‧電極墊 230‧‧‧electrode pads

24,302‧‧‧導電柱體 24,302‧‧‧Electrical cylinder

260‧‧‧第一開孔 260‧‧‧ first opening

270‧‧‧第二開孔 270‧‧‧Second opening

30‧‧‧線路增層結構 30‧‧‧Line layering structure

300‧‧‧介電層 300‧‧‧ dielectric layer

301‧‧‧線路層 301‧‧‧circuit layer

d‧‧‧厚度 D‧‧‧thickness

第1A圖係為習知打線型封裝結構之剖面示意圖;第1B圖係為習知COB型封裝結構之剖面示意圖;第1C圖係為習知光感應封裝結構之剖面示意圖; 第2A至2E圖係為本發明之電子封裝結構之第一實施例之各種態樣之剖視示意圖;其中,第2A’及2B’圖係為第2A及2B圖之另一方式;第3A至3C圖係為本發明之電子封裝結構之第二實施例之各種態樣之剖視示意圖;其中,第3A’及3B’圖係為第3A及3B圖之另一方式;以及第4A及4B圖係為本發明之電子封裝結構之第三實施例之各種態樣之剖視示意圖。 1A is a schematic cross-sectional view of a conventional wire-type package structure; FIG. 1B is a schematic cross-sectional view of a conventional COB-type package structure; and FIG. 1C is a schematic cross-sectional view of a conventional light-sensing package structure; 2A to 2E are schematic cross-sectional views showing various aspects of the first embodiment of the electronic package structure of the present invention; wherein, the 2A' and 2B' views are another mode of the 2A and 2B drawings; 3C is a schematic cross-sectional view of various aspects of a second embodiment of the electronic package structure of the present invention; wherein, FIGS. 3A' and 3B' are another mode of FIGS. 3A and 3B; and 4A and 4B is a cross-sectional view showing various aspects of a third embodiment of the electronic package structure of the present invention.

以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second", "one" and "the" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the invention without substantial changes.

第2A至2E圖係為本發明之電子封裝結構2a-2e之第 一實施例之各種態樣之剖視示意圖。本實施例之電子封裝結構2a-2e係可應用於例如指紋辨識或影像感測器之產品等。 2A to 2E are diagrams of the electronic package structure 2a-2e of the present invention. A schematic cross-sectional view of various aspects of an embodiment. The electronic package structure 2a-2e of the present embodiment can be applied to, for example, a product of a fingerprint recognition or image sensor.

如第2A圖所示,該電子封裝結構2a係包括:一第一絕緣層20、一第二絕緣層200、一電子元件23、一導電柱體24以及一第一線路層21和一第二線路層22。 As shown in FIG. 2A, the electronic package structure 2a includes a first insulating layer 20, a second insulating layer 200, an electronic component 23, a conductive pillar 24, and a first wiring layer 21 and a second. Circuit layer 22.

所述之第一絕緣層20係具有相對之第一表面20a與第二表面20b。於本實施例中,該第一絕緣層20係例如鑄模化合物(molding compound)、介電材(dielectric material)、如環氧樹脂(Epoxy)、聚醯亞胺(Polyimide,簡稱PI)、其它感光或非感光性材料等之有機樹脂,且於該第一絕緣層20之第一表面20a上可依需求形成一材質相同或不同於該第一絕緣層20之第二絕緣層200。其中,該第一絕緣層20與該第二絕緣層200亦可同時形成。 The first insulating layer 20 has opposite first and second surfaces 20a, 20b. In this embodiment, the first insulating layer 20 is, for example, a molding compound, a dielectric material, an epoxy resin (Epoxy), a polyimide (PI), or other photosensitive materials. Or an organic resin such as a non-photosensitive material, and a second insulating layer 200 having the same material or different from the first insulating layer 20 may be formed on the first surface 20a of the first insulating layer 20. The first insulating layer 20 and the second insulating layer 200 may also be formed at the same time.

所述之電子元件23係埋設於該第一絕緣層20中。於本實施例中,該電子元件23係為感測器元件,例如半導體晶片結構,其具有一作用面23a與相對該作用面23a之非作用面23b,該作用面23a上具有一如光感區或指紋感應之感應區231與複數電極墊230,以令該感應區231與該些電極墊230外露於該第一絕緣層20之第一表面20a。 The electronic component 23 is embedded in the first insulating layer 20. In this embodiment, the electronic component 23 is a sensor component, such as a semiconductor wafer structure, having an active surface 23a and an inactive surface 23b opposite to the active surface 23a. The active surface 23a has a light perception. The sensing area 231 and the plurality of electrode pads 230 are exposed to the sensing area 231 and the electrode pads 230 are exposed on the first surface 20a of the first insulating layer 20.

因該電子元件23嵌埋於該第一絕緣層20中,故於製作時,無需製作習知封裝膠體,因而能降低整體結構之厚度。 Since the electronic component 23 is embedded in the first insulating layer 20, it is not necessary to fabricate a conventional encapsulant at the time of fabrication, so that the thickness of the overall structure can be reduced.

所述之第一線路層21係設於該第一絕緣層20之第一 表面20a上並接觸該些電極墊230以電性連接該電子元件23,且該第一線路層21未遮蓋該感應區231。於本實施例中,係以圖案化製程之電鍍、沉積或蝕刻方式形成如銅材之第一線路層21。 The first circuit layer 21 is disposed on the first of the first insulating layer 20 The surface of the electrode pad 230 is electrically connected to the electronic component 23, and the first circuit layer 21 does not cover the sensing region 231. In the present embodiment, the first wiring layer 21 such as copper is formed by plating, deposition or etching in a patterning process.

於本實施例中,所述之電子封裝結構2a復包括一第二線路層22,係結合於該第一絕緣層20之第二表面20b。例如,該第二線路層22自該第二表面20b嵌埋於該第一絕緣層20中,其中,該第二線路層22之表面可齊平或略低於該第一絕緣層20之第二表面20b;或者,該第二線路層22亦可設於該第一絕緣層20之第二表面20b之上。 In the embodiment, the electronic package structure 2a includes a second circuit layer 22 bonded to the second surface 20b of the first insulating layer 20. For example, the second circuit layer 22 is embedded in the first insulating layer 20 from the second surface 20b, wherein the surface of the second circuit layer 22 may be flush or slightly lower than the first insulating layer 20. The second surface layer 22b may be disposed on the second surface 20b of the first insulating layer 20.

再者,係以圖案化製程之電鍍、沉積或蝕刻方式形成如銅材之第二線路層22。 Furthermore, a second wiring layer 22 such as a copper material is formed by electroplating, deposition or etching of a patterning process.

又,部分該第二線路層22可復接觸該電子元件23之非作用面23b,以供該電子元件23散熱。 Moreover, a portion of the second circuit layer 22 can contact the non-active surface 23b of the electronic component 23 for heat dissipation of the electronic component 23.

另外,所述之電子封裝結構2a復包括複數導電柱體24,係埋設於該第一絕緣層20中並電性連接該第一線路層21,使該第二線路層22藉由該些導電柱體24電性連接該第一線路層21,但該第一線路層21並未電性導通至該電子元件23之非作用面23b。 In addition, the electronic package structure 2a includes a plurality of conductive pillars 24 embedded in the first insulating layer 20 and electrically connected to the first circuit layer 21, so that the second circuit layer 22 is electrically conductive. The pillar 24 is electrically connected to the first wiring layer 21, but the first wiring layer 21 is not electrically connected to the inactive surface 23b of the electronic component 23.

於另一實施例中,如第2A’圖所示,該第二線路層22並未接觸該電子元件23之非作用面23b,亦即該第二線路層22與該電子元件23之非作用面23b之間具有該第一絕緣層20,且該第一線路層21、該些導電柱體24與該第二線路層22之導電路徑係延伸至該電子元件23之非作用面 23b下方。 In another embodiment, as shown in FIG. 2A', the second circuit layer 22 does not contact the non-active surface 23b of the electronic component 23, that is, the second circuit layer 22 and the electronic component 23 are inactive. The first insulating layer 20 is disposed between the faces 23b, and the conductive paths of the first circuit layer 21, the conductive pillars 24 and the second circuit layer 22 extend to the inactive surface of the electronic component 23. Below 23b.

因以該第一線路層21直接電性連接該電子元件23,故無需以打線方式電性連接該電子元件23與該第一線路層21,因而有利於降低整體結構之厚度。 Since the electronic component 23 is directly electrically connected to the first circuit layer 21, the electronic component 23 and the first wiring layer 21 need not be electrically connected by wire bonding, thereby reducing the thickness of the overall structure.

如第2B圖所示,係對應第2A圖之結構,所述之電子封裝結構2b復包括設於該第一絕緣層20之第二表面20b上之複數導電元件25。具體地,該些導電元件25係設於該第二線路層22上以電性連接該第二線路層22。 As shown in FIG. 2B, the electronic package structure 2b includes a plurality of conductive elements 25 disposed on the second surface 20b of the first insulating layer 20. Specifically, the conductive elements 25 are disposed on the second circuit layer 22 to electrically connect the second circuit layer 22.

於本實施例中,該些導電元件25係為各種態樣,如焊球、焊錫凸塊、銅凸塊等,並無特別限制。 In the present embodiment, the conductive elements 25 are in various aspects, such as solder balls, solder bumps, copper bumps, and the like, and are not particularly limited.

於另一方式中,如第2B’圖所示,係對應第2A’圖之結構,該第二線路層22並未接觸該電子元件23之非作用面23b,亦即該第二線路層22與該電子元件23之非作用面23b之間具有該第一絕緣層20。 In another aspect, as shown in FIG. 2B', corresponding to the structure of FIG. 2A', the second circuit layer 22 does not contact the non-active surface 23b of the electronic component 23, that is, the second circuit layer 22 The first insulating layer 20 is provided between the non-active surface 23b of the electronic component 23.

如第2C圖所示,係對應第2B圖之結構,所述之電子封裝結構2c復包括一第一絕緣保護層26’,係設於該第一絕緣層20之第一表面20a與該第一線路層21上,且該第一絕緣保護層26’未遮蓋該感應區231。例如,該第一絕緣保護層26’係為介電材。 As shown in FIG. 2C, the electronic package structure 2c includes a first insulating protective layer 26' disposed on the first surface 20a of the first insulating layer 20 and the first portion. A circuit layer 21 is disposed, and the first insulating protective layer 26' does not cover the sensing region 231. For example, the first insulating protective layer 26' is a dielectric material.

再者,該電子封裝結構2c亦可不形成該第二線路層22,使該些導電元件25可直接接觸地設於該導電柱體24上。 Furthermore, the electronic package structure 2c may not form the second circuit layer 22, so that the conductive elements 25 can be directly contacted on the conductive pillar 24.

如第2D圖所示之電子封裝結構2d,為依第2B及2C圖之另一態樣,該第一絕緣保護層26係為介電層或防焊層 (solder mask),且該第一絕緣保護層26外露部分該第一線路層21。例如,該第一絕緣保護層26具有複數第一開孔260,以令部分該第一線路層21外露於各該第一開孔260;或者(未圖示),可令該第一絕緣保護層之表面齊平該第一線路層之表面,使該第一絕緣保護層外露該第一線路層之頂面。 The electronic package structure 2d shown in FIG. 2D is another aspect of FIGS. 2B and 2C, and the first insulating protective layer 26 is a dielectric layer or a solder resist layer. (solder mask), and the first insulating protective layer 26 exposes a portion of the first wiring layer 21. For example, the first insulating protection layer 26 has a plurality of first openings 260 to expose a portion of the first circuit layer 21 to each of the first openings 260; or (not shown) to protect the first insulation The surface of the layer is flush with the surface of the first circuit layer such that the first insulating protective layer exposes the top surface of the first circuit layer.

又,所述之電子封裝結構2d復包括一第二絕緣保護層27,係設於該第一絕緣層20之第二表面20b與該第二線路層22上。例如,該第二絕緣保護層27係為介電層或防焊層(solder mask)。 Moreover, the electronic package structure 2d further includes a second insulating protective layer 27 disposed on the second surface 20b of the first insulating layer 20 and the second wiring layer 22. For example, the second insulating protective layer 27 is a dielectric layer or a solder mask.

另外,該第二絕緣保護層27外露部分該第二線路層22,以供結合該些導電元件25。例如,該第二絕緣保護層27具有複數第二開孔270,以令部分該第二線路層22外露於各該第二開孔270;或者(未圖示),可令該第二絕緣保護層之表面齊平該第二線路層之表面,使該第二絕緣保護層外露該第二線路層之頂面,以結合該些導電元件。 In addition, the second insulating protective layer 27 exposes a portion of the second wiring layer 22 for bonding the conductive elements 25. For example, the second insulating protection layer 27 has a plurality of second openings 270 to expose a portion of the second circuit layer 22 to each of the second openings 270; or (not shown) to protect the second insulation The surface of the layer is flush with the surface of the second circuit layer such that the second insulating protective layer exposes the top surface of the second circuit layer to bond the conductive elements.

如第2E圖所示之電子封裝結構2e,依第2C及2D圖之另一態樣,該第一絕緣保護層26’係遮蓋該感應區231,以密封該感應區231。 The electronic package structure 2e shown in Fig. 2E, according to another aspect of the 2C and 2D drawings, the first insulating protective layer 26' covers the sensing region 231 to seal the sensing region 231.

第3A至3C圖係為本發明之電子封裝結構3a-3c之第二實施例之各種態樣之剖視示意圖。本實施例與第一實施例之差異在於多層線路之設計,其它構造大致相同,故以下詳述差異處,而不贅述相同處。 3A to 3C are cross-sectional views showing various aspects of the second embodiment of the electronic package structure 3a-3c of the present invention. The difference between this embodiment and the first embodiment lies in the design of the multilayer circuit, and the other configurations are substantially the same, so the differences will be described in detail below, and the same points will not be described.

如第3A及3A’圖所示,係對應第2A及2A’圖之結構, 該電子封裝結構3a復包括一線路增層結構30,係設於該第一絕緣層20之第二表面20b上並藉由該第二線路層22與該些導電柱體24電性連接至該第一線路層21。 As shown in Figures 3A and 3A', the structure corresponding to Figures 2A and 2A' is The electronic package structure 3a further includes a line build-up structure 30 disposed on the second surface 20b of the first insulating layer 20 and electrically connected to the conductive pillars 24 via the second circuit layer 22 The first circuit layer 21.

於本實施例中,該線路增層結構30係具有至少一介電層300及設於該介電層300上之線路層301,且該線路層301藉由設於該介電層300中之導電柱體302電性連接該第二線路層22。 In the present embodiment, the circuit build-up structure 30 has at least one dielectric layer 300 and a circuit layer 301 disposed on the dielectric layer 300, and the circuit layer 301 is disposed in the dielectric layer 300. The conductive pillar 302 is electrically connected to the second circuit layer 22.

再者,該線路層301係外露於該介電層300,以供結合該些導電元件25。 Moreover, the circuit layer 301 is exposed to the dielectric layer 300 for bonding the conductive elements 25.

如第3B及3B’圖所示,係對應第2B及2B’圖所示之結構,該電子封裝結構3b可依照第2C或2D圖之構造之任一技術特徵作變化。舉例而言,依第2C圖之其中一技術特徵,將如介電層或防焊層之第一絕緣保護層26設於該第一絕緣層20之第一表面20a與該第一線路層21上,且該第一絕緣保護層26未遮蓋該感應區231。 As shown in Figs. 3B and 3B', in correspondence with the structures shown in Figs. 2B and 2B', the electronic package structure 3b can be changed in accordance with any of the technical features of the structure of the 2C or 2D. For example, according to one of the technical features of FIG. 2C, a first insulating protective layer 26 such as a dielectric layer or a solder resist layer is disposed on the first surface 20a of the first insulating layer 20 and the first wiring layer 21 The first insulating protective layer 26 does not cover the sensing region 231.

如第3C圖所示之電子封裝結構3c,係對應第2E圖所示之結構,即如介電材之第一絕緣保護層26’遮蓋該感應區231。 The electronic package structure 3c as shown in Fig. 3C corresponds to the structure shown in Fig. 2E, that is, the first insulating protective layer 26' such as a dielectric material covers the sensing region 231.

第4A及4B圖係為本發明之電子封裝結構4a,4b之第三實施例之各種態樣之剖視示意圖。本實施例與上述兩實施例之差異在於本實施例之電子封裝結構4a,4b係應用於相機鏡頭,例如新增透光件40之設計,其它構造大致相同,故以下詳述差異處,而不贅述相同處。 4A and 4B are cross-sectional views showing various aspects of a third embodiment of the electronic package structures 4a, 4b of the present invention. The difference between this embodiment and the above two embodiments is that the electronic package structures 4a, 4b of the present embodiment are applied to a camera lens, for example, the design of the new light transmissive member 40, and the other structures are substantially the same, so the differences are detailed below. Do not repeat the same place.

如第4A及4B圖所示,以第2D及3B圖為例,該電子 封裝結構4a,4b復包括一透光件40,例如鏡片或玻璃,其遮蓋於該電子元件23之感應區231上。例如,該透光件40黏貼於該第一絕緣保護層26上,而無需製作習知支撐件,故能降低整體結構之厚度。 As shown in Figures 4A and 4B, taking the 2D and 3B diagrams as an example, the electron The package structure 4a, 4b further comprises a light transmissive member 40, such as a lens or glass, which is covered on the sensing region 231 of the electronic component 23. For example, the light transmissive member 40 is adhered to the first insulating protective layer 26 without forming a conventional support member, so that the thickness of the overall structure can be reduced.

於本實施例中,如第4A圖所示之電子封裝結構4a,該第一絕緣保護層26之表面係為齊平該第一線路層21之表面。 In the present embodiment, as shown in FIG. 4A, the surface of the first insulating protective layer 26 is flush with the surface of the first wiring layer 21.

或者,如第4B圖所示之電子封裝結構4b,該第一絕緣保護層26係為包覆該第一線路層21。 Alternatively, as shown in FIG. 4B, the first insulating protective layer 26 covers the first wiring layer 21.

綜上所述,本發明之電子封裝結構2a-2e,3a-3c,4a-4b主要藉由將該電子元件23嵌埋於該第一絕緣層20中,且該第一線路層21電性連接該電子元件23,故於製作時,無需考量打線之線弧或封裝膠體之厚度,因而容易控制該第一絕緣層20之厚度,以達到更好均勻性及更薄的厚度。 In summary, the electronic package structures 2a-2e, 3a-3c, 4a-4b of the present invention are mainly embedded in the first insulating layer 20 by the electronic component 23, and the first circuit layer 21 is electrically Since the electronic component 23 is connected, it is not necessary to consider the thickness of the wire arc or the thickness of the encapsulant at the time of fabrication, so that the thickness of the first insulating layer 20 can be easily controlled to achieve better uniformity and a thinner thickness.

再者,因採用非半導體製程加工,故能降低製作成本。 Furthermore, since the non-semiconductor process is used, the manufacturing cost can be reduced.

又,該電子封裝結構2a-2e,3a-3c,4a-4b易於隨產品需求而調整結構及設計,故其設計彈性佳。 Moreover, the electronic package structures 2a-2e, 3a-3c, 4a-4b are easy to adjust the structure and design according to product requirements, so that the design flexibility is good.

另外,上述實施例係適用於平面網格陣列封裝(Land Grid Array,簡稱LGA)或球柵陣列封裝(Ball Grid Array,簡稱BGA)。 In addition, the above embodiments are applicable to a Land Grid Array (LGA) or a Ball Grid Array (BGA).

上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範 圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as follows. Listed around.

2a‧‧‧電子封裝結構 2a‧‧‧Electronic package structure

20‧‧‧第一絕緣層 20‧‧‧First insulation

20a‧‧‧第一表面 20a‧‧‧ first surface

20b‧‧‧第二表面 20b‧‧‧second surface

200‧‧‧第二絕緣層 200‧‧‧Second insulation

21‧‧‧第一線路層 21‧‧‧First line layer

22‧‧‧第二線路層 22‧‧‧Second circuit layer

23‧‧‧電子元件 23‧‧‧Electronic components

23a‧‧‧作用面 23a‧‧‧Action surface

23b‧‧‧非作用面 23b‧‧‧Non-active surface

230‧‧‧電極墊 230‧‧‧electrode pads

231‧‧‧感應區 231‧‧‧ Sensing area

24‧‧‧導電柱體 24‧‧‧Electrical cylinder

Claims (24)

一種電子封裝結構,係包括:一絕緣層,係具有相對之第一表面與第二表面;一電子元件,係埋設於該絕緣層中,且具有外露於該絕緣層之第一表面的至少一感應區及複數電極墊;以及一第一線路層,係設於該絕緣層之第一表面上並接觸該些電極墊以電性連接該電子元件,且該第一線路層未遮蓋該感應區。 An electronic package structure comprising: an insulating layer having opposite first and second surfaces; an electronic component embedded in the insulating layer and having at least one exposed on the first surface of the insulating layer a sensing region and a plurality of electrode pads; and a first circuit layer disposed on the first surface of the insulating layer and contacting the electrode pads to electrically connect the electronic component, and the first circuit layer does not cover the sensing region . 如申請專利範圍第1項所述之電子封裝結構,復包括一第二線路層,係結合於該絕緣層之第二表面並電性連接該第一線路層。 The electronic package structure of claim 1, further comprising a second circuit layer bonded to the second surface of the insulating layer and electrically connected to the first circuit layer. 如申請專利範圍第2項所述之電子封裝結構,復包括一絕緣保護層,係設於該絕緣層之第二表面與該第二線路層上。 The electronic package structure of claim 2, further comprising an insulating protective layer disposed on the second surface of the insulating layer and the second circuit layer. 如申請專利範圍第3項所述之電子封裝結構,其中,該絕緣保護層外露部分該第二線路層。 The electronic package structure of claim 3, wherein the insulating protective layer exposes a portion of the second circuit layer. 如申請專利範圍第2項所述之電子封裝結構,其中,該第二線路層接觸該電子元件。 The electronic package structure of claim 2, wherein the second circuit layer contacts the electronic component. 如申請專利範圍第2項所述之電子封裝結構,其中,該第二線路層未接觸該電子元件。 The electronic package structure of claim 2, wherein the second circuit layer does not contact the electronic component. 如申請專利範圍第1項所述之電子封裝結構,復包括複數導電柱體,係埋設於該絕緣層中並電性連接該第一線路層。 The electronic package structure of claim 1, further comprising a plurality of conductive pillars embedded in the insulating layer and electrically connected to the first circuit layer. 如申請專利範圍第1項所述之電子封裝結構,復包括設於該絕緣層之第二表面上之複數導電元件。 The electronic package structure of claim 1, further comprising a plurality of conductive elements disposed on the second surface of the insulating layer. 如申請專利範圍第1項所述之電子封裝結構,復包括一絕緣保護層,係設於該絕緣層之第一表面與該第一線路層上,且該絕緣保護層未遮蓋該感應區。 The electronic package structure of claim 1, further comprising an insulating protective layer disposed on the first surface of the insulating layer and the first circuit layer, and the insulating protective layer does not cover the sensing region. 如申請專利範圍第9項所述之電子封裝結構,其中,該絕緣保護層外露部分該第一線路層。 The electronic package structure of claim 9, wherein the insulating protective layer exposes a portion of the first circuit layer. 如申請專利範圍第1項所述之電子封裝結構,復包括一線路增層結構,係設於該絕緣層之第二表面上並電性連接該第一線路層。 The electronic package structure of claim 1, further comprising a line build-up structure disposed on the second surface of the insulating layer and electrically connected to the first circuit layer. 如申請專利範圍第1項所述之電子封裝結構,復包括一透光件,係遮蓋於該電子元件之感應區上。 The electronic package structure of claim 1, further comprising a light transmissive member covering the sensing area of the electronic component. 一種電子封裝結構,係包括:一絕緣層,係具有相對之第一表面與第二表面;一電子元件,係埋設於該絕緣層中,且具有外露於該絕緣層之第一表面的至少一感應區及複數電極墊;一第一線路層,係設於該絕緣層之第一表面上並接觸該些電極墊以電性連接該電子元件,且該第一線路層未遮蓋該感應區;以及一絕緣保護層,係遮蓋該感應區。 An electronic package structure comprising: an insulating layer having opposite first and second surfaces; an electronic component embedded in the insulating layer and having at least one exposed on the first surface of the insulating layer a sensing layer and a plurality of electrode pads; a first circuit layer disposed on the first surface of the insulating layer and contacting the electrode pads to electrically connect the electronic component, and the first circuit layer does not cover the sensing region; And an insulating protective layer covering the sensing area. 如申請專利範圍第13項所述之電子封裝結構,復包括一第二線路層,係結合於該絕緣層之第二表面並電性連接該第一線路層。 The electronic package structure of claim 13 further comprising a second circuit layer bonded to the second surface of the insulating layer and electrically connected to the first circuit layer. 如申請專利範圍第14項所述之電子封裝結構,復包括另一絕緣保護層,係設於該絕緣層之第二表面與該第二線路層上。 The electronic package structure of claim 14, further comprising another insulating protective layer disposed on the second surface of the insulating layer and the second circuit layer. 如申請專利範圍第15項所述之電子封裝結構,其中,該另一絕緣保護層外露部分該第二線路層。 The electronic package structure of claim 15, wherein the another insulating protective layer exposes a portion of the second circuit layer. 如申請專利範圍第14項所述之電子封裝結構,其中,該第二線路層接觸該電子元件。 The electronic package structure of claim 14, wherein the second circuit layer contacts the electronic component. 如申請專利範圍第14項所述之電子封裝結構,其中,該第二線路層未接觸該電子元件。 The electronic package structure of claim 14, wherein the second circuit layer does not contact the electronic component. 如申請專利範圍第13項所述之電子封裝結構,復包括複數導電柱體,係埋設於該絕緣層中並電性連接該第一線路層。 The electronic package structure of claim 13 further comprising a plurality of conductive pillars embedded in the insulating layer and electrically connected to the first circuit layer. 如申請專利範圍第13項所述之電子封裝結構,復包括設於該絕緣層之第二表面上之複數導電元件。 The electronic package structure of claim 13 further comprising a plurality of conductive elements disposed on the second surface of the insulating layer. 如申請專利範圍第13項所述之電子封裝結構,其中,該絕緣保護層復設於該絕緣層之第一表面與該第一線路層上。 The electronic package structure of claim 13, wherein the insulating protective layer is disposed on the first surface of the insulating layer and the first circuit layer. 如申請專利範圍第21項所述之電子封裝結構,其中,該絕緣保護層外露部分該第一線路層。 The electronic package structure of claim 21, wherein the insulating protective layer exposes a portion of the first circuit layer. 如申請專利範圍第13項所述之電子封裝結構,復包括一線路增層結構,係設於該絕緣層之第二表面上並電性連接該第一線路層。 The electronic package structure of claim 13 further comprising a line build-up structure disposed on the second surface of the insulating layer and electrically connected to the first circuit layer. 如申請專利範圍第13項所述之電子封裝結構,復包括一透光件,係遮蓋於該電子元件之感應區上。 The electronic package structure of claim 13 further comprising a light transmissive member covering the sensing area of the electronic component.
TW104101444A 2015-01-16 2015-01-16 Electronic package structure TWI611544B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW104101444A TWI611544B (en) 2015-01-16 2015-01-16 Electronic package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW104101444A TWI611544B (en) 2015-01-16 2015-01-16 Electronic package structure

Publications (2)

Publication Number Publication Date
TW201628152A true TW201628152A (en) 2016-08-01
TWI611544B TWI611544B (en) 2018-01-11

Family

ID=57181862

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104101444A TWI611544B (en) 2015-01-16 2015-01-16 Electronic package structure

Country Status (1)

Country Link
TW (1) TWI611544B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI620287B (en) * 2017-03-21 2018-04-01 矽品精密工業股份有限公司 Package structure and the manufacture thereof
TWI689015B (en) * 2018-10-08 2020-03-21 開曼群島商鳳凰先驅股份有限公司 Electronic package and manufacturing method thereof
CN111003682A (en) * 2018-10-08 2020-04-14 凤凰先驱股份有限公司 Electronic package and manufacturing method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100544007C (en) * 2005-11-16 2009-09-23 鸿富锦精密工业(深圳)有限公司 Encapsulation structure for image sensor
TWI313050B (en) * 2006-10-18 2009-08-01 Advanced Semiconductor Eng Semiconductor chip package manufacturing method and structure thereof
TWI562411B (en) * 2012-11-30 2016-12-11 Ind Tech Res Inst Package of optoelectronic device
US9324664B2 (en) * 2013-02-22 2016-04-26 Unimicron Technology Corp. Embedded chip package structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI620287B (en) * 2017-03-21 2018-04-01 矽品精密工業股份有限公司 Package structure and the manufacture thereof
TWI689015B (en) * 2018-10-08 2020-03-21 開曼群島商鳳凰先驅股份有限公司 Electronic package and manufacturing method thereof
CN111003682A (en) * 2018-10-08 2020-04-14 凤凰先驱股份有限公司 Electronic package and manufacturing method thereof

Also Published As

Publication number Publication date
TWI611544B (en) 2018-01-11

Similar Documents

Publication Publication Date Title
JP6548949B2 (en) Electronic package structure
US10304890B2 (en) Electronic device package and fabricating method thereof
TWI496270B (en) Semiconductor package and method of manufacture
TWI569390B (en) Electronic package and method of manufacture
TWI555098B (en) Electronic package structure and the manufacture thereof
TWI652787B (en) Electronic package and its manufacturing method
US9613894B2 (en) Electronic package
TWI594382B (en) Electronic package and method of manufacture
TW201603215A (en) Package structure and method of manufacture
US10204865B2 (en) Electronic package and conductive structure thereof
TW201320266A (en) Semiconductor package and method of fabricating the same
TWI559464B (en) Package module and its substrate structure
TWI591739B (en) Method of manufacture a package stack-up structure
TWI611544B (en) Electronic package structure
TW201926607A (en) Electronic package and method of manufacture
TWI612650B (en) Electronic package structure
TWI567843B (en) Package substrate and the manufacture thereof
TWI689015B (en) Electronic package and manufacturing method thereof
TWI606562B (en) Electronic package structure
US11417581B2 (en) Package structure
TWI672786B (en) Electronic package and method of manufacture
CN111003682A (en) Electronic package and manufacturing method thereof
TWM555065U (en) Electronic package and its package substrate
TW201318132A (en) Semiconductor package and fabrication method thereof
TWI607676B (en) Package substrate and its electronic package and the manufacture thereof