TWI594382B - Electronic package and method - Google Patents

Electronic package and method Download PDF

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Publication number
TWI594382B
TWI594382B TW105136121A TW105136121A TWI594382B TW I594382 B TWI594382 B TW I594382B TW 105136121 A TW105136121 A TW 105136121A TW 105136121 A TW105136121 A TW 105136121A TW I594382 B TWI594382 B TW I594382B
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TW
Taiwan
Prior art keywords
electronic component
insulating layer
layer
electronic
height
Prior art date
Application number
TW105136121A
Other languages
Chinese (zh)
Other versions
TW201818516A (en
Inventor
Mu Hsuan Chan
Yu Po Wang
Original Assignee
Siliconware Precision Industries Co Ltd
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Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW105136121A priority Critical patent/TWI594382B/en
Application granted granted Critical
Publication of TWI594382B publication Critical patent/TWI594382B/en
Publication of TW201818516A publication Critical patent/TW201818516A/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Description

Electronic package and its manufacturing method

The present invention relates to a semiconductor packaging technology, and more particularly to a multi-chip electronic package and a method of fabricating the same.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. Currently used in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (MCM) A crystalline package module, or a three-dimensional stacking of wafers into a three-dimensional integrated circuit (3D IC) wafer stacking technology.

1A to 1B are cross-sectional views showing a conventional multi-wafer module packaging process.

As shown in FIG. 1A, the first wafer 11 and the second wafer 12 are disposed on the release layer 10a of a carrier 10 by an adhesive layer 100, and are molded to form an encapsulant 13 so that the encapsulant 13 is formed. The first and second wafers 11, 12 are coated. Specifically, the first wafer 11 and the second wafer 12 are provided with a metal pillar 15 and a first passivation layer 101, 102, and the metal pillar 15 is covered with a second passivation layer 14.

As shown in FIG. 1B, a portion of the encapsulant 13 and the first and second passivation layers 101, 102, 14 are removed by polishing to expose the metal post 15 to the encapsulant 13.

However, in the conventional multi-wafer module packaging process, when performing the polishing process, the total thickness (such as the thickness of the first passivation layer 101, 102, the second passivation layer 14, and the encapsulant 13) of each layer must be considered and controlled. That is, the multilayer passivation layer must be ground so that the process capability of the polishing process is insufficient, resulting in over-grinding or workability problems. In particular, when the original thickness of the first wafer and the second wafer are different, if the first passivation layer and the second passivation layer are superposed, the total thickness of the two layers will be significantly different, resulting in over-grinding problems or partial portions of the wafer. The wafer will have insufficient grinding problems.

Therefore, how to overcome the shortcomings of the prior art is a technical problem that is currently being solved by all walks of life.

In view of the above-mentioned deficiencies of the prior art, the present invention provides an electronic package comprising: a first electronic component; a first insulating layer disposed on the first electronic component and the second electronic component; a cladding layer, a package Covering the first electronic component, and exposing the first insulating layer to the cladding layer; the second insulating layer is formed on the cladding layer and the first insulating layer; and the circuit layer is formed on the first layer The second insulating layer is electrically connected to the first electronic component.

The invention provides a method for manufacturing an electronic package, comprising: disposing at least one first electronic component on a carrier, and the first electronic component is provided with a first insulating layer; forming a cladding layer on the carrier And covering the first insulating layer with the first electronic component; removing a portion of the cladding layer and the portion of the first An insulating layer for exposing the first insulating layer to the cladding layer; forming a second insulating layer on the cladding layer and the first insulating layer; and forming a wiring layer on the second insulating layer and electrically Connected to the first electronic component.

In the foregoing method, the removing comprises removing the carrier.

In the above electronic package and method of manufacturing the same, the first electronic component has an opposite active surface and an inactive surface, and the first insulating layer is disposed on the active surface.

In the above electronic package and method of manufacturing the same, the upper surface of the cladding layer is flush with the upper surface of the first insulating layer.

The electronic package and the manufacturing method thereof include a plurality of conductive blind vias formed in the first insulating layer and the second insulating layer, wherein the wiring layer is electrically connected to the first electron through the conductive blind via element.

In the foregoing electronic package and method of manufacturing the same, the method further comprises forming a plurality of conductive elements on the circuit layer.

In the foregoing electronic package and method of manufacturing the same, the second electronic component is embedded in the cladding layer, and the height of the second electronic component is different from the height of the first electronic component, and the first insulating layer is The second electronic component is disposed on the second electronic component, and the circuit layer is electrically connected to the second electronic component.

For example, the first electronic component and the second electronic component have opposite active and non-active surfaces, the first insulating layer is disposed on the active surface, and the active surface of the first electronic component and the cladding layer The distance between the upper surfaces is greater than the distance between the active surface of the second electronic component and the upper surface of the cladding.

Furthermore, the height between the second electronic component and the first electronic component The difference is less than 10um. Alternatively, the height of the second electronic component is greater than the height of the first electronic component.

Moreover, the total height of the second electronic component and the first insulating layer is different from the total height of the first electronic component and the first insulating layer.

In addition, the total height of the second electronic component and the first insulating layer is equal to the total height of the first electronic component and the first insulating layer.

In addition, the thickness of the first insulating layer on the first electronic component does not match the thickness of the first insulating layer on the second electronic component.

In another aspect, the forming includes forming the conductive blind vias in the first insulating layer and the second insulating layer, and electrically connecting the wiring layer to the first electronic component and the second electronic component through the conductive blind via.

It can be seen that the electronic package of the present invention and the method for manufacturing the same are mainly formed by forming only a single insulating layer (ie, a first insulating layer) on the first electronic component when the first electronic component is disposed on the carrier. The multilayer insulating layer and the metal pillar are not formed, so that only one insulating layer needs to be removed without removing the two insulating layers, so that the manufacturing method of the invention can improve the grinding process capability and can be reduced compared with the prior art. Process (such as: yellow light, electroplated copper column, etc.) and cost savings.

10,20‧‧‧Carrier

10a, 20a‧‧‧Fractal layer

100‧‧‧Adhesive layer

101,102‧‧‧First passivation layer

11‧‧‧First chip

12‧‧‧second chip

13‧‧‧Package colloid

14‧‧‧Second passivation layer

15‧‧‧Metal column

2,4‧‧‧Electronic package

200‧‧‧ bonding layer

201,202,301,302‧‧‧First insulation

21‧‧‧First electronic components

21a, 22a‧‧‧ action surface

21b, 22b‧‧‧ non-active surface

210,220‧‧‧electrode pads

22‧‧‧Second electronic components

23‧‧‧Cladding

23a‧‧‧ first surface

23b‧‧‧ second surface

24‧‧‧Second insulation

240‧‧‧Blind hole

25‧‧‧Line layer

250‧‧‧conductive blind holes

26‧‧‧Conductive components

27‧‧‧Insulation protective layer

a, b‧‧‧ distance

D, H, L‧‧‧ total height

d, h‧‧‧ height

t, t1, t2‧‧‧ thickness

1A to 1B are schematic cross-sectional views showing a conventional multi-wafer module packaging process; FIGS. 2A to 2F are cross-sectional views showing the manufacturing method of the electronic package of the present invention; and FIGS. 3A to 3B are diagrams 2A to 2C; Profile of another embodiment Schematic; and Figures 4A through 4F are schematic cross-sectional views of other embodiments of Figures 2A through 2C.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2F are schematic cross-sectional views showing the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A, at least one first electronic component 21 and at least one second electronic component 22 are disposed on a carrier 20, and the first and second electronic components 21, 22 are provided with a first insulating layer 201, 202. Wherein the height d of the second electronic component 22 relative to the carrier 20 is different from the first electronic component The height h of the member 21 relative to the carrier 20, and the height difference between the two is less than 10 um (i.e., dh < 10 um), that is, the first electronic component 21 and the second electronic component are on the same alignment basis. 22 thickness is different, the thickness difference is less than 10um.

In this embodiment, the first and second electronic components 21, 22 are active components, passive components, or a combination thereof, and the active components are, for example, semiconductor wafers, and the passive components are, for example, resistors, capacitors, and inductors. . For example, the first electronic component 21 and the second electronic component 22 are semiconductor wafers having opposite opposing surfaces 21a, 22a and non-active surfaces 21b, 22b having a plurality of electrode pads 210, 220, and The first electronic component 21 and the second electronic component 22 are adhered to the release layer 20a of the carrier 20 by a bonding layer 200 with its non-active surfaces 21b, 22b.

Furthermore, the height d of the second electronic component 22 (the thickness of the bonding layer 200 is extremely thin, negligible) is greater than the height h of the first electronic component 21 (the thickness of the bonding layer 200 is extremely thin and negligible), and The thicknesses t of the first insulating layers 201, 202 are uniform, such that the total height D of the second electronic component 22 and the first insulating layer 202 is different from (greater than) the total height of the first electronic component 21 and the first insulating layer 201. H.

In another embodiment, as shown in FIG. 3A, the thickness t1 of the first insulating layer 301 on the first electronic component 21 and the thickness of the second insulating layer 302 on the second electronic component 22 T2 may be inconsistent, and the total height L of the second electronic component 22 and the first insulating layer 202 may be equal to the total height L of the first electronic component 21 and the first insulating layer 201.

In addition, the material of the first insulating layer 201, 202 is formed as oxidation. A passivation material of tantalum or tantalum nitride, or a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP).

As shown in FIG. 2B, a cladding layer 23 is formed on the carrier 20 to cover the first insulating layer 201, 202, the first electronic component 21 and the second electronic component 22.

In the present embodiment, the cladding layer 23 has opposite first and second surfaces 23a, 23b, and the cladding layer 23 is bonded to the release layer 20a of the carrier 20 with its second surface 23b.

As shown in FIG. 2C, the first surface 23a of the cladding layer 23 is flushed to the surface of the first insulating layer 201, 202 by the leveling process, so that the first insulating layer 201, 202 is exposed to the cladding layer 23. . The first insulating layers 201, 202 are respectively used to protect the active surfaces 21a, 22a of the first electronic component 21 and the second electronic component 22, thereby avoiding damage to the active surface during the leveling process.

In the present embodiment, the cladding layer 23 is an insulating material, such as an encapsulant of epoxy resin, which may be formed on the carrier 20 by lamination or molding.

Furthermore, the leveling process removes a portion of the material of the first insulating layer 202 at one of the locations (removing part of the material of the first insulating layer 201 at another location as needed) and the cladding layer by grinding. Part of the material of 23. It should be understood that, if the process of FIG. 3A is continued, after removing the material of the cladding layer 23 after the leveling process, the structure similar to that of FIG. 2C can be obtained, as shown in FIG. 3B. The first surface 23a of the cladding 23 is flush with the surface of the first insulating layer 301, 302.

Moreover, as shown in FIG. 3B (or the same as FIG. 2C), the distance a between the active surface 21a of the first electronic component 21 and the first surface 23a of the cladding layer 23 is greater than the second electronic component 22. The distance b between the active surface 22a and the first surface 23a of the cladding layer 23.

Further, the height difference between the height d of the second electronic component 22 and the height h of the first electronic component 21 is less than 10 μm to ensure good workability. If the height difference between the two is greater than 10 um, there is a problem of poor workability, for example, the first insulating layer 201, 301 reaching the first electronic component 21 cannot be ground, so that the first insulation on the first electronic component 21 is caused. The layers 201, 301 do not expose the first surface 23a of the cladding layer 23.

As shown in FIG. 2D, a second insulating layer 24 is formed on the first surface 23a of the cladding layer 23 and the first insulating layer 201, 202, and a plurality of blind vias 240 are formed on the second insulating layer 24 and the second insulating layer 24. In an insulating layer 201, 202, the electrode pads 210, 220 are correspondingly exposed to the blind hole 240.

In this embodiment, the material of the second insulating layer 24 is a passivation material such as yttrium oxide or tantalum nitride, or a poly-p-dioxene benzene (PBO) or a polyimide (PI). Prepreg (PP) dielectric material.

Furthermore, the material of the second insulating layer 24 may be the same or different from the material of the first insulating layer 201, 202.

As shown in FIG. 2E, a circuit layer 25 is formed on the second insulating layer 24, and a plurality of conductive vias 250 are formed integrally with the circuit layer 25 to electrically connect the circuit layer 25. And electrode pads 210, 220 of the first electronic component 21 and the second electronic component 22. Then, forming a complex number such as The conductive element 26 of the solder ball is on the circuit layer 25 for subsequent connection to an electronic device such as a package structure, a circuit board or a wafer (not shown).

In this embodiment, the material forming the wiring layer 25 and the conductive blind vias 250 is copper.

Furthermore, an insulating protective layer 27 such as a solder resist layer may be formed on the wiring layer 25, and a plurality of openings are formed in the insulating protective layer 27 to expose portions of the surface of the wiring layer 25 to the openings. The holes are formed to form the conductive element 26 on the exposed surface of the circuit layer 25 in the opening.

As shown in FIG. 2F, the carrier 20 and the release layer 20a thereon are removed, and the bonding layer 200 is exposed. The bonding layer 200 may also be removed to expose the non-active surfaces 21b, 22b of the first and second electronic components 21, 22 to the second surface 23b of the cladding layer 23.

Therefore, in the method of the present invention, when the first and second electronic components 21, 22 are disposed on the carrier 20, only the first insulating layer 201, 202 is formed on the first and second electronic components 21, 22 to serve as a buffer layer (protecting the active surface 21a, 22a), and after removing a portion of the material of the first insulating layer 202, continuing to form the wiring layer 25, thereby only grinding a passivation layer (ie, the first insulating layer 201, 202) The method of the present invention can improve the processing capability of the grinding process, and can reduce the process (such as yellow light, electroplated copper, etc.) and save cost compared to the prior art.

It should be understood that, as shown in FIGS. 4A to 4F, the electronic package 4 of the present invention may be fabricated only for a single first electronic component 21.

Moreover, when the total height L of the second electronic component 22 and the first insulating layer 202 is equal to the total height of the first electronic component 21 and the first insulating layer 201 When the degree is L, there is no difference in height between the two places, so there is no problem of over-grinding or insufficient workability, and thus the process capability can be increased.

The invention also provides an electronic package 2, 4 comprising: at least one electronic component (first electronic component 21 and / or a second electronic component 22), a first insulating layer 201, 202, 301, 302, a cladding layer 23, a The second insulating layer 24 and the wiring layer 25.

The height h of the first electronic component 21 is different from the height d of the second electronic component 22.

The first insulating layer 201, 202, 301, 302 is disposed on the first electronic component 21 and the second electronic component 22.

The cladding layer 23 covers the first and second electronic components 21, 22, and exposes the first insulating layer 201, 202, 301, 302 to the cladding layer 23.

The second insulating layer 24 is disposed on the cladding layer 23 and the first insulating layer 201, 202, 301, 302.

The circuit layer 25 is formed on the second insulating layer 24 and electrically connected to the first electronic component 21 and the second electronic component 22 through the conductive via hole 250.

In one embodiment, a distance a between the first electronic component 21 and the first surface 23a of the cladding layer 23 is greater than between the second electronic component 22 and the first surface 23a of the cladding layer 23. Distance b.

In one embodiment, the height difference between the height d of the second electronic component 22 and the height h of the first electronic component 21 is less than 10 um.

In an embodiment, the height d of the second electronic component 22 is greater than the first The height h of an electronic component 21.

In one embodiment, the total height D of the second electronic component 22 and the first insulating layer 202 is different from the total height H of the first electronic component 21 and the first insulating layer 201.

In one embodiment, the total height L of the second electronic component 22 and the first insulating layer 302 is equal to the total height L of the first electronic component 21 and the first insulating layer 301.

In one embodiment, the thicknesses t1, t2 of the first insulating layers 301, 302 are inconsistent.

In one embodiment, the first surface 23a of the cladding layer 23 is flush with the surface of the first insulating layer 201, 202, 301, 302.

In one embodiment, a plurality of conductive elements 26 are formed on the circuit layer 25.

In summary, the electronic package of the present invention is formed by forming only a single insulating layer on the first electronic component when the first electronic component is disposed on the carrier. The layer can be used to improve the processing capability of the grinding process, and can reduce the process (such as yellow light, electroplated copper column, etc.) and save cost.

Moreover, when the total height of the second electronic component and the first insulating layer is equal to the total height of the first electronic component and the first insulating layer, the problem of over-grinding or insufficient workability can be avoided, thereby increasing the process ability.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. change. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Electronic package

200‧‧‧ bonding layer

201,202‧‧‧First insulation

21‧‧‧First electronic components

21b, 22b‧‧‧ non-active surface

22‧‧‧Second electronic components

23‧‧‧Cladding

23a‧‧‧ first surface

23b‧‧‧ second surface

24‧‧‧Second insulation

25‧‧‧Line layer

250‧‧‧conductive blind holes

26‧‧‧Conductive components

27‧‧‧Insulation protective layer

Claims (21)

  1. An electronic package includes: a first electronic component; a second electronic component having a height different from a height of the first electronic component; and a first insulating layer disposed on the first electronic component and the second electronic component And the total height of the height of the second electronic component is equal to or different from the total height of the first electronic component and the thickness of the first insulating layer; the cladding layer The first electronic component and the second electronic component are coated, and the first insulating layer is exposed on the cladding layer; the second insulating layer is formed on the cladding layer and the first insulating layer; And a circuit layer formed on the second insulating layer and electrically connecting the first electronic component and the second electronic component.
  2. The electronic package of claim 1, wherein the first electronic component has an opposite active surface and an inactive surface, and the first insulating layer is disposed on the active surface.
  3. The electronic package of claim 1, wherein the upper surface of the cladding layer is flush with the upper surface of the first insulating layer.
  4. The electronic package of claim 1, further comprising a plurality of conductive blind holes formed in the first insulating layer and the second insulating layer, wherein the circuit layer is electrically connected to the conductive via hole The first electronic component.
  5. The electronic package of claim 1, further comprising a plurality of conductive elements formed on the circuit layer.
  6. The electronic package of claim 1, wherein the first electronic component and the second electronic component have opposite active and non-active surfaces, the first insulating layer is disposed on the active surface, and The distance between the active surface of the first electronic component and the upper surface of the cladding layer is greater than the distance between the active surface of the second electronic component and the upper surface of the cladding layer.
  7. The electronic package of claim 1, wherein the height difference between the second electronic component and the first electronic component is less than 10 um.
  8. The electronic package of claim 1, wherein the height of the second electronic component is greater than the height of the first electronic component.
  9. The electronic package of claim 1, wherein the thickness of the first insulating layer on the first electronic component does not match the thickness of the first insulating layer on the second electronic component.
  10. The electronic package of claim 1, further comprising a plurality of conductive blind holes formed in the first insulating layer and the second insulating layer, wherein the circuit layer is electrically connected to the conductive via hole The first electronic component and the second electronic component.
  11. An electronic package is formed by: providing at least one first electronic component and at least one second electronic component on a carrier, and the first electronic component and the second electronic component are provided with a first insulating layer, wherein The height of the second electronic component is different from the a height of the first electronic component, and a total height of the second electronic component added to the thickness of the first insulating layer is equal to or different from a height of the first electronic component and a thickness of the first insulating layer a total height; forming a cladding layer on the carrier to cover the first insulating layer, the second electronic component and the first electronic component; removing a portion of the cladding layer and a portion of the first insulating layer to a first insulating layer is exposed on the cladding layer; a second insulating layer is formed on the cladding layer and the first insulating layer; and a wiring layer is formed on the second insulating layer and electrically connected to the first electronic component With the second electronic component.
  12. The method of manufacturing an electronic package according to claim 11, wherein the first electronic component has an opposite active surface and an inactive surface, and the first insulating layer is disposed on the active surface.
  13. The method of manufacturing an electronic package according to claim 11, wherein the upper surface of the cladding layer is flush with the upper surface of the first insulating layer.
  14. The method for manufacturing an electronic package according to claim 11, further comprising forming a plurality of conductive via holes in the first insulating layer and the second insulating layer, and electrically connecting the circuit layer through the conductive via holes To the first electronic component.
  15. The method of manufacturing an electronic package according to claim 11 further comprising forming a plurality of conductive elements on the circuit layer.
  16. The method of manufacturing an electronic package according to claim 11, wherein the first electronic component and the second electronic component have opposite surfaces And a non-active surface, the first insulating layer is disposed on the active surface, and a distance between an active surface of the first electronic component and an upper surface of the cladding layer is greater than an active surface of the second electronic component The distance between the surfaces above the cladding.
  17. The method of manufacturing an electronic package according to claim 11, wherein a height difference between the second electronic component and the first electronic component is less than 10 um.
  18. The method of manufacturing an electronic package according to claim 11, wherein the height of the second electronic component is greater than the height of the first electronic component.
  19. The method of manufacturing an electronic package according to claim 11, wherein a thickness of the first insulating layer on the first electronic component is inconsistent with a thickness of the first insulating layer on the second electronic component.
  20. The method for manufacturing an electronic package according to claim 11, further comprising forming a plurality of conductive via holes in the first insulating layer and the second insulating layer, and electrically connecting the circuit layer through the conductive via holes To the first electronic component and the second electronic component.
  21. The method of manufacturing an electronic package according to claim 11 further comprises removing the carrier.
TW105136121A 2016-11-07 2016-11-07 Electronic package and method TWI594382B (en)

Priority Applications (1)

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TW105136121A TWI594382B (en) 2016-11-07 2016-11-07 Electronic package and method
CN201611011829.7A CN108074904A (en) 2016-11-07 2016-11-17 Electronic package and method for manufacturing same

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TWI594382B true TWI594382B (en) 2017-08-01
TW201818516A TW201818516A (en) 2018-05-16

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US20140197535A1 (en) * 2012-05-18 2014-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
TW201517183A (en) * 2013-10-18 2015-05-01 Taiwan Semiconductor Mfg Semiconductor device and manufacturing method thereof

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