TWI606562B - Electronic package structure - Google Patents
Electronic package structure Download PDFInfo
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- TWI606562B TWI606562B TW104101442A TW104101442A TWI606562B TW I606562 B TWI606562 B TW I606562B TW 104101442 A TW104101442 A TW 104101442A TW 104101442 A TW104101442 A TW 104101442A TW I606562 B TWI606562 B TW I606562B
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- electronic component
- package structure
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Solid State Image Pick-Up Elements (AREA)
Description
本發明係有關一種電子封裝結構,尤指一種能薄型化之電子封裝結構及導電結構。 The invention relates to an electronic package structure, in particular to an electronic package structure and a conductive structure which can be thinned.
隨著電子產業的發達,現今的電子產品已趨向輕薄短小與功能多樣化的方向設計,半導體封裝技術亦隨之開發出不同的封裝型態。 With the development of the electronics industry, today's electronic products have been designed in a light, short, and versatile manner, and semiconductor packaging technologies have also developed different packaging types.
目前應用於感測器元件或相機鏡頭之電子元件大都仍採用打線(Wire bonding)封裝型式、或晶片直接板上封裝(Chip On Board,簡稱COB)型式。 Most of the electronic components currently used in sensor components or camera lenses are still in the wire bonding package type or the Chip On Board (COB) type.
如第1A圖所示,習知打線型封裝結構1係包括:一基板10、一電子元件13以及一封裝膠體18。 As shown in FIG. 1A, the conventional wire-type package structure 1 includes a substrate 10, an electronic component 13, and an encapsulant 18.
所述之基板10係於上、下側設有第一線路層11與第二線路層12,且藉由形成於其中之通孔或盲孔型導電體14電性連接該第一與第二線路層11,12,並於上、下側形成第一絕緣保護層16與第二絕緣保護層17,以令部分該第一與第二線路層11,12外露於該第一與第二絕緣保護層16,17,且令複數導電元件15形成於該第二線路層12上。 The substrate 10 is provided with a first circuit layer 11 and a second circuit layer 12 on the upper and lower sides, and is electrically connected to the first and second through a via hole or a blind via type conductor 14 formed therein. The circuit layers 11, 12 are formed with a first insulating protective layer 16 and a second insulating protective layer 17 on the upper and lower sides to expose portions of the first and second circuit layers 11, 12 to the first and second insulating layers. The layers 16, 17 are protected and a plurality of conductive elements 15 are formed on the second wiring layer 12.
所述之電子元件13係為感測器元件,其形成於該基板10上側並藉由複數金線130電性連接該第一線路層11,且該電子元件13之上表面係具有一感應區131以作為指紋辨識之用。 The electronic component 13 is a sensor component formed on the upper side of the substrate 10 and electrically connected to the first circuit layer 11 by a plurality of gold wires 130, and the upper surface of the electronic component 13 has a sensing area. 131 for use as fingerprint identification.
所述之封裝膠體18係形成於該基板10上側並包覆該電子元件13與該些金線130。 The encapsulant 18 is formed on the upper side of the substrate 10 and covers the electronic component 13 and the gold wires 130.
於習知打線型封裝結構1中,該封裝膠體18覆蓋該感應區131上之有效感應之厚度d需極薄(否則無法感測),因而需極高的精度。 In the conventional wire-type package structure 1, the thickness d of the effective sensing of the encapsulant 18 covering the sensing region 131 needs to be extremely thin (otherwise, it cannot be sensed), and thus requires extremely high precision.
然而,該金線130具有一定的拉高線弧,且模封製程需具有足夠高度以使該封裝膠體18均勻覆蓋該電子元件13,導致難以控制該封裝膠體18之極薄厚度,以致於該打線型封裝結構1無法達到薄化之需求。 However, the gold wire 130 has a certain height of the arc, and the molding process needs to have a height sufficient to uniformly cover the electronic component 13 by the encapsulant 18, which makes it difficult to control the extremely thin thickness of the encapsulant 18, so that The wire-type package structure 1 cannot meet the demand for thinning.
第1B圖係為習知COB型封裝結構1’之剖面示意圖。如第1B圖所示,該COB型封裝結構1’係包括:一基板10’、一相機鏡頭之IC電子元件13、一透光件19以及一封裝膠體18,且該基板10’係可參考第1A圖所示之構造。 Fig. 1B is a schematic cross-sectional view showing a conventional COB type package structure 1'. As shown in FIG. 1B, the COB type package structure 1' includes: a substrate 10', an IC electronic component 13 of a camera lens, a light transmissive member 19, and an encapsulant 18, and the substrate 10' is referenced. The structure shown in Fig. 1A.
所述之電子元件13係形成於該基板10’上側並藉由複數金線130電性連接該基板10’,且該電子元件13之上表面係具有一感應區131以作為光感應之用。 The electronic component 13 is formed on the upper side of the substrate 10' and electrically connected to the substrate 10' by a plurality of gold wires 130. The upper surface of the electronic component 13 has a sensing region 131 for light sensing.
所述之透光件19係藉由複數支撐件190形成於該電子元件13之上表面並遮蓋該感應區131。 The light transmissive member 19 is formed on the upper surface of the electronic component 13 by a plurality of support members 190 and covers the sensing region 131.
所述之封裝膠體18係為非透光材,其形成於該基板10上側並包覆該透光件19、電子元件13與該些金線130, 且該透光件19之上表面外露於該封裝膠體18。 The encapsulant 18 is a non-transparent material, and is formed on the upper side of the substrate 10 and covers the transparent member 19, the electronic component 13 and the gold wires 130. The upper surface of the light transmissive member 19 is exposed to the encapsulant 18 .
於習知COB型封裝結構1’中,相機鏡頭需薄型化。惟,該電子元件13需黏貼於該基板10’上,且該透光件19需藉由該些支撐件190設於該電子元件13上,使得該COB型封裝結構1’之整體厚度不易薄型化。 In the conventional COB type package structure 1', the camera lens needs to be thinned. The electronic component 13 is to be adhered to the substrate 10 ′, and the transparent component 19 is disposed on the electronic component 13 by the support member 190 , so that the overall thickness of the COB package structure 1 ′ is not easy to be thin. Chemical.
為了解決上述問題,遂有應用半導體的矽穿孔(Through Silicon Via,簡稱TSV)技術進行封裝。如第1C圖所示,習知光感應封裝結構1”係包括:一矽基板10”以及一透光件19’。 In order to solve the above problems, there is a semiconductor silicon-on-silicon (Through Silicon Via, TSV) technology for packaging. As shown in Fig. 1C, the conventional photo-sensing package structure 1" includes a substrate 10" and a light-transmissive member 19'.
所述之矽基板10”係於上、下側設有第一線路層11與第二線路層12,且藉由形成於其中之導電矽穿孔100電性連接該第一線路層11與第二線路層12,並於上側形成感應區131,而下側形成絕緣保護層17’,以令部分該第二線路層12外露於該絕緣保護層17’,且令複數導電元件15形成於該第二線路層12之外露表面上。 The first substrate layer 11 and the second circuit layer 12 are disposed on the upper and lower sides, and the first circuit layer 11 and the second layer are electrically connected by the conductive germanium through holes 100 formed therein. The circuit layer 12 has a sensing region 131 formed on the upper side, and an insulating protective layer 17' is formed on the lower side to expose a portion of the second wiring layer 12 to the insulating protective layer 17', and the plurality of conductive elements 15 are formed in the first layer The two circuit layers 12 are exposed on the surface.
所述之透光件19’係藉由黏著層190’形成於該矽基板10”上側並遮蓋該感應區131。 The light transmissive member 19' is formed on the upper side of the crucible substrate 10" by an adhesive layer 190' and covers the sensing region 131.
惟,習知光感應封裝結構1”中,因製作導電矽穿孔100之成本昂貴、整合難度高、技術難度高,尤其是應用於感測器元件或相機鏡頭之電子元件均為高成本。 However, in the conventional light-sensing package structure 1", the cost of manufacturing the conductive perforation 100 is expensive, the integration difficulty is high, and the technical difficulty is high, especially the electronic components applied to the sensor element or the camera lens are high in cost.
因此,如何克服上述習知技術之種種問題,實已成為目前業界亟待克服之難題。 Therefore, how to overcome the various problems of the above-mentioned prior art has become a difficult problem to be overcome in the industry.
鑑於上述習知技術之種種缺失,本發明係提供一種電 子封裝結構,係包括:一絕緣體,係具有相對之第一表面與第二表面;一電子元件,係自該第一表面埋設於該絕緣體中,且具有外露於該第一表面的至少一感應區;以及一導電結構,係設於該絕緣體之第一表面上並電性連接該電子元件,且該導電結構未遮蓋該感應區。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides an electric The sub-package structure includes: an insulator having opposite first and second surfaces; an electronic component embedded in the insulator from the first surface and having at least one sensing exposed on the first surface And a conductive structure disposed on the first surface of the insulator and electrically connected to the electronic component, and the conductive structure does not cover the sensing region.
本發明復提供一種電子封裝結構,係包括:一絕緣體,係具有相對之第一表面與第二表面;一電子元件,係自該第一表面埋設於該絕緣體中並凸出該絕緣體之第一表面,且具有外露於該第一表面的至少一感應區;以及一具有高度差之導電結構,係設於該絕緣體之第一表面上並電性連接該電子元件,且該導電結構未遮蓋該感應區。 The present invention further provides an electronic package structure comprising: an insulator having opposite first and second surfaces; an electronic component embedded in the insulator from the first surface and protruding first of the insulator a surface having at least one sensing region exposed on the first surface; and a conductive structure having a height difference, disposed on the first surface of the insulator and electrically connecting the electronic component, and the conductive structure does not cover the Sensing area.
前述之兩種電子封裝結構中,該絕緣體中具有連通該第一表面並電性連接該導電結構之一線路結構。 In the above two electronic package structures, the insulator has a line structure that communicates with the first surface and is electrically connected to the conductive structure.
前述之兩種電子封裝結構中,該導電結構係透過一結合層設於該絕緣體之第一表面上,且該結合層未遮蓋該感應區。 In the above two electronic package structures, the conductive structure is disposed on the first surface of the insulator through a bonding layer, and the bonding layer does not cover the sensing region.
前述之兩種電子封裝結構中,該導電結構係引腳架,且以複數導電凸塊連接該電子元件或另一電子元件。 In the above two electronic package structures, the conductive structure is a lead frame, and the electronic component or another electronic component is connected by a plurality of conductive bumps.
前述之兩種電子封裝結構中,該導電結構係包含一具有複數開孔之引腳架及複數設於該些開孔中之導電凸塊,且該些導電凸塊係電性連接該電子元件。 In the above two electronic package structures, the conductive structure includes a lead frame having a plurality of openings and a plurality of conductive bumps disposed in the openings, and the conductive bumps are electrically connected to the electronic component .
前述之兩種電子封裝結構中,該導電結構係具有複數凸接點,且該些凸接點係電性連接該電子元件 In the above two electronic package structures, the conductive structure has a plurality of protruding contacts, and the protruding contacts are electrically connected to the electronic component
前述之兩種電子封裝結構中,復包括形成於該絕緣體 之第二表面上之複數導電元件。 In the foregoing two electronic package structures, the complex includes the insulator formed on the insulator a plurality of conductive elements on the second surface.
前述之兩種電子封裝結構中,該絕緣體之第一表面上具有用以設置該電子元件之至少一凹部。 In the above two electronic package structures, the first surface of the insulator has at least one recess for arranging the electronic component.
前述之兩種電子封裝結構中,該電子元件係凸出該絕緣體之第一表面。 In the two electronic package structures described above, the electronic component protrudes from the first surface of the insulator.
前述之兩種電子封裝結構中,復包括覆蓋該感應區之一覆蓋層。 In the foregoing two electronic package structures, the cover layer covers one of the sensing regions.
前述之兩種電子封裝結構中,該導電結構係為階梯狀。 In the above two electronic package structures, the conductive structure is stepped.
前述之兩種電子封裝結構中,復包括結合於該絕緣體之另一電子元件,例如該另一電子元件為主動元件、被動元件或其組合。舉例而言,該另一電子元件係部分設於該絕緣體中而部分凸出該第一表面上,且該另一電子元件電性連接該導電柱體;或者,該另一電子元件係全部設於該絕緣體中;或者,該另一電子元件係全部設於該第一表面上。 In the foregoing two electronic package structures, another electronic component coupled to the insulator is included, for example, the other electronic component is an active component, a passive component, or a combination thereof. For example, the other electronic component is partially disposed in the insulator and partially protrudes from the first surface, and the other electronic component is electrically connected to the conductive pillar; or the other electronic component is completely disposed. In the insulator; or the other electronic component is all disposed on the first surface.
前述之兩種電子封裝結構中,復包括用以遮蓋該感應區之一透光件。 In the foregoing two electronic package structures, a light transmissive member for covering the sensing region is further included.
前述之兩種電子封裝結構中,復包括複數導電柱體,係埋設於該絕緣層中並電性連接該導電結構。 In the foregoing two electronic package structures, the plurality of conductive pillars are embedded in the insulating layer and electrically connected to the conductive structure.
由上可知,本發明之電子封裝結構,主要藉由埋設該電子元件於該絕緣體中,故能降低整體結構之厚度。 As can be seen from the above, the electronic package structure of the present invention mainly reduces the thickness of the overall structure by embedding the electronic component in the insulator.
1‧‧‧打線型封裝結構 1‧‧‧Wire type package structure
1’‧‧‧COB型封裝結構 1'‧‧‧COB type package structure
1”‧‧‧光感應封裝結構 1”‧‧‧Light-sensing package structure
10,10’‧‧‧基板 10,10’‧‧‧substrate
10”‧‧‧矽基板 10"‧‧‧矽 substrate
100‧‧‧導電矽穿孔 100‧‧‧ Conductive piercing
11‧‧‧第一線路層 11‧‧‧First line layer
12‧‧‧第二線路層 12‧‧‧Second circuit layer
13,23,26,40‧‧‧電子元件 13,23,26,40‧‧‧Electronic components
130‧‧‧金線 130‧‧‧ Gold wire
131,231‧‧‧感應區 131,231‧‧‧sensing area
14‧‧‧通孔或盲孔型導電體 14‧‧‧through hole or blind via conductor
15,25‧‧‧導電元件 15,25‧‧‧ conductive elements
16‧‧‧第一絕緣保護層 16‧‧‧First insulation protection layer
17‧‧‧第二絕緣保護層 17‧‧‧Second insulation protection layer
17’‧‧‧絕緣保護層 17'‧‧‧Insulating protective layer
18‧‧‧封裝膠體 18‧‧‧Package colloid
19,19’,50‧‧‧透光件 19,19’, 50‧‧‧Lighting parts
190‧‧‧支撐件 190‧‧‧Support
190’,33‧‧‧黏著層 190’, 33‧‧‧ adhesive layer
2a-2d,2a’-2d’,3,3’,4,4’,5,5’‧‧‧電子封裝結構 2a-2d, 2a'-2d', 3, 3', 4, 4', 5, 5' ‧ ‧ electronic package structure
20‧‧‧絕緣體 20‧‧‧Insulator
20a‧‧‧第一表面 20a‧‧‧ first surface
20b‧‧‧第二表面 20b‧‧‧second surface
21,21’,21”,31‧‧‧覆蓋層 21, 21’, 21”, 31‧‧ Cover
22‧‧‧線路層 22‧‧‧Line layer
220,240‧‧‧電性接觸墊 220,240‧‧‧Electrical contact pads
23a‧‧‧作用面 23a‧‧‧Action surface
23b‧‧‧非作用面 23b‧‧‧Non-active surface
230‧‧‧電極墊 230‧‧‧electrode pads
24‧‧‧導電柱體 24‧‧‧Electrical cylinder
27‧‧‧線路結構 27‧‧‧Line structure
28a-28d,38a-38d‧‧‧導電結構 28a-28d, 38a-38d‧‧‧ conductive structure
28‧‧‧引腳架 28‧‧‧Lead frame
280,280’,283‧‧‧導電凸塊 280,280',283‧‧‧conductive bumps
281‧‧‧開孔 281‧‧‧ openings
282‧‧‧凸接點 282‧‧‧ convex joints
284‧‧‧黏著材 284‧‧‧Adhesive
29,39‧‧‧結合層 29, 39‧‧‧ bonding layer
300‧‧‧凹部 300‧‧‧ recess
d‧‧‧厚度 D‧‧‧thickness
第1A圖係為習知打線型封裝結構之剖面示意圖;第1B圖係為習知COB型封裝結構之剖面示意圖; 第1C圖係為習知光感應封裝結構之剖面示意圖;第2-1至2-4圖係為本發明之電子封裝結構之導電結構之各種實施例之剖視示意圖;第2A至2D圖係為本發明之電子封裝結構之第一實施例之剖視示意圖;其中,第2A’至2D’圖係為第2A至2D圖之另一態樣;第3及3’圖係為本發明之電子封裝結構之第二實施例之剖視示意圖;其中,第3A至3C圖係為第3圖之導電結構之其它態樣;第4、4’及4”圖係為本發明之電子封裝結構之第三實施例之剖視示意圖;以及第5及5’圖係為本發明之電子封裝結構之第四實施例之剖視示意圖。 1A is a schematic cross-sectional view of a conventional wire-type package structure; FIG. 1B is a schematic cross-sectional view of a conventional COB-type package structure; 1C is a schematic cross-sectional view of a conventional photo-sensing package structure; and FIGS. 2-1 to 2-4 are cross-sectional views showing various embodiments of the conductive structure of the electronic package structure of the present invention; FIGS. 2A to 2D are A schematic cross-sectional view of a first embodiment of an electronic package structure of the present invention; wherein the 2A' to 2D' views are another aspect of the 2A to 2D drawings; and the 3rd and 3' drawings are the electronic package of the present invention. A cross-sectional view of a second embodiment of the structure; wherein, FIGS. 3A to 3C are other aspects of the conductive structure of FIG. 3; and FIGS. 4, 4' and 4" are the first embodiment of the electronic package structure of the present invention. 3 is a schematic cross-sectional view of a fourth embodiment of the electronic package structure of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如 “上”、“下”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. At the same time, as quoted in this manual The terms "upper", "lower", "first", "second" and "one" are used for convenience of description only, and are not intended to limit the scope of the invention, and the relative relationship changes. Or, if it is not specifically changed, it is considered to be within the scope of the invention.
第2A至2D圖係為本發明之電子封裝結構2a-2d之第一實施例之剖視示意圖。本實施例之電子封裝結構2a-2d係應用於指紋辨識或影像感測器等之產品。 2A to 2D are cross-sectional views showing a first embodiment of the electronic package structure 2a-2d of the present invention. The electronic package structures 2a-2d of this embodiment are applied to products such as fingerprint recognition or image sensors.
再者,以下各實施例係說明應用第2-1至2-4圖所示之導電結構28a-28d。 Furthermore, the following embodiments illustrate the application of the conductive structures 28a-28d shown in Figures 2-1 to 2-4.
如第2A及2A’圖所示,所述之電子封裝結構2a係包括一絕緣體20、一電子元件23、一線路結構27以及一導電結構28a。 As shown in Figures 2A and 2A', the electronic package structure 2a includes an insulator 20, an electronic component 23, a wiring structure 27, and a conductive structure 28a.
所述之絕緣體20係具有相對之第一表面20a與第二表面20b。於本實施例中,該絕緣體20係為鑄模化合物(molding compound)、介電材(dielectric material)、如環氧樹脂(Epoxy)、聚醯亞胺(Polyimide,簡稱PI)、其它感光或非感光性材料等之有機樹脂。 The insulator 20 has opposite first and second surfaces 20a, 20b. In this embodiment, the insulator 20 is a molding compound, a dielectric material, such as an epoxy resin (Epoxy), a polyimide (PI), or other photosensitive or non-photosensitive. An organic resin such as a material.
所述之電子元件23係嵌埋於該絕緣體20中。於本實施例中,該電子元件23係為感測器元件,例如半導體晶片結構,其具有一作用面23a與相對該作用面23a之非作用面23b,該作用面23a上具有一如光感區或指紋辨識之感應區231與複數電極墊230,以令該作用面23a齊平或略低該絕緣體20之第一表面20a,使該感應區231與該些電極墊230外露於該絕緣體20之第一表面20a。 The electronic component 23 is embedded in the insulator 20. In this embodiment, the electronic component 23 is a sensor component, such as a semiconductor wafer structure, having an active surface 23a and an inactive surface 23b opposite to the active surface 23a. The active surface 23a has a light perception. The sensing area 231 and the plurality of electrode pads 230 are disposed such that the active surface 23a is flush or slightly lower than the first surface 20a of the insulator 20, and the sensing area 231 and the electrode pads 230 are exposed to the insulator 20. The first surface 20a.
所述之線路結構27形成於該絕緣體20中並連通該絕緣體20之第一表面20a與第二表面20b。 The line structure 27 is formed in the insulator 20 and communicates with the first surface 20a and the second surface 20b of the insulator 20.
於本實施例中,該線路結構27包含複數線路層22與複數導電柱體24,且各該線路層22之間藉由該些導電柱體24相互電性導通,並使該導電柱體24連通該第一表面20a,以令其端面作為電性接觸墊240,而該線路層22連通該第二表面20b,以令該線路層22之外露表面作為電性接觸墊220。具體地,以圖案化製程之電鍍、沉積或蝕刻方式形成如銅材之線路層22與導電柱體24。 In this embodiment, the circuit structure 27 includes a plurality of circuit layers 22 and a plurality of conductive pillars 24, and each of the circuit layers 22 is electrically connected to each other by the conductive pillars 24, and the conductive pillars 24 are electrically connected to each other. The first surface 20a is connected to have its end surface as the electrical contact pad 240, and the circuit layer 22 communicates with the second surface 20b to make the exposed surface of the circuit layer 22 serve as the electrical contact pad 220. Specifically, the wiring layer 22 such as copper and the conductive pillar 24 are formed by plating, deposition or etching of a patterning process.
再者,該線路層22之電性接觸墊220可齊平、略高或略低於該絕緣體20之第二表面20b,且該導電柱體24之電性接觸墊240亦可齊平、略高或略低於該第一表面20a。 Furthermore, the electrical contact pads 220 of the circuit layer 22 can be flush, slightly higher or slightly lower than the second surface 20b of the insulator 20, and the electrical contact pads 240 of the conductive pillars 24 can also be flush and slightly High or slightly lower than the first surface 20a.
又,該線路層22並未接觸該電子元件23之非作用面23b,亦即該線路層22與該電子元件23之非作用面23b之間具有該絕緣體20。 Moreover, the circuit layer 22 does not contact the inactive surface 23b of the electronic component 23, that is, the insulator 20 is provided between the wiring layer 22 and the non-active surface 23b of the electronic component 23.
所述之導電結構28a係如第2-1圖所示,其設於該絕緣體20之第一表面20a上並電性連接該電子元件23與該線路結構27,且該導電結構28a未遮蓋該感應區231。 The conductive structure 28a is disposed on the first surface 20a of the insulator 20 and electrically connected to the electronic component 23 and the circuit structure 27, and the conductive structure 28a does not cover the conductive structure 28a. Sensing area 231.
於本實施例中,該導電結構28a係為引腳架,其以複數如焊錫或金屬膠製成之導電凸塊280接觸該些電極墊230與該電性接觸墊240以電性連接該電子元件23與該線路結構27。 In this embodiment, the conductive structure 28a is a lead frame, and the plurality of conductive bumps 280, such as solder or metal glue, are in contact with the electrode pads 230 and the electrical contact pads 240 to electrically connect the electrons. Element 23 and the line structure 27.
再者,該導電結構28a係藉由結合層29設於該絕緣體20之第一表面20a上,其中,該結合層29係為介電材或 防焊材等之絕緣材,且該結合層29係可覆蓋該電子元件23之局部作用面23a而未覆蓋該感應區231。 Moreover, the conductive structure 28a is disposed on the first surface 20a of the insulator 20 by the bonding layer 29, wherein the bonding layer 29 is a dielectric material or An insulating material such as a solder resist material, and the bonding layer 29 covers the local active surface 23a of the electronic component 23 without covering the sensing region 231.
如第2A圖所示,該電子封裝結構2a係適用於平面網格陣列封裝(Land Grid Array,簡稱LGA),即直接以該線路層22之電性接觸墊220接置於一如電路板之電子裝置(圖略)上。 As shown in FIG. 2A, the electronic package structure 2a is suitable for a planar grid array (LGA), that is, directly connected to the electrical contact pad 220 of the circuit layer 22, such as a circuit board. On the electronic device (figure omitted).
或者,如第2A’圖所示,該電子封裝結構2a’復包括形成於該絕緣體20之第二表面20b上之複數導電元件25,以適用於球柵陣列封裝(Ball Grid Array,簡稱BGA),故於後續製程中,該些導電元件25接置於一如電路板之電子裝置(圖略)上。 Alternatively, as shown in FIG. 2A', the electronic package structure 2a' includes a plurality of conductive elements 25 formed on the second surface 20b of the insulator 20 for use in a Ball Grid Array (BGA). Therefore, in the subsequent process, the conductive elements 25 are placed on an electronic device (not shown) such as a circuit board.
於本實施例中,該些導電元件25係為各種態樣,如焊球、焊錫凸塊、銅凸塊等,並無特別限制,且該些導電元件25係形成於該線路層22之電性接觸墊220上以電性連接該線路結構27。 In the present embodiment, the conductive elements 25 are in various aspects, such as solder balls, solder bumps, copper bumps, etc., and are not particularly limited, and the conductive elements 25 are formed on the circuit layer 22 The contact pad 220 is electrically connected to the line structure 27.
再者,如第2A’圖所示,所述之電子封裝結構2a’復包括形成於該導電結構28a上之一如絕緣材之覆蓋層21,以覆蓋該感應區231。具體地,該覆蓋層21之材質與該結合層29之材質可為相同(如圖中所示)或不相同,且該覆蓋層21與該結合層29可同時製作或分開製作(如圖中所示)。 Furthermore, as shown in FIG. 2A', the electronic package structure 2a' includes a cover layer 21 formed on the conductive structure 28a, such as an insulating material, to cover the sensing region 231. Specifically, the material of the cover layer 21 and the material of the bonding layer 29 may be the same (as shown in the figure) or different, and the cover layer 21 and the bonding layer 29 may be simultaneously or separately fabricated (as shown in the figure). Shown).
又,如第2A’圖所示,該導電結構28a、該些導電柱體24與該線路層22之導電路徑係延伸至該電子元件23之非作用面23b下方。 Further, as shown in FIG. 2A', the conductive structure 28a, the conductive paths of the conductive pillars 24 and the wiring layer 22 extend below the non-active surface 23b of the electronic component 23.
另外,該導電結構之其它種類的應用可參考第2B至 2D圖具體說明如下。 In addition, other types of applications of the conductive structure can be referred to 2B to The 2D diagram is described in detail below.
如第2B圖所示之電子封裝結構2b,係依第2A圖之結構,該導電結構28b係如第2-2圖所示,其包含一具有複數開孔281之引腳架28及複數導電凸塊280,且該些導電凸塊280對應設於該些開孔281中以電性連接該些電極墊230與導電柱體24。 The electronic package structure 2b shown in FIG. 2B is a structure according to FIG. 2A. The conductive structure 28b is as shown in FIG. 2-2, and includes a lead frame 28 having a plurality of openings 281 and a plurality of conductive layers. The bumps 280 , and the conductive bumps 280 are correspondingly disposed in the openings 281 to electrically connect the electrode pads 230 and the conductive pillars 24 .
於製作時,先將該引腳架28設於該絕緣體20之第一表面20a上,且各該開孔281係對應該些電極墊230與該些導電柱體24(即該電性接觸墊240)之位置,再形成如焊錫或金屬膠之導電材於該開孔281中以作為該導電凸塊280。 The lead frame 28 is disposed on the first surface 20a of the insulator 20, and each of the openings 281 corresponds to the electrode pads 230 and the conductive pillars 24 (ie, the electrical contact pads). At the position of 240), a conductive material such as solder or metal paste is formed in the opening 281 to serve as the conductive bump 280.
再者,如第2B’圖所示之電子封裝結構2b’,可於該導電結構28b上形成一覆蓋層21’,以覆蓋該感應區231,且該覆蓋層21’之材質與該結合層29之材質係不相同。 Furthermore, as shown in FIG. 2B', the electronic package structure 2b' can form a cover layer 21' on the conductive structure 28b to cover the sensing region 231, and the material of the cover layer 21' and the bonding layer The material of 29 is different.
如第2C圖所示之電子封裝結構2c,係對應該第2A圖之結構,該導電結構28c係如第2-3圖所示,其具有複數一體成型之凸接點282以作為導電凸塊,且該些凸接點282係藉由黏著材284(如導電膠或絕緣膠)結合並電性連接該些電極墊230與導電柱體24。 The electronic package structure 2c shown in FIG. 2C corresponds to the structure of FIG. 2A. The conductive structure 28c is as shown in FIG. 2-3, and has a plurality of integrally formed bump contacts 282 as conductive bumps. The bumps 282 are bonded and electrically connected to the conductive pads 24 by adhesive materials 284 (such as conductive paste or insulating glue).
於製作時,於一平直之引腳架上側進行沖壓,以於該引腳架下側形成該些凸接點282。 During fabrication, stamping is performed on the upper side of a straight lead frame to form the bump contacts 282 on the lower side of the lead frame.
再者,如第2C’圖所示之電子封裝結構2c’,可於該導電結構28c上形成一覆蓋層21”,以覆蓋該感應區231。例如,該覆蓋層21”之材質與該結合層29之材質相同,故兩 者可同時製作。 Furthermore, the electronic package structure 2c' shown in FIG. 2C' can form a cover layer 21" on the conductive structure 28c to cover the sensing area 231. For example, the material of the cover layer 21" is combined with the material. Layer 29 is the same material, so two Can be made at the same time.
如第2D圖所示之電子封裝結構2d,係對應該第2A圖之結構,該導電結構28d如第2-4圖所示,其上、下側分別具有複數導電凸塊280,283,且設於下側之該些導電凸塊280係電性連接該些電極墊230與導電柱體24,而設於上側之該些導電凸塊283係用以外接其它電子元件26。 The electronic package structure 2d shown in FIG. 2D corresponds to the structure of FIG. 2A. The conductive structure 28d has a plurality of conductive bumps 280, 283 on the upper and lower sides, as shown in FIG. The conductive bumps 280 on the lower side are electrically connected to the electrode pads 230 and the conductive pillars 24, and the conductive bumps 283 disposed on the upper side are externally connected to the other electronic components 26.
於本實施例中,該電子元件26係為主動元件、被動元件或其組合者,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。於此,該電子元件26係為被動元件。 In this embodiment, the electronic component 26 is an active component, a passive component, or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. Here, the electronic component 26 is a passive component.
再者,如第2D’圖所示之電子封裝結構2d’,可於該導電結構28d上形成一覆蓋層21,以覆蓋該感應區231與該電子元件26。 Furthermore, as shown in the electronic package structure 2d' shown in FIG. 2D, a cover layer 21 may be formed on the conductive structure 28d to cover the sensing region 231 and the electronic component 26.
本發明之電子封裝結構2a-2d,2a-2d’,因該電子元件23嵌埋於該絕緣體20中,故能降低整體結構之厚度。 In the electronic package structures 2a-2d, 2a-2d' of the present invention, since the electronic component 23 is embedded in the insulator 20, the thickness of the overall structure can be reduced.
再者,因該導電結構28a-28d係為直條型的引腳架,故不會產生弧度,因而有利於降低整體結構之厚度。 Moreover, since the conductive structures 28a-28d are straight-type lead frames, no curvature is generated, which is advantageous for reducing the thickness of the overall structure.
第3及3’圖係為本發明之電子封裝結構3,3’之第二實施例之剖視示意圖。本實施例與第一實施例之差異在於嵌埋電子元件23之方式。 The third and third views are schematic cross-sectional views of a second embodiment of the electronic package structure 3, 3' of the present invention. The difference between this embodiment and the first embodiment lies in the manner in which the electronic component 23 is embedded.
如第3及3’圖所示,該絕緣體20之第一表面20a上具有一凹部300,以將該電子元件23設於該凹部300中。 As shown in Figures 3 and 3', the first surface 20a of the insulator 20 has a recess 300 in the electronic component 23 in the recess 300.
於本實施例中,該電子元件23以其非作用面23b藉由黏著層33設於該凹部300之底面上,且該電子元件23凸 出該絕緣體20之第一表面20a,故該導電結構38a需設計成具有高度差之引腳架,如階梯狀。 In this embodiment, the electronic component 23 is disposed on the bottom surface of the recess 300 by the adhesive layer 33 with its non-active surface 23b, and the electronic component 23 is convex. The first surface 20a of the insulator 20 is formed, so that the conductive structure 38a is designed to have a height difference of a lead frame, such as a stepped shape.
再者,如第3圖所示,可形成一覆蓋層31於該絕緣體20之第一表面20a上,以令該覆蓋層31包覆該導電結構38a與該些導電凸塊280並覆蓋該感應區231,且該覆蓋層31復形成於該凹部300中以固定該電子元件23。 Moreover, as shown in FIG. 3, a cover layer 31 may be formed on the first surface 20a of the insulator 20 such that the cover layer 31 covers the conductive structure 38a and the conductive bumps 280 and covers the sensing layer. A region 231 is formed, and the cover layer 31 is formed in the recess 300 to fix the electronic component 23.
或者,如第3’圖所示,亦可先將該導電結構38a藉由一結合層39設於該絕緣體20之第一表面20a上,以藉由該結合層39固定部分該導電凸塊280’,且該結合層39復形成於該凹部300中以固定該電子元件23,但該結合層39未覆蓋該感應區231,之後再形成一覆蓋層31於該結合層39上,以令該覆蓋層31包覆該導電結構38a與部分該導電凸塊280並覆蓋該感應區231。 Alternatively, as shown in FIG. 3', the conductive structure 38a may be first disposed on the first surface 20a of the insulator 20 by a bonding layer 39 to fix a portion of the conductive bump 280 by the bonding layer 39. ', and the bonding layer 39 is formed in the recess 300 to fix the electronic component 23, but the bonding layer 39 does not cover the sensing region 231, and then a cover layer 31 is formed on the bonding layer 39. The cover layer 31 covers the conductive structure 38a and a portion of the conductive bump 280 and covers the sensing region 231.
因此,該覆蓋層31之材質與該結合層39之材質可為相同或不相同,且該覆蓋層31與該結合層39可同時製作或分開製作。 Therefore, the material of the cover layer 31 and the material of the bonding layer 39 may be the same or different, and the cover layer 31 and the bonding layer 39 may be fabricated simultaneously or separately.
另外,該具有高度差之導電結構之種類並不限於上述,例如,依第3圖所示之電子封裝結構3將第2B至2D圖所示之導電結構設計成具有高度差之結構,如第3A至3C圖所示之導電結構38b-38d。 In addition, the type of the conductive structure having the height difference is not limited to the above. For example, the electronic package structure 3 shown in FIG. 3 designs the conductive structure shown in FIGS. 2B to 2D to have a structure with a height difference, such as Conductive structures 38b-38d shown in Figures 3A through 3C.
本發明之電子封裝結構3,3’,因該電子元件23設於該絕緣體20之凹部300中,故能降低整體結構之厚度。 In the electronic package structure 3, 3' of the present invention, since the electronic component 23 is provided in the recess 300 of the insulator 20, the thickness of the overall structure can be reduced.
第4及4’圖係為本發明之電子封裝結構4,4’之第三實施例之剖視示意圖。本實施例與第二實施例之差異在於新 增被動元件40,其它構造大致相同,故以下詳述差異處,而不贅述相同處。 4 and 4' are schematic cross-sectional views showing a third embodiment of the electronic package structure 4, 4' of the present invention. The difference between this embodiment and the second embodiment lies in the new The passive component 40 is increased, and the other configurations are substantially the same, so the differences will be described in detail below, and the same points will not be described.
如第4及4’圖所示,該電子封裝結構4,4’復包括自該第一表面20a嵌設於該絕緣體20中的另一電子元件40。 As shown in Figures 4 and 4', the electronic package structure 4, 4' includes a further electronic component 40 embedded in the insulator 20 from the first surface 20a.
於本實施例中,該另一電子元件40係為主動元件、被動元件或其組合者,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。於此,該另一電子元件40係為被動元件。 In this embodiment, the other electronic component 40 is an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. Here, the other electronic component 40 is a passive component.
再者,該另一電子元件40係部分設於該絕緣體20中而部分凸出該第一表面20a上,且該另一電子元件40電性連接該導電柱體24。 Furthermore, the other electronic component 40 is partially disposed in the insulator 20 to partially protrude from the first surface 20a, and the other electronic component 40 is electrically connected to the conductive pillar 24.
又,該另一電子元件40亦可全部設於該絕緣體20中(如第4’圖所示)、或全部設於該第一表面20a上(如第4”圖所示)。 Further, the other electronic component 40 may be entirely provided in the insulator 20 (as shown in Fig. 4') or entirely on the first surface 20a (as shown in Fig. 4).
另外,如第4’或4”圖所示,可形成一覆蓋層31於該絕緣體20之第一表面20a上,以令該覆蓋層31包覆該些電子元件23,40與該導電結構38a並覆蓋該感應區231。 In addition, as shown in FIG. 4' or 4", a cover layer 31 may be formed on the first surface 20a of the insulator 20 such that the cover layer 31 covers the electronic components 23, 40 and the conductive structure 38a. The sensing area 231 is covered.
第5及5’圖係為本發明之電子封裝結構5,5’之第五實施例之剖視示意圖。本實施例與上述各實施例之差異在於本實施例之電子封裝結構5,5’係應用於相機鏡頭,例如新增透光件50,其它構造大致相同,故以下詳述差異處,而不贅述相同處。 The fifth and fifth views are schematic cross-sectional views of a fifth embodiment of the electronic package structure 5, 5' of the present invention. The difference between this embodiment and the above embodiments is that the electronic package structure 5, 5' of the embodiment is applied to a camera lens, for example, a new light transmissive member 50 is added, and other structures are substantially the same, so the differences are detailed below, instead of Describe the same place.
如第5圖所示,該電子封裝結構5復包括一遮蓋該電子元件23之感應區231的透光件50,例如鏡片或玻璃元 件。 As shown in FIG. 5, the electronic package structure 5 further includes a light transmissive member 50 covering the sensing region 231 of the electronic component 23, such as a lens or a glass element. Pieces.
於本實施例中,係對應第2A圖之結構,該透光件50設於該導電結構28a上,因而無需製作習知支撐件,故能降低整體結構之厚度。 In the present embodiment, corresponding to the structure of FIG. 2A, the light transmissive member 50 is disposed on the conductive structure 28a, so that it is not necessary to fabricate a conventional support member, so that the thickness of the overall structure can be reduced.
或者,如第5’圖所示,係對應第2A’圖之結構,亦可於該覆蓋層21上設置該透光件50。因此,該透光件50之設置並無特別限制。 Alternatively, as shown in Fig. 5', the light transmissive member 50 may be provided on the cover layer 21 in accordance with the structure of Fig. 2A'. Therefore, the arrangement of the light transmitting member 50 is not particularly limited.
另外,本發明之上述各實施例中,該線路層22亦可接觸(或以黏著層結合)該電子元件23之非作用面23b,以供該電子元件23散熱。 In addition, in the above embodiments of the present invention, the circuit layer 22 may also contact (or bond with an adhesive layer) the non-active surface 23b of the electronic component 23 for heat dissipation of the electronic component 23.
綜上所述,本發明之電子封裝結構,係藉由將該電子元件嵌設於該絕緣體中,故能降低整體結構之厚度。 In summary, the electronic package structure of the present invention can reduce the thickness of the overall structure by embedding the electronic component in the insulator.
再者,以如引腳架之導電結構電性連接該電子元件,故於製作時,無需考量打線之線弧或封裝膠體之厚度,因而容易控制該電子封裝結構之厚度,以達到更薄的厚度。 Furthermore, the electronic component is electrically connected by a conductive structure such as a lead frame. Therefore, it is not necessary to consider the thickness of the wire arc or the thickness of the encapsulant during manufacture, so that the thickness of the electronic package structure can be easily controlled to achieve a thinner thickness. thickness.
又,因採用非半導體製程加工,故能降低製作成本,且該電子封裝結構易於隨產品需求而調整結構及設計,故其設計彈性佳。 Moreover, since the non-semiconductor process is used, the manufacturing cost can be reduced, and the electronic package structure is easy to adjust the structure and design according to the product requirements, so the design flexibility is good.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2a‧‧‧電子封裝結構 2a‧‧‧Electronic package structure
20‧‧‧絕緣體 20‧‧‧Insulator
20a‧‧‧第一表面 20a‧‧‧ first surface
20b‧‧‧第二表面 20b‧‧‧second surface
22‧‧‧線路層 22‧‧‧Line layer
220,240‧‧‧電性接觸墊 220,240‧‧‧Electrical contact pads
23‧‧‧電子元件 23‧‧‧Electronic components
23a‧‧‧作用面 23a‧‧‧Action surface
23b‧‧‧非作用面 23b‧‧‧Non-active surface
230‧‧‧電極墊 230‧‧‧electrode pads
231‧‧‧感應區 231‧‧‧ Sensing area
24‧‧‧導電柱體 24‧‧‧Electrical cylinder
27‧‧‧線路結構 27‧‧‧Line structure
28a‧‧‧導電結構 28a‧‧‧Electrical structure
280‧‧‧導電凸塊 280‧‧‧Electrical bumps
29‧‧‧結合層 29‧‧‧Combination layer
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