TWI529898B - Semiconductor package and fabrication method thereof - Google Patents

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package that reduces manufacturing cost and a method of fabricating the same.

With the rapid development of the electronics industry, electronic products tend to be light, thin and short in terms of type, and gradually become a high-performance, high-function, high-speed research and development direction in terms of functions. In order to meet the needs of multi-functionality, various electronic components in electronic products must be integrated, and must also meet the needs of miniaturization, and develop a technology of package on package (POP).

As shown in FIG. 1 , the conventional stacked package structure 1 is formed by stacking at least two semiconductor packages 1a, 1b. The semiconductor package 1a includes a package substrate 10, is disposed on the package substrate 10, and is wired. a semiconductor wafer 13 electrically connected to the package substrate 10, an encapsulant 14 covering the semiconductor wafer 13, and a bump 17a disposed on the package substrate 10 to connect another semiconductor package 1b, wherein Other electronic devices or packages are also attached to the underside of the package substrate 10 by solder balls 17b.

As the semiconductor process is more advanced, the distance between the I/O contacts on the semiconductor wafer 13 is getting smaller and smaller, and the distance between the lines on the corresponding package substrate 10 is also smaller.

However, in the conventional stacked package structure 1, the main material of the package substrate 10 is a polymer compound, such as BT (bismaleimide triazine) resin, which is limited by the process capability, so that the package substrate 10 cannot be applied to the wafer I/O connection. A product having a dot pitch of less than 50 μm; in addition, the conventional production of the substrate requires a large-format copper foil substrate containing BT resin for fabrication, and the circuit accumulation is not high, resulting in a small number of singulations of the package substrate 10, so the substrate product, The unit per hour (UPH) of the package structure and the stacked package structure 1 is not so high that the manufacturing cost cannot be reduced, which causes a bottleneck in the development of the package stacking technology.

Furthermore, the semiconductor wafer 13 is electrically connected to the bonding pad 100 of the package substrate 10 by a gold wire 11 , so that each of the bonding pads 100 needs to have a certain distance between each other. If the distance between the bonding pads 100 is too small, it will be disadvantageous. In the wire bonding process, it is easy to cause the gold wire 11 to contact and short circuit.

Moreover, in order to match a certain distance between the wire bonding pads 100, the package substrate 10 needs to have a certain layout area, so that the volume of the package substrate 10 cannot be reduced, and the need for miniaturization cannot be satisfied.

Therefore, how to overcome various problems of the prior art is an important issue.

In order to overcome the problems of the prior art, the present invention provides a semiconductor package comprising: a germanium-containing substrate having opposite first and second surfaces, and the first and second surfaces of the germanium-containing substrate The first and second circuit layers respectively have a conductive via to electrically connect the first and second circuit layers; the semiconductor component is disposed on the first surface of the germanium-containing substrate, and is electrically The first circuit layer is connected to the first circuit layer; the insulating material is formed on the first surface of the germanium-containing substrate to cover the semiconductor element; the third circuit layer is formed on the insulating material; and the conductive blind hole is Formed in the insulating material to electrically connect the first and third circuit layers.

The invention provides a method for fabricating a semiconductor package, comprising: providing a germanium-containing substrate having a first surface and a second surface opposite to each other, wherein the first and second surfaces of the germanium-containing substrate respectively have first and second a second circuit layer, wherein the germanium-containing substrate has conductive vias for electrically connecting the first and second circuit layers; combining a semiconductor component on the first surface of the germanium-containing substrate, and the semiconductor component is electrically connected to the first a circuit layer; forming an insulating material on the first surface of the germanium-containing substrate to cover the semiconductor element; and forming a third circuit layer on the insulating material, and forming a conductive blind hole electrically connected in the insulating material The first and third circuit layers.

In the above method, the process of the conductive via hole may include: forming a blind hole in the insulating material by patterning by laser or exposure and development, and then forming a metal material in the blind hole.

In the above semiconductor package and method of manufacturing the same, the germanium-containing substrate is a glass substrate, a germanium substrate or a wafer (which may be a wafer after being singulated).

In the foregoing semiconductor package and method of fabricating the same, the first circuit layer may have a first electrical connection pad to electrically connect the semiconductor component.

In the foregoing semiconductor package and the method of manufacturing the same, the carrier may be attached to the second surface of the germanium-containing substrate, and the second circuit layer may have a second electrical connection pad for electrically connecting the Carrier.

In the foregoing semiconductor package and method of fabricating the same, the semiconductor device may have a contact pad electrically coupled to the first wiring layer.

In the foregoing semiconductor package and method of manufacturing the same, the insulating material is a dry film or an encapsulant.

In the foregoing semiconductor package and method of manufacturing the same, the third circuit layer may have a third electrical connection pad to electrically connect the electronic device.

In addition, in the foregoing semiconductor package and the method of manufacturing the same, a solder resist layer may be formed on the insulating material, the third wiring layer, the germanium-containing substrate, and the second wiring layer, and may have a plurality of openings to expose the second and the second Three electrical connection pads.

As can be seen from the above, the semiconductor package of the present invention and the method for fabricating the same are mainly used to carry the semiconductor device using a germanium-containing substrate with conductive vias, so that the germanium-containing substrate can be applied to the I/O of the semiconductor device by the conductive via. A product having a dot pitch of less than 50 μm, and in the subsequent singulation process, the number of singulations of the ruthenium-containing substrate of the present invention can be greatly increased compared with the BT resin substrate of the prior art, thereby improving the semiconductor package and the package structure. Production per unit time (UPH) to reduce manufacturing costs.

Furthermore, the conductive vias in the germanium-containing substrate and the conductive vias in the insulating material serve as conductive paths, so that the semiconductor device can be electrically connected to the first circuit layer in a flip-chip manner, thereby eliminating the need for a wire bonding process. Compared with the prior art, the present invention can increase the wiring density of the first, second and third circuit layers to improve the functionality and the electrical transmission rate, and the conductive via or the conductive blind via does not short circuit.

Moreover, the third circuit layer is formed by using the space on the insulating material, and the layout area of the germanium-containing substrate can be reduced according to requirements (such as the commonly used 8吋, 12吋 wafer), so that the volume of the overall structure can be reduced to achieve The purpose of miniaturization.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower" and "one" are used in the description for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship may be changed or Adjustments, where there is no material change, are considered to be within the scope of the invention.

Please refer to FIGS. 2A to 2F for the fabrication of the semiconductor package 3 of the present invention.

As shown in FIG. 2A, a germanium-containing substrate 30 having a first surface 30a and a second surface 30b opposite to each other is provided, and the first and second surfaces 30a, 30b of the germanium-containing substrate 30 respectively have a first and The second circuit layer 31, 32.

In this embodiment, the ytterbium-containing substrate 30 has a plurality of conductive vias 300 electrically connected to the first and second circuit layers 31, 32, and the first and second circuit layers 31, 32 respectively have a first The second electrical connection pads 310, 320.

Furthermore, the germanium-containing substrate 30 is a panel of a glass substrate, a plate of a germanium substrate, or a wafer.

As shown in FIG. 2B, at least one semiconductor component 33 is bonded to the first surface 30a of the germanium-containing substrate 30, and the semiconductor component 33 is electrically connected to the first electrical connection pad 310 of the first circuit layer 31.

In this embodiment, the semiconductor component 33 has a plurality of contact pads 330 for electrically bonding to the first electrical connection pads 310.

Furthermore, the semiconductor element 33 may be a wafer type active element or a passive element, but is not particularly limited.

As shown in FIG. 2C, an insulating material 34 is formed on the first surface 30a of the germanium-containing substrate 30 and the first wiring layer 31 to cover the semiconductor element 33. The insulating material 34 is a dry film or an encapsulant.

As shown in FIG. 2D, a plurality of blind vias 340 are formed in the insulating material 34 by laser or patterned exposure development.

As shown in FIG. 2E, a third circuit layer 35 is formed on the insulating material 34 by a patterning process, and a metal material is collectively plated in the blind via 340 to serve as a conductive blind via 36. The conductive blind vias 36 are electrically connected to the first and third circuit layers 31, 35, and form a semiconductor package 3, and the first, second and third circuit layers 31, 32, 35 form a fan out (fan out ) Line type.

In the embodiment, the third circuit layer 35 has a plurality of third electrical connection pads 350.

As shown in FIG. 2F, a first solder resist layer 38a is formed on the insulating material 34 and the third wiring layer 35, and a second solder resist layer 38b is formed on the second surface 30b of the germanium containing substrate 30 and the first The first and second solder resist layers 38a, 38b have a plurality of openings 380, so that the second and third electrical connection pads 320, 350 are respectively exposed to the openings 380.

As shown in FIG. 2G, after singulation, an electronic device 3b is stacked on the first solder resist layer 38a on the insulating material 34, and the electronic device 3b is electrically connected to the third electrical property by the conductive member 37b. Connect the pad 350.

In the embodiment, the semiconductor package 3 has the same structure as the electronic device 3b. In other embodiments, the structure of the electronic device 3b may be different from the semiconductor package 3. Therefore, the structure of the electronic device 3b is not particularly limited.

In addition, the second surface 30b of the ytterbium-containing substrate 30 is disposed on a carrier (not shown), and the second electrical connection pad 320 of the second circuit layer 32 is electrically connected by the conductive component 37a. Carrier. The carrier may be a circuit board or another semiconductor package, and the structure of the other semiconductor package may be the same as or different from the first semiconductor package, and is not particularly limited. Further, the conductive members 37a, 37b are solder materials or solder pins.

The semiconductor package 3 of the present invention is formed by using the germanium-containing substrate 30 to carry the semiconductor device 33, so that the germanium-containing substrate 30 can be applied to the contact pads 330 of the semiconductor device 33 with a pitch of less than 50 μm. In addition, the use of the ruthenium-containing substrate in the subsequent singulation process can greatly increase the number of singulations of the ruthenium-containing substrate 30 of the present invention compared to the BT resin substrate of the prior art, thereby enhancing the present invention. The production yield (UPH) per unit time of the semiconductor package 3 is to reduce the manufacturing cost.

Moreover, the conductive via 300 and the conductive via 36 serve as conductive paths, so that the semiconductor device 33 can be electrically connected to the first circuit layer 31 in a flip-chip manner, thereby eliminating the need for a wire bonding process, thereby increasing the first The wiring density of the second and third circuit layers 31, 32, 35 enhances the functionality and electrical transmission rate, and the conductive via or conductive blind via does not short circuit.

Further, by forming the third wiring layer 35 by the space on the insulating material 34, the layout area of the germanium-containing substrate 30 can be reduced as required, so that the volume of the entire structure can be reduced to achieve miniaturization.

In addition, after the semiconductor package 3 is diced, the present invention provides a semiconductor package 3a, comprising: a germanium-containing substrate 30' having a first surface 30a and a second surface 30b opposite thereto, and a germanium-containing substrate 30 The semiconductor element 33 on the first surface 30a is formed on the first surface 30a of the germanium-containing substrate 30' to cover the insulating material 34 of the semiconductor element 33.

The germanium-containing substrate 30' is a glass substrate, a germanium substrate or a wafer, and the first and second surfaces 30a, 30b have first and second circuit layers 31, 32, respectively, and the germanium-containing substrate 30' The conductive via 300 is electrically connected to the first and second circuit layers 31, 32. The first circuit layer 31 has a first electrical connection pad 310 for electrically connecting the semiconductor component 33, and the second circuit layer 32 has a second electrical connection pad 320 for electrical connection. A carrier (not shown) on the second surface 30b of the germanium-containing substrate 30'.

The semiconductor component 33 has a contact pad 330 for electrically bonding to the first electrical connection pad 310.

The insulating material 34 has a third circuit layer 35 thereon, and has a conductive blind hole 36 in the insulating material 34 to electrically connect the first and third circuit layers 31, 35, and the first and second And the third circuit layers 31, 32, 35 form a fan-out line type.

The semiconductor package 3a further includes: a first solder resist layer 38a formed on the insulating material 34 and the third wiring layer 35, a second surface 30b formed on the germanium containing substrate 30, and the second circuit layer The second solder resist layer 38b on the second and second solder resist layers 38a, 38b has a plurality of openings 380, so that the second and third electrical connection pads 320, 350 are respectively exposed to the openings 380.

In summary, the semiconductor package of the present invention and the method for manufacturing the same are carried out by using a germanium-containing substrate having a conductive via to carry the semiconductor device, so that the germanium-containing substrate can be applied to a product having a contact pad pitch of less than 50 μm. The output per unit time of the semiconductor package reduces the manufacturing cost, increases the wiring density, improves the functionality and the electrical transmission rate, and reduces the size of the overall structure by utilizing the space efficiently, thereby achieving miniaturization.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1. . . Stacked package structure

1a. . . Semiconductor package

1b. . . Semiconductor package

10. . . Package substrate

100. . . Line mat

11. . . Gold Line

13. . . Semiconductor wafer

14. . . Encapsulant

17a. . . Bump

17b. . . Solder ball

3,3a. . . Semiconductor package

3b. . . Electronic device

30,30’. . . Yttrium-containing substrate

30a. . . First surface

30b. . . Second surface

300. . . Conductive perforation

31. . . First circuit layer

310. . . First electrical connection pad

32. . . Second circuit layer

320. . . Second electrical connection pad

33. . . Semiconductor component

330. . . Contact pad

34. . . Insulating material

340. . . Blind hole

35. . . Third circuit layer

350. . . Third electrical connection pad

36. . . Conductive blind hole

37a, 37b. . . Conductive component

38a. . . First solder mask

38b. . . Second solder mask

380. . . Opening

The first system is a schematic cross-sectional view of a conventional stacked package structure;

2A to 2G are schematic cross-sectional views showing the manufacturing method of the semiconductor package of the present invention.

3. . . Semiconductor package

30. . . Yttrium-containing substrate

30a. . . First surface

30b. . . Second surface

300. . . Conductive perforation

31. . . First circuit layer

32. . . Second circuit layer

33. . . Semiconductor component

34. . . Insulating material

340. . . Blind hole

35. . . Third circuit layer

350. . . Third electrical connection pad

36. . . Conductive blind hole

Claims (18)

A semiconductor package comprising: a germanium-containing substrate having opposite first and second surfaces, wherein the first and second surfaces of the germanium-containing substrate have first and second circuit layers, respectively a conductive via is electrically connected to the first and second circuit layers; a semiconductor component is disposed over the first surface of the germanium-containing substrate, and the semiconductor component has a plurality of contact pads, and the contact pads are in contact And bonding to the first circuit layer, the semiconductor device is electrically connected to the first circuit layer, and the contact pads are located above the first surface of the germanium-containing substrate; and the insulating material is formed on the germanium-containing substrate a first surface for coating the semiconductor element; a third circuit layer formed on the insulating material; and a conductive blind hole formed in the insulating material to electrically connect the first and third circuit layers . The semiconductor package of claim 1, wherein the germanium-containing substrate is a glass substrate, a germanium substrate or a wafer. The semiconductor package of claim 1, wherein the first circuit layer has a first electrical connection pad to electrically connect the semiconductor component. The semiconductor package of claim 1, wherein the second surface of the germanium-containing substrate is used to connect the carrier, and the second circuit layer is electrically connected to the carrier. The semiconductor package of claim 4, wherein the second circuit layer has a second electrical connection pad for electrically connecting the carrier. The semiconductor package of claim 5, further comprising a solder resist layer formed on the germanium-containing substrate and the second circuit layer, and having a plurality of openings to expose the second electrical connection pad At the opening. The semiconductor package of claim 1, wherein the third circuit layer has a third electrical connection pad for electrically connecting the electronic device. The semiconductor package of claim 7, further comprising a solder resist layer formed on the insulating material and the third circuit layer, and having a plurality of openings to expose the third electrical connection pad The opening. The semiconductor package of claim 1, wherein the insulating material is a dry film or an encapsulant. A method of fabricating a semiconductor package, comprising: providing a germanium-containing substrate having a first surface and a second surface, wherein the first and second surfaces of the germanium-containing substrate have first and second circuit layers, respectively; Further, the germanium-containing substrate has conductive vias for electrically connecting the first and second circuit layers; a semiconductor device is bonded over the first surface of the germanium-containing substrate, and the semiconductor device has contact pads to make the contacts The pad is contacted and bonded to the first circuit layer, the semiconductor device is electrically connected to the first circuit layer, and the contact pads are located above the first surface of the germanium-containing substrate; Forming an insulating material on the first surface of the germanium-containing substrate to encapsulate the semiconductor element; and forming a third circuit layer on the insulating material, and forming a conductive blind via in the insulating material to electrically connect the first And the third circuit layer. The method of fabricating a semiconductor package according to claim 10, wherein the germanium-containing substrate is a glass substrate, a germanium substrate or a wafer. The method of fabricating a semiconductor package according to claim 10, wherein the first circuit layer has a first electrical connection pad to electrically connect the semiconductor component. The method of manufacturing a semiconductor package according to claim 10, wherein a carrier is disposed on the second surface of the germanium-containing substrate, and the second circuit layer is electrically connected to the carrier. The method of fabricating a semiconductor package according to claim 13 , wherein the second circuit layer has a second electrical connection pad for electrically connecting the carrier. The method for manufacturing a semiconductor package according to claim 14, further comprising forming a solder resist layer on the germanium-containing substrate and the second circuit layer, and forming a plurality of openings on the solder resist layer to make the first Two electrical connection pads are exposed to the opening. The method of fabricating a semiconductor package according to claim 10, wherein the third circuit layer has a third electrical connection pad for electrically connecting the electronic device. The method for manufacturing a semiconductor package according to claim 16, further comprising forming a solder resist layer on the insulating material and the third circuit layer, and forming The plurality of openings are opened on the solder resist layer to expose the third electrical connection pad to the opening. The method of manufacturing a semiconductor package according to claim 10, wherein the process of the conductive via hole comprises: first forming a blind hole in the insulating material by laser or exposure and development, and forming Metal is in the blind hole.